Semiconductor device

Abstract

The present disclosure provides a semiconductor device, comprising: an interlayer dielectric layer on a substrate; a first connection line filling a first trench of the interlayer dielectric layer, the first trench having a first width; and a second connection line filling a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line comprising: a first metal layer covering an inner sidewall of the second trench, a barrier layer covering a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer comprising a first metal, and the second metal layer comprising a second metal different from the first metal.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2019-0109083 entitled "Semiconductor Device", filed with the Korean Intellectual Property Office on September 3, 2019, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor and a method of manufacturing the same. Background Technology

[0004] Semiconductor devices are advantageous in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices that incorporate both storage and logic elements. With the rapid development of the electronics industry, the demand for highly integrated semiconductor devices is increasing. For example, there is a growing need for semiconductor devices with high reliability, high speed, and / or versatility. Semiconductor devices have become increasingly complex and integrated to meet these required characteristics. Summary of the Invention

[0005] According to some example embodiments, a semiconductor device may include: an interlayer dielectric layer on a substrate; a first interconnect filling a first trench in the interlayer dielectric layer, the first trench having a first width; and a second interconnect filling a second trench in the interlayer dielectric layer. The second trench may have a second width greater than the first width. The second interconnect may include: a first metal layer covering the inner sidewalls of the second trench, a barrier layer covering the bottom surface of the second trench, and a second metal layer located on the first metal layer and the barrier layer. The first interconnect and the first metal layer may include a first metal. The second metal layer may include a second metal different from the first metal.

[0006] According to some example embodiments, a semiconductor device can include a substrate including a first active region; a first active pattern on the first active region; a first source / drain pattern on an upper portion of the first active pattern; a gate electrode across the first active pattern; an interlayer dielectric layer covering the first source / drain pattern and the gate electrode; and a first connection line and a second connection line in the interlayer dielectric layer. The first connection line can have a first width. The second connection line can have a second width greater than the first width. The second connection line can include a first metal layer on inner sidewalls of a trench of the interlayer dielectric layer, a barrier layer on a bottom surface of the trench of the interlayer dielectric layer, and a second metal layer on the first metal layer and the barrier layer. The first connection line and the first metal layer can include a first metal. The second metal layer can include a second metal different from the first metal.

[0007] According to some example embodiments, a semiconductor device can include a substrate including a first active region; a first active pattern on the first active region; a first source / drain pattern on an upper portion of the first active pattern; a gate electrode across the first active pattern; an interlayer dielectric layer covering the first source / drain pattern and the gate electrode; and a first connection line and a second connection line in the interlayer dielectric layer. The first connection line can have a first width. The second connection line can have a second width greater than the first width. The second connection line can include a first metal layer on inner sidewalls of a trench of the interlayer dielectric layer, a barrier layer on a bottom surface of the trench of the interlayer dielectric layer, and a second metal layer on the first metal layer and the barrier layer. The first connection line and the first metal layer can include a first metal. The second metal layer can include a second metal different from the first metal. BRIEF DESCRIPTION OF DRAWINGS

[0008] The features will become apparent from a consideration of the detailed description and drawings in which:

[0009] Figure 1 A flowchart of a method of manufacturing a semiconductor device according to some example embodiments is shown.

[0010] Figures 2A to 2F Cross-sectional views of stages in a method of manufacturing a semiconductor device according to some example embodiments are shown.

[0011] Figure 3 A graph showing a relationship between a width and a resistance of a metal material included in a semiconductor device according to some example embodiments is shown.

[0012] Figure 4 A plan view of a semiconductor device according to some example embodiments is shown.

[0013] Figure 5A , Figure 5B , Figure 5C and Figure 5D show cross-sectional views taken along lines A-A’, B-B’, C-C’, and D-D’ in Figure 4 , respectively.

[0014] Figure 6 , Figure 8 , Figure 10 and Figure 12 show plan views of stages in a method of manufacturing a semiconductor device according to some example embodiments.

[0015] Figure 7 , Figure 9A , Figure 11A and Figure 13A show cross-sectional views taken along line A-A’ in Figure 6 , Figure 8 , Figure 10 and Figure 12 , respectively.

[0016] Figure 9B , Figure 11B and Figure 13B show cross-sectional views taken along line B-B’ in Figure 8 , Figure 10 and Figure 12 , respectively.

[0017] Figure 9C , Figure 11C and Figure 13C show cross-sectional views taken along line C-C’ in Figure 8 , Figure 10 and Figure 12 , respectively.

[0018] Figure 13D cross-sectional views taken along lines D-D' in Figure 12

[0019] Figure 14A Figure 14B Figure 14C and Figure 14D show cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in Figure 4 show a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0020] Figure 1 shows a flowchart of a method of manufacturing a semiconductor device according to some example embodiments. Figures 2A to 2F shows cross-sectional views of stages in a method of manufacturing a semiconductor device according to some example embodiments.

[0021] Referring to Figure 1 and Figure 2A , an interlayer dielectric layer 130 can be provided on a substrate. The substrate can be a compound semiconductor substrate or a semiconductor substrate including at least one of, for example, silicon, germanium, silicon-germanium, etc. For example, the substrate can be a silicon substrate. The interlayer dielectric layer 130 can include at least one of tetraethoxysilane (TEOS), a low-k dielectric material, etc.

[0022] A trench for forming a connection line can be formed on the interlayer dielectric layer 130 (S10). For example, on the interlayer dielectric layer 130, a first trench TR1 can be formed to have a first width, and a second trench TR2 can be formed to have a second width greater than the first width.

[0023] Referring to Figure 1 and Figure 2B , a first metal MT1 can be deposited on the interlayer dielectric layer 130 (S20). The first metal MT1 can be deposited by, for example, one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0024] The first metal MT1 can completely fill the first trench TR1, for example, due to the smaller width of the first trench TR1, and can partially fill the second trench TR2. For example, the first metal MT1 can cover an inner sidewall TR2_S and a bottom surface TR2_B of the second trench TR2, for example, the first metal MT1 can be conformally formed on an inner surface of the second trench TR2.

[0025] The first metal MT1 can include at least one of, for example, cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), and molybdenum (Mo). For example, the first metal MT1 can include ruthenium (Ru).​​​

[0026] Referring to Figure 1 and Figure 2C A portion of the first metal MT1 formed on the interlayer dielectric layer 130 can be removed (S30). The portion of the first metal MT1 can be removed by an etching process, for example, a back-etching process.

[0027] The etching process can remove the first metal MT1 covering the uppermost surface of the interlayer dielectric layer 130 and the bottom surface TR2_B of the second trench TR2. The first metal MT1 covering the inner sidewall TR2_S of the second trench TR2 can be left as the first metal layer MB1.

[0028] The first metal MT1 filling the first trench TR1 can be left inside the first trench TR1. As Figure 2C shown, the first metal MT1 can completely fill the first trench TR1, thereby forming the first connection line M1. For example, the first connection line M1 can have an aspect ratio of about 1.5 to about 3.5, for example, a ratio of its depth to width.

[0029] Referring to Figure 1 and Figure 2D A barrier layer BR can be selectively deposited on a portion of the interlayer dielectric layer 130 (S40). The barrier layer BR can cover the top surface of the interlayer dielectric layer 130 and the bottom surface TR2_B of the second trench TR2, for example, the barrier layer BR can be formed directly only on the exposed surface of the interlayer dielectric layer 130 to maintain the first connection line M1 exposed.

[0030] The barrier layer BR can be a self-assembled monolayer (SAM), and can include at least one of, for example, hafnium nitride (HfN), tungsten nitride (WN), tungsten carbonitride (WCN), hafnium oxide (HfO), and tungsten oxide (WO). For example, the barrier layer BR can be deposited by one of, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0031] Referring to Figure 1 and Figure 2E A second metal MT2 can be deposited on the interlayer dielectric layer 130 (S50). For example, as Figure 2E shown, the second metal MT2 can cover the exposed surface of the barrier layer BR and the exposed surface of the first connection line M1, for example, the second metal MT2 can completely fill the second trench TR2. The second metal MT2 can be formed by one of, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and electroplating (EP).

[0032] The second metal MT2 can be different from the first metal MT1 and can include, for example, at least one of copper (Cu), ruthenium (Ru), molybdenum (Mo), platinum (Pt), iridium (Ir), rhodium (Rh), and titanium nitride (TiN). For example, the second metal MT2 can include copper (Cu).

[0033] Referring to Figure 1 and Figure 2F A portion of the second metal MT2 deposited on the interlayer dielectric layer 130 can be removed (S60). The portion of the second metal MT2 can be removed by a planarization process (e.g., chemical mechanical polishing (CMP)). For example, as shown in FIG. 6B, the second metal MT2 can be planarized such that a top surface thereof is coplanar with a top surface of the first connection line M1. Figure 2F

[0034] The second metal MT2 can be deposited in the second trench TR2 to contact a portion of the first metal layer MB1 (on a sidewall of the second trench TR2) and a portion of the barrier layer BR (on a bottom of the second trench TR2), thereby forming a second metal layer MB2 in the second trench TR2. The second connection line M2 can be composed of the second metal layer MB2 in the second trench TR2 and the first metal layer MB1 and the barrier layer BR. For example, as shown in FIG. 6C, an aspect ratio of the second connection line M2 can be less than an aspect ratio of the first connection line M1, for example, the aspect ratio of the second connection line M2 can be about 0.5 to about 1.5. Figure 2F

[0035] Figure 3 A graph showing a relationship between a width and a resistance of a metal material included in a semiconductor device according to some example embodiments is shown.

[0036] Referring to Figure 3 When the width of the second metal MT2 is in a range less than or equal to a certain width, the resistance of the second metal MT2 can rapidly increase as its width decreases. Accordingly, at or below the certain width, the resistance of the first metal MT1 can be less than the resistance of the second metal MT2. For example, at a first point of the graph in Figure 3 , the resistance of the first metal MT1 can be less than the resistance of the second metal MT2, while at a second point of the graph in Figure 3 , the resistance of the second metal MT2 can be less than the resistance of the first metal MT1.

[0037] Referring back to Figure 2F , the first metal MT1 can fill the first trench TR1 having a first width (e.g., according to the graph of FIG. 7A), and the second metal MT2 can fill the second trench TR2 having a second width (according to the graph of FIG. 7B). Figure 3 Figure 3 ​​​The second trench TR2 can be filled with the first metal layer MB1 including the first metal MT1 and the second metal layer MB2 including the second metal MT2. In other words, the second trench TR2 can include a hybrid connection line containing both the first metal MT1 and the second metal MT2, for example, a hybrid Ru / Cu connection line including a minimum amount of ruthenium around a copper line (for example, to minimize costs and to eliminate a separate CMP process of ruthenium) to improve costs and resistance of the connection line. Accordingly, because the semiconductor device according to the embodiment includes the first metal MT1 and the second metal MT2 whose resistances differ according to their widths, it is possible to reduce resistance of the semiconductor device and to improve its operating speed.

[0038] Figure 4 A top view of a semiconductor device according to some example embodiments is shown. Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D Cross-sectional views taken along lines A-A', B-B', C-C', and D-D' in Figure 4 are shown, respectively.

[0039] Referring to Figure 4 and Figures 5A to 5D , a logic cell LC can be disposed on the substrate 100. The logic cell LC can be provided with logic transistors constituting a logic circuit.

[0040] The substrate 100 can include a first active region PR and a second active region NR. In an embodiment, the first active region PR can be a PMOSFET region, and the second active region NR can be an NMOSFET region.

[0041] The first active region PR and the second active region NR can be defined by a fourth trench TR4 formed at an upper portion of the substrate 100 Figure 5C and Figure 5D . The fourth trench TR4 can be located between the first active region PR and the second active region NR. The first active region PR and the second active region NR can be spaced apart from each other in a first direction D1 across the fourth trench TR4. The first active region PR and the second active region NR can each extend in a second direction D2 intersecting the first direction D1.

[0042] The first active pattern AP1 and the second active pattern AP2 can be disposed on the first active region PR and the second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 can extend parallel to each other in the second direction D2. The first active pattern AP1 and the second active pattern AP2 can be vertical protruding portions of the substrate 100. The third trench TR3 can be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The third trench TR3 can be shallower than the fourth trench TR4.

[0043] The device isolation layer ST can fill the third trench TR3 and the fourth trench TR4. The device isolation layer ST can include, for example, a silicon oxide layer. The first active pattern AP1 and the second active pattern AP2 can have upper portions (see Figure 5D ) protruding vertically upward from the device isolation layer ST. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 can each have a fin shape. The device isolation layer ST can not cover the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The device isolation layer ST can cover lower side walls of the first active pattern AP1 and the second active pattern AP2.

[0044] The first source / drain pattern SD1 can be disposed on the upper portion of the first active pattern AP1. The first source / drain pattern SD1 can be an impurity region having a first conductivity type (e.g., p-type). The first channel pattern CH1 can be interposed between pairs of the first source / drain pattern SD1. The second source / drain pattern SD2 can be disposed on the upper portion of the second active pattern AP2. The second source / drain pattern SD2 can be an impurity region having a second conductivity type (e.g., n-type). The second channel pattern CH2 can be interposed between pairs of the second source / drain pattern SD2.

[0045] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed through a selective epitaxial growth process. For example, the uppermost surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be coplanar with the uppermost surfaces of the first channel pattern CH1 and the second channel pattern CH2 Figure 5A and Figure 5B ). In another example, the uppermost surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the uppermost surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0046] The first source / drain pattern SD1 can include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Thus, the first source / drain pattern SD1 can provide the first channel pattern CH1 with compressive stress. For example, the second source / drain pattern SD2 can include the same semiconductor element (e.g., Si) as that of the substrate 100.

[0047] The gate electrode GE can be disposed to extend in the first direction D1 while straddling the first active pattern AP1 and the second active pattern AP2. The gate electrode GE can be arranged along the second direction D2. The gate electrode GE can be vertically overlapped with the first channel pattern CH1 and the second channel pattern CH2 Figure 5A and Figure 5B ). Each gate electrode GE can surround a top surface and opposing sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2 Figure 5D

[0048] Referring back to Figure 5D , the gate electrode GE can be disposed on the first top surface TS1 of the first channel pattern CH1 and on at least one first sidewall SW1 of the first channel pattern CH1. The gate electrode GE can be disposed on the second top surface TS2 of the second channel pattern CH2 and on at least one second sidewall SW2 of the second channel pattern CH2. In this sense, the transistor according to the present embodiment can be a three-dimensional field effect transistor (e.g., FinFET) in which the first channel pattern CH1 and the second channel pattern CH2 are three-dimensionally surrounded by the gate electrode GE.

[0049] Referring back to Figure 4 and Figures 5A to 5D , a pair of gate spacers GS can be disposed on opposing sidewalls of each gate electrode GE. The gate spacer GS can extend in the first direction D1 along the gate electrode GE. A top surface of the gate spacer GS can be higher than a top surface of the gate electrode GE. The top surface of the gate spacer GS can be coplanar with a top surface of the first interlayer dielectric layer 110, which will be discussed below. For example, the gate spacer GS can include one or more of SiCN, SiCON, and SiN. In another example, the gate spacer GS can include a multi-layer including two or more of SiCN, SiCON, and SiN.

[0050] ​A gate capping pattern GP can be disposed on each gate electrode GE. The gate capping pattern GP can extend along the gate electrode GE in the first direction Dl. The gate capping pattern GP can include a material having etch selectivity with respect to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, which will be discussed below. For example, the gate capping pattern GP can include one or more of SiON, SiCN, SiCON, and SiN.

[0051] A gate dielectric pattern GI can be interposed between the gate electrode GE and the first active pattern API and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI can extend along a bottom surface of the gate electrode GE that is located above the gate dielectric pattern GI. For example, the gate dielectric pattern GI can cap a first top surface TS1 and a first sidewall SW1 of the first channel pattern CH1. The gate dielectric pattern GI can cap a second top surface TS2 and a second sidewall SW2 of the second channel pattern CH2. The gate dielectric pattern GI can cap a top surface of the device isolation layer ST that is located below the gate electrode GE (see FIG. 1). Figure 5D

[0052] In an embodiment, the gate dielectric pattern GI can include a high-k dielectric material having a dielectric constant greater than that of a silicon oxide layer. For example, the high-k dielectric material can include one or more of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0053] The gate electrode GE can include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern can be disposed on the gate dielectric pattern GI and adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern can include a work function metal that controls a threshold voltage of the transistor. The thickness and composition of the first metal pattern can be adjusted to obtain a desired threshold voltage.

[0054] The first metal pattern can include a metal nitride layer. For example, the first metal pattern can include nitrogen (N) and at least one metal, such as at least one of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). The first metal pattern can also include carbon (C). The first metal pattern can include a plurality of work function metal layers stacked.

[0055] The second metal pattern can include a metal having a lower electrical resistance than that of the first metal pattern. For example, the second metal pattern can include one or more of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0056] ​A first interlayer dielectric layer 110 can be disposed on the substrate 100. The first interlayer dielectric layer 110 can cover the gate spacers GS and the first and second source / drain patterns SD1, SD2. A top surface of the first interlayer dielectric layer 110 can be substantially coplanar with a top surface of the gate cap pattern GP and a top surface of the gate spacer GS. A second interlayer dielectric layer 120, which covers the gate cap pattern GP, can be disposed on the first interlayer dielectric layer 110. A third interlayer dielectric layer 130 (i.e., an interlayer dielectric layer 130) can be disposed on the second interlayer dielectric layer 120, e.g., the second interlayer dielectric layer 120 can be between the first interlayer dielectric layer 110 and the third interlayer dielectric layer 130.

[0057] A pair of separation structures DB, which face each other (e.g., are spaced apart from each other) in the second direction D2, can be disposed on opposite sides of the logic cell LC. The separation structures DB can extend in the first direction D1 in parallel with the gate electrodes GE.

[0058] The separation structures DB can penetrate the first and second interlayer dielectric layers 110, 120 and can extend into the first and second active patterns AP1, AP2 Figure 5A and Figure 5B ). The separation structures DB can penetrate a respective one of an upper portion of the first active pattern AP1 and an upper portion of the second active pattern AP2. The separation structures DB can separate the first and second active regions PR, NR of the logic cell LC from active regions of adjacent logic cells.

[0059] The active contacts AC can be disposed to penetrate the first and second interlayer dielectric layers 110, 120 and to electrically connect with the first and second source / drain patterns SD1, SD2. Each active contact AC can be disposed between a pair of gate electrodes GE.

[0060] The active contacts AC can be self-aligned contacts. For example, the gate cap pattern GP and the gate spacer GS can be used to form the active contacts AC in a self-aligned manner. For example, as shown in Figure 5A and Figure 5B , the active contacts AC can cover at least a portion of a sidewall of the gate spacer GS. In another example, the active contacts AC can partially cover a top surface of the gate cap pattern GP.

[0061] The silicide pattern SC can be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to one of the first source / drain pattern SD1 and the second source / drain pattern SD2 through the silicide pattern SC. The silicide pattern SC can include a metal silicide, for example, one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0062] The active contact AC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM can include one or more of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM can cover sidewalls and a bottom surface of the conductive pattern FM. The barrier pattern BM can include a metal layer and a metal nitride layer. The metal layer can include one or more of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can include one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0063] The first connection line M1 and the second connection line M2 can be disposed in the third interlayer dielectric layer 130. Detailed descriptions of the first connection line M1 and the second connection line M2 are substantially the same as those described above with reference to Figures 2A to 2F .

[0064] The first connection line M1 and the second connection line M2 can extend in, for example, a second direction D2 perpendicular to the gate electrode GE. Figure 4 The cell boundary can be defined to extend in the second direction D2 on opposite sides of the logic cell LC, and the second connection line M2 can be disposed on the cell boundary. The first connection line M1 can be disposed between the second connection lines M2 and can be spaced apart from each other at regular intervals in the first direction D1.

[0065] The first lower via V1_a and the second lower via V1_b can be disposed below the first connection line M1 and the second connection line M2. The first lower via V1_a can be interposed between the active contact AC and the first connection line M1 and the second connection line M2 (in a top square overlapped with the active contact AC in Figure 4 ), while electrically connecting the active contact AC to the first connection line M1 and the second connection line M2. The second lower via V1_b can be interposed between the gate electrode GE and the first connection line M1 and the second connection line M2 (in a top square overlapped with the gate electrode GE in Figure 4The square with "+" on top overlaps with the gate electrode GE, and the gate electrode GE is electrically connected to the first connection line M1 and the second connection line M2. A damascene or dual damascene process can be performed to form the first connection line M1 and the second connection line M2 together with the first lower via V1_a or the second lower via V1_b.

[0066] Figure 6 、 Figure 8 、 Figure 10 and Figure 12 show top views of stages in a method of manufacturing a semiconductor device according to some example embodiments. Figure 7 、 Figure 9A 、 Figure 11A and Figure 13A show cross-sectional views taken along line A-A' in Figure 6 、 Figure 8 、 Figure 10 and Figure 12 . Figure 9B 、 Figure 11B and Figure 13B show cross-sectional views taken along line B-B' in Figure 8 、 Figure 10 and Figure 12 . Figure 9C 、 Figure 11C and Figure 13C show cross-sectional views taken along line C-C' in Figure 8 、 Figure 10 and Figure 12 . Figure 13D shows a cross-sectional view taken along line D-D' in Figure 12 .

[0067] Referring to Figure 6 and Figure 7 , the substrate 100 can be provided with a first active region PR and a second active region NR. The substrate 100 can be patterned to form first active patterns AP1 and second active patterns AP2. The first active patterns AP1 can be formed on the first active region PR, and the second active patterns AP2 can be formed on the second active region NR. Third trenches TR3 can be formed between the first active patterns AP1 and between the second active patterns AP2.

[0068] The substrate 100 can be patterned to form fourth trenches TR4 between the first active region PR and the second active region NR. The fourth trenches TR4 can be formed deeper than the third trenches TR3.

[0069] A device isolation layer ST filling the third trenches TR3 and the fourth trenches TR4 can be formed on the substrate 100. The device isolation layer ST can include a dielectric material, e.g., a silicon oxide layer. The device isolation layer ST can be recessed until upper portions of the first active pattern AP1 and the second active pattern AP2 are exposed. Thus, the upper portions of the first active pattern AP1 and the second active pattern AP2 can protrude vertically upward from the device isolation layer ST, e.g., protrude vertically upward above the device isolation layer ST.

[0070] Referring to Figure 8 and Figures 9A to 9C A sacrificial pattern PP spanning the first active pattern AP1 and the second active pattern AP2 can be formed. Each sacrificial pattern PP can be formed to have a linear or strip shape extending in the first direction D1. For example, the formation of the sacrificial pattern PP can include forming a sacrificial layer over an entire surface of the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer can include, e.g., a polysilicon layer.

[0071] A pair of gate spacers GS can be formed on opposite sidewalls of each sacrificial pattern PP. The gate spacers GS can also be formed on opposite sidewalls of each of the first active pattern AP1 and the second active pattern AP2. The opposite sidewalls of each of the first active pattern AP1 and the second active pattern AP2 can be exposed portions that are neither covered by the device isolation layer ST nor covered by the sacrificial pattern PP.

[0072] The formation of the gate spacers GS can include conformally forming a gate spacer layer over an entire surface of the substrate 100, and anisotropically etching the gate spacer layer. For example, the gate spacer layer can include one or more of SiCN, SiCON, and SiN. In another example, the gate spacer layer can be a multi-layer including two or more of SiCN, SiCON, and SiN.

[0073] Referring to Figure 10 and Figures 11A to 11C A recess RS can be formed on the upper portion of each of the first active pattern AP1 and the second active pattern AP2. A pair of recesses RS can be formed on opposite sides of each sacrificial pattern PP. The formation of the recess RS can include performing an etching process using the hard mask pattern MA and the gate spacer GS as etching masks to etch the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. In performing the etching process, the gate spacer GS can be removed from the opposite sidewalls of each of the first active pattern AP1 and the second active pattern AP2. The exposed device isolation layer ST can be recessed during the etching process.

[0074] A first mask layer MP can be formed to selectively cover the second active pattern AP2. The first mask layer MP can selectively cover the first active region PR, but can expose the second active region NR. The first mask layer MP can expose the first active pattern AP1.

[0075] A first source / drain pattern SD1 can be formed to fill the recess RS of the first active pattern AP1 exposed by the first mask layer MP. For example, the formation of the first source / drain pattern SD1 can include performing a selective epitaxial growth process using the exposed inner sidewall of the recess RS as a seed layer. The formation of the first source / drain pattern SD1 can define a first channel pattern CH1 between pairs of the first source / drain pattern SD1. For example, the selective epitaxial growth process can include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0076] The first source / drain pattern SD1 can include a second semiconductor element having a lattice constant greater than a lattice constant of a first semiconductor element included in the substrate 100. For example, the first semiconductor element can be silicon (Si), and the second semiconductor element can be germanium (Ge). The first source / drain pattern SD1 can be formed to have a plurality of semiconductor layers. The formation of the first source / drain pattern SD1 can include sequentially forming the semiconductor layers. For example, the semiconductor layers can constitute a buffer layer, a main layer, and a cap layer.

[0077] Referring to Figure 12 and Figures 13A to 13D The first mask layer MP can be removed. A second mask layer can be formed to selectively cover the first active pattern AP1. The second mask layer can selectively cover the first active region PR, but can expose the second active region NR. The second mask layer can expose the second active pattern AP2.

[0078] A second source / drain pattern SD2 can be formed to fill the recess RS of the second active pattern AP2 exposed by the second mask layer. For example, the formation of the second source / drain pattern SD2 can include performing a selective epitaxial growth process using the exposed inner wall of the recess RS as a seed layer. The second source / drain pattern SD2 can include a first semiconductor element, e.g., silicon (Si), which is the same as the first semiconductor element of the substrate 100. Thereafter, the second mask layer can be removed.

[0079] A first interlayer dielectric layer 110 can be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the gate spacers GS, and the hard mask pattern MA. For example, the first interlayer dielectric layer 110 can include a silicon oxide layer.

[0080] A planarization process can be performed on the first interlayer dielectric layer 110 until the top surface of the sacrificial pattern PP is exposed. An etch-back or chemical mechanical polishing (CMP) process can be employed to planarize the first interlayer dielectric layer 110. As such, the top surface of the first interlayer dielectric layer 110 can be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0081] Each of the sacrificial patterns PP can be replaced with a gate electrode GE and a gate dielectric pattern GI. For example, the exposed sacrificial patterns PP can be selectively removed. The gate dielectric pattern GI can be formed in the void space where the sacrificial pattern PP was removed. The gate electrode GE can be formed on the gate dielectric pattern GI to fill the void space.

[0082] The gate dielectric pattern GI can be conformally formed by atomic layer deposition (ALD) and / or chemical oxidation. For example, the gate dielectric pattern GI can include a high-k dielectric material. In another example, the gate dielectric pattern GI can include a ferroelectric material.

[0083] Formation of the gate electrode GE can include forming a gate electrode layer on the gate dielectric pattern GI and planarizing the gate electrode layer. For example, the gate electrode layer can include a first gate electrode layer including a metal nitride and a second gate electrode layer including a low-resistance metal.

[0084] An upper portion of the gate electrode GE can be selectively etched to recess the gate electrode GE. A top surface of the recessed gate electrode GE can be lower than a top surface of the first interlayer dielectric layer 110 and a top surface of the gate spacer GS. A gate cap pattern GP can be formed on the recessed gate electrode GE. Formation of the gate cap pattern GP can include forming a gate cap layer to cap the recessed gate electrode GE and planarizing the gate cap layer until the top surface of the first interlayer dielectric layer 110 is exposed. The gate cap layer can include one or more of SiON, SiCN, SiCON, and SiN, for example.

[0085] Referring back to Figure 4 and Figures 5A to 5D A second interlayer dielectric layer 120 and a third interlayer dielectric layer 130 can be formed on the first interlayer dielectric layer 110. First connection lines M1 and second connection lines M2 can be formed in the third interlayer dielectric layer 130. Detailed descriptions of formation of the first connection lines M1 and the second connection lines M2 are substantially the same as discussed above with reference to Figure 1 and Figures 2A to 2F The first lower via V1_a and the second lower via V1_b can be formed under the first connection lines M1 and the second connection lines M2.

[0086] Figure 14A , Figure 14B , Figure 14C and Figure 14Dcross-sectional views taken along lines A-A', B-B', C-C', and D-D' in FIGS. Figure 4 are shown, showing semiconductor devices according to some example embodiments. In the following embodiments, technical features that are repetitive of technical features discussed above with reference to Figure 4 and Figures 5A to 5D will be omitted, and differences will be discussed in detail.

[0087] Referring to Figure 4 and Figures 14A to 14D , the substrate 100 can be provided with a first active region PR and a second active region NR. A device isolation layer ST can be provided on the substrate 100. The device isolation layer ST can define a first active pattern API and a second active pattern AP2 at an upper portion of the substrate 100. The first active pattern API and the second active pattern AP2 can be defined on the first active region PR and the second active region NR, respectively.

[0088] The first active pattern API can include a first channel pattern CH1' stacked vertically. The stacked first channel pattern CH1' can be spaced apart from each other in a third direction D3. The stacked first channel pattern CH1' can vertically overlap each other. The second active pattern AP2 can include a second channel pattern CH2' stacked vertically. The stacked second channel pattern CH2' can be spaced apart from each other in the third direction D3. The stacked second channel pattern CH2' can vertically overlap each other. The first channel pattern CH1' and the second channel pattern CH2' can include one or more of, for example, silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0089] The first active pattern API can further include a first source / drain pattern SD1. The stacked first channel pattern CH1' can be interposed between a pair of adjacent first source / drain patterns SD1. The stacked first channel pattern CH1' can connect the pair of adjacent first source / drain patterns SD1 to each other.

[0090] The second active pattern AP2 can further include a second source / drain pattern SD2. The stacked second channel pattern CH2' can be interposed between a pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2' can connect the pair of adjacent second source / drain patterns SD2 to each other.

[0091] A gate electrode GE can be provided to extend in a first direction D1 while straddling the first channel pattern CH1' and the second channel pattern CH2'. The gate electrode GE can vertically overlap the first channel pattern CH1' and the second channel pattern CH2'. A pair of gate spacers GS can be provided on opposite sidewalls of the gate electrode GE. A gate cover pattern GP can be provided on the gate electrode GE.

[0092] The gate electrode GE can be around each of the first channel pattern CH1' and the second channel pattern CH2' (see Figure 14D The gate electrode GE can be disposed on the first top surface TS1 of the first channel pattern CH1', at least one first sidewall SW1 of the first channel pattern CH1', and the first bottom surface BS1 of the first channel pattern CH1'. The gate electrode GE can be disposed on the second top surface TS2 of the second channel pattern CH2', at least one second sidewall SW2 of the second channel pattern CH2', and the second bottom surface BS2 of the second channel pattern CH2'. For example, the gate electrode GE can surround the top surface, bottom surface, and opposite sidewall of each of the first channel pattern CH1' and the second channel pattern CH2'. In this sense, the transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., FinFET) in which the first channel pattern CH1' and the second channel pattern CH2' are three-dimensionally surrounded by the gate electrode GE.

[0093] The gate dielectric pattern GI' may be located between the gate electrode GE and each of the first channel pattern CH1' and the second channel pattern CH2'. The gate dielectric pattern GI' may surround each of the first channel pattern CH1' and the second channel pattern CH2'.

[0094] On the second active region NR, the dielectric pattern IP can be positioned between the gate dielectric pattern GI' and the second source / drain pattern SD2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI' and the dielectric pattern IP. In contrast, the dielectric pattern IP may not be provided on the first active region PR.

[0095] The first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 can be disposed on the entire surface of the substrate 100. The active contact AC can be configured to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, and correspondingly connected to the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0096] The third interlayer dielectric layer 130 can be disposed on the second interlayer dielectric layer 120. The first connecting line M1 and the second connecting line M2 can be disposed on the third interlayer dielectric layer 130. A detailed description of the first connecting line M1 and the second connecting line M2 is provided above. Figures 2A to 2F The basic concepts discussed are the same.

[0097] The semiconductor device according to the present embodiment can include a connection line having a metal whose resistance varies with width. Thus, the resistance of the semiconductor device can be improved. Further, since the semiconductor device according to the present embodiment includes a mixed connection line in which different metals are mixed, the performance of the semiconductor device can be improved. In this way, the semiconductor device according to the present embodiment exhibits improved electrical characteristics.

[0098] Example embodiments have been disclosed herein and, although a particular terminology is employed, it is understood that the use of such terminology is merely for descriptive purposes and is not intended to be limiting. In some instances, features, characteristics, and / or elements described in connection with a particular embodiment can be used with other embodiments unless otherwise specifically stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the spirit and scope of the present application as set forth in the following claims.

Claims

1. A semiconductor device, comprising: Substrate, the substrate including a first active region; The first active pattern is located on the first active region; The first source / drain pattern is located on the upper part of the first active pattern; A gate electrode that spans the first active pattern; An interlayer dielectric layer covering the first source / drain pattern and the gate electrode; A first connection line, the first connection line being located in the interlayer dielectric layer, the first connection line having a first width; as well as A second connection line, located in the interlayer dielectric layer, having a second width greater than the first width, and comprising: The first metal layer located on the inner sidewall of the trench in the interlayer dielectric layer, A barrier layer located on the bottom surface of the trench in the interlayer dielectric layer, the bottom surface of the barrier layer being coplanar with the bottom surface of the first metal layer, and A second metal layer is located on the first metal layer and the barrier layer, the first connecting line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

2. The semiconductor device according to claim 1, wherein, The substrate further includes: Second active region; A second active pattern, the second active pattern being located on the second active region; and The second source / drain pattern is located on top of the second active pattern.

3. The semiconductor device of claim 2, further comprising a device isolation layer covering the lower sidewalls of the first active pattern and the lower sidewalls of the second active pattern, wherein the upper portion of each of the first active pattern and the second active pattern protrudes vertically over the device isolation layer.

4. The semiconductor device according to claim 2, wherein, The first active pattern includes a plurality of vertically stacked first channel patterns. The second active pattern includes a plurality of vertically stacked second channel patterns. The gate electrodes are configured as multiple. The first gate electrode of the plurality of gate electrodes is disposed on the top surface, bottom surface and opposite sidewall of each of the first channel patterns, and The second gate electrode of the plurality of gate electrodes is disposed on the top surface, bottom surface and opposite sidewall of each second channel pattern.

5. The semiconductor device according to claim 1, wherein, Within the first width, the resistance of the first metal is less than the resistance of the second metal, and During the second width, the resistance of the second metal is less than the resistance of the first metal.

6. The semiconductor device according to claim 1, wherein, The first metal includes at least one of cobalt, ruthenium, rhodium, iridium, and molybdenum, and The second metal includes at least one of copper, ruthenium, molybdenum, platinum, iridium, rhodium, and titanium nitride.

7. The semiconductor device according to claim 1, wherein, The first metal includes ruthenium, and the second metal includes copper.

8. The semiconductor device according to claim 1, wherein, The aspect ratio of the first connecting line is 1.5 to 3.

5.

9. The semiconductor device according to claim 1, wherein, The aspect ratio of the second connecting line is 0.5 to 1.

5.

10. The semiconductor device according to claim 1, wherein, The barrier layer includes at least one of hafnium nitride, tungsten nitride, tungsten carbonitride, hafnium oxide, and tungsten oxide.

11. The semiconductor device according to claim 1, wherein, The first metal layer only contacts a portion of the bottom surface of the trench.

12. The semiconductor device according to claim 11, wherein, The first metal layer of the second connecting line is conformal only on the inner sidewall of the trench among all the inner surfaces of the trench.

13. The semiconductor device according to claim 11, wherein, The barrier layer of the second connecting line is in direct contact only with the bottom surface of the trench, which is one of the inner surfaces of the trench.

14. A semiconductor device, comprising: A logic cell located on a substrate, the logic cell comprising a first active region and a second active region spaced apart from each other in a first direction; A first active pattern and a second active pattern, the first active pattern and the second active pattern are respectively located on the first active region and the second active region, and the first active pattern and the second active pattern extend in a second direction intersecting the first direction; The first source / drain pattern and the second source / drain pattern are located on the upper part of the first active pattern and the upper part of the second active pattern, respectively. A plurality of gate electrodes, the plurality of gate electrodes extending in the first direction and intersecting with the first active pattern and the second active pattern, the plurality of gate electrodes being arranged in the second direction; An interlayer dielectric layer covering the plurality of gate electrodes and the first source / drain pattern and the second source / drain pattern; as well as A first connection line is located in the interlayer dielectric layer, the first connection line has a first width and is electrically connected to one or more of the first source / drain pattern and the second source / drain pattern and the plurality of gate electrodes; as well as A second connection line, located in the interlayer dielectric layer, has a second width greater than the first width and is electrically connected to one or more of the first source / drain pattern and the second source / drain pattern. Wherein, the first connecting line and the second connecting line extend parallel to each other in the second direction, and The second connecting line includes: A first metal layer is located on the inner sidewall of the trench in the interlayer dielectric layer. A barrier layer, located on the bottom surface of the trench in the interlayer dielectric layer, wherein the bottom surface of the barrier layer is coplanar with the bottom surface of the first metal layer, and A second metal layer is located on top of the first metal layer and the barrier layer. The first connecting line and the first metal layer comprise ruthenium, and the second metal layer comprises copper.

15. The semiconductor device according to claim 14, wherein, The aspect ratio of the first connecting line is 1.5 to 3.5, and the aspect ratio of the second connecting line is 0.5 to 1.

5.

16. The semiconductor device according to claim 14, wherein, The barrier layer includes at least one of hafnium nitride, tungsten nitride, tungsten carbonitride, hafnium oxide, and tungsten oxide.

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