System and method for ups system bypass switch control

Abstract

Uninterruptible power supply system bypass switch control is disclosed. Systems and methods are provided that receive input power and provide output power to a load. In one example, a power system includes an input configured to be coupled to a power source and receive input power from the power source, an output configured to be coupled to a load and provide output power to the load, a bypass switch coupled to the input and the output and configured to selectively couple the input to the output to transfer the input power to the output as the output power, and a switch controller coupled to the bypass switch and including a communication interface, the switch controller configured to detect a link reset at the communication interface and, in response to detecting the link reset, control the bypass switch to be in a bypass operating state in which the bypass switch transfers the input power to the output as the output power.

Description

background Technical Field

[0002] At least one example according to this disclosure generally involves providing reliable power to a critical load.

[0003] Discussion of related technologies

[0004] Uninterruptible power supply (UPS) systems provide power to critical loads and include online UPS and offline UPS. Online UPS provides regulated alternating current (AC) power and backup AC power in the event of an interruption of the primary AC power source. Offline UPS typically does not provide regulation of the input AC power, but provides backup AC power in the event of a primary AC power outage. Overview

[0005] According to one aspect, a power system is provided, comprising: an input terminal configured to be coupled to and receive input power from a power source; an output terminal configured to be coupled to a load and provide output power to the load; a power conversion circuit coupled to the input terminal and the output terminal and configured to receive the input power and provide the output power; a bypass switch coupled to the input terminal and the output terminal and configured to selectively couple the input terminal to the output terminal to transfer the input power to the output terminal as output power; and a switch controller coupled to the bypass switch and including a communication interface, the switch controller being configured to detect a link reset at the communication interface and, in response to detecting a link reset, control the bypass switch to be in a bypass operation state, wherein the bypass switch transfers the input power to the output terminal as output power.

[0006] Some embodiments include a unit controller coupled to a power conversion circuit and including a communication interface coupled to a communication interface of a switching controller. The unit controller is configured to detect fault conditions and generate a link reset at the communication interface in response to detecting a fault condition. The unit controller may include watchdog logic configured to detect fault conditions by reaching a timeout threshold. In some examples, the timeout threshold may be approximately 500 microseconds or less. In some examples, the timeout threshold may be approximately 400 microseconds or less, and the link loss detection time may be less than approximately 100 microseconds.

[0007] In some embodiments, the switch controller may be further configured to acknowledge a link reset after an acknowledgment period and, in response to acknowledging the link reset, control the bypass switch to be in bypass operation. In some embodiments, the acknowledgment period may be approximately 500 microseconds or less.

[0008] In some embodiments, the switch controller includes a field-programmable gate array (FPGA), and the communication interface includes a physical layer interface circuit, which is coupled to the FPGA via a medium-independent interface.

[0009] According to another aspect, a power system is provided, comprising: an input terminal configured to be coupled to and receive input power from a power source; an output terminal configured to be coupled to a load and provide output power to the load; a bypass switch coupled to the input terminal and the output terminal and configured to selectively couple the input terminal to the output terminal to transfer the input power to the output terminal as output power; and a switch controller coupled to the bypass switch and including a communication interface, the switch controller being configured to detect a link reset at the communication interface and, in response to detecting a link reset, control the bypass switch to be in a bypass operation state, wherein the bypass switch transfers the input power to the output terminal as output power.

[0010] According to another aspect, a power system is provided, comprising: an input terminal configured to be coupled to and receive input power from a power source; an output terminal configured to be coupled to a load and provide output power to the load; a power conversion circuit coupled to the input terminal and the output terminal and configured to receive input power and provide output power; and a unit controller coupled to the power conversion circuit and configured with a communication interface, the unit controller being configured to detect fault conditions and generate a link reset condition at the communication interface in response to detecting fault conditions.

[0011] Some embodiments also include a bypass switch and a switch controller. The bypass switch is coupled to the input and output and configured to selectively couple the input to the output to deliver input power to the output as output power. The switch controller is coupled to the bypass switch and configured with a communication interface coupled to a communication interface of the unit controller. The switch controller is configured to detect a link reset condition at the communication interface and, in response to detecting the link reset condition, control the bypass switch to a bypass operation state, wherein the bypass switch delivers input power to the output as output power. The switch controller may also be configured to acknowledge the link reset condition after an acknowledgment period and, in response to acknowledging the link reset condition, control the bypass switch to a bypass operation state. In some embodiments, the acknowledgment period may be 400 microseconds or less. In some embodiments, the acknowledgment period may be approximately 500 microseconds or less.

[0012] According to various embodiments, the unit controller may include watchdog logic configured to detect fault conditions by reaching a timeout threshold, and in some examples, the timeout threshold may be 500 microseconds or less.

[0013] In some embodiments, the unit controller includes a field-programmable gate array (FPGA), and the communication interface includes a physical layer interface circuit, which is coupled to the FPGA via a medium-independent interface.

[0014] According to another aspect, a method for providing output power to a load is provided. The method includes: receiving input power from a power source; in a first operating mode, processing the input power through a power conversion circuit to provide output power to the load, the power conversion circuit being controlled by a unit controller; detecting a fault condition of at least one of the power conversion circuit or the unit controller; resetting a communication interface by the unit controller in response to detecting the fault condition; detecting the communication interface reset by a switch controller; and controlling a bypass switch by the switch controller in response to the communication interface reset to provide the input power to the load as output power in a second operating mode.

[0015] Some embodiments include monitoring events that occur at regular intervals by a unit controller, wherein detecting a fault condition includes detecting that the event failed to occur within a timeout threshold.

[0016] Some embodiments include a switch controller acknowledging the detection of a communication interface reset after an acknowledgment period, wherein a control bypass switch responds to the acknowledgment detection of the communication interface reset in a second operating mode.

[0017] According to various embodiments, the control bypass switch is configured in the second operating mode to occur substantially within one millisecond of the fault condition.

[0018] In some embodiments, resetting the communication interface includes controlling the physical layer circuitry.

[0019] In some embodiments, detecting a communication interface reset includes receiving an interrupt from the physical layer circuitry via a medium-independent interface.

[0020] According to another aspect, a high-speed communication system is provided for transmitting one or more conditions between two or more controllers. The system includes a first controller comprising a first communication interface having a first physical layer interface circuitry, the first controller being configured to detect a condition and generate a link reset at the first physical layer interface circuitry in response to detecting the condition. The system also includes a second controller operatively coupled to the first controller and comprising a second communication interface having a second physical layer interface circuitry, the second controller being configured to detect a link reset at the second physical layer interface circuitry and output a signal indicating condition detection in response to detecting a link reset.

[0021] In some embodiments, the second controller is further configured to acknowledge a link reset after an acknowledgment period and take corrective action in response to acknowledging the link reset. The acknowledgment period may be approximately 500 microseconds or less. The first controller may include watchdog logic configured to detect a condition by reaching a timeout threshold. The timeout threshold may be approximately 500 microseconds or less. The first controller includes a field-programmable gate array (FPGA), and physical layer interface circuitry is coupled to the FPGA via a media-independent interface.

[0022] Other aspects, embodiments, examples, and advantages of these exemplary aspects and embodiments are also discussed in detail below. The examples disclosed herein may be combined with other examples in any manner consistent with at least one of the principles disclosed herein, and references to “example,” “some examples,” “alternative examples,” “various examples,” “an example,” etc., are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described may be included in at least one example. The appearance of these terms herein does not necessarily refer to the same example. Attached Figure Description

[0023] Various aspects of at least one embodiment are discussed below with reference to the accompanying drawings, which are not intended to be drawn to scale. The drawings are included to provide illustration and further understanding of the various aspects and embodiments, and are incorporated in and form a part of this specification, but are not intended as a definition of limitation on the claimed systems and methods. In the drawings, each identical or substantially identical component shown in the various figures may be represented by similar or analogous numbers. For clarity, not every component may be labeled in every figure. In the figures:

[0024] Figure 1 This is a block diagram of an example uninterruptible power supply (UPS) system;

[0025] Figure 2 This is a block diagram of an example of a unit controller and a bypass switch controller, each interconnected in the UPS via a communication channel;

[0026] Figure 3 This is a flowchart of an example method for operating a UPS; and

[0027] Figure 4 This is an example block diagram of a computing component that can be configured to implement one or more aspects of this disclosure. Detailed description

[0028] The systems and methods discussed herein pertain to uninterruptible power supply (UPS) systems and methods that may include unit controllers controlling various power switching, conversion circuits, battery charging, etc., and bypass switches that allow power to be directly supplied to the load (e.g., by coupling power to the load and bypassing other circuitry) during a failure in any unit controller or other component. The UPS systems and methods described herein may include communication components based on an internal Ethernet network. The Ethernet communication components provide a controller area network and are controlled in a manner that allows for rapid detection of unit controller failures, enabling the bypass switch controller to function and close the bypass switch to continue supplying power to the load during fault conditions. Conventional systems and methods may not be able to use Ethernet-based communication as a controller area network because Ethernet connectivity may not be suitable for embedded real-time applications.

[0029] The examples of methods and systems discussed herein are not intended to limit their application to the details of the structure and arrangement of components set forth in the following description or shown in the accompanying drawings. The methods and systems can be implemented in other embodiments and can be practiced or performed in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. Specifically, the actions, components, elements, and features discussed in conjunction with any one or more examples are not intended to exclude similar actions in any other examples.

[0030] Furthermore, the wording and terminology used herein are for descriptive purposes and should not be considered restrictive. Any reference to examples, embodiments, components, elements, or actions of systems and methods mentioned herein in the singular may also include plural embodiments, and any reference to any embodiment, component, element, or action mentioned herein in the plural form may also include only the singular embodiments. Singular or plural references are not intended to limit the currently disclosed systems or methods, their components, actions, or elements. The use of “including,” “comprising,” “having,” “comprising,” “involving,” and variations thereof herein should include the items listed thereafter and their equivalents, as well as additional items. References to “or” are to be interpreted as inclusive, such that any term described using “or” may indicate any single, more than one, or all of the described terms. Additionally, in the event of any inconsistency in the use of terminology between this document and documents incorporated herein by reference, the terminology used in the incorporated documents shall supplement the terminology used in this document; in the case of irreconcilable inconsistencies, the terminology used in this document shall prevail.

[0031] Uninterruptible power supply (UPS) systems are typically used to provide regulated, uninterrupted power to sensitive and / or critical loads or any load that requires a reliable power source. Figure 1An example of an online UPS 100 according to aspects and embodiments disclosed herein is shown. The UPS 100 includes a converter 110 having an AC power input 120, a DC output 140, and (optionally) a DC input 130. The DC output 140 provides power to an inverter 150, which converts the DC power to AC power and provides AC power at an AC power output 160 to power a load 164. A unit controller 170 controls the operation of the converter 110, the inverter 150, and various other components. In various embodiments, one or more batteries and / or battery charging components may be included, and a power conditioning and control module (PCCM) may couple a DC source to the (optional) DC input 130.

[0032] Bypass switch 180 is included and can sometimes couple AC input 120 to AC output 160, bypassing converter 110 and inverter 150, to provide AC power from AC input 120 to AC output 160, for example, during periods of operational failure of converter 110, inverter 150, unit controller 170, or other components. Therefore, bypass switch 180 may include bypass switch controller (BSC) 182, which controls bypass switch 180 to be in an open-circuit condition or a closed-circuit condition at different times.

[0033] Unit controller 170 and bypass switch controller 182 can communicate with each other via a communication channel 184, which may be referred to as a controller area network (CAN). Communication channel 184 enables internal communication between the controllers (e.g., unit controller 170 and bypass switch controller 182). In conventional systems, the CAN can be, for example, a serial interface, such as an RS-485 / TIA-485 interface commonly referred to as a 485 bus, or a similar interface. However, the aspects and embodiments disclosed herein use packetized or datagram-oriented communication interfaces (e.g., Ethernet (e.g., IEEE 802.3) type interfaces) as communication channel 184 to enable communication between the controllers.

[0034] At least one challenge in providing such a communication interface for controller area communication includes meeting timing requirements for relaying faults in unit controller 170. For example, a fault in unit controller 170 may require a rapid response from bypass switch controller 182, such as by operating bypass switch 180 in a closed condition to resume power supply to AC output 160 quickly enough. In various embodiments, it may be desirable for bypass switch controller 182 to react in approximately 1 millisecond or less. In various embodiments, bypass switch controller 182 responds to a fault in unit controller 170 by closing bypass switch 180 within 800 to 1,200 microseconds (e.g., 0.8 to 1.2 milliseconds). The aspects and embodiments disclosed herein control and / or monitor standardized packet-oriented communication interfaces in a manner that allows for rapid detection of faults in unit controller 170 without requiring the transmission of proprietary protocols over the interface. Communication channel 184 can operate according to any of various standards (e.g., IEEE 802.3 or the like) and can utilize the operation described herein to provide rapid indication of a fault in unit controller 170.

[0035] Figure 2 An example of a subsystem 200 is shown, comprising a unit controller 170 and a bypass switch controller 182 communicating via a communication channel 184, which is an Ethernet-based communication channel. Each of the unit controller 170 and the bypass switch controller 182 may include a media-independent interface (MII) to a physical layer (PHY) chip 186, which may be a gigabit media-independent interface (GMII / RGMII) implementing a standardized physical layer interface, such as an Ethernet physical layer interface. In at least one embodiment, the PHY chip 186 may be a Marvell chip implementing an integrated 10 / 100 / 1000 Mbps Ethernet transceiver. ®The 88E1512P semiconductor chip. For example, each of the unit controller 170 and the bypass switch controller 182 may include an Ethernet Media Access Controller (EMAC) that communicates with the PHY chip 186 via a media-independent interface. In various embodiments, the PHY chip 186b and GMII may be considered part of the bypass switch controller 182 and cooperate with the EMAC to form a communication interface to the bypass switch controller. In various embodiments, the PHY chip 186a and GMII may be considered part of the unit controller 170 and cooperate with the EMAC to form a communication interface to the unit controller. In various embodiments, each of the unit controller 170 and the bypass switch controller 182 may include a Reduced Instruction Set Computing (RISC) based processor and may be an Advanced RISC Machine (ARM) processor that may be integrated with or within a Field Programmable Gate Array (FPGA), as shown. For example, in at least one embodiment, any one or both of the unit controller 170 and the switch bypass controller 182 may be an Altera system including an embedded ARM Cortex-A9MP core and FPGA programmable logic. ® (Intel) ® Cyclone ® V SoC. However, in various embodiments, different processors and / or processor architectures, including different hardware architectures and instruction sets, may be included and may be connected to or otherwise control the PHY chip in various ways.

[0036] For the example described herein, unit controller 170 can be monitored to find faults, and bypass switch controller 182 can detect such faults using the systems and methods described herein. However, various embodiments can use the systems or methods according to the aspects and embodiments described herein to monitor any system, processor, controller, etc., and detect such faults at any other system, processor, controller, etc., via communication channels that can otherwise operate according to various standards, even if such standards may not provide real-time or time-critical communication of fault messages, and even if such standards may not be suitable for time-critical or real-time embedded applications.

[0037] Continue to refer to Figure 2 According to the system and method disclosed herein, a fault in unit controller 170 can be “transmitted” to bypass switch controller 182 and detected by bypass switch controller 182 through a purposeful physical layer reset.

[0038] For example, unit controller 170 may include watchdog logic 172 encoded in an FPGA or equivalent circuit, and the ARM processor may run tasks that "feed" the watchdog logic 172 at regular intervals. For example, the processor may run a process that regularly provides instructions for regular operation, such as resetting the clock or timer of watchdog logic 172, and watchdog logic 172 may monitor that the clock has not exceeded a threshold. For example, if the clock is reset at regular intervals, for example, under normal operation of unit controller 170, the clock will not exceed the threshold, but if the processor malfunctions, the clock may exceed the threshold. When watchdog logic 172 detects that a timeout threshold has been met, watchdog logic 172 controls PHY chip 186a at 174 to reset communication link 184. For example, in at least one embodiment, the processor may run a task that updates watchdog logic 172 at a rate of 10 kHz (e.g., every 100 microseconds). Watchdog logic 172 monitors such operations, and if, for example, a timeout threshold of 500 microseconds has elapsed without being updated, watchdog logic 172 can reset PHY chip 186a to indicate to bypass switch controller 182 that a fault has occurred in unit controller 170.

[0039] On the other side of communication channel 184, bypass switch controller 182 may include FPGA logic dedicated to detecting reset conditions, such as link down conditions, supported by PHY chip 186b. In various embodiments, bypass switch controller 182 may be configured to program PHY chip 186b to detect and notify of link down events, such as providing interrupt 188 upon detection of a link loss. Receiving such interrupt 188 may be interpreted by bypass switch controller 182 as an indication of a fault at unit controller 170, and bypass switch controller 182 may close bypass switch 180 in response to interrupt 188. Thus, bypass switch 180 may be placed in a closed condition to bypass various other power components to continue supplying power to load 164 (see [link to relevant documentation]) during fault conditions. Figure 1 It provides AC power. For example, if watchdog logic 172 controls PHY chip 186a to reset upon a threshold timeout of, for example, 500 microseconds, bypass switch controller 182 can be notified of a fault at unit controller 170 within a response time of 1.0 millisecond.

[0040] In some embodiments, the bypass switch controller 182 can confirm that the received interrupt 188 is, for example, a fault notification rather than a temporary link loss, by subsequently checking the registers of the PHY chip 186b after a period of time. In some embodiments, the bypass switch controller 182 can set a hardware timer for a specific interval and can confirm with the PHY chip 186b that the link remains unavailable at the end of the interval. In such an embodiment, the bypass switch controller 182 can interpret a subsequent link failure event, in which the link remains unavailable for a certain time interval, as an indication that the unit controller 170 has failed. In response, the bypass switch controller 182 can close the bypass switch 180.

[0041] For example, in various embodiments, unit controller 170 may include watchdog logic that controls the PHY chip to reset the communication link if unit controller 170 fails to maintain normal operation by a timeout threshold period (e.g., as detected by resetting or "feeding" the watchdog logic at intervals). In some embodiments, the timeout threshold may be 500 microseconds or less. In various embodiments, bypass switch controller 182 may provide link loss interruption 188 by controlling the PHY chip to detect the reset of the communication link, and may interpret the reset of the communication link as a message that unit controller 170 has failed, and may close bypass switch 180 in response. In some embodiments, bypass switch controller 182 may confirm that interruption 188 is a link loss event based on PHY chip 186b, and may optionally set a hardware time to reconfirm the link loss event after the confirmation period. In some embodiments, the confirmation period may be 500 microseconds. In other embodiments, to account for the detection time of link loss by the PHY chip, the confirmation period may be less than 500 microseconds to achieve a 1-millisecond response time. For example, in one embodiment of auto-negotiation used to achieve a fast response time, the detection time for link loss can be 100 microseconds, and the acknowledgment period used is 400 microseconds.

[0042] Therefore, in some embodiments, a 1.0 ms response time can be achieved by combining a 500 microsecond timeout threshold period of unit controller 170 (e.g., before sending a fault message in the form of a link reset) with a 400 microsecond acknowledgment period of bypass switch controller 182 (e.g., before interpreting a link reset as a fault message). Furthermore, various embodiments may use various timeout threshold periods or similar periods associated with watchdog logic 172 and / or various acknowledgment periods associated with acknowledgment timers or similar timers to achieve other response times.

[0043] Figure 3An example method 300, which can be implemented by a unit controller 170 and a bypass switch controller 182 in a UPS, is shown. According to example method 300, the unit controller 170 includes a watchdog function that monitors (block 310) for faults by detecting whether a timeout threshold is met. If the timeout threshold is met, a fault is detected, and the watchdog function controls the PHY interface to reset (block 330). The bypass switch controller 182 can detect a physical layer reset (e.g., a link failure condition) (block 340), and in some embodiments, the physical layer reset can be interpreted as a fault notification, and the bypass switch 180 can be closed in response. In other embodiments, the bypass switch controller 182 can wait for an acknowledgment period (block 350) and acknowledge the physical layer reset when the acknowledgment period expires (block 360). If the physical layer reset is acknowledged, the bypass switch controller 182 interprets the acknowledged physical layer reset as a fault notification and closes the bypass switch 180 in response (block 370). In various embodiments, fault detection can be performed in different or additional ways. For example, in addition to or in place of the watchdog scheme, various hardware fault detection schemes can be combined to detect faults, and PHY reset can be triggered or caused by any of the various fault detection mechanisms, such as as a fault notification.

[0044] Figure 4 An example block diagram of computing components forming a computing system 400 is illustrated, which may be configured to implement one or more aspects disclosed herein. For example, controllers 170, 182, or the like may include the computing system 400, or the computing system 400 may be included in a UPS (e.g., UPS 100) to provide controller functionality, or to provide a management interface to an operator, or to communicate with other devices (e.g., a communication interface of a utility grid 124), and so on.

[0045] For example, computing system 400 may include a computing platform, such as a computing platform based on a general-purpose computing processor, a dedicated processor, or a microcontroller. Computing system 400 may include specially programmed dedicated hardware (e.g., application-specific integrated circuits (ASICs)) or more generally designed hardware (e.g., field-programmable gate arrays (FPGAs)) or a general-purpose processor or any combination thereof. Furthermore, various aspects of this disclosure may be implemented as specialized software executing on computing system 400.

[0046] The computing system 400 may include a processor / ASIC 406 connected to one or more memory devices 410 (e.g., disk drives, memory, flash memory, embedded or on-chip memory, or other devices for storing data). The memory 410 may be used to store programs and data during operation of the computing system 400. Components of the computing system 400 may be coupled by interconnect mechanisms 408, which may include one or more buses and / or networks. The interconnect mechanisms 408 enable communication, such as data and instructions, to be exchanged between components of the computing system 400. The computing system 400 may also include one or more input devices 404, which may include, for example, a keyboard, mouse, touchscreen, and interfaces for connecting such devices. The computing system 400 may also include one or more output devices 402, which may include, for example, a display, buzzer, alarm, or other audio indicator, light, or other visual indicator, and interfaces for such devices. Furthermore, in addition to or as an alternative to the interconnect mechanisms 408, the computing system 400 may also include one or more interfaces (not shown) that allow the computing system 400 to be connected to a communication network.

[0047] The computing system 400 may include a storage unit 412, which may include a computer-readable and / or writable non-volatile medium in which signals may be stored to provide a program to be executed by the processor / ASIC 406 or to provide information stored on or in the medium to be processed by the program. The medium may be, for example, a hard disk or flash memory or other non-volatile memory (including various types of programmable read-only memory (PROM)), and in some examples may include random access memory (RAM). In some embodiments, the processor may cause data to be read from the non-volatile medium into another memory 410, which allows the processor / ASIC 406 to access the information faster than the medium. The memory 410 may be a volatile random access memory, such as dynamic random access memory (DRAM) or static RAM. It may be located in the storage unit 412 or in the memory 410. The processor / ASIC 406 may manipulate the data in the memory 410 and copy the data to the storage device 412 after processing is complete. One or both of the memory 410 and storage device 412 may be integrated into the processor / ASIC 406.

[0048] The computing system 400 may include a computer platform programmable using a high-level computer programming language. The computing system 400 may also be implemented using specially programmed or dedicated hardware (such as an ASIC). The processor / ASIC 406 may execute a low-level operating system and may also execute a high-level operating system, which may be, for example, Windows, available from Microsoft; macOS, System X, or iOS, available from Apple; Solaris, available from Sun Microsystems; UNIX and / or LINUX, available from various sources; or Android, available from Google. Many other operating systems may be used, including bare-metal and / or virtual computing systems.

[0049] In some embodiments, the UPS has one or more controllers according to the aspects and embodiments disclosed herein, which may include a processor, which may be any of the above-described or other suitable processors (including FPGA and / or ASIC), and may run an instruction set or otherwise operate logically to implement control of the various components as discussed above.

[0050] Based on the aspects and embodiments disclosed herein, some embodiments of UPS methods and systems can provide single-phase or three-phase power and can receive input power in single-phase or three-phase form from any one or any combination of various power inputs. The embodiments disclosed herein can use multiple power sources, including energy storage, renewable energy, and non-renewable energy, to provide uninterrupted power to critical loads and / or the utility grid. In some embodiments, conventional and modern sources, as well as future energy sources, are adapted by various power conditioning and control modules (PCCMs).

[0051] In some embodiments, the converter (e.g., converter 110) may be or may include a power factor correction (PFC) circuit, and may aggregate power from one energy source at a time, or may controllably aggregate power from multiple energy sources, and may provide power to one or more energy outputs. Additionally, converter 110 may include a power interface capable of receiving and providing power; for example, AC input 120 may receive AC power input, but may also act as a power output when, for example, converter 110 converts excess renewable or stored energy to feed power back into the utility grid.

[0052] In various embodiments, the controller (e.g., the controller discussed above) can be a system control module (SCM), which is an intelligent power manager that selects which energy sources(s) to use at any given time to maintain power to the load and minimize energy costs. Such a controller can achieve energy arbitrage by utilizing energy storage devices during peak electricity rates and recharging them during off-peak rates. The UPS and controller discussed above can also sell excess renewable or battery power back to the utility via a bypass loop or a bidirectional front-end power converter (e.g., from AC input 120), which can also be controlled by the controller.

[0053] At least one embodiment discussed above uses an Ethernet-based communication system in a power device to provide high-speed detection of fault conditions. In other embodiments, the systems and methods described herein can be used in other types of high-speed communication systems and devices other than power devices. For example, in a system having a first controller and a second controller (each with a communication interface), a link reset of the communication channel between the first and second controllers can be used to transmit fault conditions, other alarms, and notifications about one or more conditions between the first and second controllers. Current systems typically do not provide high-speed communication systems for transmitting notifications about one or more conditions between two or more controllers. This is a technical problem. An exemplary embodiment of a high-speed communication system for transmitting one or more conditions between two or more controllers may include a first controller including a first communication interface having a first physical layer interface circuit, the first controller being configured to detect a condition and generate a link reset at the first physical layer interface circuit in response to detecting the condition. An exemplary embodiment may also include a second controller operatively coupled to the first controller and including a second communication interface having a second physical layer interface circuit, the second controller being configured to detect a link reset at the second physical layer interface circuit and output a signal indicating condition detection in response to detecting a link reset. The aforementioned combination of features includes a high-speed communication system architecture used as a technical solution to the aforementioned technical problems. This technical solution is not routine and is unconventional in the field of high-speed communication system design. This technical solution is a practical application of an exemplary high-speed communication system design that solves the aforementioned technical problems and constitutes an improvement in the technical field of high-speed communication system design, at least by facilitating faster data transmission between two controllers.

[0054] Having described several aspects of at least one embodiment of this disclosure, it should be appreciated that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the claimed systems and methods. Therefore, the foregoing description and drawings are merely by way of example.

Claims

1. A power system comprising: an input configured to be coupled to a power source and to receive input power from the power source; an output configured to be coupled to a load and to provide output power to the load; a power conversion circuit coupled to the input and the output and configured to receive the input power and to provide the output power; a bypass switch coupled to the input and the output and configured to selectively couple the input to the output to transfer the input power to the output as the output power; a switch controller coupled to the bypass switch and including a communication interface, the switch controller configured to detect a link reset at the communication interface and, in response to detecting the link reset, to control the bypass switch to be in a bypass operating state in which the bypass switch transfers the input power to the output as the output power; and a cell controller coupled to the power conversion circuit and including a communication interface coupled to the communication interface of the switch controller, the cell controller configured to detect a fault condition and, in response to detecting the fault condition, to generate the link reset at the communication interface. The cell controller includes watchdog logic configured to detect the fault condition by reaching a timeout threshold.

2. The power system of claim 1, wherein, The timeout threshold is about 400 microseconds or less, and a link loss detection time is less than about 100 microseconds.

3. The power system of claim 2, wherein, The switch controller is further configured to acknowledge the link reset after an acknowledgement period and, in response to acknowledging the link reset, to control the bypass switch to be in the bypass operating state.

4. The power system of claim 1, wherein, The acknowledgement period is about 500 microseconds or less.

5. The power system of claim 4, wherein, The switch controller includes a field programmable gate array, and the communication interface includes a physical layer interface circuit, and the physical layer interface circuit is coupled to the field programmable gate array through a media independent interface.

6. The power system of claim 1, wherein, 7. A power system comprising: an input configured to be coupled to a power source and to receive input power from the power source; an output configured to be coupled to a load and to provide output power to the load; a power conversion circuit coupled to the input and the output and configured to receive the input power and to provide the output power; a cell controller coupled to the power conversion circuit and including a communication interface, the cell controller configured to detect a fault condition and, in response to detecting the fault condition, to generate a link reset at the communication interface; a bypass switch coupled to the input and the output and configured to selectively couple the input to the output to transfer the input power to the output as the output power; and a switch controller coupled to the bypass switch and including a communication interface coupled to the communication interface of the cell controller, the switch controller configured to detect the link reset at the communication interface and, in response to detecting the link reset, to control the bypass switch to be in a bypass operating state. ​ ​ 8. The power system of claim 7, wherein, In the bypass operating state, the bypass switch passes the input power to the output terminal as the output power.

9. The power system of claim 8, wherein, The switch controller is further configured to acknowledge the link reset after an acknowledgement period, and to control the bypass switch to be in the bypass operating state in response to acknowledging the link reset.

10. The power system of claim 9, wherein, The acknowledgement period is about 500 microseconds or less.

11. The power system of claim 7, wherein, The unit controller includes watchdog logic configured to detect the fault condition by reaching a timeout threshold.

12. The power system of claim 11, wherein, The timeout threshold is about 500 microseconds or less.

13. The power system of claim 7, wherein, The unit controller includes a field programmable gate array, and the communication interface includes a physical layer interface circuit, and the physical layer interface circuit is coupled to the field programmable gate array through a media independent interface.

14. A high speed communication system for communicating one or more conditions between two or more controllers, comprising: a first controller including a first communication interface having a first physical layer interface circuit, the first controller configured to detect a condition, and to generate a link reset at the first physical layer interface circuit in response to detecting the condition; and a second controller operably coupled to the first controller and including a second communication interface having a second physical layer interface circuit, the second controller configured to detect the link reset at the second physical layer interface circuit, and to output a signal indicative of the detected condition in response to detecting the link reset.

15. The system of claim 14, wherein, The second controller is further configured to acknowledge the link reset after an acknowledgement period, and to take a corrective action in response to acknowledging the link reset.

16. The system of claim 15, wherein, The acknowledgement period is about 500 microseconds or less.

17. The system of claim 14, wherein, The first controller includes watchdog logic configured to detect the condition by reaching a timeout threshold.

18. The system of claim 17, wherein, The timeout threshold is about 500 microseconds or less.

19. The system of claim 14, wherein, The first controller includes a field programmable gate array, and the first physical layer interface circuit is coupled to the field programmable gate array through a media independent interface.

20. A method of providing output power to a load, the method comprising: receiving input power from a power source; in a first operating mode, processing the input power through a power conversion circuit to provide output power to the load, the power conversion circuit controlled by a unit controller, the unit controller including a communication interface having a physical layer interface circuit; detecting a fault condition of at least one of the power conversion circuit or the unit controller; resetting, by the unit controller, the physical layer interface circuit of the communication interface in response to detecting the fault condition; detecting, by a switch controller, a communication interface reset; and controlling, by the switch controller, a bypass switch in response to the communication interface reset to provide the input power to the load as the output power in a second operating mode.

21. The method of claim 20, further comprising monitoring, by the unit controller, for an event to occur at regular intervals, wherein detecting the fault condition includes detecting that the event fails to occur within a timeout threshold.

22. The method of claim 20, further comprising acknowledging detection of the communication interface reset by the switch controller after an acknowledgement period, wherein controlling the bypass switch in the second operating mode is responsive to the acknowledged detection of the communication interface reset.

23. The method of claim 22, wherein controlling the bypass switch in the second operating mode is configured to occur substantially within one millisecond of the fault condition.

24. The method of claim 20, wherein resetting the communication interface comprises controlling the physical layer interface circuit via a media independent interface.

25. The method of claim 20, wherein detecting the communication interface reset comprises receiving an interrupt from the physical layer interface circuit via a media independent interface.

26. A non-transitory computer-readable storage medium storing instructions that, when executed by at least one computer processor, cause the at least one computer processor to perform the method of any of claims 20-25.

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