A / D conversion device

Abstract

The present invention discloses an A / D conversion device (6; 306; 406; 506; 606), which operates in a mode including at least one of a ΔΣ mode, a cyclic mode, and a hybrid mode. The A / D conversion device includes: a first block (14) that processes an analog input signal (Vin) through a first amplifier (24); a second block (15) including a second amplifier (24b); a quantization unit (13; 213) that quantizes one of the outputs of the first block and the second block; and a control circuit (9) that switches the mode to perform control corresponding to the mode.

Description

Technical Field

[0001] The present disclosure relates to analog-to-digital (A / D) conversion devices. Background Art

[0002] The present applicant has proposed a technique for performing A / D conversion processing using a hybrid mode in which a ΔΣ method and a cyclic method are combined (for example, see Patent Document 1). According to the A / D conversion device described in Patent Document 1, in the hybrid mode, A / D conversion processing is performed by the ΔΣ method to generate high-order bits, and then A / D conversion is performed on the remaining part by the cyclic method to generate low-order bits. In the hybrid mode, the A / D conversion device uses operational amplifiers (equal to amplifiers) configured in each of a first block and a second block for both the ΔΣ method and the cyclic method to implement A / D conversion processing.

[0003] In the hybrid mode, gain error degrades linearity, so a high-gain amplifier is required to minimize the gain error. When applying the A / D conversion device disclosed in Patent Document 1, it is necessary to prepare high-gain operational amplifiers of the same size for the first block and the second block. In addition, when using high-gain operational amplifiers for the first block and the second block, the current consumption of each amplifier increases, which is not desirable.

[0004] [Patent Document 1] JP-2017-163473-A Summary of the Invention

[0005] An object of the present disclosure is to provide an A / D conversion device capable of reducing power consumption while reducing the configuration area.

[0006] The present disclosure relates to an A / D conversion device (6; 306; 406; 506; 606) that operates in at least two or more modes, the two modes being: a ΔΣ mode in which an analog input signal (Vin) is subjected to A / D conversion processing by the ΔΣ method; and a hybrid mode in which an analog input signal (Vin) is subjected to A / D conversion processing by the ΔΣ method, and then A / D conversion processing is performed on the remaining part by the cyclic method.

[0007] According to the present disclosure, a first block (14) is configured to receive an input of an analog input signal (Vin) and be able to process the signal by using a first amplifier (24), and a second block (15) includes a second amplifier (24b) and receives an input of the output voltage of the first block. A quantization unit (13; 213) is configured to receive an input of one of the outputs of the first block and the second block and be able to quantize the output. A control circuit (9) implements control for switching between the above modes.

[0008] In the ΔΣ mode, the control circuit controls the switches such that the quantization unit quantizes the output by using the first amplifier of the first block and the second amplifier of the second block, and the output of the second block is subjected to A / D conversion processing by the ΔΣ method. On the other hand, in the hybrid mode, the control circuit controls the switches such that the output of the first amplifier of the first block is subjected to A / D conversion processing by using the first amplifier of the first block without using the second amplifier of the second block, while the quantization unit quantizes the output by the ΔΣ method, and then the remaining part is subjected to A / D conversion processing by the cyclic method by using the first amplifier.

[0009] The present disclosure relates to an A / D conversion device (6; 306; 406; 506; 606) that operates in at least two or more modes, the two modes being: a ΔΣ mode in which an analog input signal (Vin) is subjected to A / D conversion processing by the ΔΣ method; and a cyclic mode in which the analog input signal (Vin) is subjected to A / D conversion processing by the cyclic method.

[0010] According to the present disclosure, in the ΔΣ mode, the control circuit controls the switches such that the output of the second block is subjected to A / D conversion processing by the ΔΣ method by using the first amplifier of the first block and the second amplifier of the second block, while the quantization unit quantizes the output. In the cyclic mode, the control circuit controls the switches such that the output of the first amplifier of the first block is subjected to A / D conversion processing by the cyclic method by using the first amplifier of the first block without using the second amplifier of the second block, while the quantization unit quantizes the output.

[0011] The present disclosure relates to an A / D conversion device (6; 306; 406; 506; 606) that operates in any one of a ΔΣ mode, a cyclic mode, and a hybrid mode. In the ΔΣ mode, an analog input signal (Vin) is subjected to A / D conversion processing by the ΔΣ method; in the cyclic mode, the analog input signal (Vin) is subjected to A / D conversion processing by the cyclic method; in the hybrid mode, the analog input signal (Vin) is subjected to A / D conversion processing by the ΔΣ method, and then the remaining part is subjected to A / D conversion processing by the cyclic method.

[0012] According to the present disclosure, in the ΔΣ mode, the control circuit controls the switches such that, by using the first amplifier of the first block and the second amplifier of the second block, A / D conversion processing of the output of the second block is performed by the ΔΣ method while the quantization unit quantizes the output. In the hybrid mode, the control circuit controls the switches such that A / D conversion processing of the output of the first amplifier of the first block is performed by using the first amplifier of the first block without using the second amplifier of the second block, while the quantization unit quantizes the output by the ΔΣ method, and then A / D conversion processing of the residual part is performed by the cyclic method by using the first amplifier. In the cyclic mode, the control circuit controls the switches such that A / D conversion processing of the output of the first amplifier of the first block is performed by the cyclic method by using the first amplifier of the first block without using the second amplifier of the second block, while the quantization unit quantizes the output.

[0013] According to the present disclosure, in the ΔΣ mode, by using the first amplifier of the first block and the second amplifier of the second block, second-order modulation characteristics are provided and the effect of noise shaping can be increased, so that the A / D conversion accuracy can be maintained with high precision. On the other hand, in modes other than the ΔΣ mode (hybrid mode and cyclic mode), operations can be performed by using only the first amplifier of the first block, thus eliminating the need to employ a high-gain amplifier for the second amplifier of the second block. As a result, the configuration area for the second amplifier can be reduced. In addition, current consumption can be reduced. Generally, the ΔΣ mode is characterized by high precision, and the hybrid mode and the cyclic mode are characterized by high speed, so that the modes can be selectively used according to the user's requirements.

[0014] According to the present disclosure, the block (414) receives an input of an analog input signal (Vin) and is capable of processing the signal by using an amplifier, and the quantization unit (13) quantizes the output. The control circuit (9) switches the mode and controls the switches to perform control corresponding to the mode. The first sampling capacitor (Cs1) is connected to be able to sample the analog input signal, and the first capacitor (Csd1) is connected to be able to sample the analog input signal.

[0015] The second sampling capacitor (Cs2) is connected to be able to sample the output voltage of the block. The first capacitor switching circuit (20) is capable of charging / discharging the first capacitor (Csd1) constituting the first digital-to-analog (D / A) converter (25), and the second capacitor switching circuit (420b) is capable of charging / discharging the second capacitor (Csd2) constituting the second D / A converter (25b).

[0016] In the ΔΣ mode, the control circuit performs a first ΔΣ operation by executing switch control so as to cause a first capacitor to sample an analog input signal by using an amplifier of the block. The control circuit performs a second ΔΣ operation by executing switch control so as to charge or discharge the first capacitor of the first D / A converter according to the digital output of the quantization unit and input an output voltage integrated by using the amplifier, while causing a second sampling capacitor to sample the output voltage. The control circuit performs a third ΔΣ operation by executing switch control so as to charge or discharge the second capacitor of the second D / A converter and the second sampling capacitor according to the digital output of the quantization unit and input an output voltage integrated by using the amplifier to the quantization unit.

[0017] After that, the control circuit repeats the second ΔΣ operation and the third ΔΣ operation to perform an A / D conversion process on the output voltage integrated by using the amplifier of the block by the ΔΣ method, while causing the quantization unit to quantize the output voltage.

[0018] According to the present disclosure, in the hybrid mode, the control circuit performs a fourth ΔΣ operation by executing switch control so as to sample an analog input signal in a first sampling capacitor by using an amplifier of the block. The control circuit performs a fifth ΔΣ operation by executing switch control so as to charge or discharge the first capacitor of the first D / A converter and the first sampling capacitor according to the digital output of the quantization unit and input an output voltage integrated by using the amplifier to the quantization unit. After that, the control circuit repeats the fourth ΔΣ operation and the fifth ΔΣ operation to perform an A / D conversion process on the output voltage of the amplifier of the block by the ΔΣ method, while causing the quantization unit to quantize the output voltage and performing an A / D conversion process on the residual part by the cyclic method.

[0019] According to the present disclosure, in the cyclic mode, the control circuit performs an A / D conversion process on the output voltage integrated by using an amplifier of the block by the cyclic method, while causing the quantization unit to quantize the output voltage.

[0020] According to the present disclosure, in all modes including the ΔΣ mode, operations can be performed by using an amplifier of a single block, thus eliminating the need to provide a second block that is conventionally required. As a result, the configuration area for the second block can be reduced. In addition, current consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the reference drawings. In the drawings:

[0022] Figure 1 is an electrical configuration diagram of an A / D conversion device in a first embodiment;

[0023] Figure 2is an explanatory diagram schematically showing the processing flow for one cycle in the ΔΣ mode;

[0024] Figure 3 is an explanatory diagram schematically showing one operation stage (part 1) in the ΔΣ mode;

[0025] Figure 4 is an explanatory diagram schematically showing one operation stage (part 2) in the ΔΣ mode;

[0026] Figure 5 is an explanatory diagram schematically showing one operation stage (part 3) in the ΔΣ mode;

[0027] Figure 6 is an explanatory diagram schematically showing the processing flow for one cycle in the hybrid mode;

[0028] Figure 7 is an explanatory diagram schematically showing one operation stage (part 1) in the hybrid mode;

[0029] Figure 8 is an explanatory diagram schematically showing one operation stage (part 2) in the hybrid mode;

[0030] Figure 9 is an explanatory diagram schematically showing one operation stage (part 3) in the hybrid mode;

[0031] Figure 10 is an explanatory diagram schematically showing one operation stage (part 4) in the hybrid mode;

[0032] Figure 11 is an explanatory diagram schematically showing one operation stage (part 5) in the hybrid mode;

[0033] Figure 12 is an explanatory diagram schematically showing one operation stage (part 6) in the hybrid mode;

[0034] Figure 13 is an explanatory diagram schematically showing the processing flow for one cycle in the loop mode;

[0035] Figure 14 is an explanatory diagram schematically showing one operation stage (part 1) in the loop mode;

[0036] Figure 15 is an explanatory diagram schematically showing one operation stage (part 2) in the loop mode;

[0037] Figure 16 is an electrical configuration diagram showing the quantization unit of the second embodiment;

[0038] Figure 17 is an electrical configuration diagram showing the A / D conversion device of the third embodiment;

[0039] Figure 18 is an electrical configuration diagram inside the amplifier;

[0040] Figure 19 is an electrical configuration diagram showing the A / D conversion device of the fourth embodiment and an explanatory diagram schematically showing one operation stage (part 1) in the ΔΣ mode;

[0041] Figure 20 is an explanatory diagram schematically showing one operation stage (part 2) in the ΔΣ mode;

[0042] Figure 21 is an explanatory diagram schematically showing one operation stage (part 3) in the ΔΣ mode;

[0043] Figure 22 is an explanatory diagram schematically showing one operation stage (part 1) in the hybrid mode;

[0044] Figure 23 is an explanatory diagram schematically showing one operation stage (part 2) in the hybrid mode;

[0045] Figure 24 is an electrical configuration diagram showing the A / D conversion device of the fifth embodiment and an explanatory diagram schematically showing one operation stage (part 1) in the hybrid mode;

[0046] Figure 25 is an explanatory diagram schematically showing one operation stage (part 2) in the hybrid mode;

[0047] Figure 26 is an explanatory diagram schematically showing one operation stage (part 3) in the hybrid mode;

[0048] Figure 27 is an electrical configuration diagram showing the A / D conversion device of the sixth embodiment and an explanatory diagram schematically showing one operation stage (part 1) in the hybrid mode; and

[0049] Figure 28 is an explanatory diagram schematically showing one operation stage (part 2) in the hybrid mode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] Hereinafter, some embodiments of the A / D conversion device will be described with reference to the drawings. In each of the following embodiments, the same or similar reference numerals are used to indicate the same or similar configurations, and the description thereof will be omitted if necessary.

[0051] First Embodiment

[0052] Figure 1 The A / D conversion device 6 shown therein performs A / D conversion processing on the analog input signal Vin, and is configured to operate in the ΔΣ mode, the cyclic mode, and the hybrid mode. In the ΔΣ mode, A / D conversion processing is performed on the analog input signal Vin by the ΔΣ method. In the cyclic mode, A / D conversion processing is performed on the analog input signal Vin by the cyclic method. And in the hybrid mode, A / D conversion processing is performed on the analog input signal Vin by the ΔΣ method to generate high-order bits, and then A / D conversion processing is performed on the remaining part by the cyclic method. The control circuit 9 switches the mode and controls the switch to perform control corresponding to each mode. The detailed operations of these modes will be described later.

[0053] The switch 7 is configured to be switched according to the control signal of the control circuit 9. When operating the A / D conversion device 6 in the ΔΣ mode, the control circuit 9 switches the switch 7 to connect the A / D conversion device 6 and the digital filter 8, thereby taking the output of the digital filter 8 as the output data Do.

[0054] When the control circuit 9 operates the A / D conversion device 6 in the cyclic mode or the hybrid mode, the switch 7 is switched to be connected according to the output of the A / D conversion device 6 without inserting the digital filter 8, thereby taking the output as the output data Do. Hereinafter, the configuration of the A / D conversion device 6 and the operations in the ΔΣ mode, the cyclic mode, and the hybrid mode will be described. The A / D conversion device 6 uses a digital integrator to perform processing in the hybrid mode. The digital integrator is used when combining the high-order bits generated by the A / D conversion processing in the ΔΣ method and the low-order bits generated by the A / D conversion processing in the cyclic method. Although the digital integrator is also classified as a digital filter, since the digital integrator is a function required for the combined processing of high-order bits and low-order bits, the digital integrator will be described independently of the digital filter 8 whose filter characteristics may become any.

[0055] <Configuration of the A / D conversion device 6>

[0056] As Figure 1 shown, the A / D conversion device 6 includes a signal processing unit 12 and a quantization unit 13. The signal processing unit 12 includes a first block 14 and a second block 15. The analog input signal Vin is input to the input terminal Tis of the first block 14.

[0057] The first block 14 includes capacitor switching circuits 20, 21, 22, 23 and an operational amplifier 24 as a first amplifier. The non-inverting input terminal of the operational amplifier 24 is connected to an analog ground line to which a ground potential is applied. The non-inverting input terminal of the operational amplifier 24 is connected to a common output node Na of the capacitor switching circuits 20, 21, 22. The output voltage Vo1 of the operational amplifier 24 is input to an input node Nb of the second block 15.

[0058] The capacitor switching circuit 20 includes a capacitor Cs1, switches SS11 to SS14, SSD11, and a digital-to-analog (D / A) converter 25. The capacitor Cs1 is used as a sampling capacitor for sampling an analog input signal Vin input from an input terminal Tis. The capacitor Cs1 is charged or discharged in response to switches SS11 to SS14 that are turned on or off by a control circuit 9. One terminal of the capacitor Cs1 is connected to the input terminal Tis via the switch SS11 and to the analog ground line via the switch SS14. The other terminal of the capacitor Cs1 is connected to the node Na via the switch SS13 and to the analog ground line via the switch SS12.

[0059] The D / A converter 25 includes a plurality of switches SDD1T, SDD1M, SDD1B and a capacitor Csd1. The capacitor Csd1 is used as a D / A converter (DAC) capacitor of the D / A converter 25. The switch SSD11 is connected between an input terminal Tis and the other terminal of the capacitor Csd1. The switch SSD11 is a switch that is controlled when the capacitor Csd1 is used as a sampling capacitor and can be turned on / off by the control circuit 9. The capacitor Csd1 can also serve as a sampling capacitor configured to sample the analog input signal Vin input from the input terminal Tis through the switch SSD11.

[0060] The control circuit 9 selectively turns on the switches SDD1T, SDD1M, SDD1B to apply any one of the converted outputs Vrefp, Vcm, Vrefm of the quantization unit 13 to the other terminal of the capacitor Csd1. The converted outputs Vrefp, Vcm, Vrefm of the quantization unit 13 are equivalent to analog voltages obtained by performing a D / A conversion process on the output digital values of the quantization unit 13 and, for example, have a relationship Vrefp > Vcm > Vrefm, where Vcm is an analog ground voltage. Hereinafter, the selected converted output will be abbreviated as VR when necessary.

[0061] The capacitor switching circuit 21 includes a capacitor Ccc1, switches SC11, SC14, SCD11 to SCD13, and a D / A converter 26. The capacitor Ccc1 is configured to be charged or discharged in response to the switches SC11, SC14, SCD12, SCD13 that are all turned on or off by the control circuit 9. One terminal of the capacitor Ccc1 is connected to the node Na via the switch SCD13 and to the analog ground via the switch SCD12. The other terminal of the capacitor Ccc1 is connected to the node Nb via the switch SC11 and to the analog ground via the switch SC14.

[0062] The D / A converter 26 includes a plurality of switches SCD1T, SCD1M, SCD1B and a capacitor Ccd1. The control circuit 9 selectively turns on the switches SCD1T, SCD1M, SCD1B to apply any one of the converted outputs Vrefp, Vcm, Vrefm of the quantization unit 13 to the other terminal of the capacitor Ccd1. The switch SCD11 is connected between the output node Nb of the first block 14 and the other terminal of the capacitor Ccd1. The switches SC11, SCD11 are the switches used when sampling the voltage of the output node Nb to the capacitors Ccc1, Ccd1 by the cyclic method, and the switches SC11, SCD11 are configured to be controlled to be turned on / off by the control circuit 9.

[0063] The capacitor switching circuit 22 includes a capacitor Ccc2, switches SC21, SC24, SCD21 to SCD23, and a D / A converter 27. The capacitor Ccc2 is configured to be charged or discharged in response to the switches SC21, SC24, SCD22, SCD23 that are all turned on or off by the control circuit 9. One terminal of the capacitor Ccc2 is connected to the node Na via the switch SCD23 and to the analog ground via the switch SCD22. The other terminal of the capacitor Ccc2 is connected to the node Nb via the switch SC21 and to the analog ground via the switch SC24.

[0064] The D / A converter 27 includes a plurality of switches SCD2T, SCD2M, SCD2B and a capacitor Ccd2. The control circuit 9 selectively turns on the switches SCD2T, SCD2M, SCD2B to apply any one of the converted outputs Vrefp, Vcm, Vrefm of the quantization unit 13 to the other terminal of the capacitor Ccd2. The switch SCD21 is connected between the output node Nb of the first block 14 and the other terminal of the capacitor Ccd2. The switches SC21, SCD21 are the switches used when sampling the voltage of the output node Nb to the capacitors Ccc2, Ccd2 by the cyclic method, and the switches SC21, SCD21 are configured to be controlled to be turned on / off by the control circuit 9.

[0065] The capacitor switching circuit 23 includes switches SF11, SF14 to SF18, SA12, and capacitors Cf11, Cf12. The capacitors Cf11, Cf12 are configured as feedback capacitors between the input node Na and the output node Nb of the operational amplifier 24. One terminal of the capacitor Cf11 is connected to the node Na and connected to the analog ground via the switch SA12. The other terminal of the capacitor Cf11 is connected to the node Nb via the switch SF11 and connected to the analog ground via the switch SF14.

[0066] One terminal of the capacitor Cf12 is connected to the node Na via the switch SF17 and connected to the analog ground via the switch SF16. The other terminal of the capacitor Cf12 is connected to the node Nb via the switch SF15 and connected to the analog ground via the switch SF18.

[0067] The second block 15 is connected in cascade after the first block 14. The second block 15 includes capacitor switching circuits 20b, 23b, and an operational amplifier 24b as a second amplifier. The non-inverting input terminal of the operational amplifier 24b is connected to the analog ground. The inverting input terminal of the operational amplifier 24b is connected to the output node Na2 of the capacitor switching circuit 20b.

[0068] The capacitor switching circuit 20b includes a capacitor Cs2, switches SS21 to SS24, and a D / A converter 25b. The capacitor Cs2 serves as a sampling capacitor configured to sample the output voltage Vo1 input from the output node Nb of the first block 14 through the switch SS21. The capacitor Cs2 is charged or discharged in response to the switches SS21 to SS24 that are all turned on or off by the control circuit 9.

[0069] One terminal of the capacitor Cs2 is connected to the node Nb via the switch SS21 and connected to the analog ground via the switch SS24. The other terminal of the capacitor Cs2 is connected to the node Na2 via the switch SS23 and connected to the analog ground via the switch SS22.

[0070] The D / A converter 25b includes a plurality of switches SDD2T, SDD2M, SDD2B, and a capacitor Csd2. The control circuit 9 selectively turns on the switches SDD2T, SDD2M, SDD2B to apply any one of the converted outputs Vrefp, Vcm, Vrefm of the quantization unit 13 to the other terminal of the capacitor Csd2.

[0071] The capacitor switching circuit 23b includes switches SF21, SF24, SA21, and a capacitor Cf21. The capacitor Cf21 is configured as a feedback capacitor between the input node Na2 and the output node Nb2 of the operational amplifier 24b. One terminal of the capacitor Cf21 is connected to the node Na2 and is connected to the analog ground via the switch SA22. The other terminal of the capacitor Cf21 is connected to the node Nb2 via the switch SF21 and is connected to the analog ground via the switch SF24.

[0072] The switch SCMP1 is connected between the output node Nb of the first block 14 and the input node of the quantization unit 13. The switch SCMP2 is connected between the output node Nb2 of the second block 15 and the input node of the quantization unit 13. The control circuit 9 can selectively input the output voltage Vo1 of the first block 14 or the output voltage Vo2 of the second block 15 to the quantization unit 13 by selectively turning on the switches SCMP1 and SCMP2. The quantization unit 13 is composed of an A / D converter and can quantize the output voltage Vo1 of the first block 14 or the output voltage Vo2 of the second block 15. The quantization unit 13 generates a quantization value Qo as a three-level (1.5-bit) digital output and outputs the quantization value Qo to the control circuit 9.

[0073] <Operation description in each mode>

[0074] Hereinafter, the operations of the first block 14 and the second block 15 in the ΔΣ mode, the cyclic mode, and the hybrid mode will be described. In the following description of the operations, the switches that will be controlled to be turned on by the control circuit 9 in each mode will be described, and the description of the switches that will be controlled to be turned off will be omitted if necessary.

[0075] (1) ΔΣ mode

[0076] In Figure 2 the ΔΣ mode shown in the cycle diagram in, the A / D conversion device 6 performs a so-called oversampling type A / D conversion process. In Figure 2 ,"Reset", "Sample", and "Hold" respectively represent the timings for performing the reset operation, the ΔΣ sampling operation, and the ΔΣ hold operation. The first block 14 and the second block 15 simultaneously and parallelly perform the reset operation, the ΔΣ sampling operation, and the ΔΣ hold operation. The first block 14 and the second block 15 perform the reset operation in step S1, the ΔΣ sampling operation in step S2, and then the ΔΣ hold operation in step S3.

[0077] Then, as shown in steps S4, S5, …, Sn-1, Sn, the ΔΣ sampling operation and the ΔΣ holding operation are repeated. At this time, in the A / D conversion device 6, the quantization unit 13 continues to output digitally while performing oversampling of these operations a predetermined number of times to perform A / D conversion processing, and the digital filter 8 performs low-pass filtering on the output of the quantization unit 13 to generate output data Do.

[0078] <Reset operation>

[0079] As Figure 3 shown, the control circuit 9 turns on the switches SS14, SS12, SDD1M, SC14, SCD12, SCD1M, SC24, SCD22, SCD2M, SA12, SF14, SF16, SF18 to discharge the charges stored in the capacitors Cs1, Csd1, Ccc1, Ccd1, Ccc2, Ccd2, Cf11, Cf12 to the analog ground, thereby resetting the first block 14. The control circuit 9 turns on the switches SS22, SS24, SDD2M, SA22, SF24 to discharge the charges stored in the capacitors Cs2, Csd2, Cf21 to the analog ground, thereby resetting the second block 15. The control circuit 9 performs a reset process on the digital filter 8 before setting the ΔΣ mode.

[0080] <ΔΣ sampling operation in the ΔΣ mode>

[0081] As Figure 4 shown, the control circuit 9 turns on the switches SSD11, SS12, SS14, SCD1M, SCD12, SC14, SCD2M, SCD22, SC24, SF11, SF15, SF17 of the first block 14. At this time, the control circuit 9 turns on the switches SSD11, SS12, SS14 of the first block 14 so that the capacitor Csd1 samples the analog input signal Vin. The control circuit 9 turns on the switches SF11, SF15, SF17, whereby the capacitors Cf11, Cf12 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 24.

[0082] The control circuit 9 turns on the switches SS21, SS22, SDD2M, SF21 of the second block 15 to input the output voltage Vo1 of the output node Nb of the first block 14 to the other terminal of the capacitor Cs1. At this time, the capacitor Cs2 samples the output voltage Vo1 of the first block 14.

[0083] On the other hand, when the control circuit 9 turns on the switch SF21, the capacitor Cf21 is connected between the input node Na2 and the output node Nb2 of the operational amplifier 24b. Therefore, the second block 15 can output a voltage corresponding to the charge stored in the capacitor Cf21 from the node Nb2. In addition, the control circuit 9 turns on the switch SCMP2 to connect the output node Nb2 of the second block 15 to the quantization unit 13. Therefore, the quantization unit 13 quantizes the output voltage Vo2 of the second block 15 and digitally outputs the quantized voltage to the control circuit 9. The control circuit 9 selects the converted output VR for the subsequent ΔΣ hold operation.

[0084] <ΔΣ Hold Operation in ΔΣ Mode>

[0085] As Figure 5 shown, the control circuit 9 turns on the switches SS14, SS13, SCD1M, SCD12, SC14, SCD2M, SCD22, SC24, SF11, SF15, SF17 of the first block 14. At this time, when the control circuit 9 turns on the switch SS13, one end of the capacitors Cs1 and Csd1 can be connected to the inverting input terminal of the operational amplifier 24. In addition, when the control circuit 9 turns on the switches SF11, SF15, SF17, the capacitors Cf11 and Cf12 can be connected in parallel to the input / output terminal of the operational amplifier 24.

[0086] In addition, the control circuit 9 turns on the switch (assumed to be SDD1T here) corresponding to the converted output VR. During the above <ΔΣ sampling operation>, charge is stored in the capacitor Csd1, but during the above <ΔΣ hold operation>, the residual charge obtained by subtracting the charge corresponding to the converted output VR of the quantization unit 13 from the stored charge in the capacitor Csd1 and fed back is transferred to each of the capacitors Cf11 and Cf12. Thus, the residual charge is stored in the capacitors Cf11 and Cf12, and the integrator 24a outputs an integration voltage corresponding to the charge stored in the capacitors Cf11 and Cf12 from the node Nb.

[0087] On the other hand, the control circuit 9 turns on switches SS23, SS24, SF21, and the switch (here, assumed to be SDD2T) of the D / A converter 25b corresponding to the converted output VR in the second block 15. During the above <ΔΣ sampling operation>, charges are stored in the capacitor Cs2, but during the <ΔΣ hold operation>, the residual charges obtained by subtracting the charges corresponding to the converted output VR of the quantization unit 13 from the stored charges in the capacitor Cs2 and then fed back are transferred to the capacitor Cf21. Thus, the residual charges are stored in the capacitor Cf21, and the operational amplifier 24b outputs an integration voltage corresponding to the stored charges in the capacitor Cf21 obtained by the integrator 24ba from the node Nb2.

[0088] As Figure 2 shown, the first block 14 and the second block 15 alternately and repeatedly perform the above <ΔΣ sampling operation> and <ΔΣ hold operation> a predetermined number of times simultaneously. In the ΔΣ mode, the first block 14 and the second block 15 are in the same operating state at the same timing. When the control circuit 9 of the A / D conversion device 6 oversamples these operations, the quantization unit 13 continues to output values, and the digital filter 18 performs low-pass filtering on the output values of the quantization unit 13 to generate the output data Do.

[0089] In this way, in the ΔΣ mode, the operational amplifier 24 of the first block 14 and the operational amplifier 24b of the second block 15 perform A / D conversion processing by the ΔΣ method, while the output of the second block 15 is quantized by the quantization unit 13, so that the A / D conversion has a second-order modulation characteristic and the influence of noise shaping becomes larger, enabling A / D conversion with high precision.

[0090] As Figures 3 to 5 shown, in the ΔΣ mode, the control circuit 9 keeps the switches SCD12, SCD1M, SC14, SCD22, SCD2M, SC24 of the first block 14 turned on. Therefore, the voltages across the capacitors Ccc1, Ccd1, Ccc2, Ccd2 are kept at zero.

[0091] (2) Hybrid mode

[0092] Figure 6 shows the cycle diagram of the hybrid mode, and Figure 6 "Reset", "Sample", "Hold", and "Amp" in

[0093] As Figure 6As shown, in the hybrid mode, the A / D conversion device 6 performs A / D conversion processing on the analog input signal Vin by the ΔΣ method using the operational amplifier 24b of the first block 14 and not using the second block 15, and then performs A / D conversion processing on the residual signal by the cyclic method. In the hybrid mode, the A / D conversion device 6 performs A / D conversion processing by the ΔΣ method and then performs amplification processing before performing A / D conversion processing by the cyclic method, but this is not restrictive.

[0094] <Reset operation in hybrid mode>

[0095] First, in S21, the control circuit 9 resets the first block 14 and the second block 15 simultaneously. The processing operation at this time is the same as the reset operation in the ΔΣ mode, and thus its description will be omitted. After that, the A / D conversion device 6 alternately repeats the ΔΣ sampling operation and the ΔΣ holding operation of the ΔΣ method a predetermined number of times (for example, dozens of times) using only the first block 14. Refer to Figure 6 S22 to S25 in

[0096] <ΔΣ sampling operation in hybrid mode>

[0097] As Figure 7 shown, the control circuit 9 turns on the switches SDD1M, SS11, SS12 of the first block 14, thereby causing the capacitor Cs1 to sample the analog input signal Vin. At the same time, the control circuit 9 turns on the switches SF11, SF15, SF17, so that the capacitors Cf11, Cf12 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 24.

[0098] The control circuit 9 turns on the switch SCMP1 to connect the output node Nb of the first block 14 to the quantization unit 13. Therefore, the quantization unit 13 quantizes the output voltage Vo1 of the first block 14 and digitally outputs the output voltage Vo1 to the control circuit 9, and the control circuit 9 selects the converted output VR for the subsequent ΔΣ holding operation.

[0099] On the other hand, the control circuit 9 turns on the switches SS22, SS24, SDD2M, SF21 of the second block 15 to set the two end potentials of the capacitors Cs2, Csd2 to the ground level, and makes the second amplifier formed by the operational amplifier 24 enter the feedback state, thereby enabling the second block 15 to enter the non-operating state.

[0100] <ΔΣ holding operation in hybrid mode>

[0101] As Figure 8As shown, the control circuit 9 turns on the switches SS14, SS13 of the first block 14 and the switch (here, assumed to be SDD1T) of the D / A converter 25 corresponding to the converted output VR to connect one end of the capacitors Cs1, Csd1 to the inverting input terminal of the operational amplifier 24. During the above ΔΣ sampling operation, charge is stored in the capacitor Cs1, but during the ΔΣ holding operation, the residual charge obtained by subtracting the charge corresponding to the converted output VR from the stored charge of the capacitor Cs1 and fed back is transferred to each of the capacitors Cf11, Cf12. Thus, the residual charge is stored in the capacitors Cf11, Cf12, and the operational amplifier 24 outputs an integrated voltage corresponding to the stored charge of the capacitors Cf11, Cf12 obtained by the integrator 24a from the node Nb.

[0102] As described above, the A / D conversion device 6 performs A / D conversion processing by the ΔΣ method by repeatedly performing the <ΔΣ sampling operation in the hybrid mode> and the <ΔΣ holding operation in the hybrid mode> a predetermined number of times.

[0103] <Amplification operation in the hybrid mode>

[0104] The A / D conversion device 6 repeats the ΔΣ sampling operation and the ΔΣ holding operation a predetermined number of times, and then amplifies the signal in the first block 14 in Figure 6 S26. At this time, as shown in Figure 9 the control circuit 9 turns off the switch SS13 to disconnect the capacitors Csd1, Cs1 from the node Na, turns off the switch SF15 and turns on the switch SF18 to disconnect the output node Nb side of the capacitor Cf12. Therefore, the operational amplifier 24 and the capacitor Cf11 amplify the signal according to the charge stored in the capacitor Cf12 and output the amplified signal to the node Nb. The control circuit 9 turns on the switches SS12, SS14, SDD1M of the first block 14 so that the charge stored in the capacitors Csd1, Cs1 becomes zero.

[0105] <Loop operation part 1 in the hybrid mode>

[0106] After the A / D conversion device 6 amplifies the signal, the A / D conversion processing is performed by the loop method in Figure 6 S27 to S31. First, as shown in Figure 10 the control circuit 9 turns on the switches SC24, SCD22, SCD2M to release the charge stored in the capacitors Ccc2, Ccd2 and perform reset. Moreover, the control circuit 9 turns on the switches SF11, SF16, SF18 to connect the capacitor Cf11 between the input node Na and the output node Nb of the operational amplifier 24, and at the same time releases the charge stored in the capacitor Cf12 to perform reset.

[0107] The control circuit 9 turns on the switches SC11, SCD11, and SCD12 to connect the node Nb to one end of the capacitors Ccc1 and Ccd1, and samples the output voltage Vo1 of the first block 14 into the capacitors Ccc1 and Ccd1.

[0108] <Cyclic operation section 2 in the hybrid mode>

[0109] Next, as Figure 11 shown, the control circuit 9 turns on the switches SC14, SCD13, and the switch (here, assumed to be SCD1T) corresponding to the converted output VR of the quantization unit 13 of the D / A converter 26. Thereby, one end of the capacitors Ccc1 and Ccd1 is connected to the input node Na of the operational amplifier 24. In the above cyclic operation section 1, the output voltage Vo1 is sampled by the capacitors Ccc1 and Ccd1, but in the cyclic operation section 2, the residual charge obtained by subtracting the charge corresponding to the converted output VR from the stored charge of the capacitors Ccc1 and Ccd1 and fed back is transferred to the capacitor Cf11.

[0110] Thereby, the residual charge is stored in the capacitor Cf11.

[0111] At the same time, the control circuit 9 turns on the switches SC21, SCD21, and SCD22 to connect the node Nb to one end of the capacitors Ccc2 and Ccd2, and samples the output voltage Vo1 of the first block 14 into the capacitors Ccc2 and Ccd2. As a result, the first block 14 can perform a cyclic sampling operation by using the capacitor switching circuit 22, perform a cyclic holding operation by using the capacitor switching circuit 21, and be able to perform the cyclic sampling operation and the cyclic holding operation simultaneously.

[0112] <Cyclic operation section 3 in the hybrid mode>

[0113] Next, as Figure 12 shown, the control circuit 9 turns on the switches (here, assumed to be SCD2T) corresponding to the switches SC24, SCD23, and the converted output VR of the quantization unit 13 of the D / A converter 27 to connect one end of the capacitors Ccc2 and Ccd2 to the inverting input terminal of the operational amplifier 24. In the above cyclic operation section 2, the output voltage Vo1 is sampled in the capacitors Ccc2 and Ccd2, but in the cyclic operation section 3, the residual charge obtained by subtracting the charge corresponding to the converted output VR from the stored charge of the capacitors Ccc2 and Ccd2 and fed back is transferred to the capacitor Cf11. Thereby, the residual charge is stored in the capacitor Cf11.

[0114] Meanwhile, the control circuit 9 turns on the switches SC11, SCD11, and SCD12 to connect the node Nb to one end of the capacitors Ccc1 and Ccd1, and samples the output voltage Vo1 of the first block 14 onto the capacitors Ccc1 and Ccd1. As a result, the first block 14 can perform a cyclic sampling operation by using the capacitor switching circuit 21, and at the same time perform a cyclic holding operation by using the capacitor switching circuit 22, and can perform the cyclic sampling operation and the cyclic holding operation simultaneously.

[0115] After that, the first block 14 repeats the cyclic operation part 2 and the cyclic operation part 3. Therefore, the control circuit 9 sequentially adds the quantization value Qo to the high-order bits generated by the ΔΣ method in S21 to S26. The quantization value Qo is obtained by A / D conversion processing through a cyclic method while changing the order as the low-order bits after S27, and takes the added result as the output data Do. In this way, the final A / D conversion result can be obtained.

[0116] (3) Cyclic mode

[0117] As Figure 13 shown, in the cyclic mode, the A / D conversion device 6 performs A / D conversion processing on the analog input signal Vin by using the configuration of the first block 14 through a cyclic method without using the second block 15.

[0118] <Reset operation in cyclic mode>

[0119] First, in S41, the control circuit 9 performs a reset operation on the first block 14 and the second block 15 simultaneously. The processing operation at this time is the same as the reset operation in the ΔΣ mode shown in Figure 3 , and thus its description will be omitted. After that, in S42 to S47, the A / D conversion device 6 alternately repeats the cyclic sampling operation and the cyclic holding operation of the cyclic method a predetermined number of times (for example, dozens of times) by using only the first block 14.

[0120] <Cyclic sampling operation in cyclic mode>

[0121] As Figure 14 shown, the control circuit 9 turns on the switches SDD1M, SS11, and SS12 of the first block 14, causing the capacitor Cs1 to sample the analog input signal Vin. At the same time, the control circuit 9 turns on the switches SF11, SF16, and SF18 to connect the capacitor Cf11 between the input node Na and the output node Nb of the operational amplifier 24. The control circuit 9 turns on the switch SCMP1 to input the output voltage Vo1 of the node Nb to the quantization unit 13.

[0122] Next, as Figure 15As shown, the control circuit 9 turns on switches SS13 and SS14 to transfer the charge stored in capacitor Cs1 to capacitor Cf11. At the same time, the control circuit 9 turns on switches SC11, SCD11, and SCD12 to connect node Nb to one end of capacitors Ccc1 and Ccd1, and samples the output voltage Vo1 of the first block 14 to capacitors Ccc1 and Ccd1. Thus, the first block 14 can perform a cyclic sampling operation by using the capacitor switching circuit 21.

[0123] After that, the first block 14 repeats the same operations as <Cyclic operation part 2 in the hybrid mode> and <Cyclic operation part 3 in the hybrid mode>. This is the same as described above and its description will be omitted. Therefore, the A / D conversion process can be performed by the cyclic method using the first block 14 without using the second block 15.

[0124] <Summary of this embodiment>

[0125] According to this embodiment, the A / D conversion device 6 performs the A / D conversion process in the ΔΣ mode by using the first block 14 and the second block 15, and performs the A / D conversion process in the hybrid mode and the cyclic mode by using only the first block 14. Thus, in modes other than the ΔΣ mode, that is, in the hybrid mode and the cyclic mode, the A / D conversion device 6 does not need to operate the second block 15, and does not need to adopt a high-gain amplifier for the operational amplifier 24b in the second block 15. As a result, compared with the related art, the configuration area for the second block 15 can be made smaller, and the current consumption can be reduced.

[0126] In the hybrid mode and the cyclic mode, since the second block 15 is not used, an operational amplifier with a low gain error can be used for the operational amplifier 24b of the second block 15 compared with the operational amplifier 24 of the first block 14.

[0127] In this embodiment, in the A / D conversion device 6, capacitor Csd1 is used as a sampling capacitor in the ΔΣ mode, and capacitor Cs1 is used as a sampling capacitor in the hybrid mode and the cyclic mode. That is, when the capacitance values of capacitors Cs1 and Csd1 are set to different capacitance values from each other, the input sampling capacitance value can be switched between the ΔΣ mode and other modes.

[0128] Generally, when the ΔΣ mode is adopted, due to the influence of oversampling, the A / D conversion accuracy becomes higher than the A / D conversion accuracy in the cyclic mode, but even when the capacitance value of the sampling capacitor Csd1 is reduced when the ΔΣ mode is adopted, the A / D conversion accuracy can be maintained. In this case, the configuration area for the sampling capacitor Csd1 can be minimized. On the contrary, the A / D conversion accuracy in the ΔΣ mode can be further improved by setting a large capacitance value for the sampling capacitor Csd1.

[0129] Second Embodiment

[0130] As Figure 16 shown, a quantization unit 213 may be provided to replace quantization unit 13. The quantization unit 213 includes a first quantizer 213a that quantizes the output voltage Vo2 of the second block 15 in the ΔΣ mode, and a second quantizer 213b that quantizes the output voltage Vo1 of the first block 14 in a mode other than the ΔΣ mode (i.e., for example, a hybrid mode, a cyclic mode).

[0131] The first quantizer 213a is constituted by an A / D converter and outputs a converted output Qo1 obtained by quantizing the output voltage Vo1 to the control circuit 9. The control circuit 9 turns on or off the switches of the D / A converters 25 to 27 of the first block 14 according to the converted output Qo1 of the first quantizer 213a in the hybrid mode and the cyclic mode. The second quantizer 213b is constituted by an A / D converter and outputs a converted output Qo2 of the second quantizer 213b obtained by quantizing the output voltage Vo2 to the control circuit 9.

[0132] The control circuit 9 turns on or off the corresponding switches of the D / A converters 25 to 27 and the D / A converter 25b of the first block 14 and the second block 15 according to the converted output Qo2 of the second quantizer 213b in the ΔΣ mode. Therefore, the first quantizer 213a and the second quantizer 213b can be used separately for each mode.

[0133] Third Embodiment

[0134] Figure 17 An electrical configuration of an A / D conversion device 306 according to the third embodiment is shown. The A / D conversion device 306 includes a signal processing unit 312. The signal processing unit 312 has substantially the same configuration as the signal processing unit 12, except that an operational amplifier 324b is provided to replace the operational amplifier 24b. The operational amplifier 324b is configured to be able to operate with low power consumption.

[0135] As described in the first embodiment, in the hybrid mode and the cyclic mode other than the ΔΣ mode, the second block 15 is in a non-operating state. For this reason, as Figure 17 shown, the control circuit 9 preferably transforms the operational amplifier 324b into a sleep state by outputting a current cut-off signal Scut to the operational amplifier 324b of the second block 15. As a result, the operating current of the operational amplifier 324b can be cut off, and the operating current can be reduced in modes other than the ΔΣ mode.

[0136] As Figure 18As shown, operational amplifier 324b includes an input amplification stage 31, a current cut-off unit 32, and a discrete-time common-mode feedback circuit 33 (abbreviated as CMFB circuit 33 hereinafter). The input amplification stage 31 is formed by combining p-channel MOSFETs Mp1 to Mp4 and n-channel MOSFETs Mn1 to Mn6 in the form shown, and is configured in a so-called folded cascode type. The circuit topology of the input amplification stage 31 is not limited to the form shown.

[0137] The current cut-off unit 32 is formed by forming a p-channel MOSFET_Mpc and an n-channel MOSFET_Mnc in the form shown, and is configured such that the input amplification stage 31 can be switched between effective and ineffective by adjusting the bias voltage applied to the input amplification stage 31.

[0138] When receiving the input of the current cut-off signal Scut from the control circuit 9, the operational amplifier 324b generates signals Cutp / Cutn that change complementarily to the current cut-off signal Scut by using an inverter or the like, and applies the generated signals to the p-channel MOSFET_Mpc and the n-channel MOSFET_Mnc of the current cut-off unit 32. The current cut-off unit 32 can reduce the current consumed in the input amplification stage 31 by cutting off the conduction path of the input amplification stage 31.

[0139] The CMFB circuit 33 includes switches SCM1, SCM2, a p-channel MOSFET_Mp7, an n-channel MOSFET_Mn7, and capacitors Ca, Cb in the form shown. The circuit topology of the CMFB circuit 33 is not limited to the form shown.

[0140] The control circuit 9 applies control signals to the switches SCM1, SCM2 to conduct or cut off the switches SCM1, SCM2 complementarily. Then, the input amplification stage 31 can hold the average voltage (AOUTP + AOUTM) / 2 of its output analog voltages AOUTM, AOUTP at a predetermined voltage VCM, and the CMFB circuit 33 can feedback the average value of the output voltage Vo2 of the operational amplifier 324b to hold the average value at the predetermined voltage VCM during normal operation.

[0141] When the control circuit 9 stops the operation of the CMFB circuit 33 by stopping the application of control signals to the switches SCM1 and SCM2 while the current cut-off unit 32 is cutting off the current of the input amplifier stage 31, the output analog voltages AOUTP and AOUTM can also be fixed to the power supply voltage VDD or the ground level. In this case, it takes a certain amount of recovery time for the CMFB circuit 33 to return to the same operating state as the normal state and for the average voltage (AOUTP + AOUTM) / 2 of the output analog voltages AOUTM and AOUTP to reach the predetermined voltage VCM.

[0142] Therefore, the control circuit 9 continuously outputs control signals applied to the switches SCM1 and SCM2 even when the current of the input amplifier stage 31 is cut off by the current cut-off unit 32, so as to desirably continue the operation of the CMFB circuit 33.

[0143] Then, even when the operational amplifier 324b operates at low power due to the action of the current cut-off unit 32, the control circuit 9 can terminate the cut-off operation of the current cut-off unit 32, enabling the operational amplifier 324b to immediately resume operation and reducing the recovery time until the operational amplifier 324b returns to normal operation.

[0144] Although not shown here, especially when the first block 14 requires a high-gain amplifier in the mixed mode, it is preferable to add the operational amplifier 24 of the first block 14 to Figure 18 the configuration of the folded cascode type input amplifier stage 31 shown in

[0145] A gain-boosting amplifier is constituted by using a fully differential OP amplifier that sets the drains of MOSFET_Mn3 and Mn4 as inputs and connects the gates of MOSFET_Mn5 and Mn6 to the output, and a fully differential OP amplifier that sets the sources of MOSFET_Mp3 and Mp4 as inputs and connects the gates of MOSFET_Mn3 and Mn4 to the output.

[0146] However, since the second block 15 is not required in the mixed mode, there is no need to construct a gain-boosting amplifier in the operational amplifier 324b of the second block 15, and the configuration area for the gain-boosting amplifier circuit can be reduced. In addition, the current consumption can be reduced.

[0147] According to this embodiment, since the control circuit 9 operates the CMFB circuit 33 of the operational amplifier 324b of the second block 15 and does not operate the input amplifier stage 31 as another circuit, the current consumption can be cut off when the second block 15 is not operating, and the operation can be quickly resumed when the operational amplifier 324b of the second block 15 is switched to the required mode (i.e., the ΔΣ mode).

[0148] Fourth Embodiment

[0149] Figure 19 The A / D conversion device 406 shown in Figure 19 includes a signal processing unit 412, a quantization unit 13, and a control circuit 9. The signal processing unit 412 of this embodiment consists of a block 414. The description of the block 414 will focus on the parts that are different from those of the first block 14 in the first embodiment.

[0150] The block 414 includes capacitor switching circuits 20 to 22, 420b, 423b, and an operational amplifier 24. The capacitor switching circuits 20 to 22 have the same configuration as the capacitor switching circuits 20 to 22 inside the first block 14 described in the first embodiment. The D / A converter 25 is equivalent to the first D / A converter, and the capacitor Csd1 is equivalent to the first capacitor. The capacitor Cs1 is equivalent to the first sampling capacitor. The capacitor switching circuit 20 is equivalent to the first capacitor switching circuit capable of charging / discharging the capacitor Csd1 that constitutes the D / A converter 25.

[0151] The capacitor switching circuit 420b includes switches SS21 to SS24, a capacitor Cs2, and a D / A converter 25b. The D / A converter 25b is equivalent to the second D / A converter and has the same configuration as the D / A converter 25b inside the second block 15 described in the first embodiment, but with different connections. The capacitor Csd2 is equivalent to the second capacitor. The capacitor switching circuit 420b is equivalent to the second capacitor switching circuit capable of charging / discharging the capacitor Csd2 that constitutes the D / A converter 25b.

[0152] One terminal of the capacitor Cs2 is connected to the node Nb via the switch SS21 and to the analog ground via the switch SS24. The other terminal of the capacitor Cs2 is connected to the node Na via the switch SS23 and to the analog ground via the switch SS22.

[0153] The D / A converter 25b includes a plurality of switches SDD2T, SDD2M, SDD2B, and a capacitor Csd2. The other terminal of the capacitor Cs2 is connected to the node Na via the switch SS23 and to the analog ground via the switch SS22. The control circuit 9 selectively turns on the switches SDD2T, SDD2M, SDD2B to apply any one of the converted outputs Vrefp, Vcm, Vrefm of the quantization unit 13 to the other terminal of the capacitor Csd2.

[0154] The capacitor switching circuit 423b is constituted by combining the capacitor switching circuit 23 and the capacitor switching circuit 23b described in the first embodiment, and includes switches SF11 to SF14, SF15 to SF18, SF21 to SF24, SA12, and capacitors Cf11, Cf12, Cf21.

[0155] The capacitors Cf11, Cf12, Cf21 are configured as feedback capacitors between the input node Na and the output node Nb of the operational amplifier 24. One terminal of the capacitor Cf11 is connected to the node Na via the switch SF13 and to the analog ground via the switch SF12. The other terminal of the capacitor Cf11 is connected to the node Nb via the switch SF11 and to the analog ground via the switch SF14.

[0156] One terminal of the capacitor Cf12 is connected to the node Na via the switch SF17 and to the analog ground via the switch SF16. The other terminal of the capacitor Cf12 is connected to the node Nb via the switch SF15 and to the analog ground via the switch SF18.

[0157] One terminal of the capacitor Cf12 is connected to the node Na via the switch SF23 and to the analog ground via the switch SF22. The other terminal of the capacitor Cf12 is connected to the node Nb via the switch SF21 and to the analog ground via the switch SF24. The node Na is connected to the analog ground via the switch SA12.

[0158] The output voltage Vo1 of the node Nb is input to the quantization unit 13. The quantization unit 13 is configured using an A / D converter. Other configurations are the same as those of the first embodiment, and thus the description will be omitted.

[0159] (1) ΔΣ mode

[0160] In the ΔΣ mode, after performing a reset operation, the A / D conversion device 406 repeats the ΔΣ sampling operation and the ΔΣ holding operation. At this time, in the A / D conversion device 406, the quantization unit 213 continues digital output while performing oversampling a predetermined number of times on the ΔΣ sampling operation and the ΔΣ holding operation to perform A / D conversion processing, and the digital filter 8 performs low-pass filtering on the output value of the quantization unit 13 to generate the output data Do.

[0161] <Reset operation in the ΔΣ mode>

[0162] Although the reset operation is not shown, the control circuit 9 performs on / off control of each switch to discharge the charges stored in all the capacitors Cs1, Csd1, Cs2, Csd2, Cf11, Cf12, Cf21. The control circuit 9 performs a reset process on the digital filter 8 before setting the ΔΣ mode.

[0163] <Operation part 1 in the ΔΣ mode: Equivalent to the first ΔΣ operation>

[0164] As Figure 19 shown, the control circuit 9 turns on the switches SSD11, SS12, SS14, thereby causing the capacitor Csd1 (equivalent to the first capacitor) to sample the analog input signal Vin.

[0165] In addition, the control circuit 9 turns on the switches SF21, SF23 to connect the capacitor Cf2 between the input / output terminals of the operational amplifier 24.

[0166] The capacitor switching circuits 21, 22 hold the charges stored in the capacitors Ccc1, Ccd1, Ccc2, Ccd2 in the reset state.

[0167] <Operation part 2 in the ΔΣ mode: Equivalent to the second ΔΣ operation>

[0168] As Figure 20 shown, the control circuit 9 turns on the switches SS14, SS13 and the switch (here, assumed to be SDD1T) of the D / A converter 25 corresponding to the converted output VR to connect one end of the capacitors Cs1, Csd1 to the input node Na of the operational amplifier 24. In addition, the control circuit 9 turns on the switches SF11, SF13 to connect the capacitor Cf11 between the input node Na and the output node Nb of the operational amplifier 24.

[0169] In the operation part 1 of the ΔΣ mode, the analog input signal Vin is sampled by the capacitor Csd1, but in the operation part 2 of the ΔΣ mode, the residual charge obtained by subtracting the charge corresponding to the converted output VR from the stored charge of the capacitor Csd1 and fed back is transferred to the capacitor Cf11. Thus, the residual charge is stored in the capacitor Cf11. At the same time, the control circuit 9 turns on the switches SS21, SS22, SDD2M, thereby causing the capacitor Cs2 (equivalent to the second sampling capacitor) to sample the output voltage Vo1.

[0170] Therefore, the block 414 calculates the integral voltage corresponding to the stored charge of the capacitor Cf1 obtained by the integrator 24a, can output the output voltage Vo1 from the node Nb to the quantization unit 13, and can sample the output voltage Vo1 into the capacitor Cs2.

[0171] <Operation Part 3 in ΔΣ Mode: Equivalent to the Third ΔΣ Operation>

[0172] Again, as in Figure 21 shown, the control circuit 9 turns on the switches SSD11, SS12, and SS14, causing the capacitor Csd1 to sample the analog input signal Vin.

[0173] At the same time, the control circuit 9 turns on the switches (here, assumed to be SDD2T) of the D / A converter 25b corresponding to the switches SS24, SS23, and the converted output VR to connect one end of the capacitors Cs2 and Csd2 to the inverting input terminal of the operational amplifier 24. In addition, the control circuit 9 turns on the switches SF21 and SF23 to connect the capacitor Cf21 between the input node Na and the output node Nb of the operational amplifier 24. Therefore, the block 414 can calculate the integrated voltage corresponding to the stored charge of the capacitor Cf21 obtained by the integrator 24a and output the output voltage Vo1 from the node Nb to the quantization unit 13.

[0174] At the timing of the above <Operation Part 2 in ΔΣ Mode>, the charge can be sampled in the capacitor Cs2, but at the timing of <Operation Part 3 in ΔΣ Mode>, the residual charge obtained by subtracting the charge corresponding to the converted output VR of the quantization unit 13 from the stored charge of the capacitor Cs2 and then fed back is transferred to the capacitor Cf21. Thus, the residual charge is stored in the capacitor Cf21.

[0175] Moreover, afterwards, the block 414 only repeats the above <Operation Part 2 in ΔΣ Mode> and <Operation Part 3 in ΔΣ Mode> a predetermined number of times. When the control circuit 9 of the A / D conversion device 406 oversamples these operations, the quantization unit 13 continues to output values, and the digital filter 8 performs low-pass filtering on the output values of the quantization unit 13 to generate the output data Do.

[0176] (2) Hybrid Mode

[0177] In the hybrid mode according to this embodiment, the control circuit 9 switches each switch in the block 414 according to the switching process for each switch in the first block 14 in the hybrid mode according to the first embodiment.

[0178] <ΔΣ Sampling Operation in Hybrid Mode: Equivalent to the Fourth ΔΣ Operation>

[0179] In the block 414, after performing the above <Reset Operation in ΔΣ Mode>, the control circuit 9 turns on the switches SDD1M, SS11, and SS12, causing the capacitor Cs1 (equivalent to the first sampling capacitor) to sample the analog input signal Vin, as Figure 22As shown. At the same time, the control circuit 9 turns on the switches SF11, SF13, SF15, and SF17 to connect the capacitors Cf11 and Cf12 in parallel between the input node Na and the output node Nb of the operational amplifier 24.

[0180] <ΔΣ Hold Operation in Hybrid Mode: Equivalent to the Fifth ΔΣ Operation>

[0181] After that, as Figure 23 shown, the control circuit 9 turns on the switches SS14 and SS13 of the block 414 and the corresponding switch (here, assumed to be SDD1T) of the D / A converter 25 for the converted output VR to connect one end of the capacitors Cs1 and Csd1 to the inverting input terminal of the operational amplifier 24.

[0182] During the above ΔΣ sampling operation, charge is stored in the capacitor Cs1, but during the ΔΣ hold operation, the residual charge obtained by subtracting the charge corresponding to the converted output VR from the stored charge in the capacitor Cs1 and then fed back is transferred to the capacitors Cf11 and Cf12.

[0183] Thus, the residual charge is stored in the capacitors Cf11 and Cf12, and the block 414 outputs from the node Nb the integration voltage corresponding to the stored charge in the capacitors Cf11 and Cf12 obtained by the integrator 24a. In addition, the quantization unit 13 quantizes the output voltage Vo1 of the block 414 and digitally outputs the quantization voltage to the control circuit 9, and the control circuit 9 selects the converted output VR for the subsequent ΔΣ hold operation.

[0184] As described above, the A / D conversion device 406 performs the A / D conversion process by the ΔΣ method by repeating the <ΔΣ Sampling Operation in Hybrid Mode> and the <ΔΣ Hold Operation in Hybrid Mode> a predetermined number of times to generate high-order bits.

[0185] <Amplification Operation in Hybrid Mode>

[0186] The A / D conversion device 406 repeats the <ΔΣ Sampling Operation in Hybrid Mode> and the <ΔΣ Hold Operation in Hybrid Mode> a predetermined number of times, and then amplifies the signal. At this time, although not shown, the control circuit 9 turns off the switch SS13 to disconnect the capacitors Csd1 and Cs1 from the node Na, turns off the switch SF15 and turns on the switch SF18 to disconnect the output node Nb side of the capacitor Cf12, whereby the operational amplifier 24 and the capacitor Cf11 can amplify the signal according to the charge stored in the capacitor Cf12 and output the amplified signal to the node Nb. This operation is the same as that in the first embodiment described with reference to Figure 9 description.

[0187] <Cyclic Operation in Hybrid Mode>

[0188] After the signal is amplified by the A / D conversion device 406, the A / D conversion process is performed by a cyclic method. Block 414 performs the A / D conversion process by a cyclic method using the capacitor switching circuits 21, 22 and the capacitor Cf11 of the capacitor switching circuit 423b. The control content of the control circuit 9 for each switch is the same as that of <the <hybrid mode (cyclic operation parts 1 to 3)> in the first embodiment described above>, and its description will be omitted. Figures 10 to 12 The control content of <the <hybrid mode (cyclic operation parts 1 to 3)> in the first embodiment described above> is the same, and its description will be omitted.

[0189] The control circuit 9 performs a predetermined digital integration process on the quantization value Qo generated by the A / D conversion process by the ΔΣ method using a digital integrator to generate a high-order bit, sequentially adds the quantization value Qo obtained by the A / D conversion process by the cyclic method to the generated high-order bit value, and uses the added result as the output data Do. In this way, the final A / D conversion result can be obtained.

[0190] (3) Cyclic mode

[0191] Similarly in the cyclic mode, block 414 performs the A / D conversion process by a cyclic method using the capacitor switching circuits 21, 22 and the capacitor Cf11 of the capacitor switching circuit 423b. The control content of the control circuit 9 for each switch is the same as that of <the "(3) Cyclic mode" in the first embodiment described above>, and its description will be omitted accordingly. Figures 13 to 15 The control content of <the "(3) Cyclic mode" in the first embodiment described above> is the same, and its description will be omitted.

[0192] As shown in this embodiment, even when the A / D conversion device 406 has a basic configuration with one stage including block 414, the A / D conversion device 406 can be operated in each of the following modes: (1) ΔΣ mode, (2) cyclic mode, and (3) hybrid mode. As a result, while achieving the same effects as in the first embodiment, the circuit can be simplified, the circuit scale can be reduced, and the power can also be reduced.

[0193] Fifth embodiment

[0194] Figure 24 and Figure 25 The A / D conversion device 506 shown in <the fifth embodiment> includes a signal processing unit 512, a quantization unit 13, and a control circuit 9. The signal processing unit 512 of this embodiment is composed of a first block 514 and a second block 15. The description of the first block 514 will focus on the parts different from those of the first block 14 in the first embodiment.

[0195] The capacitor switching circuit 523 is connected between the input node Na and the output node Nb of the operational amplifier 24. The capacitor switching circuit 523 is provided to replace the capacitor switching circuit 23 of the first block 14, and has a configuration in which the capacitor Cf12 and the switches SF15 to SF18 for switching the charging / discharging of the capacitor Cf12 are omitted from the capacitor switching circuit 23. Therefore, the circuit configuration area can be reduced by the configuration area for the capacitor Cf12 and the switches SF15 to SF18.

[0196] In actual use, the control circuit 9 can connect the capacitors Ccc1, Ccd1, Ccc2, Ccd2 of the capacitor switching circuits 21, 22 used in the cyclic method to the capacitor Cf11 (equivalent to the feedback capacitor) of the capacitor switching circuit 523 and use the capacitors.

[0197] For example, in the <ΔΣ sampling operation in the hybrid mode> and <ΔΣ holding operation in the hybrid mode> described in the first embodiment, the control circuit 9 turns on the switches SC11, SCD11, SCD13, SF11 to enable Figure 24 and Figure 25 to achieve the connection of the capacitors Cf11, Ccc1, Ccd1 between the input node Na and the output node Nb of the operational amplifier 24 shown in, whereby the capacitors Cf11, Ccc1, Ccd1 can all act as feedback capacitors.

[0198] Therefore, the capacitors Ccc1, Ccd1 used when sampling the output voltage Vo1 of the first block 14 by the cyclic method can generally be used as feedback capacitors, and can further replace the capacitor Cf12 shown in the above embodiment.

[0199] In the A / D conversion device 506, when amplification is performed after the repetition of the ΔΣ sampling operation and the ΔΣ holding operation in the hybrid mode, the control circuit 9 turns on the switches SCD 1M, SCD 13, SF11, SC14 to enable signal amplification according to the charges stored in the capacitors Ccc1, Ccd1, Cf11, as Figure 26 shown in. The cyclic sampling operation and the cyclic holding operation in the second half of the hybrid mode can be implemented by the same control method as in the above embodiment, and therefore the detailed description thereof will be omitted.

[0200] Sixth Embodiment

[0201] As Figure 27 and Figure 28As shown in [the figure], the A / D conversion device 606 includes a signal processing unit 612, a quantization unit 13, and a control circuit 9. The signal processing unit 612 of this embodiment is composed of a first block 514 and a second block 15. The difference between the sixth embodiment and the first embodiment lies in how to sample the analog input signal Vin.

[0202] In the <ΔΣ sampling operation in the hybrid mode>, as Figure 27 shown in [the figure], the control circuit 9 turns on the switches SSD11, SS11, and SS12 so that the capacitors Csd1 and Cs1 can be connected in parallel and the analog input signal Vin can be input.

[0203] After that, in the <ΔΣ hold operation in the hybrid mode>, as Figure 28 shown in [the figure], the control circuit 9 turns on the switches SS14 and SS13 of the first block 14 and the switch (here, assumed to be SDD1T) of the D / A converter 25 corresponding to the converted output VR, so that one end of the capacitors Cs1 and Csd1 is connected to the inverting input terminal of the operational amplifier 24.

[0204] During the above ΔΣ sampling operation, charges are stored in each of the capacitors Cs1 and Csd1. However, during the ΔΣ hold operation, as shown in the above embodiment, the residual charges obtained by subtracting the charges corresponding to the converted output VR from the stored charges of the capacitors Cs1 and Csd1 and then fed back are transferred to the capacitors Cf11 and Cf12. Therefore, the first block 614 outputs the integrated voltage corresponding to the stored charges of the capacitors Cf11 and Cf12 obtained by the integrator 24a from the node Nb.

[0205] Therefore, the capacitor Csd1 not only serves as a sampling capacitor but also as a DAC capacitor of the D / A converter 25 in the hybrid mode. For example, consider the case where the following design is made: the capacitance value of the sampling capacitor is set to 1 pF and the capacitance value of the DAC capacitor is set to 0.5 pF. As shown in the first embodiment, when the sampling capacitor of the analog input signal Vin and the DAC capacitor of the D / A converter 25 are separately configured and designed not to be shared, by setting the capacitance value of the capacitor Cs1 to 1 pF and the capacitance value of the capacitor Csd1 to 0.5 pF, a total of 1.5 pF is required.

[0206] However, as shown in this embodiment, when the sampling capacitor and the DAC capacitor are partially shared, this capacitor can be realized by setting the capacitance value of the capacitor Cs1 to 0.5 pF and the capacitance value of the capacitor Csd1 to 0.5 pF, so that the circuit can be configured using a smaller area.

[0207] According to this embodiment, since the sampling capacitor and the DAC capacitor are at least partially shared, a smaller area can be used to configure the sampling capacitor and the DAC capacitor.

[0208] Other embodiments

[0209] The converted output VR of the quantization unit 13 is not limited to three levels, but can be appropriately set according to the number of levels of the quantization value Qo in the quantization unit 13. According to this number of levels, the number of levels of the converted output VR of the D / A converters 25, 26, 27 in the capacitor switching circuits 20, 21, 22 can also be changed.

[0210] The capacitance values of the capacitors Cs1, Csd1, Cs2, Csd2, Ccc1, Ccc1, Ccc2, Ccd2, Cf11, Cf12, Cf21 can be appropriately scaled to correspond to the input / output range of each of the operational amplifiers 24, 24b.

[0211] Although the fourth embodiment has shown a form in which the quantization unit 13 is constituted by using one A / D converter, the present disclosure is not limited thereto, and a quantization unit 213 for switching between two quantizers 213a, 213b in each mode can be used.

[0212] In the above embodiment, the signal processing unit 12 is constituted by a ΔΣ modulator using blocks 14 and 15 and the quantization unit 13, but the type of the ΔΣ modulator is not limited to the above embodiment. For example, the signal processing unit 12 can be configured to operate as a second-order CIFF (cascade of integrators with positive feedback) ΔΣ modulator which is a typical example of a positive feedback ΔΣ modulator.

[0213] In the above embodiment, a single-ended circuit has been shown as the first block 14, the second block 15, etc., in which a signal is input to the inverting input terminal which is one of the inputs of the operational amplifiers 24, 25a, and the non-inverting input terminal which is the other input is connected to the analog ground. However, the circuit can be of a differential type in which a differential signal is input to a fully differential type or pseudo-differential type operational amplifier.

[0214] Although the forms of the A / D conversion devices 6, 306, 406, 506, 606 each having three modes of a ΔΣ mode, a hybrid mode, and a cyclic mode have been described, the present disclosure is not limited thereto, but can be applied to an A / D conversion device having any two of these modes.

[0215] Although the present disclosure has been described with reference to its embodiments, it is to be understood that the disclosure is not limited to the described embodiments and configurations. The present disclosure is intended to cover various modifications and equivalent arrangements. In addition, although there are various combinations and configurations, other combinations and configurations including more, fewer, or only a single element are also within the spirit and scope of the present disclosure.

Claims

1. An A / D conversion device (6; 306; 406; 506; 606) that operates in at least two or more modes, the at least two or more modes including: A ΔΣ mode, in which an analog input signal (Vin) is processed by A / D conversion processing using the ΔΣ method; and a hybrid mode, in which the analog input signal (Vin) is processed by the A / D conversion processing using the ΔΣ method, and then a residual part is processed by the A / D conversion processing using a cyclic method. The A / D conversion device includes: A first block (14) that receives the analog input signal (Vin) and processes the analog input signal through a first amplifier (24); A second block (15) that includes a second amplifier (24b) that receives the output voltage of the first block; A quantization unit (13; 213) that receives one of the outputs of the first block and the second block and quantizes the one of the outputs; and A control circuit (9) that switches between the at least two or more modes and controls the switching of the modes to perform control corresponding to the modes, where: In the ΔΣ mode, the control circuit uses the first amplifier of the first block and the second amplifier of the second block to quantize the output of the second block through the quantization unit, and processes the output by the A / D conversion processing using the ΔΣ method; and In the hybrid mode, the control circuit uses the first amplifier of the first block without using the second amplifier of the second block to quantize the output of the first amplifier of the first block through the quantization unit and process the output by the A / D conversion processing using the ΔΣ method, and then the control circuit uses the first amplifier to process the residual part by the A / D conversion processing using the cyclic method.

2. The A / D conversion device according to claim 1, where: The first block includes sampling capacitors (Cs1, Csd1) for sampling the analog input signal; and The sampling capacitors are configured to enable switching of the input sampling capacitance between the ΔΣ mode and modes other than the ΔΣ mode.

3. The A / D conversion device according to claim 1, where: The first amplifier of the first block includes an operational amplifier (24), and when the first block outputs an integral voltage, the operational amplifier (24) connects a feedback capacitor (Cf11) between an input node (Na) and an output node (Nb) of the operational amplifier; and When sampling the output of the first block using the cyclic method, the first amplifier of the first block shares another capacitor (Ccc1, Ccd1) as the feedback capacitor.

4. The A / D conversion device according to claim 1, further including: Sampling capacitors (Cs1, Csd1) for sampling the analog input signal; And A D / A converter (25), when performing the A / D conversion process using the ΔΣ method, the D / A converter (25) performs D / A conversion using a D / A converter capacitor (Csd1) according to the digital output of the quantization unit, where: At least a part of the sampling capacitor and at least a part of the D / A converter capacitor are common.

5. The A / D conversion device according to claim 1, where: The quantization unit includes: A first quantizer (213a), the first quantizer (213a) quantizes the output of the second amplifier of the second block in the ΔΣ mode; and A second quantizer (213b), the second quantizer (213b) quantizes the output of the first amplifier of the first block in a mode other than the ΔΣ mode.

6. The A / D conversion device according to any one of claims 1 to 5, further comprising: A current cut-off unit (32), the current cut-off unit (32) cuts off the current of the second amplifier (324b) of the second block in a mode other than the ΔΣ mode.

7. The A / D conversion device according to claim 6, where: In a mode other than the ΔΣ mode, the common-mode feedback circuit (33) of the second amplifier (324b) of the second block is operated, and another circuit (31) is not operated.

8. An A / D conversion device (6; 306; 406; 506; 606) that operates in at least two or more modes, the at least two or more modes including: A ΔΣ mode, where an analog input signal (Vin) is processed through an A / D conversion process using the ΔΣ method; and a cyclic mode, where the analog input signal (Vin) is processed through the A / D conversion process using the cyclic method, the A / D conversion device includes: A first block (14), the first block (14) receives the analog input signal (Vin) and processes the analog input signal through a first amplifier (24); A second block (15), the second block (15) includes a second amplifier (24b) that receives the output voltage of the first block; A quantization unit (13; 213), the quantization unit (13; 213) receives one of the outputs of the first block and the second block and quantizes the one of the outputs; and A control circuit (9), the control circuit (9) switches the at least two or more modes and controls the switching of the modes to perform control corresponding to the modes, where: In the ΔΣ mode, the control circuit uses the first amplifier of the first block and the second amplifier of the second block to quantize the output of the second block through the quantization unit, and processes the output through the A / D conversion process using the ΔΣ method; and In the cyclic mode, the control circuit uses the first amplifier of the first block without using the second amplifier of the second block to quantize the output of the first amplifier of the first block through the quantization unit, and processes the output through the A / D conversion process using the cyclic method.

9. The A / D conversion device according to claim 8, where: The first block includes sampling capacitors (Cs1, Csd1) for sampling the analog input signal; and the sampling capacitors are configured to enable switching of the input sampling capacitance between the ΔΣ mode and a mode other than the ΔΣ mode.

10. The A / D conversion device according to claim 8, wherein: the first amplifier of the first block includes an operational amplifier (24), and when the first block outputs an integration voltage, the operational amplifier (24) connects a feedback capacitor (Cf11) between an input node (Na) and an output node (Nb) of the operational amplifier; and when sampling the output of the first block using the cyclic method, the first amplifier of the first block shares another capacitor (Ccc1, Ccd1) as the feedback capacitor.

11. The A / D conversion device according to claim 8, further comprising: sampling capacitors (Cs1, Csd1) for sampling the analog input signal; and a D / A converter (25), which, when performing the A / D conversion process using the ΔΣ method, performs D / A conversion using a D / A converter capacitor (Csd1) according to the digital output of the quantization unit, wherein: at least a part of the sampling capacitors and at least a part of the D / A converter capacitors are common.

12. The A / D conversion device according to claim 8, wherein: the quantization unit includes: a first quantizer (213a) that quantizes the output of the second amplifier of the second block in the ΔΣ mode; and a second quantizer (213b) that quantizes the output of the first amplifier of the first block in a mode other than the ΔΣ mode.

13. The A / D conversion device according to any one of claims 8 to 12, further comprising: a current cut-off unit (32) that cuts off the current of the second amplifier (324b) of the second block in a mode other than the ΔΣ mode.

14. The A / D conversion device according to claim 13, wherein: in a mode other than the ΔΣ mode, the common-mode feedback circuit (33) of the second amplifier (324b) of the second block is operated, and another circuit (31) is not operated.

15. An A / D conversion device (6; 306; 406; 506; 606) that operates in at least three or more modes, said at least three or more modes including: A ΔΣ mode, in which an analog input signal (Vin) is processed by an A / D conversion process using the ΔΣ method; a cyclic mode, in which the analog input signal (Vin) is processed by the A / D conversion process using the cyclic method; and a hybrid mode, in which the analog input signal (Vin) is processed by the A / D conversion process using the ΔΣ method and then the remaining part is processed by the A / D conversion process using the cyclic method, the A / D conversion device includes: A first block (14) that receives the analog input signal (Vin) and processes the analog input signal through a first amplifier (24); A second block (15) that includes a second amplifier (24b) receiving the output voltage of the first block; A quantization unit (13; 213) that receives one of the outputs of the first block and the second block and quantizes the one of the outputs; and A control circuit (9) that switches the at least three or more modes and controls the switching of the modes to perform control corresponding to the modes, wherein: In the ΔΣ mode, the control circuit uses the first amplifier of the first block and the second amplifier of the second block to quantize the output of the second block through the quantization unit and processes the output through the A / D conversion process using the ΔΣ method; In the hybrid mode, the control circuit uses the first amplifier of the first block without using the second amplifier of the second block to quantize the output of the first amplifier of the first block through the quantization unit using the ΔΣ method and processes the output through the A / D conversion process, and then the control circuit uses the first amplifier to process the remainder through the A / D conversion process using the cyclic method; and In the cyclic mode, the control circuit uses the first amplifier of the first block without using the second amplifier of the second block to quantize the output of the first amplifier of the first block through the quantization unit and processes the output through the A / D conversion process using the cyclic method.

16. The A / D conversion device according to claim 15, wherein: The first block includes sampling capacitors (Cs1, Csd1) for sampling the analog input signal; and The sampling capacitors are configured to enable switching of the input sampling capacitance between the ΔΣ mode and modes other than the ΔΣ mode.

17. The A / D conversion device according to claim 15, wherein: The first amplifier of the first block includes an operational amplifier (24), and when the first block outputs an integration voltage, the operational amplifier (24) connects a feedback capacitor (Cf11) between an input node (Na) and an output node (Nb) of the operational amplifier; and When sampling the output of the first block using the cyclic method, the first amplifier of the first block shares another capacitor (Ccc1, Ccd1) as the feedback capacitor.

18. The A / D conversion device according to claim 15, further comprising: Sampling capacitors (Cs1, Csd1) for sampling the analog input signal; And A D / A converter (25), when performing the A / D conversion process using the ΔΣ method, the D / A converter (25) performs D / A conversion using a D / A converter capacitor (Csd1) according to the digital output of the quantization unit, where: At least a part of the sampling capacitor and at least a part of the D / A converter capacitor are common.

19. The A / D conversion device according to claim 15, where: The quantization unit includes: A first quantizer (213a), which quantizes the output of the second amplifier of the second block in the ΔΣ mode; and A second quantizer (213b), which quantizes the output of the first amplifier of the first block in a mode other than the ΔΣ mode.

20. The A / D conversion device according to any one of claims 15 to 19, further including: A current cut-off unit (32), which cuts off the current of the second amplifier (324b) of the second block in a mode other than the ΔΣ mode.

21. The A / D conversion device according to claim 20, where: In a mode other than the ΔΣ mode, the common-mode feedback circuit (33) of the second amplifier (324b) of the second block is operated, and another circuit (31) is not operated.

22. An A / D conversion device that operates in at least two or more modes, where the at least two or more modes include: A ΔΣ mode, in which an analog input signal (Vin) is processed through an A / D conversion process using the ΔΣ method; and a hybrid mode, in which the analog input signal (Vin) is processed through the A / D conversion process using the ΔΣ method, and then the remaining part is processed through the A / D conversion process using a cyclic method. The A / D conversion device includes: A block (414), which receives the analog input signal (Vin) and processes the analog input signal through an amplifier; A quantization unit (13; 213) that quantizes the output of the block; A control circuit (9), which switches the at least two or more modes and controls the switching of the modes to perform control corresponding to the modes; A first sampling capacitor (Cs1) for sampling the analog input signal; A first capacitor (Csd1) for sampling the analog input signal; A second sampling capacitor (Cs2) for sampling the output voltage of the block; A first capacitor switching circuit (20), which charges and discharges the first capacitor (Csd1) constituting the first D / A converter (25); and A second capacitor switching circuit (420b), which charges and discharges a second capacitor (Csd2) constituting the second D / A converter (25b), where: In the ΔΣ mode, the control circuit Performs a first ΔΣ operation: sampling the analog input signal in the first capacitor using the amplifier of the block, Perform a second ΔΣ operation: Charge or discharge the first capacitor of the first D / A converter according to the digital output of the quantization unit, input the output voltage (Vo1) integrated by the amplifier into the quantization unit, and sample the output voltage using the second sampling capacitor. Perform a third ΔΣ operation: Charge and discharge the second sampling capacitor and the second capacitor (Cs2) of the second D / A converter according to the digital output of the quantization unit, and input the output voltage integrated by the amplifier into the quantization unit, and Repeat the second ΔΣ operation and the third ΔΣ operation to perform quantization using the quantization unit and process the output voltage integrated by the amplifier of the block through the A / D conversion process using the ΔΣ method; and In the hybrid mode, the control circuit Perform a fourth ΔΣ operation: Sample the analog input signal in the first sampling capacitor using the amplifier of the block. Perform a fifth ΔΣ operation: Charge or discharge the first sampling capacitor and the first capacitor of the first D / A converter according to the digital output of the quantization unit, and input the output voltage integrated by the amplifier into the quantization unit, and Repeat the fourth ΔΣ operation and the fifth ΔΣ operation to process the output voltage of the amplifier of the block through the A / D conversion process using the ΔΣ method and process the residue through the A / D conversion process using the cyclic method.

23. An A / D conversion device that operates in at least two or more modes, where the at least two or more modes include: A ΔΣ mode, in which an analog input signal (Vin) is processed through an A / D conversion process using the ΔΣ method; and a cyclic mode, in which the analog input signal (Vin) is processed through the A / D conversion process using the cyclic method, the A / D conversion device comprising: A block that receives the analog input signal (Vin) and processes the analog input signal through an amplifier; A quantization unit (13; 213) that quantizes the output of the block; A control circuit (9) that switches the at least two or more modes and controls the switching of the modes to perform control corresponding to the modes; A first sampling capacitor (Cs1) for sampling the analog input signal; A first capacitor (Csd1) for sampling the analog input signal; A second sampling capacitor (Cs2) for sampling the output voltage of the block; A first capacitor switching circuit (20) that charges and discharges the first capacitor (Csd1) constituting the first D / A converter (25); and A second capacitor switching circuit (420b) that charges and discharges the second capacitor (Csd2) constituting the second D / A converter (25b), wherein: In the ΔΣ mode, the control circuit Perform a first ΔΣ operation: sample the analog input signal in the first capacitor using the amplifier of the block, Perform a second ΔΣ operation: charge or discharge the first capacitor of the first D / A converter according to the digital output of the quantization unit, input the output voltage (Vo1) integrated by the amplifier into the quantization unit, and sample the output voltage using the second sampling capacitor, Perform a third ΔΣ operation: charge and discharge the second sampling capacitor and the second capacitor (Cs2) of the second D / A converter according to the digital output of the quantization unit, and input the output voltage integrated by the amplifier into the quantization unit, and Repeat the second ΔΣ operation and the third ΔΣ operation to perform quantization using the quantization unit and process the output voltage integrated by the amplifier of the block through the A / D conversion process using the ΔΣ method; and In the cyclic mode, the control circuit performs quantization using the quantization unit and processes the output voltage integrated by the amplifier of the block through the A / D conversion process using the cyclic method.

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