Electronic device and method of manufacturing the same

Abstract

The present application provides an electronic device including a semiconductor memory and a manufacturing method thereof. The semiconductor memory includes: a plurality of lower lines arranged above a substrate and extending in a first direction; a plurality of upper lines arranged above the lower lines and extending in a second direction intersecting the first direction; a plurality of storage cells arranged between the lower lines and the upper lines and arranged overlapping with the intersection area of ​​the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0112790, filed on September 11, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This patent document relates to memory circuits and their applications in electronic devices or electronic systems. Background Art

[0004] Recently, as electronic devices tend toward miniaturization, low power consumption, high performance, multi-functions, etc., the art needs semiconductor devices capable of storing information in various electronic devices such as computers, portable communication devices, etc., and research has been conducted on these semiconductor devices. Such semiconductor devices include semiconductor devices that can store data by utilizing the characteristic of switching between different resistance states according to applied voltage or current, such as RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electric fuses, etc. Summary of the invention

[0005] The technology disclosed in this patent document includes various embodiments of electronic devices and methods of manufacturing the same, wherein the electronic devices can achieve high integration and reduce process difficulty while ensuring the characteristics of a memory cell.

[0006] In one embodiment, an electronic device includes a semiconductor memory, which includes: a plurality of lower lines, which are arranged above a substrate and extend in a first direction; a plurality of upper lines, which are arranged above the lower lines and extend in a second direction intersecting the first direction; a plurality of storage cells, which are arranged between the lower lines and the upper lines and overlap with the intersection area of ​​the lower lines and the upper lines; and an air gap, which is located between the upper lines and extends in the second direction.

[0007] In another embodiment, an electronic device includes a semiconductor memory, which includes a plurality of stacked structures stacked on a substrate, wherein a first stacked structure among the plurality of stacked structures includes: a plurality of first lower lines extending in a first direction; a plurality of first upper lines formed above the first lower lines and extending in a second direction intersecting the first direction; a plurality of first storage cells arranged between the first lower lines and the first upper lines and arranged overlapping with an intersection area of ​​the first lower lines and the first upper lines; and a first air gap located between the first upper lines and extending in a second direction, and a second stacked structure includes: a plurality of second lower lines extending in the second direction; a plurality of second upper lines formed above the second lower lines and extending in the first direction; a plurality of second storage cells arranged between the second lower lines and the second upper lines and arranged overlapping with an intersection area of ​​the second lower lines and the second upper lines; and a second air gap located between the second upper lines and extending in the first direction.

[0008] In another embodiment, a method for manufacturing an electronic device including a semiconductor memory includes: forming a first conductive layer and a storage material above a substrate; etching the first conductive layer and the material layer using a first mask pattern having a line shape extending in a first direction to form a lower line and a storage material pattern extending in the first direction; forming a second conductive layer above the storage material pattern; etching the second conductive layer and the storage material pattern using a second mask pattern having a line shape extending in a second direction intersecting the first direction to form an upper line extending in the second direction and a columnar storage cell; forming an insulating layer between the storage cells and between the upper lines; and forming an air gap within the insulating layer, the air gap being located between the upper lines and extending in the second direction.

[0009] These and other aspects, embodiments and associated advantages are described in more detail in the drawings, the description and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1D is a diagram illustrating a semiconductor memory according to an embodiment of the present disclosure.

[0011] FIG. 2A to FIG. 2J is a diagram illustrating a method of manufacturing a semiconductor memory according to an embodiment of the present disclosure.

[0012] FIG. 3A to FIG. 3C is a diagram illustrating a semiconductor memory according to another embodiment of the present disclosure.

[0013] Figure 4 is an example of a configuration diagram of a microprocessor implementing a storage circuit based on the disclosed technology.

[0014] Figure 5is an example of a configuration diagram of a processor implementing a storage circuit based on the disclosed technology.

[0015] Figure 6 is an example of a configuration diagram of a system implementing a storage circuit based on the disclosed technology.

[0016] Figure 7 is an example of a configuration diagram of a data storage system implementing a storage circuit based on the disclosed technology.

[0017] Figure 8 is an example of a configuration diagram of a memory system implementing a memory circuit based on the disclosed technology. DETAILED DESCRIPTION

[0018] Various examples and implementations of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0019] The drawings may not necessarily be drawn to scale, and in some cases, the proportions of at least some of the structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example having two or more layers in a multilayer structure is shown in the drawings or in the specification, the relative positional relationship of these layers or the order in which these layers are arranged as shown reflects the specific embodiment of the described or shown example, and different relative positional relationships or different orders of arranging these layers are possible. In addition, the examples of multilayer structures described or shown may not reflect all of the layers present in the specific multilayer structure (for example, one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in the described or shown multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0020] Figures 1A to 1D is a diagram illustrating a semiconductor memory according to an embodiment of the present disclosure. Figure 1A It is a floor plan. Figure 1B is along Figure 1A A cross-sectional view taken along line XX′. Figure 1C is along Figure 1A A cross-sectional view taken along line YY′. Figure 1D Shows Figures 1A to 1C An example of a storage unit.

[0021] refer to Figures 1A to 1C, the memory device of the present embodiment may include a substrate 100, a plurality of lower lines 110, a plurality of upper lines 130, a plurality of memory cells 120, and an insulating layer 140 having an air gap AG. The lower lines 110 may be disposed above the substrate 100 and extend in a first direction parallel to the line XX′. The upper lines 130 may be disposed above the lower lines 110 and extend in a second direction parallel to the line YY′. The memory cells 120 may be disposed between the lower lines 110 and the upper lines 130 and overlap with a cross region of the lower lines 110 and the upper lines 130. Here, the cross region is a region where the lower lines 110 and the upper lines 130 intersect from a plan view, for example Figure 1A 1 is used to illustrate the area inside the dotted line of the memory cell 120. The insulating layer 140 may fill the space between the lower lines 110, between the upper lines 130, and between the memory cells 120. Air gaps AG may be formed in the insulating layer 140. Each air gap AG may be located between two adjacent upper lines 130.

[0022] The substrate 100 may include a lower structure (not shown) that may include, for example, a transistor for controlling the lower line 110 and / or the upper line 130 .

[0023] The lower wires 110 may extend in the first direction and be spaced apart from each other in the second direction. The lower wires 110 may include a conductive material such as a metal or a metal nitride. The thickness of the lower wires 110 is Figure 1B It is indicated by the reference symbol T1.

[0024] The upper line 130 may be spaced apart from the lower line 110 in the vertical direction. The upper line 130 may extend in the second direction and be spaced apart from each other in the first direction. The upper line 130 may include a conductive material such as a metal or a metal nitride. The thickness of the upper line 130 may be Figure 1B It is indicated by the reference symbol T2.

[0025] In one embodiment, the thickness T2 of the upper line 130 may be greater than the thickness T1 of the lower line 110. As will be described later, due to the nature of the etching process for patterning the upper line 130 and the lower line 110, the upper line 130 may have a relatively small width, while the lower line 110 may have a relatively large width. In this case, if the upper line 130 and the lower line 110 have the same thickness, a problem of relatively large sheet resistance of the upper line 130 may occur. To solve this problem, the sheet resistance of the upper line 130 may be reduced by making the thickness T2 of the upper line 130 greater than the thickness T1 of the lower line 110.

[0026] As an example, the lower line 110 may be used as a word line, and the upper line 130 may be used as a bit line. However, as another example, the lower line 110 may be used as a bit line, and the upper line 130 may be used as a word line.

[0027] Each memory cell 120 may store data and may have a multi-layered structure.

[0028] As an example, Figure 1D As shown, the memory cell 120 may include a lower electrode layer 121, a selection element layer 123, an intermediate electrode layer 125, a memory layer 127, and an upper electrode layer 129 stacked sequentially. However, the layer structure of the memory cell 120 may be changed. For example, the positions of the selection element layer 123 and the memory layer 127 may be exchanged. Alternatively, although not shown, in addition to the above-mentioned layers 121 to 129, the memory cell 120 may further include one or more layers that improve the characteristics of the memory cell 120. Alternatively, at least one of the lower electrode layer 121, the intermediate electrode layer 125, and the upper electrode layer 129 may be omitted.

[0029] The lower electrode layer 121 may be located at the lowermost portion of the memory cell 120 and may be used as a channel for transmitting a current or voltage supplied from the lower line 110. The selection element layer 123 may control access to the memory layer 127. The middle electrode layer 125 may electrically connect the selection element layer 123 to the memory layer 127 to physically separate the two. The memory layer 127 may store different data. The upper electrode layer 129 may be located at the uppermost portion of the memory cell 120 to serve as a channel for transmitting a current or voltage supplied from the upper line 130.

[0030] When the level of the applied voltage or current is equal to or less than a certain threshold, the selection element layer 123 may substantially prevent the current from flowing, and when the level of the applied voltage or current is higher than the certain threshold, the selection element layer 123 may allow the current to flow which increases sharply in proportion to the magnitude of the applied voltage or current. The selection element layer 123 may use a metal-insulator-transition (MIT) device such as NbO 2 or TiO 2 ; Mixed ionic electronic conductive (MIEC) devices, such as ZrO 2 (Y 2 O 3 )、Bi 2 O 3 -BaO or (La 2 O 3 )x(CeO 2 )1-x; OTS devices comprising chalcogenide-based materials such as Ge 2 Sb 2 Te 5 、As 2 Te 3 、As 2 or As 2 Se 3; or a tunneling insulating layer, which is formed of a thin film including various insulating materials (such as silicon oxide, silicon nitride, and metal oxide, etc.), and allows electrons to tunnel under a specific voltage or a specific current condition. The selection element layer 123 may have a single-layer structure or a multi-layer structure having selection element characteristics using a combination of two or more layers.

[0031] The storage layer 127 may store different data in various ways. As an example, the storage layer 127 may include a variable resistance layer that switches between different resistance states according to an applied voltage or current. The variable resistance layer may include materials used in RRAM, PRAM, FRAM, or MRAM, for example, metal oxides such as transition metal oxides or perovskite-based materials, phase change materials such as chalcogenide-based materials, ferroelectric materials, and ferromagnetic materials, etc. The variable resistance layer may have a single-layer structure or a multilayer structure that shows variable resistance characteristics using a combination of more than two layers. As an example, the variable resistance layer may include a phase change material that switches between a crystalline state and an amorphous state by Joule heat generated by a current flowing therethrough. When the phase change material is in a crystalline state, the phase change material may have a low resistance state, and when the phase change material is in an amorphous state, the phase change material may have a high resistance state.

[0032] The lower electrode layer 121 , the middle electrode layer 125 , and the upper electrode layer 129 may have a single-layer structure or a multi-layer structure including various conductive materials such as metal, metal nitride, carbon, or the like.

[0033] Reference again Figures 1A to 1C The insulating layer 140 may include silicon oxide, a low-k material having a lower dielectric constant than silicon oxide, or a combination of a low-k material and silicon oxide.

[0034] In the insulating layer 140, the air gap AG may be formed between the upper lines 130 and may have a line shape extending in the second direction. The air gap AG may be filled with air or in a vacuum. The role and / or reason for forming the air gap AG may be as follows.

[0035] Heat may be generated when operating the memory cell 120. For example, when the memory cell 120 includes a phase change material, heat may be generated due to a programming operation and an erasing operation of the memory cell 120. When reading data stored in the memory cell 120, the heat associated with the read operation may cause a read disturbance in which the phase change material in a low resistance state (i.e., a crystalline state) changes to a high resistance state (i.e., an amorphous state). Reducing the capacitance of the structure near the memory cell 120 may reduce the read disturbance. In the present embodiment, the capacitance between the upper lines 130 may be reduced by forming an air gap AG between the upper lines 130.

[0036] The thickness of the air gap AG in the vertical direction may be equal to or less than the thickness T2 of the upper line 130. Specifically, the lower surface of the air gap AG may be disposed at a height higher than or equal to the upper surface of the memory cell 120. When the lower surface of the air gap AG extends below the upper surface of the memory cell 120, the formation of the air gap AG may damage the integrity of the memory cell 120 during the manufacturing process of the memory device, which will be discussed below. FIG. 2A to FIG. 2J The manufacturing method is described in more detail in the description.

[0037] In addition, despite Figure 1B The cross-section of the middle air gap AG is shown to have an elliptical shape, however, the present disclosure is not limited thereto, and the air gap AG may have other shapes in other embodiments.

[0038] At least a portion of the air gap AG may contact the insulating layer 140. Therefore, both the air gap AG and the insulating layer 140 surrounding the air gap AG may be disposed between the upper lines 130. In this case, if the insulating layer 140 includes a low-k material, the capacitance between the upper lines 130 may be further reduced.

[0039] Meanwhile, even when the air gap AG is located between the lower lines 110, the capacitance near the memory cell 120 can be reduced. However, if the air gap AG exists between the lower lines 110, over-etching may occur in the etching process for forming the memory cell 120, thereby corroding the lower structure, such as the substrate 100. In addition, as indicated by the experimental data in Table 1, when the air gap AG is formed between the upper lines 130, the capacitance can be further reduced, compared with the embodiment in which the air gap AG is formed only between the lower lines 110. Therefore, it is desirable to form the air gap AG between the upper lines 130.

[0040] FIG. 2A to FIG. 2J is a diagram illustrating a method of manufacturing a semiconductor memory according to an embodiment of the present disclosure. Figures 2A to 2J Based on Figure 1A The cross-section of portion P1 taken along lines XX′ and YY′ is shown.

[0041] refer to Figure 2A A conductive layer 210 for forming a lower line and a multilayer structure 220 for forming a memory cell may be formed over a substrate 200. The multilayer structure 220 may include a lower electrode conductive layer 221, a selection element material layer 223, an intermediate electrode conductive layer 225, a memory material layer 227, and an upper electrode conductive layer 229.

[0042] Subsequently, a first mask pattern M1 having a line shape extending in the first direction may be formed over the multilayer structure 220 .

[0043] refer to Figure 2BBy etching the multilayer structure 220 and the conductive layer 210 using the first mask pattern M1 as an etch barrier, a lower line 210A and a multilayer pattern 220A may be formed.

[0044] The lower lines 210A may be spaced apart from each other in the second direction while extending in the first direction.

[0045] Each of the multilayer patterns 220A may include a lower electrode conductive layer pattern 221A, a selection element material layer pattern 223A, an intermediate electrode conductive layer pattern 225A, a storage material layer pattern 227A, and an upper electrode conductive layer pattern 229A. In addition, the multilayer patterns 220A may overlap the lower lines 210A, respectively, and have a line shape extending in the first direction.

[0046] As described above, this etching process may be performed by an anisotropic etching process using an etching gas, etc. Therefore, although not shown, the stack structure of the lower line 210A and the multilayer pattern 220A may have a shape whose width increases from top to bottom.

[0047] Subsequently, a first insulating layer 242 may be formed to fill a space between the lower line 210A and the stack structure of the multilayer pattern 220A. The first insulating layer 242 may include various insulating materials such as silicon oxide, a low-k material, or a combination thereof.

[0048] The first mask pattern M1 may be removed in this etching process or may be removed through an additional removal process.

[0049] refer to Figure 2C , a conductive layer 230 for forming an upper line may be formed over the multilayer pattern 220A and the first insulating layer 242 .

[0050] Subsequently, a second mask pattern M2 having a line shape extending in the second direction may be formed over the conductive layer 230 .

[0051] refer to Figure 2D By etching the conductive layer 230 and the multi-layer pattern 220A using the second mask pattern M2 as an etch barrier, the upper line 230A and the memory cell 220B may be formed.

[0052] The upper lines 230A may be arranged to be spaced apart from each other in the first direction while extending in the second direction.

[0053] The memory cell 220B may have a columnar shape overlapping the lower line 210A and the upper line 230A. Two sidewalls of the memory cell 220B in the first direction may be aligned with two sidewalls of the upper line 230A, and two sidewalls of the memory cell 220B in the second direction may be aligned with two sidewalls of the lower line 210A. The memory cell 220B may include a lower electrode layer 221B, a selection element layer 223B, an intermediate electrode layer 225B, a memory layer 227B, and an upper electrode layer 229B.

[0054] In this etching process, the first insulating layer 242 may also be etched simultaneously in a region not overlapping the second mask pattern M2 to form a first insulating layer pattern 242A. The first insulating layer pattern 242A may be alternately arranged with the memory cells 220B along the second direction with pillars between the memory cells 220B.

[0055] As described above, this etching process may be an anisotropic etching process using an etching gas or the like. Therefore, although not shown, the stacked structure of the memory cell 220B and the upper line 230A may have a shape in which the width in the first direction increases from the top to the bottom. As a result, even if the first mask pattern M1 and the second mask pattern M2 have the same line width, the width of the upper line 230A in the first direction may be smaller than the width of the lower line 210A in the second direction. In this case, in order to prevent the sheet resistance of the upper line 230A from increasing, the thickness of the upper line 230A may be greater than the thickness of the lower line 210A.

[0056] Subsequently, a second insulating layer 244 may be formed to fill the space formed by etching the conductive layer 230, the multilayer pattern 220A, and the first insulating layer 242. The second insulating layer 244 may be disposed between the stacked structure of the memory cell 220B and the upper line 230A and between the stacked structure of the first insulating layer pattern 242A and the upper line 230A. The second insulating layer 244 may include various insulating materials, such as silicon oxide, a low-k material, or a combination thereof. Before forming the second insulating layer 244, an insulating spacer (not shown) may also be formed on the sidewalls of the upper line 230A and the memory cell 220B.

[0057] The second mask pattern M2 may be removed in this etching process or through an additional removal process.

[0058] refer to Figure 2E , a portion of the second insulating layer 244 exposed by the upper line 230A may be removed to form a recess R having a predetermined depth in the second insulating layer 244 .

[0059] The recess R may be formed by a wet etching method. In addition, the depth of the recess R may be controlled so that the lower surface of the recess R is located at a level higher than or equal to the upper surface of the memory cell 220B (e.g., the upper surface of the upper electrode layer 229B). Therefore, when the recess R is formed, the sidewalls of the memory cell 220B, in particular the sidewalls of the upper electrode layer 229B, may not be exposed. In this embodiment, since the upper surface of the memory cell 220B contacts the lower surface of the upper line 230A, the lower surface of the recess R may be set at the same height as or above the lower surface of the upper line 230A. In another embodiment, if there is an additional layer (not shown) between the upper line 230A and the memory cell 220B, the lower surface of the recess R may be located at a height equal to or higher than the upper surface of the memory cell 220B and below the lower surface of the upper line 230A.

[0060] In a plan view, the recess R may have a linear shape extending in the second direction between the upper lines 230A. In addition, in a cross-sectional view taken along line XX′, the width of the recess R may decrease from top to bottom. Therefore, in a cross-sectional view taken along line XX′, the lower surface of the recess R may have a shape in which the edge is relatively high and the center is relatively low.

[0061] refer to Figure 2F , you can Figure 2E A sacrificial layer 250 is formed over the resulting structure.

[0062] The sacrificial layer 250 may be formed to a thickness sufficient to fill the recess R. In addition, the sacrificial layer 250 may be formed of a film (eg, a carbon-based film) that is easily removed in a subsequent process. As an example, the sacrificial layer 250 may be formed by coating a spin-on carbon (SOC) layer.

[0063] refer to Figure 2G , the sacrificial layer 250 on the upper line 230A may be removed to form a sacrificial layer pattern 250A filling the recess R.

[0064] The removal of the sacrificial layer 250 may be performed by an etch-back process so that the upper surface of the upper line 230A is exposed. In addition, the removal of the sacrificial layer 250 may be performed so that the upper surface of the sacrificial layer pattern 250A is lowered to a predetermined amount below the upper surface of the upper line 230A. This is to allow the passivation layer pattern (see Figure 2J 260A in the figure) contacts the side structure (e.g., the side of the upper line 230A). In the present embodiment, the lower surface of the sacrificial layer pattern 250A may have substantially the same shape as the lower surface of the recess R. In the cross-sectional view taken along the line XX', the upper surface of the sacrificial layer pattern 250A may have a shape in which the edge is relatively high and the center is relatively low, but the present disclosure is not limited thereto. In another embodiment, the sacrificial layer pattern 250A may have a substantially flat upper surface.

[0065] Subsequently, a passivation layer 260 may be formed over the upper lines 230A and the sacrificial layer patterns 250A.

[0066] The passivation layer 260 can be used to protect the upper line 230A and other similar structures during the subsequent process of removing the sacrificial layer pattern 250A, and can be used to maintain the space formed by removing the sacrificial layer pattern 250A. The passivation layer 260 can be formed of an insulating material and can have a low thickness that enables a gas or plasma to pass through to remove the sacrificial layer pattern 250A. For example, the passivation layer 260 may include an ultra-low temperature oxide (ULTO) layer. In the present embodiment, the passivation layer 260 may have an uneven upper surface that follows the contour present in the lower structure. As a result, the portion of the passivation layer 260 disposed above the sacrificial layer pattern 250A may have a concave shape or a recessed shape that reflects the recessed shape of the sacrificial layer pattern 250A.

[0067] refer to Figure 2H , only the sacrificial layer pattern 250A may be removed while maintaining the passivation layer 260. A space formed by removing the sacrificial layer pattern 250A may form an air gap AG.

[0068] The removal of the sacrificial layer pattern 250A may be performed by using a gas or plasma that passes through the passivation layer 260. When the sacrificial layer pattern 250A includes a carbon-based material (such as SOC), the sacrificial layer pattern 250A may be removed by a process using oxygen plasma (e.g., a photoresist stripping process). As described above, since the lower surface of the sacrificial layer pattern 250A is disposed at a height higher than or equal to the upper surface of the memory cell 220B (particularly, the upper surface of the upper electrode layer 229B), the sidewall of the upper electrode layer 229B may not be exposed. Therefore, even if the upper electrode layer 229B and the sacrificial layer pattern 250A include the same carbon-based material, during the process of removing the sacrificial layer pattern 250A, the electrode layer 229B may not be removed.

[0069] The air gap AG may be filled with air or in a vacuum state. Like the depression R, the air gap AG may have a linear shape extending in the first direction between the upper lines 230A in a plan view. In addition, in a cross-sectional view taken along the line XX', the air gap AG may have a shape substantially the same as that of the sacrificial layer pattern 250A. That is, the lower surface of the air gap AG may have a concave shape with a relatively high edge and a relatively low center. In addition, the upper surface of the air gap AG may have a concave shape with a relatively high edge and a relatively low center, but the upper surface of the air gap AG may be less concave than the lower surface of the air gap AG. In other words, the upper surface of the air gap AG may have a concave shape with a first concavity, and the lower surface of the air gap AG may have a concave shape with a second concavity, which is greater than the first concavity. The lower surface of the air gap AG may be located at a height higher than or equal to that of the upper surface of the memory cell 220B.

[0070] By forming the air gap AG, the capacitance between the upper lines 230A can be reduced. In addition, in addition to the air gap AG, the second insulating layer 244 exists between the upper lines 230A. When the second insulating layer 244 includes a low-k material, the effect of reducing the capacitance can be further improved.

[0071] refer to Fig.2I , a third insulating layer 270 may be formed over the passivation layer 260 .

[0072] Subsequent processes may benefit from having a substantially flat surface to deposit structures thereon. Therefore, when the passivation layer 260 does not have a flat upper surface, for example due to a concave surface disposed above the air gap AG, a third insulating layer 270 may be formed to provide a flat surface. The third insulating layer 270 may be formed to have a thickness sufficient to fill the recessed portion of the passivation layer 260. For reference, when the stacked structure includes the lower line 210A, the upper line 230A, and the memory cell 220B therebetween, a plurality of stacked structures may be repeatedly formed in the vertical direction. In other words, a plurality of stacked structures may be stacked on top of each other to form a multi-layer memory structure.

[0073] The third insulating layer 270 may include various insulating materials, such as silicon oxide, low-k materials, or combinations thereof. The third insulating layer 270 may be formed of substantially the same material as the first insulating layer 242 and / or the second insulating layer 244. When the third insulating layer 270 includes a low-k material, the capacitance between the upper lines 230A may be further reduced.

[0074] refer to Figure 2J A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed until the upper surface of the upper line 230A is exposed. As a result, a passivation layer pattern 260A and a third insulation layer pattern 270A may be formed over the air gap AG.

[0075] The passivation layer pattern 260A may be formed to cover the air gap AG while being attached to and supported by a sidewall structure (e.g., a sidewall of the upper line 230A or an insulating spacer (not shown) of the sidewall of the upper line 230A). The third insulating layer pattern 270A may be present on the passivation layer pattern 260A. The space above the air gap AG may be filled with the passivation layer pattern 260A and the third insulating layer pattern 270A or filled with the passivation layer pattern 260A. The upper surface of the passivation layer pattern 260A or the upper surfaces of the passivation layer pattern 260A and the third insulating layer pattern 270A may be disposed at the same height as the upper surface of the upper line 230A to form a flat surface.

[0076] Thus, a lower surface of the air gap AG may be surrounded by the second insulating layer 244 , and an upper surface of the air gap AG may be covered by the passivation layer pattern 260A and the third insulating layer pattern 270A.

[0077] Figures 1A to 1C or Figure 2J Only one stacked structure is shown. However, multiple stacked structures can be repeatedly stacked in the vertical direction, thereby increasing the integration of the memory device. However, stacked structures adjacent in the vertical direction can share an upper line or a lower line. For this reason, if the word line is located at a lower position and the bit line is located at a higher position in one stacked structure, then in another stacked structure immediately above the lower stacked structure, the bit line can be located at a lower position and the word line can be located at a higher position. In other words, stacked structures adjacent in the vertical direction can mirror each other in the vertical direction. An embodiment of this structure will be described by reference to FIG. 3A to FIG. 3C .

[0078] FIG. 3A to FIG. 3C is a diagram illustrating a semiconductor memory according to another embodiment of the present disclosure. Figure 3A It is a floor plan. Figure 3B is along Figure 3A A cross-sectional view taken along line XX′. Figure 3C is along Figure 3A A cross-sectional view taken along line YY′.

[0079] refer to FIG. 3A to FIG. 3C , the memory device of this embodiment may include a plurality of stacked structures 310, 320, 330, and 340 sequentially stacked above a substrate 300. In this embodiment, four stacked structures 310, 320, 330, and 340 are formed, but the number of stacked structures may be variously changed. For ease of description, the plurality of stacked structures 310, 320, 330, and 340 may be referred to as a first stacked structure 310, a second stacked structure 320, a third stacked structure 330, and a fourth stacked structure 340, according to the distance from the substrate 300.

[0080] The first stack structure 310 may include: a plurality of first lower lines 311, which are arranged above the substrate 300 and extend in a first direction parallel to the line XX'; a plurality of first upper lines 313, which are arranged above the first lower lines 311 and extend in a second direction parallel to the line YY'; a plurality of first storage cells 312, which are arranged between the first lower lines 311 and the first upper lines 313 and overlap with their intersection areas; and a first interlayer insulating layer 314, which fills the space between the first lower lines 311, the space between the first storage cells 312, and the space between the first upper lines 313, and has a first air gap AG1 located between the first upper lines 313.

[0081] The first stacked structure 310 may be Figures 1A to 1C The stacked structures are substantially the same. Therefore, the thickness T1 of the first lower line 311 may be less than the thickness T2 of the first upper line 313. The first air gap AG1 may have a linear shape extending in the second direction, and its lower surface may be disposed at a height higher than or equal to the upper surface of the first storage unit 312. The cross-sectional shape of the first air gap AG1 is shown as having an elliptical shape. However, in another embodiment, the first air gap AG1 may have another shape, for example, Figure 2J The first interlayer insulating layer 314 may include various insulating materials, and in particular, may include a low-k material.

[0082] The second stack structure 320 may include: a plurality of second lower lines 321, which are arranged above the first stack structure 310 and extend in the second direction; a plurality of second upper lines 323, which are arranged above the second lower lines 321 and extend in the first direction; a plurality of second storage cells 322, which are arranged between the second lower lines 321 and the second upper lines 323 and overlap with their intersection areas; and a second interlayer insulating layer 324, which fills the space between the second lower lines 321, the space between the second storage cells 322, and the space between the second upper lines 323, and has a second air gap AG2 located between the second upper lines 323.

[0083] The second stack structure 320 may share one line with the first stack structure 310. To this end, unlike the first stack structure 310, in the second stack structure 320, the second lower line 321 disposed below the second storage unit 322 may extend in the second direction, and the second upper line 323 disposed above the second storage unit 322 may extend in the first direction.

[0084] The manufacturing process of the second stack structure 320 may be substantially the same as the manufacturing process of the first stack structure 310, but the lines extending in the second direction (i.e., the second lower lines 321) may be patterned first, and the lines extending in the first direction (i.e., the second upper lines 323) may be patterned subsequently. More specifically, after forming the conductive layer for the lower lines and the multilayer structure for the memory cells, the process of using Figure 2C The second mask pattern M2 instead of Figure 2A The etching process of the first mask pattern M1 is performed to form the lower line and the multi-layer pattern. Then, after forming the conductive layer for the upper line over the lower line and the multi-layer pattern, the etching process using the first mask pattern M2 can be performed. Figure 2A An etching process is performed on the first mask pattern M1 to form upper lines and memory cells.

[0085] In the second stack structure 320, the thickness of the second upper line 323 may be greater than the thickness of the second lower line 321. Since the same manufacturing process as that of the first stack structure 310 is repeated (except for the direction of the mask pattern), the thickness of the second lower line 321 may be the same as the thickness of the first lower line 311, as shown by reference numeral T1. In addition, the thickness of the second upper line 323 may be the same as the thickness of the first upper line 313, as shown by reference numeral T2.

[0086] Since the first upper line 313 and the second lower line 321 are in direct contact with each other, the first upper line 313 and the second lower line 321 can be effectively used as the same line in the operation of the memory device. If the first upper line 313 is used as a bit line, the second lower line 321 can be used as a bit line, and if the first upper line 313 is used as a word line, the second lower line 321 can be used as a word line. That is, the first stacked structure 310 and the second stacked structure 320 can share a word line or a bit line. However, in order to prevent the defects as described above, the first air gap AG1 can be located between the first upper lines 313, but not between the second lower lines 321.

[0087] In addition, since the second air gap AG2 is disposed between the second upper lines 323 in the second stacked structure 320, the second air gap AG2 may have a linear shape extending in the first direction. The lower surface of the second air gap AG2 may be located at a height higher than or equal to the upper surface of the second storage unit 322. The cross-sectional shape of the second air gap AG2 is shown as having a circular shape. However, in another embodiment, the second air gap AG2 may have another shape, for example, Figure 2J The second interlayer insulating layer 324 may include various insulating materials, and in particular, may include a low-k material.

[0088] The third stack structure 330 may include: a plurality of third lower lines 331 disposed above the second stack structure 320 and extending in the first direction; a plurality of third upper lines 333 disposed above the third lower lines 331 and extending in the second direction; a plurality of third storage cells 332 disposed between the third lower lines 331 and the third upper lines 333 and disposed overlapping with their crossing regions; and a third interlayer insulating layer 334 filling spaces between the third lower lines 331, spaces between the third storage cells 332, and spaces between the third upper lines 333. A third air gap AG3 may be located between the third upper lines 333.

[0089] The third stack structure 330 may share a word line or a bit line with the second stack structure 320. To this end, the third stack structure 300 may have substantially the same structure as the first stack structure 310, and a detailed description will be omitted for the sake of brevity.

[0090] The fourth stack structure 340 may include: a plurality of fourth lower lines 341 disposed above the third stack structure 330 and extending in the second direction; a plurality of fourth upper lines 343 disposed above the fourth lower lines 341 and extending in the first direction; a plurality of fourth storage cells 342 disposed between the fourth lower lines 341 and the fourth upper lines 343 and disposed overlapping with their intersection regions; and a fourth interlayer insulating layer 344 filling spaces between the fourth lower lines 341, spaces between the fourth storage cells 342, and spaces between the fourth upper lines 343. A fourth air gap AG4 may be located between the fourth upper lines 343.

[0091] The fourth stack structure 340 may share a word line or a bit line with the third stack structure 330. To this end, the fourth stack structure 340 may have substantially the same structure as the second stack structure 320, and a detailed description will be omitted for the sake of brevity.

[0092] In this way, odd-numbered stacked structures among a plurality of stacked structures stacked in the vertical direction can have the same structure, and even-numbered stacked structures can have the same structure. Bit lines or word lines of stacked structures adjacent to each other in the vertical direction can contact each other so that they share a conductive path. The upper line of the lower stacked structure and the lower line of the upper stacked structure adjacent to the lower stacked structure in the vertical direction can extend in the same direction.

[0093] As shown in the following table, it has been confirmed through experiments that FIG. 3A to FIG. 3C The air gaps formed between the wires in the stacked structure shown have the effect of reducing capacitance.

[0094] Table 1 shows the capacitance values ​​measured in five different cases. Each case includes Figures 3A-3CThe stacking of four stacked structures stacked on each other as shown, and the capacitance using specific insulating materials was measured. In case 1, silicon oxide is used as an interlayer insulating layer between the upper wires of each stacked structure and between the lower wires of each stacked structure, and there is no air gap. In case 2, low-k material is used as an interlayer insulating layer between the upper wires of each stacked structure and between the lower wires of each stacked structure, and there is no air gap. In case 3, low-k material is used as an interlayer insulating layer between the upper wires of each stacked structure and between the lower wires of each stacked structure, and there is an air gap between the lower wires of each stacked structure. In case 4, low-k material is used as an interlayer insulating layer between the upper wires of each stacked structure and between the lower wires of each stacked structure, and an air gap is formed between the upper wires of each stacked structure. In case 5, low-k material is used as an interlayer insulating layer between the upper wires of each stacked structure and between the lower wires of each stacked structure, and an air gap is formed between the upper wires of each stacked structure and between the lower wires of each stacked structure. The capacitance values ​​of these structures in femtofarads are shown in the bottom row of Table 1.

[0095] [Table 1]

[0096]

[0097] Table 1 shows that capacitance is reduced by both air gap and low-k material.

[0098] Specifically, the capacitance of case 4 where an air gap exists between the upper lines is smaller than the capacitance of case 3 where an air gap exists between the lower lines.

[0099] If the process can be precisely controlled to prevent process defects, the lowest level of capacitance can be achieved when air gaps exist both between the lower lines and between the upper lines as in Case 5.

[0100] However, if it is difficult to precisely control the process, air gaps may be formed only between the upper lines as in Case 4, thereby preventing process defects while still achieving a certain amount of capacitance reduction.

[0101] In summary, according to the memory device and the manufacturing method thereof of the present embodiment, by placing an air gap between the upper line in the stacked structure including the lower line and the memory cell disposed at the intersection of the upper line and the lower line, process defects can be prevented, and external capacitance can be reduced to prevent data writing caused by a read operation. In addition, the integration of the semiconductor device can be increased by stacking a plurality of stacked structures in the vertical direction. According to the present embodiment, even if a plurality of stacked structures are stacked in the vertical direction, there is still an advantage of being able to reduce capacitance without increasing the difficulty of the process.

[0102] The above and other memory circuits or semiconductor devices based on the disclosed technology may be used in a variety of devices or systems. Figure 4-Figure 8Some examples are provided of devices or systems that may implement the memory circuits disclosed herein.

[0103] Figure 4 is an example of a configuration diagram of a microprocessor implementing a storage circuit based on the disclosed technology.

[0104] refer to Figure 4 , the microprocessor 1000 may perform tasks for controlling and adjusting a series of processes of receiving data from various external devices, processing data, and outputting processing results to external devices. The microprocessor 1000 may include a storage unit 1010, an operation unit 1020, and a control unit 1030, etc. The microprocessor 1000 may be various data processing units such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0105] The storage unit 1010 is a component that stores data in the microprocessor 1000, such as a processor register or registers, etc. The storage unit 1010 may include a data register, an address register, a floating point register, etc. In addition, the storage unit 1010 may include various registers. The storage unit 1010 may perform the following functions: temporarily storing data to be operated by the operation unit 1020, result data of the operation, and addresses where data for the operation are stored.

[0106] According to an embodiment, the memory cell 1010 may include one or more of the above-mentioned semiconductor devices. For example, the memory cell 1010 may include: a plurality of lower lines, which are arranged above the substrate and extend in a first direction; a plurality of upper lines, which are arranged above the lower lines and extend in a second direction intersecting the first direction; a plurality of memory cells, which are arranged between the lower lines and the upper lines and overlap with the intersection area of ​​the lower lines and the upper lines; and an air gap, which is located between the upper lines and extends in the second direction. In this way, in the memory cell 101, the integration can be increased, and the data storage characteristics can be improved. As a result, the size of the microprocessor 1000 can be reduced and its operating characteristics can be improved.

[0107] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and the like.

[0108] The control unit 1030 may receive signals from the storage unit 1010 , the operation unit 1020 , and external devices of the microprocessor 1000 , perform extraction and decoding of commands, and control signal input and output of the microprocessor 1000 , and execute a process represented by a program.

[0109] The microprocessor 1000 according to the present embodiment may further include a cache memory unit 1040 that can temporarily store data to be input from an external device other than the storage unit 1010 or data to be output to an external device. In this case, the cache memory unit 1040 can exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0110] Figure 5 is an example of a configuration diagram of a processor implementing a storage circuit based on the disclosed technology.

[0111] refer to Figure 5 , the processor 1100 can improve performance and realize multi-functions by including various functions in addition to the functions of a microprocessor, which performs tasks for controlling and adjusting a series of processes for receiving data from various external devices, processing data, and outputting processing results to external devices. The processor 1100 may include a core unit 1110 used as a microprocessor, a cache memory unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal devices and external devices. The processor 1100 may include various systems on chip (SoCs) such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0112] The core unit 1110 of the present embodiment is a component that performs an arithmetic logic operation on data input from an external device, and may include a storage unit 1111 , an operation unit 1112 , and a control unit 1113 .

[0113] The storage unit 1111 is a component that stores data in the processor 1100, such as a processor register or register. The storage unit 1111 may include a data register, an address register, a floating point register, etc. In addition, the storage unit 1111 may include various registers. The storage unit 1111 may perform the following functions: temporarily store data to be operated by the operation unit 1112, the result data of the operation, and the address where the data for the operation is stored. The operation unit 1112 is a component that performs operations in the processor 1100. The operation unit 1112 may perform four arithmetic operations, logical operations according to the result of the control unit 1113 decoding the command, etc. The operation unit 1112 may include at least one arithmetic logic unit (ALU), etc. The control unit 1113 may receive signals from the storage unit 1111, the operation unit 1112, and the external device of the processor 1100, perform extraction and decoding of commands, and control the signal input and output of the processor 1100, and run the processing represented by the program.

[0114] The cache memory unit 1120 is a component that temporarily stores data to compensate for the difference in data processing speed between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache memory unit 1120 may include a main storage part 1121, a secondary storage part 1122, and a tertiary storage part 1123. Generally, the cache memory unit 1120 includes the main storage part 1121 and the secondary storage part 1122, and in the case where a high storage capacity is required, a tertiary storage part 1123 may be included. As the situation requires, the cache memory unit 1120 may include an increased number of storage parts. That is, the number of storage parts included in the cache memory unit 1120 may be changed according to the design. The speeds at which the main storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 store and recognize data may be the same or different. In the case where the speeds of the respective storage parts 1121, 1122, and 1123 are different, the speed of the main storage part 1121 may be the largest. At least one of the main storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit 1120 may include one or more of the semiconductor devices according to the embodiments described above. For example, the cache memory unit 1120 may include: a plurality of lower lines, which are arranged above the substrate and extend in a first direction; a plurality of upper lines, which are arranged above the lower lines and extend in a second direction intersecting the first direction; a plurality of storage cells, which are arranged between the lower lines and the upper lines and overlap with the intersection area of ​​the lower lines and the upper lines; and an air gap, which is located between the upper lines and extends in the second direction. In this way, the integration degree can be increased, and the data storage characteristics in the cache memory unit 1120 can be improved. As a result, the size of the processor 1100 can be reduced and its operating characteristics can be improved.

[0115] Despite Figure 511 shows that the main storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 are all configured inside the cache memory unit 1120, but it should be noted that the main storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit can all be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device can be compensated. At the same time, it should be noted that the main storage part 1121 of the cache memory unit 1120 can be set inside the core unit 1110, while the secondary storage part 1122 and the tertiary storage part 1123 can be configured outside the core unit 1110 to enhance the function of compensating for the difference in data processing speed. In another embodiment, the main storage part 1121 and the secondary storage part 1122 can be set inside the core unit 1110, while the tertiary storage part 1123 can be set outside the core unit 1110.

[0116] The bus interface 1130 is a component that connects the core unit 1110 , the cache unit 1120 , and external devices and allows data to be efficiently transferred.

[0117] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or may be connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the core unit 1110 described above. In the case where the processor 1100 includes a plurality of core units 1110, a main storage part 1121 of the cache memory unit 1120 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110, and a secondary storage part 1122 and a tertiary storage part 1123 may be configured outside the plurality of core units 1110 in a manner of being shared through the bus interface 1130. The processing speed of the main storage part 1121 may be greater than the processing speeds of the secondary storage part 1122 and the tertiary storage part 1123. In another embodiment, the main storage part 1121 and the secondary storage part 1122 can be configured in each core unit 1110 corresponding to the number of multiple core units 1110, and the tertiary storage part 1123 can be configured outside the multiple core units 1110 in a manner shared through the bus interface 1130.

[0118] The processor 1100 according to the present embodiment may further include: an embedded storage unit 1140 for storing data, a communication module unit 1150 that can send data to an external device and receive data from an external device in a wired or wireless manner, a memory control unit 1160 that drives an external storage device, and a media processing unit 1170 that processes data processed in the processor 1100 or data input from an external input device and outputs the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of different modules and devices. In this case, the added plurality of modules can exchange data with the core unit 1110 and the cache memory unit 1120 and with each other through the bus interface 1130.

[0119] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), and memory with similar functions to the above memory, etc. Non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memory with similar functions.

[0120] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0121] The memory control unit 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, for example, devices that can control IDE (Integrated Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (International Personal Computer Memory Card Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC), and Compact Flash (CF) Card, etc.

[0122] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external input device in the form of images, voices, and other forms, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), a high-definition multimedia interface (HDMI) controller, and the like.

[0123] Figure 6 is an example of a configuration diagram of a system implementing a storage circuit based on the disclosed technology.

[0124] refer to Figure 6 , the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems that use a processor to operate, such as computers, servers, PDAs (personal digital assistants), portable computers, network tablets, wireless phones, mobile phones, smart phones, digital music players, PMPs (portable multimedia players), cameras, global positioning systems (GPS), video cameras, voice recorders, telematics, audio-visual (AV) systems, and smart TVs, etc.

[0125] The processor 1210 may decode input commands, process operations, comparisons, etc. for data stored in the system 1200, and control these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single / multi-core processor, a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), etc.

[0126] The main memory device 1220 is a memory that can temporarily store, call and run program codes or data from the auxiliary memory device 1230 when running a program, and can save the stored content even when the power is cut off. The main memory device 1220 may include one or more semiconductor devices according to the above-mentioned embodiments. For example, the main memory device 1220 may include: a plurality of lower lines, which are arranged on a substrate and extend in a first direction; a plurality of upper lines, which are arranged above the lower lines and extend in a second direction intersecting the first direction; a plurality of storage cells, which are arranged between the lower lines and the upper lines and overlap with the intersection area of ​​the lower lines and the upper lines; and an air gap, which is located between the upper lines and extends in the second direction. In this way, the integration can be increased, and the data storage characteristics in the main memory device 1220 can be improved. As a result, the size of the system 1200 can be reduced and its operating characteristics can be improved.

[0127] In addition, the main memory device 1220 may also include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type, etc., in which all contents are erased when the power is cut off. Different from this, the main memory device 1220 may not include the semiconductor device according to the embodiment, but may include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type, etc., in which all contents are erased when the power is cut off.

[0128] The auxiliary memory device 1230 is a memory device for storing program code or data. Although the speed of the auxiliary memory device 1230 is slower than that of the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The auxiliary memory device 1230 may include one or more semiconductor devices according to the above-mentioned embodiments. For example, the auxiliary memory device 1230 may include: a plurality of lower wires, which are arranged above the substrate and extend in a first direction; a plurality of upper wires, which are arranged above the lower wires and extend in a second direction intersecting the first direction; a plurality of storage cells, which are arranged between the lower wires and the upper wires and overlap with the intersection area of ​​the lower wires and the upper wires; and an air gap, which is located between the upper wires and extends in the second direction. Thus, the integration can be increased, and the data storage characteristics in the auxiliary memory device 1230 can be improved. As a result, the size of the system 1200 can be reduced and its operating characteristics can be improved.

[0129] In addition, the auxiliary storage device 1230 may also include a data storage system (see Figure 7The auxiliary memory device 1230 may include a magnetic tape, a magnetic disk, a laser disk, a magneto-optical disk, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card. Different from this, the auxiliary memory device 1230 may not include the semiconductor device according to the embodiment, but may include a data storage system (see Figure 7 1300 in the reference numeral 1300), such as a magnetic tape, a magnetic disk, an optical laser disk, a magneto-optical disk using both magnetic and optical properties, a solid state disk (SSD), a USB memory (Universal Serial Bus memory), a Secure Digital (SD) card, a mini Secure Digital (mSD) card, a micro Secure Digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a Memory Stick card, a Smart Media (SM) card, a MultiMedia Card (MMC), an embedded MMC (eMMC), and a Compact Flash (CF) card.

[0130] The interface device 1240 can be used to perform the exchange of commands and data between the system 1200 of the present embodiment and the external device. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HIDs), and communication devices. The communication device may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0131] Figure 7 is an example of a configuration diagram of a data storage system implementing a storage circuit based on the disclosed technology.

[0132] refer to Figure 7, the data storage system 1300 may include a storage device 1310 having a non-volatile characteristic as a component for storing data, a controller 1320 for controlling the storage device 1310, an interface 1330 for connecting with an external device, and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read only memory (CDROM), a digital versatile disk (DVD), and a solid state disk (SSD), and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

[0133] The storage device 1310 may include a nonvolatile memory that semi-permanently stores data. The nonvolatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM).

[0134] The controller 1320 may control data exchange between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing the following operations: processing a command input from the outside of the data storage system 1300 through the interface 1330, and the like.

[0135] The interface 1330 is used to perform the exchange of commands and data between the data storage system 1300 and the external device. In the case where the data storage system 1300 is a card type, the interface 1330 can be compatible with interfaces used in devices such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (mSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, etc., or compatible with interfaces used in devices similar to the above devices. In the case where the data storage system 1300 is a disk type, the interface 1330 can be compatible with interfaces such as IDE (integrated electronic devices), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association) and USB (universal serial bus), etc., or compatible with interfaces similar to the above interfaces. The interface 1330 can be compatible with one or more interfaces having different types from each other.

[0136] The temporary storage device 1340 can temporarily store data according to the diversity and high performance of the interface with the external device, the controller and the system to effectively transmit data between the interface 1330 and the storage device 1310. The temporary storage device 1340 for temporarily storing data may include one or more of the semiconductor devices according to the above-mentioned embodiments. The temporary storage device 1340 may include: a plurality of lower wires, which are arranged above the substrate and extend in a first direction; a plurality of upper wires, which are arranged above the lower wires and extend in a second direction intersecting the first direction; a plurality of storage cells, which are arranged between the lower wires and the upper wires and overlap with the intersection area of ​​the lower wires and the upper wires; and an air gap, which is located between the upper wires and extends in the second direction. Thus, the integration can be increased, and the data storage characteristics in the temporary storage device can be improved. As a result, the size of the data storage system can be reduced and its operating characteristics can be improved.

[0137] Figure 8 is an example of a configuration diagram of a memory system implementing a memory circuit based on the disclosed technology.

[0138] refer to Figure 8 , the storage system 1400 may include a memory 1410 having a nonvolatile characteristic as a component for storing data, a memory controller 1420 for controlling the memory 1410, and an interface 1430 for connecting with an external device, etc. The storage system 1400 may be a card type such as a solid state disk (SSD), a USB memory (Universal Serial Bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital card (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0139] The memory 1410 for storing data may include one or more of the semiconductor devices according to the above-mentioned embodiments. For example, the memory 1410 may include: a plurality of lower lines arranged above the substrate and extending in a first direction; a plurality of upper lines arranged above the lower lines and extending in a second direction intersecting the first direction; a plurality of storage cells arranged between the lower lines and the upper lines and arranged overlapping with the intersection area of ​​the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction. Thus, the integration can be increased, and the data storage characteristics in the memory 1410 can be improved. As a result, the size of the storage system can be reduced and its operating characteristics can be improved.

[0140] In addition, according to the present embodiment, the memory 1410 may also include a ROM (read-only memory) having non-volatile characteristics, a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), and a magnetic random access memory (MRAM), etc.

[0141] The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing the following operations: processing a command input from the outside of the memory system 1400 through the interface 1430.

[0142] The interface 1430 is used to perform command and data exchange between the storage system 1400 and an external device. The interface 1430 may be compatible with interfaces used in devices such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (mSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, or the like, or with interfaces used in devices similar to the above devices. The interface 1430 may be compatible with one or more interfaces having different types from each other.

[0143] The memory system 1400 according to the present embodiment may further include a buffer memory 1440 for efficiently transmitting data between the interface 1430 and the memory 1410 according to the diversification and high performance of the interface with the external device, the memory controller, and the memory system. For example, the buffer memory 1440 for temporarily storing data may include one or more of the semiconductor devices according to the embodiments described above. The buffer memory 1440 may include: a plurality of lower lines, which are arranged above the substrate and extend in a first direction; a plurality of upper lines, which are arranged above the lower lines and extend in a second direction intersecting the first direction; a plurality of storage cells, which are arranged between the lower lines and the upper lines and overlap with the intersection area of ​​the lower lines and the upper lines; and an air gap, which is located between the upper lines and extends in the second direction. Thus, the integration degree can be increased, and the data storage characteristics in the buffer memory 1440 can be improved. As a result, the size of the memory system 1400 can be reduced and its operating characteristics can be improved.

[0144] In addition, the buffer memory 1440 according to the present embodiment may also include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics. Different from this, the buffer memory 1440 may not include the semiconductor device according to the embodiment, but may include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics.

[0145] Above Figure 4-8 The features of the examples of electronic devices or systems based on the memory devices disclosed in this document can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebooks or laptop computers, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0146] Although this patent document contains many details, these details should not be interpreted as limitations on the scope of any invention or the content claimed for protection, but should be interpreted as specific descriptions of the features of a specific embodiment of a specific invention. Certain features described in the context of different embodiments in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0147] Similarly, while operations are depicted in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed to achieve the desired results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0148] Only some implementations and examples are described. Other implementations, enhancements, and changes can be made based on what is described and shown in this patent document.

Claims

1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising: a plurality of lower wires disposed above the substrate and extending in a first direction; a plurality of upper lines disposed above the lower lines and extending in a second direction intersecting the first direction; a plurality of storage units disposed between the lower line and the upper line and arranged to overlap with a crossover region of the lower line and the upper line; as well as an air gap located between the upper lines and extending in the second direction, Wherein, a lower surface of the air gap is located at a height equal to or higher than upper surfaces of the plurality of storage units.

2. The electronic device according to claim 1, wherein: The air gap is surrounded by insulating material between the upper lines.

3. The electronic device according to claim 2, wherein: The insulating material includes a low-k material.

4. The electronic device according to claim 1, wherein: The thickness of the air gap is equal to or smaller than the thickness of the upper line.

5. The electronic device according to claim 1, wherein: The thickness of the upper line is greater than the thickness of the lower line.

6. The electronic device according to claim 1, wherein: The lower surface of the air gap has a concave shape in which an edge adjacent to the upper line is higher than a center, and the upper surface of the air gap is less concave than the lower surface of the air gap.

7. The electronic device according to claim 6, wherein: An upper surface of the air gap is lower than an upper surface of the upper line.

8. The electronic device according to claim 7, wherein: The semiconductor memory further comprises: a first insulating layer disposed below a lower surface of the air gap; and A second insulating layer is disposed over the upper surface of the air gap.

9. The electronic device according to claim 8, wherein: The second insulating layer includes two layers, and A first layer of the two layers includes a material different from that of the first insulating layer, and a second layer of the two layers includes a material the same as that of the first insulating layer.

10. The electronic device according to claim 8, wherein: The second insulating layer has an upper surface coplanar with an upper surface of the upper line.

11. The electronic device according to claim 1, wherein: The memory cell includes a phase change material.

12. An electronic device comprising a semiconductor memory, the semiconductor memory comprising a plurality of stacked structures stacked above a substrate, wherein: A first stacked structure among the plurality of stacked structures comprises: a plurality of first lower wires extending in a first direction; a plurality of first upper lines formed above the first lower lines and extending in a second direction intersecting the first direction; a plurality of first storage cells disposed between the first lower line and the first upper line and disposed so as to overlap with a crossing region of the first lower line and the first upper line; and a first air gap located between the first upper lines and extending in the second direction, and The second stacked structure includes: a plurality of second lower wires extending in the second direction; a plurality of second upper lines formed above the second lower lines and extending in the first direction; a plurality of second storage cells disposed between the second lower line and the second upper line and disposed so as to overlap with a crossing region of the second lower line and the second upper line; and A second air gap located between the second upper lines and extending in the first direction wherein a lower surface of the first air gap is located at a height equal to or higher than an upper surface of the first storage unit, and A lower surface of the second air gap is located at a height equal to or higher than an upper surface of the second storage unit.

13. The electronic device according to claim 12, wherein: An upper surface of the first air gap is located at a height equal to or lower than a lower surface of the second lower line.

14. The electronic device according to claim 12, wherein: The first air gap and the second air gap are surrounded by insulating material.

15. The electronic device according to claim 14, wherein: The insulating material includes a low-k material.

16. The electronic device according to claim 12, wherein: The thickness of the first upper line is greater than the thickness of the first lower line, and The thickness of the second upper line is greater than the thickness of the second lower line.

17. The electronic device according to claim 16, wherein: The thickness of the first upper line is equal to the thickness of the second upper line, and The thickness of the first lower line is equal to the thickness of the second lower line.

18. The electronic device according to claim 12, wherein: The first upper line is in direct contact with the second lower line.

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