Display substrate, method for manufacturing the same, and display device including the display substrate

Abstract

The display substrate may include a substrate and a wiring disposed on the substrate. The wiring may include: a metal oxide layer including at least one oxide of tantalum (Ta), niobium (Nb), and titanium (Ti); and a metal layer disposed on the metal oxide layer and including copper (Cu). The thickness of the metal oxide layer may be about 1000 Å to about 2000 Å.

Description

Technical Field

[0001] Embodiments relate to display devices, and more particularly, to a display substrate including wirings, a method of manufacturing the display substrate, and an organic light emitting display device including the display substrate. Background Art

[0002] In general, a thin film transistor (TFT) may be used as a switching element for independently driving each pixel in a flat panel display device such as a liquid crystal display (LCD) and an organic light emitting display (OLED). In addition to the thin film transistor and a pixel electrode connected thereto, a display substrate including the thin film transistor may include various wirings, such as a gate line configured to transmit a gate signal to the thin film transistor and a data line configured to transmit a data voltage.

[0003] As the area of ​​a display device including such a display substrate becomes larger, the length of the wiring becomes longer, making it necessary to form the wiring by using a material having low resistance. In order to increase the transmission speed of the wiring, copper (Cu) or the like having relatively low resistance may be used as a material for the wiring.

[0004] However, when copper is used as a material for wiring, the copper layer may be easily peeled off due to poor bonding strength between the copper layer and the substrate, thereby possibly causing defects in the gate line. Meanwhile, when a titanium (Ti) layer is formed between the copper layer and the substrate to increase bonding strength between the copper layer and the substrate, during the process of manufacturing the display substrate, copper may diffuse into the titanium layer in a high temperature process, thereby increasing resistance of the wiring. Summary of the invention

[0005]

Technical issues

[0006] An object of the present invention is to provide a display substrate including wirings having relatively low resistance.

[0007] An object of the present invention is to prevent the resistance of wiring from increasing in a manufacturing process of a display substrate.

[0008]

Technical solution

[0009] In order to achieve the above-mentioned purpose of the present invention, the display substrate may include a substrate and a wiring disposed on the substrate. The wiring may include: a metal oxide layer including at least one oxide of tantalum (Ta), niobium (Nb) and titanium (Ti), and a metal layer disposed on the metal oxide layer and including copper (Cu), and the thickness of the metal oxide layer may be about to about

[0010] In an implementation, a side surface of the metal oxide layer may be continuously formed from a side surface of the metal layer.

[0011] In an embodiment, the metal layer may be disposed directly on the metal oxide layer.

[0012] In an implementation, the wiring may further include an intermetallic compound layer disposed between the metal oxide layer and the metal layer.

[0013] In an embodiment, the thickness of the intermetallic compound layer may be less than or equal to about

[0014] In an embodiment, the intermetallic compound layer may include an intermetallic compound including copper and at least one of tantalum, niobium, and titanium.

[0015] In an embodiment, a side surface of the metal oxide layer, a side surface of the intermetallic compound layer, and a side surface of the metal layer may be continuously formed.

[0016] In an embodiment, the thickness of the metal layer may be about to about

[0017] In one embodiment, the substrate comprises silicon oxide (SiO x ).

[0018] In order to achieve the above-mentioned object of the present invention, a method for manufacturing a display substrate may include: sequentially stacking a first metal layer including at least one of tantalum (Ta), niobium (Nb) and titanium (Ti) and a second metal layer including copper (Cu) on a substrate, forming wiring by partially etching the first metal layer and the second metal layer, and converting the first metal layer into a metal oxide layer by oxidation.

[0019] In an embodiment, the first metal layer may be converted into a metal oxide layer by natural oxidation.

[0020] In an embodiment, the thickness of the metal oxide layer may be about to about

[0021] In an embodiment, the first metal layer may be completely converted into a metal oxide layer by oxidation.

[0022] In an embodiment, the first metal layer may be partially converted into a metal oxide layer by oxidation.

[0023] In an embodiment, the method may further include converting a remaining portion of the first metal layer into an intermetallic compound layer by reacting the remaining portion of the first metal layer that has not been oxidized with the second metal layer.

[0024] In an embodiment, the thickness of the intermetallic compound layer may be less than or equal to about

[0025] In an embodiment, after partially converting the first metal layer into the metal oxide layer, converting the remaining portion of the first metal layer into the intermetallic compound layer may be performed.

[0026] In order to achieve the above-mentioned purpose of the present invention, a display device may include a substrate, a gate line disposed on the substrate, a thin film transistor including an active pattern, and a gate electrode overlapping the active pattern and protruding from the gate line, and a light-emitting element connected to the thin film transistor. The gate line may include: a metal oxide layer including at least one oxide of tantalum (Ta), niobium (Nb) and titanium (Ti), and a metal layer disposed on the metal oxide layer and including copper (Cu), and the thickness of the metal oxide layer may be about to about

[0027] In an implementation, a side surface of the metal oxide layer may be continuously formed from a side surface of the metal layer.

[0028] In an embodiment, the metal layer may be disposed directly on the metal oxide layer.

[0029]

Beneficial Effects

[0030] The wiring of the display substrate according to the embodiment may include: a metal oxide layer including at least one oxide of tantalum (Ta), niobium (Nb), and titanium (Ti), and a metal layer disposed on the metal oxide layer and including copper (Cu), and the thickness of the metal oxide layer may be about to about Accordingly, the wiring of the display substrate can have a relatively low resistance.

[0031] In the method for manufacturing a display substrate according to an embodiment, a first metal layer including at least one of tantalum (Ta), niobium (Nb), and titanium (Ti) and a second metal layer including copper (Cu) may be sequentially stacked on a substrate, and the first metal layer may be converted into a metal oxide layer by natural oxidation. Therefore, an additional process for converting the first metal layer into a metal oxide layer in the formation of wiring may not be required. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 FIG. 1 is a layout diagram showing a display substrate according to an embodiment of the present invention.

[0033] Figure 2 FIG. 1 is a cross-sectional view showing a display substrate according to an embodiment of the present invention.

[0034] Figure 3 FIG. 1 is a cross-sectional view showing wiring of a display substrate according to an embodiment of the present invention.

[0035] Figure 4 , Figure 5, Figure 6 , Figure 7 and Figure 8 is a cross-sectional view showing a method for manufacturing a display substrate according to one embodiment of the present invention.

[0036] Fig. 9 FIG. 1 is a cross-sectional view showing a display substrate according to another embodiment of the present invention.

[0037] Fig.10 FIG. 1 is a cross-sectional view showing wiring of a display substrate according to another embodiment of the present invention.

[0038] Fig.11 , Fig.12 , Fig.13 and Fig.14 is a cross-sectional view showing a method for manufacturing a display substrate according to another embodiment of the present invention.

[0039] Fig.15 is a cross-sectional view showing a display device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0040] Hereinafter, a display substrate, a method of manufacturing the display substrate, and a display device according to embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

[0041] In the following, reference will be made to Figure 1 and Figure 2 A configuration of a display substrate according to an embodiment of the present invention is described.

[0042] Figure 1 FIG. 1 is a layout diagram showing a display substrate according to an embodiment of the present invention. Figure 2 1 is a cross-sectional view showing a display substrate according to an embodiment of the present invention. For example, Figure 2 Can be along Figure 1 A cross-sectional view of a display substrate taken along line II-II'.

[0043] See also Figure 1 and Figure 2 According to one embodiment of the present invention, the display substrate may include a substrate 110, a thin film transistor TFT, wirings (such as a gate line GW and a data line DW) disposed on the substrate 110, and a pixel electrode 180 connected to the thin film transistor TFT. Figure 1 and Figure 2 Only one thin film transistor has been shown in FIG. 1 , but at least two thin film transistors may be provided for each pixel. For example, a switch thin film transistor and a drive thin film transistor may be provided for each pixel. A capacitor may be electrically connected between the switch thin film transistor and the drive thin film transistor.

[0044] A transparent insulating substrate may be used as the substrate 110. For example, the substrate 110 may include a substrate including silicon oxide (SiO x ) and other glass.

[0045] The active pattern 120 may be disposed on the substrate 110. Figure 2 , but in one embodiment, a buffer layer or the like may be disposed between the substrate 110 and the active pattern 120 to block diffusion of impurities through the substrate 110 .

[0046] In one embodiment, the active pattern 120 may include a silicon compound such as polysilicon. A source region and a drain region including p-type or n-type impurities may be formed at both ends of the active pattern 120, respectively. In another embodiment, the active pattern 120 may include an oxide semiconductor such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin zinc oxide (ITZO).

[0047] The gate insulating layer 130 may be disposed on the substrate 110 to cover the active pattern 120. The gate insulating layer 130 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y )wait.

[0048] The gate line GW may be disposed on the gate insulating layer 130. The gate line GW may transmit a gate signal and may extend in a row-upward direction. The gate line GW may include a gate electrode 140 having a shape protruding from the gate line GW.

[0049] The gate line GW may include metal oxide layers 141 a and 141 b , and metal layers 142 a and 142 b disposed on the metal oxide layers 141 a and 141 b .

[0050] The metal oxide layers 141a and 141b may include at least one oxide of tantalum (Ta), niobium (Nb), and titanium (Ti). For example, the metal oxide layers 141a and 141b may include tantalum pentoxide (Ta). 2 O 5 ), niobium pentoxide (Nb 2 O 5 ) or titanium dioxide (TiO 2 ). The metal layers 142a and 142b may include a metal having low resistance, such as copper (Cu).

[0051] The interlayer insulating layer 150 may be disposed on the gate insulating layer 130 to cover the gate line GW. The interlayer insulating layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0052] The data line DW and the drain electrode 162 may be disposed on the interlayer insulating layer 150. The data line DW may transmit a data voltage and may extend upward in a column to intersect the gate line GW. The data line DW may include a source electrode 161 having a shape protruding from the data line DW. The drain electrode 162 may be separated from the data line DW and may face the source electrode 161 with the gate electrode 140 interposed between the drain electrode 162 and the source electrode 161. The source electrode 161 and the drain electrode 162 may pass through the interlayer insulating layer 150 and the gate insulating layer 130 to contact the active pattern 120.

[0053] The data line DW and the drain electrode 162 may include a metal such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), niobium (Nb), and scandium (Sc), an alloy of the metal, or a nitride of the metal. For example, the data line DW and the drain electrode 162 may have a structure in which two or more mutually different metal layers such as an Al layer and a Ti layer are stacked.

[0054] The thin film transistor TFT may be defined by the above-mentioned active pattern 120, the gate insulating layer 130, the gate electrode 140, the source electrode 161 and the drain electrode 162. Figure 2 , a thin film transistor having a top gate structure in which the gate electrode 140 is disposed on the active pattern 120 has been shown, but the thin film transistor TFT may have a bottom gate structure in which the gate electrode 140 is disposed under the active pattern 120 .

[0055] A protective layer 170 may be disposed on the interlayer insulating layer 150 to cover the data line DW and the drain electrode 162. The protective layer 170 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride or an organic insulating material such as polyimide, epoxy, acrylic, and polyester.

[0056] The pixel electrode 180 may be disposed on the protective layer 170. The pixel electrode 180 may pass through the protective layer 170 to contact the drain electrode 162. In one implementation, the pixel electrode 180 may be independently disposed for each pixel.

[0057] In one embodiment, the pixel electrode 180 may be provided as a reflective electrode. In this case, the pixel electrode 180 may include a metal (such as Al, Ag, W, Cu, Ni, Cr, Mo, Ti, Pt, Ta, Nb and Sc) or an alloy of a metal. In addition, the pixel electrode 180 may include a transparent conductive material with a high work function. For example, the pixel electrode 180 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide or indium oxide. In one embodiment, the pixel electrode 180 may have a multilayer structure including a metal and a transparent conductive material.

[0058] The pixel defining layer 190 may be disposed on the protective layer 170 to cover the outer circumference of the pixel electrode 180. The pixel defining layer 190 may include a transparent organic material such as a polyimide resin or an acrylic resin.

[0059] In the following, reference will be made to Figure 3 A wiring structure of a display substrate according to an embodiment of the present invention is described.

[0060] Figure 3 1 is a cross-sectional view showing wiring of a display substrate according to an embodiment of the present invention. For example, Figure 3 The wiring can be represented by Figure 1 and Figure 2 FIG. 4 is a diagram showing a gate line GW of a display substrate according to an embodiment of the present invention.

[0061] See also Figure 3 As described above, according to one embodiment of the present invention, the gate line GW of the display substrate may include a metal oxide layer 321 and a metal layer 322 sequentially stacked on the base layer 310. The base layer 310 may be Figure 2 The substrate 110 or the gate insulating layer 130 in the embodiment.

[0062] The metal layer 322 may be directly disposed on the metal oxide layer 321. In other words, a bottom surface of the metal layer 322 may be in contact with a top surface of the metal oxide layer 321.

[0063] The side surface S1 of the metal oxide layer 321 may be continuously formed from the side surface S2 of the metal layer 322. In other words, the side surface S1 of the metal oxide layer 321 and the side surface S2 of the metal layer 322 may extend toward the base layer 310 without a step therebetween.

[0064] The metal layer 322 can make the gate line GW have low resistance, and the metal oxide layer 321 can improve the adhesive strength between the metal layer 322 and the base layer 310. In addition, the metal oxide layer 321 can prevent the material of the metal layer 322 from diffusing downward to react with the base layer 310, thereby preventing corrosion and defects of the gate line GW.

[0065] The thickness T1 of the metal oxide layer 321 may be about to about When the thickness T1 of the metal oxide layer 321 is less than about When the metal oxide layer 321 is less than 100 mm, the metal oxide layer 321 may not be sufficient to prevent the material of the metal layer 322 from diffusing downward. Meanwhile, the thickness T2 of the metal layer 322 may be about to about When the thickness T2 of the metal layer 322 is less than about When the thickness T2 of the metal layer 322 is greater than about When , the step coverage of the insulating layer covering the gate line GW will deteriorate.

[0066] In the following, reference will be made to Figures 4 to 8 As well as the above Figure 1 and Figure 2 A method for manufacturing a display substrate according to one embodiment of the present invention is described.

[0067] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 is a cross-sectional view showing a method for manufacturing a display substrate according to one embodiment of the present invention.

[0068] See also Figure 4 , the active pattern 120 may be formed on the substrate 110. For example, the active pattern 120 may be formed by depositing a semiconductor layer on the substrate 110 by sputtering or the like, and partially etching the semiconductor layer by a photolithography process or the like.

[0069] See also Figure 5 , the first metal layer 143 and the second metal layer 142 may be sequentially stacked on the substrate 110 .

[0070] First, the gate insulating layer 130 may be formed on the substrate 110 to cover the active pattern 120. For example, the gate insulating layer 130 may be deposited on the substrate 110 by chemical vapor deposition (CVD) or the like.

[0071] Thereafter, a first metal layer 143 may be formed on the gate insulating layer 130, and a second metal layer 142 may be formed on the first metal layer 143. For example, the first metal layer 143 including at least one of tantalum, niobium, and titanium may be deposited on the gate insulating layer 130 by sputtering or the like, and the second metal layer 142 including copper may be deposited on the first metal layer 143 by sputtering or the like.

[0072] The thickness of the first metal layer 143 may be about to about As described above, since the thickness of the first metal layer 143 is greater than or equal to about Therefore, it is sufficient to prevent the material of the second metal layer 142 from diffusing downward. In addition, the thickness of the second metal layer 142 may be about to about As described above, since the thickness of the second metal layer 142 is greater than or equal to about Therefore, the second metal layer 142 can have a relatively low resistance. At the same time, because the thickness of the second metal layer 142 is less than or equal to about Therefore, it is possible to prevent the step coverage of the insulating layer formed on the second metal layer 142 from being deteriorated in subsequent processes.

[0073] See also Figure 1 and Figure 6 , the gate line GW may be formed by partially etching the first metal layer 143 together with the second metal layer 142. For example, the first metal layer 143 and the second metal layer 142 may be partially etched using wet etching through a photolithography process or the like. The gate line GW may include lower metal layers 143a and 143b obtained by partially etching the first metal layer 143, and upper metal layers 142a and 142b obtained by partially etching the second metal layer 142. Because the first metal layer 143 is partially etched together with the second metal layer 142, side surfaces of the upper metal layers 142a and 142b may be continuous with side surfaces of the lower metal layers 143a and 143b, respectively.

[0074] See also Figure 7 , the lower metal layers 143a and 143b may be converted into metal oxide layers 141a and 141b by oxidation.

[0075] In one embodiment, the lower metal layers 143a and 143b may be converted into the metal oxide layers 141a and 141b by natural oxidation. For example, when oxygen and moisture contained in the substrate 110 and / or the gate insulating layer 130 are introduced into the lower metal layers 143a and 143b, the lower metal layers 143a and 143b may be converted into the metal oxide layers 141a and 141b due to the oxygen and moisture. Accordingly, an additional process for oxidizing the lower metal layers 143a and 143b may not be required.

[0076] In one embodiment, the lower metal layers 143a and 143b may be completely converted into the metal oxide layers 141a and 141b by oxidation. The lower metal layers 143a and 143b may be oxidized by oxygen and moisture contained in the substrate 110 and / or the gate insulating layer 130 disposed below the lower metal layers 143a and 143b, and the thickness of each of the oxidized lower metal layers 143a and 143b may be less than or equal to about 100 Å from the bottom surface of each of the lower metal layers 143a and 143b. As described above, since the thickness of the first metal layer 143 is less than or equal to about Therefore, the lower metal layers 143a and 143b can be completely converted into metal oxide layers 141a and 141b through oxidation.

[0077] See also Figure 8 , after the lower metal layers 143a and 143b are converted into the metal oxide layers 141a and 141b through oxidation, the active pattern 120 may be subjected to heat treatment.

[0078] First, an interlayer insulating layer 150 may be formed on the gate insulating layer 130 to cover the gate line GW. For example, the interlayer insulating layer 150 may be deposited on the gate insulating layer 130 by chemical vapor deposition, etc. In addition, a contact hole partially exposing the active pattern 120 may be formed through the interlayer insulating layer 150 and the gate insulating layer 130 by a photolithography process, etc.

[0079] Then, the active pattern 120 may be subjected to heat treatment. For example, heat HEAT at about 450° C. may be provided to the active pattern 120 by a heat source disposed outside the display substrate. In this case, impurities may be discharged from the heat-treated active pattern 120 through the contact hole, and the driving range of the thin film transistor may be adjusted, thereby improving the characteristics of the thin film transistor.

[0080] In the comparative example, when the gate line GW includes a lower metal layer instead of the metal oxide layers 141a and 141b, in the heat treatment process of the active pattern 120, the material constituting the upper metal layers 142a and 142b diffuses downward to react with the lower metal layer, thereby forming an intermetallic compound layer. For example, when the lower metal layer includes titanium, copper may diffuse into the lower metal layer, thereby forming a copper-titanium alloy (Cu 3 Ti). The intermetallic compound layer is easily formed in a high temperature environment (such as a heat treatment process). As mentioned above, when the lower metal layer is converted into the intermetallic compound layer, the resistance of the gate line GW will increase. In this case, the transmission of the gate signal transmitted through the gate line GW will be delayed.

[0081] However, in one embodiment of the present invention, since the gate line GW includes the metal oxide layers 141 a and 141 b , an intermetallic compound layer is not formed in the heat treatment process of the active pattern 120 , and the resistance of the gate line GW may be prevented from increasing.

[0082] See also Figure 1 and Figure 2 , after forming the data line DW and the drain electrode 162 , the pixel electrode 180 connected to the drain electrode 162 may be formed.

[0083] First, the data line DW and the drain electrode 162 may be formed on the interlayer insulating layer 150. For example, the data line DW and the drain electrode 162 may be formed by depositing a conductive layer on the interlayer insulating layer 150 by sputtering, etc., and partially etching the conductive layer by a photolithography process, etc. In addition, a protective layer 170 may be formed on the interlayer insulating layer 150 to cover the data line DW and the drain electrode 162.

[0084] Thereafter, the pixel electrode 180 may be formed on the protective layer 170. For example, the pixel electrode 180 may be formed by depositing a conductive layer on the protective layer 170 by sputtering, etc., and partially etching the conductive layer by a photolithography process, etc. In addition, the pixel defining layer 190 may be formed on the protective layer 170 to cover the periphery of the pixel electrode 180.

[0085] In the following, reference will be made to Figure 1 and Fig. 9 A configuration of a display substrate according to another embodiment of the present invention is described.

[0086] Fig. 9 FIG. 2 is a cross-sectional view showing a display substrate according to another embodiment of the present invention. For example, Fig. 9 Can be along Figure 1 A cross-sectional view of a display substrate taken along line II-II'.

[0087] See also Figure 1 and Fig. 9 According to another embodiment of the present invention, the display substrate may include a substrate 110, a thin film transistor TFT, wirings (such as a gate line GW and a data line DW) disposed on the substrate 110, and a pixel electrode 180 connected to the thin film transistor TFT. Fig. 9 In the description of the display substrate according to another embodiment of the present invention, the reference numerals will be omitted. Figure 2 Detailed description of components substantially the same as or similar to those of the display substrate described herein according to one embodiment of the present invention.

[0088] The gate line GW may include metal oxide layers 146a and 146b, metal layers 147a and 147b disposed over the metal oxide layers 146a and 146b, and intermetallic compound layers 148a and 148b disposed between the metal oxide layers 146a and 146b and the metal layers 147a and 147b.

[0089] The metal oxide layers 146a and 146b may include at least one oxide of tantalum, niobium, and titanium. For example, the metal oxide layers 146a and 146b may include tantalum pentoxide, niobium pentoxide, or titanium dioxide. The metal layers 147a and 147b may include a metal having a low resistance, such as copper. The intermetallic compound layers 148a and 148b may include an intermetallic compound including at least one of tantalum, niobium, and titanium and copper.

[0090] In the following, reference will be made to Fig.10 A wiring structure of a display substrate according to another embodiment of the present invention is described.

[0091] Fig.10 FIG. 1 is a cross-sectional view showing wiring of a display substrate according to another embodiment of the present invention. For example, Fig.10 The wiring can be represented by Figure 1 and Fig. 9 FIG. 4 is a diagram showing a gate line GW of a display substrate according to another embodiment of the present invention.

[0092] See also Fig.10 As described above, according to another embodiment of the present invention, the gate line GW of the display substrate may include a metal oxide layer 326, an intermetallic compound layer 328, and a metal layer 327 sequentially stacked on the base layer 310. The base layer 310 may be Fig. 9 The substrate 110 or the gate insulating layer 130 in the embodiment.

[0093] The intermetallic compound layer 328 may be interposed between the metal oxide layer 326 and the metal layer 327. In other words, the bottom surface of the intermetallic compound layer 328 may contact the top surface of the metal oxide layer 326, and the top surface of the intermetallic compound layer 328 may contact the bottom surface of the metal layer 327.

[0094] The side surface S1 of the metal oxide layer 326, the side surface S3 of the intermetallic oxide layer 328, and the side surface S2 of the metal layer 327 may be continuously formed. In other words, the side surface S1 of the metal oxide layer 326, the side surface S3 of the intermetallic oxide layer 328, and the side surface S2 of the metal layer 327 may extend toward the base layer 310 without a step therebetween.

[0095] The thickness T3 of the intermetallic compound layer 328 may be less than or equal to about When the thickness T3 of the intermetallic compound layer 328 is greater than about When the gate line GW is oxidized, the resistance of the gate line GW may increase due to the intermetallic compound layer 328 having a relatively high resistance.

[0096] In the following, reference will be made to Figures 11 to 14 As well as the above Figure 1 and Fig. 9 A method for manufacturing a display substrate according to another embodiment of the present invention is described.

[0097] Fig.11 , Fig.12 , Fig.13 and Fig.14 is a cross-sectional view showing a method for manufacturing a display substrate according to another embodiment of the present invention.

[0098] In the reference Figures 11 to 14 In the method for manufacturing a display substrate according to another embodiment of the present invention described, the reference numerals will be omitted. Figures 4 to 8 A detailed description of components substantially the same as or similar to those of the method for manufacturing a display substrate according to one embodiment of the present invention is described.

[0099] See also Fig.11 , the first metal layer 145 and the second metal layer 147 may be sequentially stacked on the substrate 110 .

[0100] The first metal layer 145 may be formed on the gate insulating layer 130, and the second metal layer 147 may be formed on the first metal layer 145. For example, the first metal layer 145 including at least one of tantalum, niobium, and titanium may be deposited on the gate insulating layer 130 by sputtering or the like, and the second metal layer 147 including copper may be deposited on the first metal layer 145 by sputtering or the like.

[0101] The thickness of the first metal layer 145 may be about to about Since the thickness of the first metal layer 145 is greater than or equal to about Therefore, it is sufficient to prevent the material of the second metal layer 147 from diffusing downward. In addition, the thickness of the second metal layer 147 may be about to about As described above, since the thickness of the second metal layer 147 is greater than or equal to about Therefore, the second metal layer 147 can have a relatively low resistance. At the same time, because the thickness of the second metal layer 147 is less than or equal to about Therefore, it is possible to prevent the step coverage of the insulating layer formed on the second metal layer 147 from being deteriorated in a subsequent process.

[0102] See also Figure 1 and Fig.12 , the gate line GW may be formed by partially etching the first metal layer 145 together with the second metal layer 147. For example, the first metal layer 145 and the second metal layer 147 may be partially etched using wet etching through a photolithography process or the like. The gate line GW may include lower metal layers 145a and 145b obtained by partially etching the first metal layer 145, and upper metal layers 147a and 147b obtained by partially etching the second metal layer 147. Because the first metal layer 145 is partially etched together with the second metal layer 147, side surfaces of the upper metal layers 147a and 147b may be continuous with side surfaces of the lower metal layers 145a and 145b, respectively.

[0103] See also Fig.13 , the lower metal layers 145a and 145b may be at least partially converted into metal oxide layers 146a and 146b by oxidation.

[0104] In one embodiment, the lower metal layers 145a and 145b may be at least partially converted into the metal oxide layers 146a and 146b by natural oxidation. For example, when oxygen and moisture included in the substrate 110 and / or the gate insulating layer 130 are introduced into the lower metal layers 145a and 145b, the lower metal layers 145a and 145b may be at least partially converted into the metal oxide layers 146a and 146b due to the oxygen and moisture. Accordingly, an additional process for at least partially oxidizing the lower metal layers 145a and 145b may not be required.

[0105] In one embodiment, the lower metal layers 145a and 145b may be partially converted into the metal oxide layers 146a and 146b by oxidation. The lower metal layers 145a and 145b may be oxidized by oxygen and moisture included in the substrate 110 and / or the gate insulating layer 130 disposed below the lower metal layers 145a and 145b, and the thickness of each of the oxidized lower metal layers 145a and 145b may be less than or equal to about 100 Å from the bottom surface of each of the lower metal layers 145a and 145b. As described above, since the thickness of the first metal layer 145 is about to about The lower metal layers 145a and 145b have a thickness of about 100 mm from the bottom surface thereof. The lower portions of the lower metal layers 145a and 145b having a thickness of 500 Å or less may be converted into metal oxide layers 146a and 146b, respectively, by oxidation.

[0106] The remaining portions of the lower metal layers 145a and 145b may not be oxidized and may remain as the intermediate metal layers 149a and 149b, respectively. In this case, the lower metal layers 145a and 145b may have a thickness of about 100 mm from the top surface thereof. Upper portions of the lower metal layers 145a and 145b having a thickness of 500 Å or less may not be oxidized and may remain as intermediate metal layers 149a and 149b, respectively.

[0107] See also Fig.14 , after the lower metal layers 145a and 145b are partially converted into the metal oxide layers 146a and 146b by oxidation, the active pattern 120 may be subjected to heat treatment.

[0108] In the heat treatment process of the active pattern 120, the material constituting the upper metal layers 147a and 147b may diffuse downward to react with the intermediate metal layers 149a and 149b, so that the intermediate metal layers 149a and 149b may be converted into intermetallic compound layers 148a and 148b. For example, when the intermediate metal layers 149a and 149b include titanium, copper may diffuse into the intermediate metal layers 149a and 149b, thereby forming a copper-titanium alloy.

[0109] In one embodiment, the thickness of each of the intermetallic compound layers 148a and 148b may be less than or equal to about Although the resistance of the intermetallic compound layers 148a and 148b may be relatively large compared to the intermediate metal layers 149a and 149b, since each of the intermetallic compound layers 148a and 148b has a resistance of about The thickness is relatively small, so the influence on the resistance of the gate line GW will not be significant.

[0110] In the following, reference will be made to Fig.15 A configuration of a display device according to one embodiment of the present invention is described.

[0111] Fig.15 1 is a cross-sectional view showing a display device according to an embodiment of the present invention. For example, Fig.15 Shows references including Figure 2 The organic light emitting display device of the display substrate according to one embodiment of the present invention is described. However, the present invention is not limited thereto, and the display device may include a display substrate according to the reference Fig. 9 A display substrate according to another embodiment of the present invention is described.

[0112] See also Fig.15 According to one embodiment of the present invention, the display device may include an organic light emitting layer 210 and a counter electrode 220, which are sequentially disposed on a display substrate according to one embodiment of the present invention. Figure 2 A description of the configuration of the display substrate is described.

[0113] The organic light emitting layer 210 may be disposed on the pixel electrode 180 and the pixel defining layer 190. The organic light emitting layer 210 may be patterned independently for each pixel to generate different color light for each pixel. The organic light emitting layer 210 may include a host material excited by holes and electrons, and a dopant material that increases light emitting efficiency by absorbing and emitting energy.

[0114] In one embodiment, if Fig.15 As shown, the organic light emitting layer 210 may be formed on the sidewalls of the pixel defining layer 190 and the top surface of the pixel electrode 180 exposed by the pixel defining layer 190, and may partially extend to the top surface of the pixel defining layer 190. In another embodiment, the organic light emitting layer 210 may be defined by the sidewalls of the pixel defining layer 190 and may be independently provided for each pixel.

[0115] In one embodiment, a hole transport layer (HTL) may be disposed between the pixel electrode 180 and the organic light emitting layer 210. In addition, an electron transport layer (ETL) may be disposed between the organic light emitting layer 210 and the counter electrode 220. The hole transport layer and / or the electron transport layer may be provided continuously and commonly in a plurality of pixels.

[0116] The hole transport layer may include a hole transport material such as 4,4'-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (NPB), 4,4'-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (TPD), N,N-di-1-naphthyl-N,N-diphenyl-1,1-biphenyl-4,4-diamine (NPD), N-phenylcarbazole and polyvinylcarbazole. In addition, the electron transport layer may include an electron transport material such as tris(8-hydroxyquinoline)aluminum (Alq 3 ), 2-(4-biphenyl)-5-(4-tert-butylphenyl-1,3,4-oxadiazole) (PBD), bis(2-methyl-8-hydroxyquinolinolato)-4-phenylphenol-aluminum (BAlq), bathocuproine (BCP), triazole (TAZ) and phenylquinoxaline.

[0117] The counter electrode 220 may be disposed on the organic light emitting layer 210 and the pixel defining layer 190. The counter electrode 220 may face the pixel electrode 180, wherein the organic light emitting layer 210 is interposed therebetween. The counter electrode 220 may include a metal having a low work function (such as Al, Ag, W, Cu, Ni, Cr, Mo, Ti, Pt, Ta, Nb, and Sc) or an alloy of metals. In one embodiment, the counter electrode 220 may be disposed in a plurality of pixels together.

[0118] The light emitting element OLED may be defined by the above-mentioned pixel electrode 180, the organic light emitting layer 210, and the counter electrode 220. The pixel electrode 180 and the counter electrode 220 may be provided as an anode and a cathode of the light emitting element OLED, respectively.

[0119] [Industrial Applicability]

[0120] The display substrate according to the embodiment of the present invention may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0121] Although a display substrate, a method for manufacturing a display substrate, and a display device including the display substrate according to an embodiment of the present invention have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by an ordinary technician in the relevant technical field without departing from the technical spirit of the present invention described in the appended claims.

[0122] [Description of Reference Numerals]

[0123] 110: Substrate

[0124] 120: Active pattern

[0125] 140: Gate electrode

[0126] 141a, 141b, 146a, 146b: Metal oxide layer

[0127] 142a, 142b, 147a, 147b: Metal layer

[0128] 148a, 148b: Intermetallic compound layer

[0129] GW: Gate line

[0130] TFT: Thin Film Transistor

[0131] OLED: Light Emitting Element

Claims

1. A display substrate, comprising: substrate; a gate insulating layer disposed on the substrate and covering the active pattern, wherein the gate insulating layer directly covers the upper surface and side surfaces of the active pattern; and A wiring disposed on the gate insulating layer, wherein the wiring comprises: a metal oxide layer containing at least one oxide of tantalum, niobium and titanium, and a metal layer disposed on the metal oxide layer and containing copper, and The thickness of the metal oxide layer is to 2 . The display substrate of claim 1 , wherein a side surface of the metal oxide layer is continuously formed from a side surface of the metal layer. 3 . The display substrate of claim 1 , wherein the metal layer is directly disposed on the metal oxide layer. 4 . The display substrate of claim 1 , wherein the wiring further comprises an intermetallic compound layer disposed between the metal oxide layer and the metal layer.

5. The display substrate according to claim 4, wherein the thickness of the intermetallic compound layer is less than or equal to 6. The display substrate of claim 4, wherein the intermetallic compound layer comprises: An intermetallic compound comprising copper and at least one of tantalum, niobium and titanium. 7 . The display substrate of claim 4 , wherein a side surface of the metal oxide layer, a side surface of the intermetallic compound layer, and a side surface of the metal layer are continuously formed.

8. The display substrate according to claim 1, wherein the thickness of the metal layer is to 9. The display substrate of claim 1, wherein the substrate comprises silicon oxide.

10. A method for manufacturing a display substrate, the method comprising: forming a gate insulating layer on the substrate and covering the active pattern, wherein the gate insulating layer directly covers the upper surface and side surfaces of the active pattern; stacking a first metal layer including at least one of tantalum, niobium and titanium and a second metal layer including copper in sequence on the gate insulating layer; forming wiring by partially etching the first metal layer and the second metal layer; as well as The first metal layer is converted into a metal oxide layer by oxidation. The method of claim 10 , wherein the first metal layer is converted into the metal oxide layer by natural oxidation.

12. The method of claim 10, wherein the thickness of the metal oxide layer is to 13. The method of claim 10, wherein the first metal layer is entirely converted into the metal oxide layer by oxidation.

14. The method of claim 10, wherein the first metal layer is partially converted into the metal oxide layer by oxidation.

15. The method of claim 14, further comprising: The remaining portion of the first metal layer that is not oxidized is converted into an intermetallic compound layer by reacting the remaining portion of the first metal layer with the second metal layer.

16. The method of claim 15, wherein the thickness of the intermetallic compound layer is less than or equal to 17 . The method of claim 15 , wherein converting the remaining portion of the first metal layer into the intermetallic compound layer is performed after converting the first metal layer partially into the metal oxide layer.

18. A display device comprising: substrate; a gate insulating layer disposed on the substrate and covering the active pattern, wherein the gate insulating layer directly covers the upper surface and side surfaces of the active pattern; A gate line disposed on the gate insulating layer; a thin film transistor including the active pattern, and a gate electrode overlapping the active pattern and protruding from the gate line; as well as a light emitting element connected to the thin film transistor, The gate line comprises: a metal oxide layer containing at least one oxide of tantalum, niobium and titanium, and a metal layer disposed on the metal oxide layer and containing copper, and The thickness of the metal oxide layer is to 19 . The display device of claim 18 , wherein a side surface of the metal oxide layer is formed continuously from a side surface of the metal layer.

20. The display device of claim 18, wherein the metal layer is directly disposed on the metal oxide layer.

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