Spatially variable wafer bias power system

Abstract

A plasma deposition system includes a wafer platform, a second electrode, a first electrode, a first high voltage pulse generator, and a second high voltage pulse generator. In some embodiments, the second electrode can be deployed close to the wafer platform. In some embodiments, the second electrode can include: a disk shape having a central aperture; a central axis; an aperture diameter and an outer diameter. In some embodiments, the first electrode can be deployed close to the wafer platform and within the central aperture of the second electrode. In some embodiments, the first electrode can include a disk shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulse generator can be electrically coupled to the first electrode. In some embodiments, the second high voltage pulse generator can be electrically coupled to the second electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,464, filed on July 27, 2018, entitled “NANOSECOND PULSER SYSTEM,” which is incorporated herein by reference in its entirety.

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,334, filed on July 28, 2018, entitled “NANOSECOND PULSER THERMAL MANAGEMENT,” which is incorporated herein by reference in its entirety.

[0004] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,457, filed on July 27, 2018, entitled “NANOSECOND PULSER PULSE GENERATION,” which is incorporated herein by reference in its entirety.

[0005] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,347, filed on July 27, 2018, and entitled “NANOSECOND PULSER ADC SYSTEM,” which is incorporated herein by reference in its entirety.

[0006] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,467, filed on July 27, 2018, entitled “EDGE RING POWER SYSTEM,” which is incorporated herein by reference in its entirety.

[0007] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,406, filed on July 27, 2018, entitled “NANOSECOND PULSER BIAS COMPENSATION,” which is incorporated herein by reference in its entirety.

[0008] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,468, filed on July 27, 2018, entitled “NANOSECOND PULSER CONTROL MODULE,” which is incorporated herein by reference in its entirety.

[0009] This application claims priority to U.S. Provisional Patent Application No. 62 / 711,523, filed on August 10, 2018, entitled “PLASMA SHEATH CONTROL FOR RF PLASMA REACTORS,” which is incorporated herein by reference in its entirety.

[0010] This application claims priority to U.S. Provisional Patent Application No. 62 / 789,523, filed on January 1, 2019, entitled “EFFICIENT NANOSECOND PULSER WITH SOURCE AND SINKCAPABILITY FOR PLASMACONTROL APPLICATIONS,” which is incorporated herein by reference in its entirety.

[0011] This application claims priority to U.S. Provisional Patent Application No. 62 / 789,526, filed on January 1, 2019, entitled “EFFICIENT ENERGY RECOVERY IN ANANOSECOND PULSERCIRCUIT,” which is incorporated herein by reference in its entirety.

[0012] This application claims priority to and is a continuation-in-part of U.S. Non-Provisional Patent Application No. 16 / 523,840, filed on July 26, 2019, entitled “NANOSECOND PULSER BIAS COMPENSATION,” which is incorporated herein by reference in its entirety. Background Art

[0013] Generating high voltage pulses with fast rise times and / or fast fall times is challenging. For example, in order to achieve fast rise times and / or fast fall times (e.g., less than about 50 ns) for high voltage pulses (e.g., greater than about 5 kV), the slope of the pulse rise and / or fall must be extremely steep (e.g., greater than 10 11 V / s). Such steep rise and / or fall times are particularly difficult to produce, particularly in circuits driving loads through low capacitance. Producing these pulses can be particularly difficult using standard electrical components in a compact manner, and / or where the pulses have variable pulse width, voltage, and repetition rate; and / or in applications with capacitive loads (e.g., such as plasmas).

[0014] In addition, the wafer yield can determine whether the process is successful. Generally, because of various defects that can occur at the edge of the wafer, the chips on the edge of the wafer may not be usable. These defects increase waste and reduce wafer yield. Summary of the invention

[0015] Some embodiments of the present invention provide a power system with a plasma load, comprising: a first high-voltage pulse generator, which outputs a first plurality of pulses, wherein the first plurality of pulses have a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulse generator, which outputs a second plurality of pulses, wherein the second plurality of pulses have a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; a chamber; a first electrode, which is disposed in the chamber and electrically coupled to the first high-voltage pulse generator; and a second electrode, which is adjacent to the first electrode and disposed in the chamber, and electrically coupled to the second high-voltage pulse generator; wherein the chamber comprises one or both of a wafer and a plasma, and the plasma is capacitively coupled to the first electrode and the second electrode with a capacitance between 10 pF and 1 μF.

[0016] Some embodiments of the present invention provide a power system with a plasma load, comprising: a first high-voltage pulse generator, which outputs a first plurality of pulses, wherein the first plurality of pulses have a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulse generator, which outputs a second plurality of pulses, wherein the second plurality of pulses have a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; a chamber; a first electrode, which is disposed in the chamber and electrically coupled to the first high-voltage pulse generator, wherein the first electrode comprises: a disk shape, a central axis, and an outer diameter; and a second electrode, which is adjacent to the first electrode and disposed in the chamber, and is electrically coupled to the second high-voltage pulse generator, wherein the second electrode comprises: a disk shape having a central aperture, wherein the first electrode is disposed in the central aperture; a central axis, which is aligned with the central axis of the first electrode, an aperture diameter, and an outer diameter.

[0017] Some embodiments of the present invention provide a method, comprising: pulsing a first high voltage pulse generator coupled to a first electrode in a plasma chamber, the first high voltage pulse generator pulsing at a first voltage greater than 1 kV and at a first pulse repetition frequency greater than 20 kHz and at a first pulse width; pulsing a second high voltage pulse generator coupled to a second electrode in the plasma chamber, the second high voltage pulse generator pulsing at a second voltage greater than 1 kV and at a second pulse repetition frequency greater than 20 kHz and at a second pulse width, wherein the first electrode and the second electrode are disposed under a wafer; measuring a parameter corresponding to a physical phenomenon occurring in the plasma chamber; and adjusting an amount of at least one of the second voltage, the second pulse repetition frequency and the second pulse generator width based on the measured parameter; wherein the parameter is a current flowing through a resistor in the first high voltage pulse generator.

[0018] Some embodiments of the present invention provide a power system with a plasma load, comprising: a first high-voltage pulse generator, which outputs a first plurality of pulses, wherein the first plurality of pulses have a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulse generator, which outputs a second plurality of pulses, wherein the second plurality of pulses have a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; a chamber; a first electrode, which is disposed in the chamber and electrically coupled to the first high-voltage pulse generator; and a second electrode, which is adjacent to the first electrode and disposed in the chamber, and electrically coupled to the second high-voltage pulse generator; wherein the chamber includes one or both of a wafer and a plasma, and the electric field across the surface of the wafer is uniform within 25%.

[0019] Some embodiments of the present invention provide a power system with a plasma load, comprising: a first high-voltage pulse generator, which outputs a first plurality of pulses, wherein the first plurality of pulses have a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulse generator, which outputs a second plurality of pulses, wherein the second plurality of pulses have a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; a chamber; a first electrode, which is disposed in the chamber and electrically coupled to the first high-voltage pulse generator; and a second electrode, which is adjacent to the first electrode and disposed in the chamber, and electrically coupled to the second high-voltage pulse generator; wherein the chamber includes one or both of a wafer and a plasma, and a coupling capacitance between the first electrode and a corresponding portion of the wafer is greater than 100 pF; and a capacitance between the second electrode and a corresponding portion of the wafer is greater than 100 pF.

[0020] Some embodiments of the present invention provide a power system with a plasma load, comprising: a first high-voltage pulse generator, which outputs a first plurality of pulses, wherein the first plurality of pulses have a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulse generator, which outputs a second plurality of pulses, wherein the second plurality of pulses have a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; a chamber; a first electrode, which is disposed in the chamber and electrically coupled to the first high-voltage pulse generator; and a second electrode, which is adjacent to the first electrode and disposed in the chamber, and electrically coupled to the second high-voltage pulse generator; wherein the first electrode has a first flat surface, and the second electrode has a second flat surface, so that the second flat surface is 25% of the sum of the first flat surface and the second flat surface.

[0021] Some embodiments of the present invention include a spatially variable wafer bias system, which may include a first high voltage pulse generator, a second high voltage pulse generator, a chamber, a first electrode, and a second electrode. In some embodiments, the first high voltage pulse generator may output a first plurality of pulses having a first voltage greater than about 1 kV, a first pulse width less than about 1 μs, and a first pulse repetition frequency greater than about 20 kHz. In some embodiments, the second high voltage pulse generator may output a second plurality of pulses having a second voltage greater than about 1 kV, a second pulse width less than about 1 μs, and a second pulse repetition frequency greater than about 20 kHz. In some embodiments, the first electrode may be disposed in the chamber and electrically coupled to the first high voltage pulse generator; and the second electrode may be disposed in the chamber adjacent to the first electrode and electrically coupled to the second high voltage pulse generator.

[0022] In some embodiments, the chamber includes one or both of a wafer and a plasma, which may be capacitively coupled to the first electrode and the second electrode via a capacitance between 10 pF and 1 μF.

[0023] In some embodiments, the electric field across the circular surface of the wafer can be uniform by less than 25%, 20%, 15%, 10%, 5% or 2% or better using the first nanosecond pulse generator and the second nanosecond pulse generator.

[0024] In some embodiments, the capacitance between the first electrode and the corresponding portion of the wafer is greater than 100 pF; and the capacitance between the second electrode and the corresponding portion of the wafer is greater than 100 pF.

[0025] In some embodiments, the chamber may include a plasma of ions accelerated onto the wafer.

[0026] In some embodiments, the first high voltage pulse generator generates an electrode voltage on the first electrode greater than about 1 kV, and the second high voltage pulse generator generates an electrode voltage on the second electrode greater than about 1 kV. In some embodiments, the ratio of the first voltage to the second voltage is less than 2 to 1, or vice versa.

[0027] In some embodiments, one or both of the first electrode and the second electrode are axially symmetric.

[0028] In some embodiments, the first electrode has a first planar surface and the second electrode has a second planar surface, such that an area of ​​the second planar surface is approximately 25% of a total area of ​​the first planar surface and the second planar surface.

[0029] In some embodiments, both the first high voltage pulse generator and the second high voltage pulse generator include a resistive output stage. In some embodiments, both the first high voltage pulse generator and the second high voltage pulse generator include an energy recovery circuit.

[0030] In some embodiments, the parameters of the first plurality of pulses are controlled independently of the parameters of the second plurality of pulses. In some embodiments, the first pulse repetition frequency and the second pulse repetition frequency are in phase with respect to each other.

[0031] In some embodiments, the capacitance between the first electrode and the second electrode is less than about 10 nF.

[0032] In some embodiments, the first electrode comprises: a disk shape, a central axis, and an outer diameter. In some embodiments, the second electrode comprises: a disk shape having a central aperture, the first electrode being disposed within the central aperture; a central axis aligned with the central axis of the first electrode; an aperture diameter, and an outer diameter.

[0033] Some embodiments of the present invention include a spatially variable wafer bias system, which may include a wafer platform, a first electrode, a second electrode, a first high voltage pulse generator, and a second high voltage pulse generator. In some embodiments, the first electrode may include a disk shape, a central axis, and an outer diameter. In some embodiments, the second electrode may include: a disk shape having a central aperture, the first electrode being disposed within the central aperture; a central axis aligned with the central axis of the first electrode, an aperture diameter, and an outer diameter. In some embodiments, the first high voltage pulse generator may be electrically coupled to the first electrode, and the first high voltage pulse generator may generate a pulse greater than 5 kV at a pulse repetition rate greater than 10 kHz. In some embodiments, the second high voltage pulse generator may be electrically coupled to the second electrode, and the second high voltage pulse generator may generate a pulse greater than 5 kV at a pulse repetition rate greater than 10 kHz.

[0034] In some embodiments, the second high voltage pulse generator provides pulses having an amplitude that is a fraction of the amplitude of the pulses provided by the first high voltage pulse generator. In some embodiments, the second high voltage pulse generator provides pulses having a pulse repetition frequency that is a fraction of the pulse repetition frequency of the pulses provided by the first high voltage pulse generator.

[0035] In some embodiments, the spatially variable wafer bias system may further include: a first resistance output stage coupled to the first high voltage pulse generator and the first electrode; and a second resistance output stage coupled to the second high voltage pulse generator and the second electrode. In some embodiments, the spatially variable wafer bias system may further include: a bias compensation circuit coupled to the first high voltage pulse generator and the first electrode.

[0036] In some embodiments, the spatially variable wafer bias system may further include: an insulating material ring disposed between the first electrode and the second electrode. In some embodiments, the wafer platform includes a dielectric material or a ceramic material. In some embodiments, the wafer platform has an outer diameter substantially similar to the outer diameter of the second electrode.

[0037] Some embodiments may include a method that may include: pulsing a first high voltage pulse generator coupled to a first electrode in a plasma chamber, the first high voltage pulse generator pulsing at a first voltage greater than about 1 kV and at a first pulse repetition frequency greater than about 20 kHz and at a first pulse width; pulsing a second high voltage pulse generator coupled to a second electrode in the plasma chamber, the second high voltage pulse generator pulsing at a second voltage greater than about 1 kV and at a second pulse repetition frequency greater than about 20 kHz and at a second pulse width. In some embodiments, the first electrode and the second electrode are disposed below a wafer. The method may also include: measuring a parameter corresponding to a physical phenomenon occurring in the plasma chamber (e.g., a clamping voltage, an electrode voltage, an electric field uniformity, an ion current, etc.). And adjusting at least one of the second voltage, the second pulse repetition frequency, and the second pulse width based on the measured parameter.

[0038] In some embodiments, the voltage or current measured at various locations within the plasma chamber corresponds to the uniformity of the electric field across the surface of the wafer.

[0039] In some embodiments, the voltage or current measured at various locations within the plasma chamber corresponds to the uniformity of the electric field ion current across the surface of the wafer.

[0040] In some embodiments, the parameter is a current flowing through a resistor in a resistive output stage or an energy recovery circuit.

[0041] Some embodiments of the present invention include a spatially variable wafer bias system. For example, the wafer bias system may include a system comprising: a disk-shaped wafer platform; a first electrode having a disk shape, the first electrode being disposed proximate to and aligned with the wafer platform; a second electrode having a disk shape and a central aperture, the central aperture being disposed proximate to and aligned with the wafer platform so that the first electrode is disposed within the central aperture; a first high voltage pulse generator electrically coupled to the first electrode; and a second high voltage pulse generator electrically coupled to the second electrode.

[0042] In some embodiments, the second high voltage pulse generator provides a pulse having an amplitude that is a fraction of the amplitude of the pulse provided by the first high voltage pulse generator. For example, the fraction may include 50%, 75%, 100%, 125%, 150%, 200%, etc.

[0043] In some embodiments, the system further includes: a first resistor output stage coupled to the first high voltage pulse generator and the first electrode.

[0044] In some embodiments, the system further includes: a second resistor output stage coupled to the second high voltage pulse generator and the second electrode.

[0045] In some embodiments, the system further includes: a bias capacitor coupled to the first high voltage pulse generator and the first electrode.

[0046] In some embodiments, the system further includes: a bias capacitor coupled to the first high voltage pulse generator and the second electrode.

[0047] In some embodiments, the first high voltage pulse generator includes one or more nanosecond pulse generators. In some embodiments, the second high voltage pulse generator includes one or more nanosecond pulse generators.

[0048] Some embodiments include a plasma deposition system comprising: a wafer platform, a first electrode, a second electrode, a first high voltage pulse generator, and a second high voltage pulse generator. In some embodiments, the second electrode may be disposed below the wafer platform. In some embodiments, the second electrode may include: a disk shape having a central aperture; a central axis; an aperture diameter and an outer diameter. In some embodiments, the first electrode may be disposed below the wafer platform and within the central aperture of the second electrode. In some embodiments, the first electrode may include a disk shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulse generator may be electrically coupled to the first electrode. In some embodiments, the first high voltage pulse generator may generate pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz. In some embodiments, the second high voltage pulse generator may be electrically coupled to the second electrode. In some embodiments, the second high voltage pulse generator may generate pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz.

[0049] Some embodiments include a plasma deposition system, comprising: a wafer platform having a first platform region and a second platform region; a first electrode disposed below the first platform region of the wafer platform; a second electrode disposed below the second platform region of the wafer platform; a first high-voltage pulse generator electrically coupled to the first electrode, the first high-voltage pulse generator generating pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz; and a second high-voltage pulse generator electrically coupled to the second electrode, the second high-voltage pulse generator generating pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz.

[0050] In some embodiments, the second high voltage pulse generator provides pulses having an amplitude that is a fraction of the amplitude of pulses provided by the first high voltage pulse generator.

[0051] In some embodiments, the second high voltage pulse generator provides pulses having a pulse repetition frequency that is a fraction of the pulse repetition frequency of pulses provided by the first high voltage pulse generator.

[0052] In some embodiments, the first high voltage pulse generator or the second high voltage pulse generator includes one or more nanosecond pulse generators.

[0053] In some embodiments, the first high voltage pulse generator or the second high voltage pulse generator includes one or more high voltage switches.

[0054] Some embodiments include a system comprising: a wafer platform; a plurality of electrodes disposed below the wafer platform; and a plurality of high voltage pulse generators electrically coupled to corresponding electrodes of the plurality of electrodes, each of the plurality of high voltage pulse generators generating pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz. In some embodiments, each of the plurality of electrodes is separated from each other by insulation. In some embodiments, each of the plurality of high voltage pulse generators generates pulses having one or both of different voltages or pulse repetition rates.

[0055] Mentioning these illustrative embodiments does not limit or define the present disclosure, but provides examples to assist in understanding it. Additional embodiments are discussed in the detailed description, and further description is provided herein. The advantages provided by one or more of the various embodiments may be further understood by examining this specification or by practicing one or more of the embodiments presented. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] These and other features, aspects and advantages of the present disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings.

[0057] Figure 1 is a circuit diagram of a nanosecond pulse generator according to some embodiments.

[0058] Figure 2 An example waveform produced by a nanosecond pulse generator is shown.

[0059] Figure 3 is another example of a nanosecond pulse generator according to some embodiments.

[0060] Figure 4A and Figure 4B is a block diagram of a spatially variable wafer bias power system according to some embodiments.

[0061] Figure 5 is a block diagram of a spatially variable wafer bias power system according to some embodiments.

[0062] Figure 6 is a schematic diagram of a spatially variable wafer bias system according to some embodiments.

[0063] Figure 7 is a schematic diagram of a spatially variable wafer bias system according to some embodiments.

[0064] Figure 8 is a schematic diagram of a spatially variable wafer bias system according to some embodiments.

[0065] Fig. 9 An illustrative computing system is shown for performing functions to facilitate implementation of the embodiments described herein. DETAILED DESCRIPTION

[0066] Systems and methods for generating different high voltage pulses on different electrodes are disclosed. For example, each of a plurality of pulse generators (e.g., a nanosecond pulse generator, an RF generator, or an HV switch) can be electrically coupled to a corresponding electrode in a plurality of electrodes. The plurality of pulse generators can generate different voltages, ion energies, or electric fields on the electrodes. This can be done for a variety of reasons (e.g., such as compensating for plasma chamber defects, wafer discontinuities, or reducing wafer edge defects). In one example, a plurality of pulse generator systems can be used to generate different electric field profiles at the edge of a wafer rather than in the middle of the wafer.

[0067] Figure 1 is a circuit diagram of a nanosecond pulse generator system 100 according to some embodiments. The nanosecond pulse generator system 100 can be implemented within a high voltage nanosecond pulse generator system. The nanosecond pulse generator system 100 can be summarized into five stages (the stages can be broken down into other stages or summarized into fewer stages, and / or may or may not include the components shown in the figure). The nanosecond pulse generator system 100 includes a pulse generator and transformer stage 101, a resistor output stage 102, a lead stage 103, a DC bias compensation circuit 104, and a load stage 106.

[0068] In some embodiments, the nanosecond pulse generator system 100 can generate pulses having a voltage greater than 2 kV, a rise time less than about 20 ns, and a frequency greater than about 10 kHz from a power supply.

[0069] In some embodiments, the pulse generator and transformer stage 101 can generate multiple high voltage pulses with high frequency and fast rise and fall times. In all of the circuits shown, the high voltage pulse generator can include a nanosecond pulse generator.

[0070] In some embodiments, the pulse generator and transformer stage 101 may include one or more solid-state switches S1 (e.g., solid-state switches (e.g., such as IGBTs, MOSFETs, SiC MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc.)), one or more snubber resistors R3, one or more snubber diodes D4, one or more snubber capacitors C5, and / or one or more freewheeling diodes D2. One or more switches and / or circuits may be arranged in parallel or in series.

[0071] In some embodiments, load stage 106 may represent an active circuit for a plasma deposition system, a plasma etching system, or a plasma sputtering system. Capacitor C2 may represent the capacitance of a dielectric material on which a wafer may sit, or capacitor C2 may represent the capacitance between an electrode and a wafer separated by a dielectric material. Capacitor C3 may represent the sheath capacitance of the plasma to the wafer. Capacitor C9 may represent the capacitance within the plasma between the chamber wall and the top surface of the wafer. Current source I2 and current source I1 may represent the ion current through the plasma sheath.

[0072] In some embodiments, the resistive output stage 102 may include one or more inductive elements represented by inductor L1 and / or inductor L5. For example, inductor L5 may represent the stray inductance of the leads in the resistive output stage 102. Inductor L1 may be configured to minimize the power flowing directly from the pulse generator and transformer stage 101 into resistor R1.

[0073] In some embodiments, resistor R1 can dissipate charge from load stage 106, for example, at a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The resistance of resistor R1 can be low to ensure that the pulse across load stage 106 has a fast fall time t f .

[0074] In some embodiments, resistor R1 may include multiple resistors arranged in series and / or in parallel. Capacitor C11 may represent the stray capacitance of resistor R1 including the capacitance of resistors arranged in series and / or in parallel. For example, the capacitance of stray capacitance C11 may be less than 5nF, 2nF, 1nF, 500pF, 250pF, 100pF, 50pF, 10pF, 1pF, etc. For example, the capacitance may be less than the load capacitance (e.g., such as less than the capacitance of C2, C3, and / or C9).

[0075] In some embodiments, multiple pulse generator and transformer stages 101 may be arranged in parallel and coupled across inductor L1 and / or resistor R1 with resistive output stage 102. Each of the multiple pulse generator and transformer stages 101 may also include diode D1 and / or diode D6.

[0076] In some embodiments, capacitor C8 may represent the stray capacitance of blocking diode D1. In some embodiments, capacitor C4 may represent the stray capacitance of diode D6.

[0077] In some embodiments, the DC bias compensation circuit 104 may include a DC voltage source V1 that may be used to bias the output voltage positively or negatively. In some embodiments, capacitor C12 isolates / separates the DC bias voltage from the resistive output stage and other circuit elements. It allows the potential to be transferred from one part of the circuit to another. In some applications, the potential offset it establishes is used to hold the wafer in place. Resistor R2 may protect / isolate the DC bias supply from high voltage pulses pulsed by the output of the pulse generator and transformer stage 101.

[0078] In this example, the DC bias compensation circuit 104 is a passive bias compensation circuit and may include a bias compensation diode D1 and a bias compensation capacitor C15. The bias compensation diode C15 may be arranged in series with the offset supply voltage V1. The bias compensation capacitor C15 may be arranged across one or both of the offset supply voltage V1 and the resistor R2. The bias compensation capacitor C15 may have a capacitance of less than 100nH to 100μF (e.g., such as approximately 100μF, 50μF, 25μF, 10μF, 2μ, 500nH, 200nH, etc.).

[0079] In some embodiments, bias capacitor C12 can allow a voltage offset between the output of the pulse generator and transformer stage 101 (e.g., at the location marked 125) and the voltage on the electrode (e.g., at the location marked 124). In operation, for example, the electrode can be at a DC voltage of -2 kV during a burst, while the output of the nanosecond pulse generator alternates between +6 kV during a pulse and 0 kV between pulses.

[0080] For example, the bias capacitor C12 is 100nF, 10nF, 1nF, 100μF, 10μF, 1μF, etc. For example, the resistor R2 may have a high resistance (eg, a resistance such as about 1kOhm, 10kOhm, 100kOhm, 1MOhm, 10MOhm, 100MOhm, etc.).

[0081] In some embodiments, the bias compensation capacitor C15 and the bias compensation diode D1 can allow a voltage offset between the output of the pulse generator and transformer stage 101 (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124) to be established at the beginning of each burst to achieve a desired equilibrium state. For example, charge is transferred from the bias capacitor C12 to the bias compensation capacitor C15 at the beginning of each burst over a process of multiple pulses (e.g., about 5-100 pulses) to establish the correct voltage in the circuit.

[0082] In some embodiments, the DC bias compensation circuit 104 may include one or more high voltage switches placed across the bias compensation diode D1 and coupled to the power source V1. In some embodiments, the high voltage switch may include multiple switches arranged in series to collectively open and close a high voltage.

[0083] The high voltage switch can be coupled in series with one or both of the inductor and the resistor. The inductor can limit the peak current through the high voltage switch. For example, the inductor can have an inductance less than about 100 μH (e.g., such as about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc.). For example, the resistor can transfer power dissipation to the resistive output stage 102. The resistance of the resistor can have a resistance less than about 1000 ohm, 500 ohm, 250 ohm, 100 ohm, 50 ohm, 10 ohm, etc.

[0084] In some embodiments, the high voltage switch may include a snubber circuit.

[0085] In some embodiments, the high voltage switch may include multiple switches arranged in series to collectively open and close the high voltage. For example, the high voltage switch may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed on November 1, 2018, entitled “High Voltage Switch with Isolated Power”, which is incorporated in its entirety into this disclosure for all purposes.

[0086] In some embodiments, the high voltage switch can be open while the pulse generator and transformer stage 101 is pulsing, and closed when the pulse generator and transformer stage 101 is not pulsing. For example, when the high voltage switch is closed, the current can be shorted across the bias compensation diode C15. Shorting this current can allow the bias between the wafer and the clamp to be less than 2 kV, which can be within acceptable tolerances.

[0087] In some embodiments, the pulse generator and transformer stage 101 can generate pulses having a high pulse voltage (e.g., a voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high pulse repetition frequency (e.g., a frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., a rise time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), a fast fall time (e.g., a fall time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), and / or a short pulse width (e.g., a pulse width less than approximately 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0088] Figure 2 Example waveforms produced by the nanosecond pulse generator system 100 are shown. In these example waveforms, the pulse waveform 205 can represent the voltage provided by the pulse generator and transformer stage 101. As shown, the pulse waveform 205 produces a pulse with the following qualities: a high voltage (e.g., greater than about 4 kV as shown in the waveform), a fast rise time (e.g., less than about 200 ns as shown in the waveform), a fast fall time (e.g., less than about 200 ns as shown in the waveform), and a short pulse width (e.g., less than about 300 ns as shown in the waveform). The waveform 210 can be represented by a point between capacitor C2 and capacitor C3 or a voltage across capacitor C3. Figure 1 The voltage at the surface of the wafer is represented in the circuit shown. The pulse waveform 215 represents the current flowing to the plasma from the pulse generator and transformer stage 101. The nanosecond pulse generator system 100 may or may not include one or both of the diodes D1 or D2.

[0089] During the transition state (e.g., during an initial number of pulses not shown in the figure), the high voltage pulses from the pulse generator and transformer stage 101 charge capacitor C2. Because the capacitance of capacitor C2 is large compared to the capacitance of capacitor C3 and / or capacitor C1, and / or because the pulse width of the pulses is short, capacitor C2 can fully charge multiple pulses from the high voltage pulse generator. Once capacitor C2 is charged, the circuit reaches a stable state, such as Figure 2 As shown in the waveform.

[0090] In the steady state, and when switch S1 is open, capacitor C2 is charged and slowly dissipates through the resistive output stage 110, as shown by the slightly rising slope of waveform 210. Once capacitor C2 is charged, and while switch S1 is open, the voltage at the surface of the wafer (the point between capacitor C2 and capacitor C3) is negative. This negative voltage may be the negative of the voltage of the pulse provided by the pulse generator and transformer stage 101. For Figure 2 In the example waveform shown, the voltage of each pulse is about 4 kV; and the steady-state voltage at the wafer is about -4 kV. This results in a negative potential across the plasma (e.g., across capacitor C3), which accelerates positive ions from the plasma to the surface of the wafer. While switch S1 is open, the charge on capacitor C2 is slowly dissipated through the resistive output stage.

[0091] When switch S1 is closed, as capacitor C2 is charged, the voltage across capacitor C2 may flip (the pulse from the pulse generator is high, as shown by waveform 205). In addition, as capacitor C2 charges, the voltage at the point between capacitor C2 and capacitor C3 (e.g., at the surface of the wafer) changes to approximately zero, as shown by waveform 210. Thus, the pulses from the high voltage pulse generator produce a plasma potential (e.g., a potential in the plasma) that rises from a negative high voltage to zero and back to a negative high voltage at a high frequency, with a fast rise time, a fast fall time, and / or a short pulse width.

[0092] In some embodiments, the action of the resistive output stage, the element represented by resistive output stage 102, can rapidly discharge the stray capacitance C1 and can allow the voltage at the point between capacitor C2 and capacitor C3 to rapidly return to its stable negative value of approximately -4 kV, as shown by waveform 210. The resistive output stage can allow the voltage at the point between capacitor C2 and capacitor C3 to exist for approximately % of the time and thus maximize the time that the ions are accelerated into the wafer. In some embodiments, the components included within the resistive output stage can be specifically selected to optimize the time that the ions are accelerated into the wafer and to keep the voltage approximately constant during that time. Thus, for example, a short pulse with a fast rise time and a fast fall time can be useful so that there can be a long period of fairly uniform negative potential.

[0093] The nanosecond pulse generator system 100 may generate various other waveforms.

[0094] Figure 3 is a circuit diagram of a nanosecond pulse generator system 300 having a pulse generator and transformer stage 101 and an energy recovery circuit 305 according to some embodiments. For example, the energy recovery circuit may replace Figure 1The resistive output stage 102 shown. In this example, the energy recovery circuit 165 can be positioned on or electrically coupled to the secondary side of the transformer T1. For example, the energy recovery circuit 165 can include a diode 330 (e.g., a crowbar diode) across the secondary side of the transformer T1. For example, the energy recovery circuit 165 can include a diode 310 and an inductor 155 (arranged in series), which can allow current to flow from the secondary side of the transformer T1 to charge the power supply C7. The diode 310 and the inductor 155 can be electrically connected to the secondary side of the transformer T1 and the power supply C7. In some embodiments, the energy recovery circuit 165 can include a diode 335 and / or an inductor 340 electrically coupled to the secondary of the transformer T1. The inductor 340 can represent a stray inductance, and / or can include the stray inductance of the transformer T1.

[0095] When the nanosecond pulse generator is on, current can charge the load stage 106 (e.g., charging capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7, some current can flow through inductor 155. When the nanosecond pulse generator is off, current can flow from the capacitor within the load stage 106 through inductor 155 to charge power supply C7 until the voltage across inductor 155 is zero. Diode 330 can prevent the capacitor within the load stage 106 from looping with the inductance in the load stage 106 or the DC bias compensation circuit 104.

[0096] For example, diode 310 may prevent charge from flowing from power source C7 to capacitors within load stage 106 .

[0097] The value of inductor 155 may be selected to control the current fall time. In some embodiments, inductor 155 may have an inductance value between 1 μH-500 μH.

[0098] In some embodiments, the energy recovery circuit 165 may include an energy recovery switch that may be used to control the flow of current through the inductor 155. For example, the energy recovery switch may be placed in series with the inductor 155. In an embodiment, when the switch S1 is open and / or no longer pulsing, the energy recovery switch may be closed to allow current to flow from the load stage 106 back to the high voltage load C7.

[0099] In some embodiments, the energy recovery switch may include multiple switches arranged in series to collectively open and close the high voltage. For example, the energy recovery switch may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed on November 1, 2018, entitled “High Voltage Switch with Isolated Power”, which is incorporated herein in its entirety for all purposes.

[0100] In some embodiments, the nanosecond pulse generator system 150 can generate Figure 2 The waveform shown is similar to the waveform.

[0101] Figure 4A is a cross-sectional side view block diagram of a spatially variable wafer bias power system 400 according to some embodiments, and Figure 4B It is a top view frame diagram. Figure 4A The cross-sectional side view shown is along the line A shown by B. The spatially variable wafer bias power system 400 includes two electrodes: a first electrode 415 and a second electrode 420. The wafer 405 can be placed on the wafer platform 410 above both the first electrode 415 and the second electrode 420. The wafer platform 410 can include a dielectric material (e.g., such as ceramic). The first electrode 415 can be disc-shaped, having a diameter that is smaller than the diameter of one or both of the wafer platform 410 or the wafer 405. The second electrode 420 can have a ring shape, having an aperture diameter that is slightly larger than the diameter of the first electrode 415 and an outer diameter that is substantially similar to one or both of the diameter of the wafer platform 410 or the wafer 405. The first electrode 415 can be placed within the aperture of the second electrode 420.

[0102] In some embodiments, the gap between the first electrode 415 and the second electrode 420 may be less than about 0.1 mm, 1.0 mm, 5.0 mm, etc. In some embodiments, the space between the first electrode 415 and the second electrode 420 may be filled with air, vacuum, insulating gas, solid dielectric material, or other insulating material.

[0103] In some embodiments, the thickness of the first electrode 415 and the second electrode 420 may be substantially the same thickness. In some embodiments, the first electrode 415 and the second electrode 420 may have different thicknesses.

[0104] In some embodiments, the second electrode 420 may have an area of ​​5% to 50% of the area of ​​the wafer platform.

[0105] In some embodiments, the first electrode 415 and the second electrode 420 may include the same material or different materials.

[0106] In some embodiments, the first high voltage pulse generator 425 can be coupled to the first electrode 415, and the second high voltage pulse generator 430 can be coupled to the second electrode 420. For example, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 can include the pulse generator and transformer stage 101 of the nanosecond pulse generator system 100.

[0107] In some embodiments, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 may provide different pulses. For example, the peak voltage provided to the second electrode 420 by the second high voltage pulse generator 430 may be different from the peak voltage provided to the first electrode 415 by the first high voltage pulse generator 425. As another example, the pulse repetition frequency provided to the second electrode 420 by the second high voltage pulse generator 430 may be different from the pulse repetition frequency provided to the first electrode 415 by the first high voltage pulse generator 425. As another example, the ion current provided to the second electrode 420 by the second high voltage pulse generator 430 may be different from the ion current provided to the first electrode 415 by the first high voltage pulse generator 425.

[0108] In some embodiments, the first high voltage pulse generator 425 and the second high voltage pulse generator may provide substantially the same pulses. For example, the peak voltage provided to the second electrode 420 by the second high voltage pulse generator 430 may be substantially the same as the peak voltage provided to the first electrode 415 by the first high voltage pulse generator 425. As another example, the pulse repetition frequency provided to the second electrode 420 by the second high voltage pulse generator 430 may be substantially the same as the pulse repetition frequency provided to the first electrode 415 by the first high voltage pulse generator 425. As another example, the ion current provided to the second electrode 420 by the second high voltage pulse generator 430 may be substantially the same as the ion current provided to the first electrode 415 by the first high voltage pulse generator 425.

[0109] The first high voltage pulse generator 425 may include any or all components of the nanosecond pulse generator system 100. The first high voltage pulse generator 425 may include any or all components of the nanosecond pulse generator system 300. In some embodiments, the first high voltage pulse generator 425 may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed on November 1, 2018, entitled “High Voltage Switch with Isolated Power”, which is incorporated in its entirety into the present disclosure for all purposes. In some embodiments, the first high voltage pulse generator 425 may include an RF generator.

[0110] The first high voltage pulse generator 425 may include any or all components of the nanosecond pulse generator system 100. The first high voltage pulse generator 425 may include any or all components of the nanosecond pulse generator system 100. In some embodiments, the first high voltage pulse generator 425 may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed on November 1, 2018, entitled “High Voltage Switch with Isolated Power”, which is incorporated in its entirety into the present disclosure for all purposes. In some embodiments, the second high voltage pulse generator 430 may include an RF generator.

[0111] In some embodiments, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 can provide separately controlled pulse bias voltages or different pulse repetition frequencies or out-of-phase pulses so that the edge voltage pulses applied to the wafer by the second electrode 420 are different from the voltage applied to the center of the wafer by the first electrode 415. For example, the separate voltages can produce a different electric field distribution pattern at the edge of the wafer compared to the center so that the electric field or bias voltage across the wafer 405 is uniform. For example, this can optimize wafer yield. In some embodiments, the second high voltage pulse generator 430 can operate at a lower voltage than the first high voltage pulse generator 425, for example, for example, the second high voltage pulse generator 430 can operate at 5%, 10%, 15%, 20%, 25%, 30%, etc. of the voltage of the first high voltage pulse generator 425.

[0112] In some embodiments, the pulses provided by the first high voltage pulse generator 425 may be independently controlled relative to the second high voltage pulse generator 430 .

[0113] In some embodiments, the spatially variable wafer bias power system may generate a uniform electric field (eg, less than approximately 5%, 10%, 15%, or 20% variation) or uniform voltage across the top of the wafer platform 410 or wafer 405 .

[0114] In some embodiments, the spatially variable wafer bias power system may generate a non-uniform electric field or a non-uniform voltage across the top of the wafer platform 410 or the wafer 405 .

[0115] In some embodiments, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 may be capacitively coupled via a capacitance between approximately 1 pF and 100 nF.

[0116] In some embodiments, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 can be linked. For example, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 can include a single nanosecond pulse generator with a voltage divider (e.g., a resistor, an inductor, or a capacitor) that generates different voltages for the first electrode 415 and the second electrode 420. As another example, a single pulse generator on the primary side of the transformer can be coupled to multiple loads (and energy recovery circuits, resistive output stages, or bias compensation circuits) coupled to different secondary windings on the secondary side of the transformer T2. Different secondary windings can have different numbers of windings to generate different voltages.

[0117] Although in Figure 4A 4. Although two electrodes are shown in FIG. 4, any number of electrodes may be used in conjunction with any number of nanosecond pulse generators in some embodiments. In some embodiments, the first electrode 415 or the second electrode 420 may include any geometric area below the wafer platform 410 having any geometric shape. Similarly, additional electrodes and nanosecond pulse generators may be included, and the additional electrodes may have any shape and be disposed in any position relative to the other electrodes and relative to the wafer platform.

[0118] In some embodiments, the leads from the first high voltage pulse generator 425 to the first electrode 415 and the leads from the second high voltage pulse generator 430 to the second electrode 420 can be grouped or bundled together. For example, such bundling can allow the total stray capacitance of the bundled leads to be less than if each lead were routed separately. For example, such bundling can also save power. In some embodiments, the leads can be arranged in a coaxial configuration or a dual lead configuration or arranged as a twisted pair. In some embodiments, the stray capacitance from the output to the ground can be less than about 100pF, or less than about 1nF or 10nF, etc. In some embodiments, the stray inductance of the output can be less than about 100nH, 1μH, 10μH, etc. In some embodiments, the capacitive coupling between each output can be less than about 100pF, 1nF, 10nF, etc.

[0119] Figure 5 is a block diagram of a spatially variable wafer bias power system 500 according to some embodiments. The spatially variable wafer bias power system 500 may include a first high voltage pulse generator 425 and a second high voltage pulse generator 430 .

[0120] The interconnection board 505 can be electrically coupled to the first high voltage pulse generator 425 and the second high voltage pulse generator 430 or an additional high voltage pulse generator. In some embodiments, the interconnection board 505 can provide a high DC voltage to each of the first high voltage pulse generator 425 or the second high voltage pulse generator 430. In some embodiments, the interconnection board 505 can provide a trigger signal to the first high voltage pulse generator 425 or the second high voltage pulse generator 430. In some embodiments, the interconnection board 405 can provide a low voltage pulse to the first high voltage pulse generator 425 or the second high voltage pulse generator 430.

[0121] In some embodiments, the interconnect board 405 may include a controller or processor that includes one or more components of the computing system 900. In some embodiments, one or more sensors may be included that measure characteristics of the plasma chamber (e.g., such as the electric field on the surface of the wafer, the uniformity of the electric field, the voltage on the first electrode 415, the voltage on the second electrode 420, the voltage across one or more resistor output stages or resistors in one or more energy recovery circuits). Based on the measurements from the sensors, the voltage, pulse width, or pulse repetition frequency of the first high voltage pulse generator 425 and the second high voltage pulse generator 430 may be adjusted.

[0122] For example, if the voltage on the second electrode 420 is measured and determined to be lower than the voltage on the first electrode 415, this may result in electric field non-uniformity across the surface of the wafer (e.g., less than about 5%, 10%, 15%, or 20% difference). The controller may adjust the pulse width of the control pulse being sent to the second high voltage pulse generator 430, which may increase the voltage generated by the second high voltage pulse generator 430 (e.g., by increasing the capacitive charging time), and thus increase the electric field on the second electrode. This process may be repeated until the electric field across the surface of the wafer is uniform (e.g., within 10%, 15%, 20%, 25%, etc.).

[0123] As another example, the voltage across the first resistive output stage and the second resistive output stage can be measured. These voltages can correspond to the ion current flowing in the chamber. The current can be affected by the electrode voltage. If the ion current to the first electrode and the ion current to the second electrode are uneven or misaligned (e.g., a difference greater than 10%, 20%, or 30%), the controller can adjust the pulse width of the control pulse being sent to the first high voltage pulse generator 425 or the second high voltage pulse generator 430, which can increase the voltage generated by the nanosecond pulse generator (e.g., by increasing the capacitive charging time), and thus increase the electric field on the corresponding electrode.

[0124] In some embodiments, pulses from the first high voltage pulse generator 425 and the second high voltage pulse generator 430 may be delivered to the energy recovery circuit 525 and the plasma chamber 535 via the chamber interface board or the bias compensation circuit 510. For example, the energy recovery circuit 525 may include the resistive output stage 102 of the nanosecond pulse generator system 100. As another example, the energy recovery circuit 525 may include the energy recovery circuit 305. As another example, the energy recovery circuit 525 may not be required. As another example, the energy recovery circuit 525 may be coupled to one or both of the first high voltage pulse generator 425 or the second high voltage pulse generator 430. In some embodiments, the plasma chamber 535 may include a plasma chamber, an etching chamber, a deposition chamber, etc. In some embodiments, the active circuit of the plasma chamber 535 may include the load stage 106.

[0125] Although two high voltage pulse generators are shown, any number may be used. For example, multiple electrode rings may be coupled to multiple high voltage pulse generators.

[0126] In some embodiments, the first high voltage pulse generator 425 may generate pulses that are different from the pulses generated by the second high voltage pulse generator 430. For example, the first high voltage pulse generator 425 may provide a pulse of at least 2 kV of pulsed output. In some embodiments, the second high voltage pulse generator 430 may provide a pulse of at least 2 kV of pulsed output that is the same as or different from the pulse provided by the first high voltage pulse generator 425.

[0127] As another example, the first high voltage pulse generator 425 can generate pulses having a first pulse repetition frequency, and the second high voltage pulse generator 430 can generate pulses having a second pulse repetition frequency. The first pulse repetition frequency and the second pulse repetition frequency can be the same or different. The first pulse repetition frequency and the second pulse repetition frequency can be in phase or out of phase with respect to each other.

[0128] As another example, the first high voltage pulse generator 425 can generate a first plurality of bursts having a first burst repetition frequency, and the second high voltage pulse generator 430 can generate a second plurality of bursts having a second burst repetition frequency. Each burst can include a plurality of pulses. The first burst repetition frequency and the second burst repetition frequency can be the same or different. The first burst repetition frequency and the second burst repetition frequency can be in phase or out of phase with respect to each other.

[0129] In some embodiments, the first high voltage pulse generator 425 and the second high voltage pulse generator 430 may be water cooled or dielectric cooled.

[0130] Figure 6is a schematic diagram of a spatially variable wafer bias system 600 according to some embodiments. The spatially variable wafer bias system 600 may include a first high voltage pulse generator 425 and a second high voltage pulse generator 430 coupled to a plasma chamber 535 .

[0131] In this example, first high voltage pulse generator 425 includes first resistive output stage 610 and first bias capacitor 615. In some embodiments, first resistive output stage 610 may not be used and an energy recovery circuit may be used, such as, for example, as shown in nanosecond pulse generator system 300.

[0132] In this example, the second high voltage pulse generator 430 includes a second resistive output stage 620 and a second bias capacitor 625. In some embodiments, the first resistive output stage 620 may not be used, and an energy recovery circuit may be used, such as, for example, as shown in nanosecond pulse generator system 300.

[0133] The first electrode 415 and the second electrode 420 are disposed in the plasma chamber 535. In this example, the first electrode 415 is disk-shaped and is disposed within the central aperture of the second electrode 420. The first high voltage pulse generator 425 is electrically coupled to the first electrode 415, and the second high voltage pulse generator 430 is electrically coupled to the second electrode 420. In some embodiments, there may be a stray coupling capacitance 630 between the first high voltage pulse generator 425 and the second high voltage pulse generator 430. For example, the stray coupling capacitance 630 may be, for example, less than about 100 pF, about 1 nF, about 10 nF, etc.

[0134] Figure 7 is a schematic diagram of a spatially variable wafer bias system 700 according to some embodiments. In this example, the spatially variable wafer bias system 700 utilizes multiple isolated secondary windings to provide different voltages on two different wafer spatial regions. The spatially variable wafer bias system 700 includes a single high voltage pulse generator 705. The single high voltage pulse generator 705 may include Figure 1 or Figure 3 1. The pulse generator and transformer stage 101 shown. In this example, two distinct secondary winding sets can be wound around the transformer T1. The first secondary winding 710 can be electrically coupled to the first resistive output stage 610 and the first bias capacitor 615 forming the first electrode channel. The second secondary winding 715 can be electrically coupled to the second resistive output stage 620 and the second bias capacitor 625 forming the second electrode channel. In some embodiments, there can be a stray coupling capacitance 630 between the first electrode channel and the second electrode channel. For example, the stray coupling capacitance 630 can be less than about 100 pF, about 1 nF, about 10 nF, etc.

[0135] In some embodiments, a first energy recovery circuit (e.g., energy recovery circuit 305) may be used instead of the first resistance output stage 610, and a second energy recovery circuit (e.g., energy recovery circuit 305) may be used instead of the second resistance output stage 620. The first energy recovery circuit and the second energy recovery circuit may be arranged in parallel.

[0136] The voltage on the first electrode 415 and the second voltage on the second electrode 420 may depend on the number of windings in the first secondary winding and the second secondary winding.

[0137] Figure 8 8 is a schematic diagram of a spatially variable wafer bias system 800 according to some embodiments. In this example, the spatially variable wafer bias system 800 utilizes a voltage divider to provide different voltages on two different wafer spatial regions. The spatially variable wafer bias system 800 includes a single high voltage pulse generator 805 and a voltage divider 810. The voltage divider 810 may include a plurality of resistors and capacitors. The values ​​of the resistors and capacitors may be selected to provide a voltage ratio of a voltage of a pulse provided to a first electrode channel that provides a pulse to a first electrode 415 to a voltage of a pulse provided to a second electrode channel that provides a pulse to a second electrode 420.

[0138] The first electrode channel may include a first resistive output stage 610 and a first biasing capacitor 615. The second electrode channel may include a second resistive output stage 620 and a second biasing capacitor 625.

[0139] In some embodiments, there may be a stray coupling capacitance 630 between the first electrode channel and the second electrode channel. For example, the stray coupling capacitance 630 may be less than about 100 pF, about 1 nF, about 10 nF, etc.

[0140] In some embodiments, a first energy recovery circuit (e.g., energy recovery circuit 305) may be used instead of the first resistance output stage 610, and a second energy recovery circuit (e.g., energy recovery circuit 305) may be used instead of the second resistance output stage 620. The first energy recovery circuit and the second energy recovery circuit may be arranged in parallel.

[0141] Unless otherwise specified, the term "substantially" means within 5% or 10% of the referenced value or within manufacturing tolerances. Unless otherwise specified, the term "approximately" means within 5% or 10% of the referenced value or within manufacturing tolerances.

[0142] Fig. 9The computing system 900 shown may be used to perform any embodiment of the present invention. As another example, the computing system 900 may be used to perform any calculation, identification, and / or determination described herein. The computing system 900 includes hardware elements that may be electrically coupled via a bus 905 (or may communicate in other ways as appropriate). The hardware elements may include one or more processors 910, including but not limited to one or more general-purpose processors and / or one or more special-purpose processors (e.g., digital signal processing chips, graphics acceleration chips, etc.); one or more input devices 915, which may include but are not limited to a mouse, a keyboard, etc.; and one or more output devices 920, which may include but are not limited to a display device, a printer, etc.

[0143] The computing system 900 may also include (and / or communicate with) one or more storage devices 925, which may include, but are not limited to, local and / or network accessible storage, and / or may include, but are not limited to, disk drives, drive arrays, optical storage devices, solid-state storage devices (e.g., random access memory ("RAM") and / or read-only memory ("ROM")), which may be programmable, flash memory updateable, etc. The computing system 900 may also include a communication subsystem 930, which may include, but are not limited to, a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device and / or a chipset (e.g., a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMax device, a cellular communication facility, etc.), etc. The communication subsystem 930 may allow data to be exchanged with a network (e.g., the network described below, to name just one example) and / or any other device described herein. In many embodiments, the computing system 900 will also include a working memory 935, which may include a RAM or ROM device, as described above.

[0144] The computing system 900 may also include software elements, shown as currently being located in the working memory 935, including an operating system 940 and / or other code (e.g., one or more application programs 945), which may include the computer program of the present invention, and / or may be designed to implement the method of the present invention and / or configure the system of the present invention, as described herein. For example, one or more processes described with respect to the method discussed above may be implemented as codes and / or instructions that can be executed by a computer (and / or a processor within a computer). These instructions and / or code sets may be stored on a computer-readable storage medium (e.g., the storage device 925 described above).

[0145] In some cases, the storage medium may be incorporated into or in communication with the computing system 900. In other embodiments, the storage medium may be separate from the computing system 900 (e.g., removable media (e.g., compact disk, etc.)), and / or provided in the form of an installation package so that the storage medium can be used to program a general-purpose computer through the instructions / code stored thereon. These instructions may take the form of executable code that can be executed by the computing system 900, and / or may take the form of source code and / or installable code, which when compiled and / or installed on the computing system 900 (e.g., using any of a variety of general-purpose compilers, installers, compression / decompression utilities, etc.), then takes the form of executable code.

[0146] Numerous specific details are set forth herein to provide a thorough understanding of the claimed subject matter. However, it will be appreciated by those skilled in the art that the claimed subject matter may be practiced without these specific details. In other instances, methods, devices, or systems known to those of ordinary skill in the art have not been described in detail so as not to obscure the claimed subject matter.

[0147] Some parts are presented in view of algorithms or symbolic representations of operations on data bits or binary digital signals stored in a computing system memory (e.g., computer memory). These algorithmic descriptions or representations are examples of techniques used by ordinary technicians in the field of data processing to convey the essence of their work to other technicians in the field. An algorithm is a self-consistent sequence of operations or similar processes that lead to a desired result. In this context, the operations or processes involve physical manipulations of physical quantities. Typically, but not necessarily, these quantities can take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared or otherwise manipulated. Mainly for reasons of common use, it has sometimes proven convenient to refer to these signals as bits, data, values, elements, symbols, characters, terms, numbers, numerical values, etc. However, it should be understood that all of these and similar terms are associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, it should be understood that throughout the specification, discussions utilizing terms such as "process," "compute," "calculate," "determine," and "identify" refer to actions or processes of a computing device (e.g., one or more computers or similar electronic computing devices) that manipulate or transform data represented as physical electronic or magnetic quantities within a memory, register, or other information storage device, transmission device, or display device of a computing platform.

[0148] The one or more systems discussed herein are not limited to any particular hardware architecture or configuration. A computing device may include any suitable arrangement of components that provide a result conditioned on one or more inputs. Suitable computing devices include multi-purpose microprocessor-based computer systems that access stored software that programs or configures a computing system from a general-purpose computing device to implement one or more embodiments of the present subject matter. Any suitable programming, scripting, or other type of language or combination of languages ​​may be used to implement the teachings contained herein in implementing software to be used in programming or configuring a computing device.

[0149] Embodiments of the methods disclosed herein may be performed in the operation of these computing devices. The order of the blocks presented in the above examples may be changed—for example, the blocks may be reordered, combined, and / or decomposed into sub-blocks. Certain blocks or processes may be performed in parallel.

[0150] The use of "suitable for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more stated conditions or values ​​may actually be based on additional conditions or values ​​beyond the stated conditions or values. The headings, lists, and numbering included herein are for ease of explanation only and are not intended to be limiting.

[0151] Although the subject matter has been described in detail with respect to specific embodiments of the subject matter, it should be understood that those skilled in the art can easily generate changes, modifications and equivalents to these embodiments when realizing the understanding of the foregoing. Accordingly, it should be understood that the present disclosure has been presented for the purpose of illustration and not limitation, and does not exclude the inclusion of such modifications, modifications and / or additions to the subject matter, as will be readily apparent to those of ordinary skill in the art.

Claims

1. A power system having a plasma load, comprising: a first high voltage pulse generator outputting a first plurality of pulses having a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high voltage pulse generator that outputs a second plurality of pulses having a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; Chamber; a first electrode disposed within the chamber and electrically coupled to the first high voltage pulse generator; and a second electrode disposed within the chamber adjacent to the first electrode and electrically coupled to the second high voltage pulse generator; The chamber includes one or both of a wafer and plasma, and the plasma is capacitively coupled to the first electrode and the second electrode with a capacitance between 10 pF and 1 μF.

2. The system of claim 1, wherein: The electric field across the surface of the wafer is uniform to within 25%.

3. The system of claim 1, wherein: The coupling capacitance between the first electrode and the corresponding part of the wafer is greater than 100 pF; and the capacitance between the second electrode and the corresponding part of the wafer is greater than 100 pF.

4. The system of claim 1, wherein: The chamber includes a plasma, ions of which are accelerated onto the wafer.

5. The system of claim 1, wherein: The first high-voltage pulse generator generates an electrode voltage on the first electrode greater than 1 kV, and the second high-voltage pulse generator generates an electrode voltage on the second electrode greater than 1 kV.

6. The system of claim 1, wherein: A ratio of the first voltage relative to the second voltage is less than 2 to 1, or vice versa.

7. The system of claim 1, wherein: One or both of the first electrode and the second electrode are axially symmetric.

8. The system of claim 1, wherein: The first electrode has a first planar surface, and the second electrode has a second planar surface, such that the second planar surface is 25% of a sum of the first planar surface and the second planar surface.

9. The system of claim 1, wherein: Both the first high voltage pulse generator and the second high voltage pulse generator include a resistive output stage.

10. The system of claim 1, wherein: Both the first high voltage pulse generator and the second high voltage pulse generator include an energy recovery circuit.

11. The system of claim 1, wherein: Parameters of the first plurality of pulses are controlled independently of parameters of the second plurality of pulses.

12. The system of claim 1, wherein: The first pulse repetition frequency and the second pulse repetition frequency are in phase with respect to each other.

13. The system of claim 1, wherein: The coupling capacitance between the first electrode and the second electrode is less than 10 nF.

14. A power system having a plasma load, comprising: a first high voltage pulse generator outputting a first plurality of pulses having a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high voltage pulse generator that outputs a second plurality of pulses having a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; Chamber; A first electrode is disposed in the chamber and electrically coupled to the first high voltage pulse generator, wherein the first electrode comprises: Disc shape, central axis, and Outside diameter; and a second electrode adjacent to the first electrode and disposed in the chamber and electrically coupled to the second high voltage pulse generator, wherein the second electrode comprises: a disk shape having a central aperture, the first electrode being disposed within the central aperture; a central axis that is aligned with the central axis of the first electrode, The aperture diameter, and outer diameter.

15. A method comprising: pulsing a first high voltage pulse generator coupled to a first electrode in a plasma chamber, the first high voltage pulse generator pulsing at a first voltage greater than 1 kV and at a first pulse repetition frequency greater than 20 kHz and at a first pulse width; pulsing a second high voltage pulse generator coupled to a second electrode in the plasma chamber, the second high voltage pulse generator pulsing at a second voltage greater than 1 kV and at a second pulse repetition frequency greater than 20 kHz and at a second pulse width, wherein the first electrode and the second electrode are disposed below a wafer; measuring parameters corresponding to physical phenomena occurring in the plasma chamber; and adjusting an amount of at least one of the second voltage, the second pulse repetition frequency, and a second pulse generator width based on the measured parameter; The parameter is a current flowing through a resistor in the first high voltage pulse generator.

16. The method of claim 15, wherein: The physical phenomena occurring within the plasma chamber correspond to the uniformity of the electric field across the surface of the wafer.

17. The method of claim 15, wherein: The physical phenomena occurring within the plasma chamber correspond to the uniformity of the ion current across the surface of the wafer.

18. A power system having a plasma load, comprising: a first high voltage pulse generator outputting a first plurality of pulses having a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high voltage pulse generator that outputs a second plurality of pulses having a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; Chamber; a first electrode disposed within the chamber and electrically coupled to the first high voltage pulse generator; and a second electrode disposed within the chamber adjacent to the first electrode and electrically coupled to the second high voltage pulse generator; Wherein the chamber includes one or both of a wafer and a plasma, the electric field across the surface of the wafer is uniform within 25%.

19. The system of claim 18, wherein: The first high-voltage pulse generator generates an electrode voltage on the first electrode greater than 1 kV, and the second high-voltage pulse generator generates an electrode voltage on the second electrode greater than 1 kV.

20. The system of claim 18, wherein: A ratio of the first voltage relative to the second voltage is less than 2 to 1, or vice versa.

21. The system of claim 18, wherein: One or both of the first electrode and the second electrode are axially symmetric.

22. The system of claim 18, wherein: Parameters of the first plurality of pulses are controlled independently of parameters of the second plurality of pulses.

23. The system of claim 18, wherein: The first pulse repetition frequency and the second pulse repetition frequency are in phase with respect to each other.

24. The system of claim 18, wherein: The coupling capacitance between the first electrode and the second electrode is less than 10 nF.

25. A power system having a plasma load, comprising: a first high voltage pulse generator outputting a first plurality of pulses having a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high voltage pulse generator that outputs a second plurality of pulses having a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; Chamber; a first electrode disposed within the chamber and electrically coupled to the first high voltage pulse generator; and a second electrode disposed within the chamber adjacent to the first electrode and electrically coupled to the second high voltage pulse generator; Wherein, the chamber includes one or both of a wafer and plasma, the coupling capacitance between the first electrode and the corresponding part of the wafer is greater than 100 pF; and the capacitance between the second electrode and the corresponding part of the wafer is greater than 100 pF.

26. The system of claim 25, wherein: The first high-voltage pulse generator generates an electrode voltage on the first electrode greater than 1 kV, and the second high-voltage pulse generator generates an electrode voltage on the second electrode greater than 1 kV.

27. The system of claim 25, wherein: A ratio of the first voltage relative to the second voltage is less than 2 to 1, or vice versa.

28. The system of claim 25, wherein: One or both of the first electrode and the second electrode are axially symmetric.

29. The system of claim 25, wherein: Parameters of the first plurality of pulses are controlled independently of parameters of the second plurality of pulses.

30. The system of claim 25, wherein: The first pulse repetition frequency and the second pulse repetition frequency are in phase with respect to each other.

31. A power system having a plasma load, comprising: a first high voltage pulse generator outputting a first plurality of pulses having a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high voltage pulse generator that outputs a second plurality of pulses having a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse repetition frequency greater than 20 kHz; Chamber; a first electrode disposed within the chamber and electrically coupled to the first high voltage pulse generator; and a second electrode disposed within the chamber adjacent to the first electrode and electrically coupled to the second high voltage pulse generator; The first electrode has a first flat surface, and the second electrode has a second flat surface, such that the second flat surface is 25% of the sum of the first flat surface and the second flat surface.

32. The system of claim 31, wherein: The first high-voltage pulse generator generates an electrode voltage on the first electrode greater than 1 kV, and the second high-voltage pulse generator generates an electrode voltage on the second electrode greater than 1 kV.

33. The system of claim 31, wherein: A ratio of the first voltage relative to the second voltage is less than 2 to 1, or vice versa.

34. The system of claim 31, wherein: One or both of the first electrode and the second electrode are axially symmetric.

35. The system of claim 31, wherein: Parameters of the first plurality of pulses are controlled independently of parameters of the second plurality of pulses.

36. The system of claim 31, wherein: The first pulse repetition frequency and the second pulse repetition frequency are in phase with respect to each other.

37. The system of claim 31, wherein: The coupling capacitance between the first electrode and the second electrode is less than 10 nF.

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