Processing circuit

Abstract

The present application relates to a device and method for multiplying signals. A multiplication circuit (100) has a first time-coded modulator (103a) and a second time-coded modulator (103b), wherein the first time-coded modulator (103a) and the second time-coded modulator (103b) are configured to receive a first combined signal (S C1 ) and the second combined signal (S C2 ) and generate respective first PWM signals (S) each having a cycle frequency that substantially depends on the square of the value of the input combined signal PWM1 ) and the second PWM signal (S PWM2 ). The first combined signal (S C1 ) corresponds to the sum of the first input signal (S1) and the second input signal (S2), and the second combined signal (S C2 ) corresponds to the difference between the first input signal (S1) and the second input signal (S2). The first time decoding converter (104a) and the second time decoding converter (104b) receive the first PWM signal and the second PWM signal and provide a corresponding first count value (D1) and a second count value (D2) based on a parameter related to the frequency of the corresponding first PWM signal or the second PWM signal. The subtractor (105) determines the difference between the first count value (D1) and the second count value (D2) and provides an output signal (D1) based on the difference. OUT ).

Description

[0001] The present application relates to methods and devices for processing signals, and in particular to devices and methods for multiplication of signals.

[0002] There are some signal processing applications in which it may be desirable to multiply a first signal, which may be received as an input analog signal, by a value represented by a second signal. For example, in some audio applications for speech processing, it may be desirable to apply variable weightings to multiple input analog signals derived from a microphone prior to some downstream processing that may involve digital processing.

[0003] Analog circuit techniques for multiplying analog signals are known, such as using nonlinearities in the electrical characteristics of active devices that are carefully biased to operate within an appropriate range. However, because analog circuits used for multiplication may suffer from device mismatch, thermal drift, power supply noise, etc., and may require relatively complex arrangements to tune operation for a range of operating conditions and manufacturing tolerances, such multiplications are conventionally implemented digitally. Therefore, the first signal and (if necessary) the second signal may be converted to digital signals, and the multiplication implemented as part of the digital processing.

[0004] Digital multiplication of two signals can be easily achieved.However, in general, digital processing may involve a relatively large number of circuit nodes that potentially change between high voltage and low voltage in each sampling cycle, which inevitably involves certain power consumption and heat generation.

[0005] In some applications, such as for battery powered devices, power consumption is a significant consideration, particularly for any process that might be expected to operate relatively frequently.

[0006] Accordingly, embodiments of the present disclosure provide processing circuits that address at least some of the issues discussed above.

[0007] Therefore, there is provided a processing circuit comprising:

[0008] a first time coded modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first PWM signal having a cyclic frequency that depends substantially on the square of a value of the first combined signal;

[0009] a second time coded modulator configured to receive a second combined signal corresponding to a difference between the first input signal and the second input signal and to generate a second PWM signal having a cyclic frequency that depends substantially on the square of a value of the second combined signal;

[0010] a first time-decoding converter configured to receive the first PWM signal and provide a first count value based on a first parameter of the first PWM signal;

[0011] a second time-decoded converter configured to receive the second PWM signal and provide a second count value based on a second parameter of the second PWM signal; and

[0012] A subtractor is configured to determine a difference between the first count value and the second count value and output an output signal based on the difference between the first count value and the second count value.

[0013] In some implementations, the first parameter may be a PWM cycle frequency of the first PWM signal, and the second parameter may be a PWM cycle frequency of the second PWM signal. The first time-decoded converter and the second time-decoded converter may each include a counter configured to receive a reference clock signal and count the number of PWM cycles in each of consecutive count periods defined by the reference clock signal to provide a count value.

[0014] In some implementations, the first parameter may be a PWM cycle period of the first PWM signal, and the second parameter may be a PWM cycle period of the second PWM signal. The first time-decoding converter and the second time-decoding converter may each include a counter configured to receive a reference clock signal and count the number of cycles of the reference clock signal in a PWM cycle period defined by a corresponding one of the first PWM signal or the second PWM signal to provide a count value. In some examples, the processing circuit is configured to limit the value of each of the first combination signal and the second combination signal to no greater than a defined limit, so that a maximum change in the cycle frequency of the corresponding first PWM signal or the second PWM signal is no greater than 25%.

[0015] In some implementations, the first time-decoding converter and the second time-decoding converter may each include a corresponding counter configured to receive a reference clock signal, and the processing circuit may be selectively operable in a first mode or a second mode. In the first operating mode, the first parameter and the second parameter may be the PWM cycle frequencies of the first PWM signal and the second PWM signal, respectively, in which case the counters of the first time-decoding converter and the second time-decoding converter may each be configured to count the number of PWM cycles in each of the consecutive counting periods defined by the reference clock signal to provide a count value. In the second operating mode, the first parameter and the second parameter may be the PWM cycle period of the first PWM signal and the second PWM signal, respectively, and the counters of the first time-decoding converter and the second time-decoding converter may each be configured to count the number of cycles of the reference clock signal in the PWM cycle period defined by the corresponding one of the first PWM signal or the second PWM signal to provide a count value. The frequency of the reference clock signal may be greater in the second mode than in the first mode.

[0016] In some examples, each of the first time-coded modulator and the second time-coded modulator may include: a forward signal path, the forward signal path is configured to receive the corresponding first combined signal or the second combined signal at a first input; and a feedback path, the feedback path forms a feedback loop with at least a portion of the forward signal path. A comparator may be located in the forward signal path within the feedback loop, and a filter arrangement may also be present within the feedback loop. In some instances, the comparator may be arranged to receive the associated first combined signal or the second combined signal at a first comparator input, and receive a signal from the feedback path at a second comparator input. The filter arrangement may be configured to apply filtering in the feedback path. In some instances, the input signal may be combined with a signal from the feedback path and supplied to a comparator input for comparison with a reference value. In this case, the filter may be configured to apply filtering to the combined signal.

[0017] In some examples, the comparator is a hysteresis comparator.

[0018] The filter arrangement may comprise a resistor-capacitor filter.

[0019] In some examples, one of the first time-coded modulator and the second time-coded modulator may include a current generator configured to receive a corresponding one of the first PWM signal or the second PWM signal output from the comparator, and generate a first controlled current signal having a first defined current during a period of a first voltage state of the PWM signal, and generate a second controlled current signal during a period of a second voltage state of the PWM signal. A capacitor may be configured to be charged and discharged by the first controlled current signal.

[0020] The processing circuit may also include: a signal combiner, the signal combiner having a first combiner element configured to combine the first input signal and the second input signal in an additive manner to generate the first combined signal and a second combiner element configured to combine the first input signal and the second input signal in a subtractive manner to generate the first combined signal. In some examples, the first combiner element may include a first current source and a second current source, the first current source and the second current source are configured to provide currents defined by the first input signal and the second input signal, respectively, wherein the first current source and the second current source are configured to supply currents with the same polarity to the output node of the first combiner element. The second combiner element may include a third current source and a fourth current source, the third current source and the fourth current source are configured to provide currents defined by the first input signal and the second input signal, respectively, wherein the third current source and the fourth current source are configured to supply currents with opposite polarities to the output node of the second combiner element.

[0021] The processing circuit may be implemented as an integrated circuit. Embodiments also relate to an electronic device comprising a processing circuit according to any of the variations discussed herein. The device may be at least one of: a battery powered device; a portable device; a communication device; a mobile phone; a smart phone; a computing device; a laptop; a notebook or tablet computer; a gaming device; a personal media player; a wearable device; a voice controlled device.

[0022] In another aspect, there is provided a multiplication circuit for multiplying a first input value by a second input value, comprising:

[0023] a first signal path configured to receive a first signal having a value corresponding to a sum of the first input value and the second input value and to generate a first output value as a function of the square of the value of the first signal;

[0024] a second signal path configured to receive a second signal having a value corresponding to a difference between the first input value and the second input value and to generate a second output value as a function of the square of the value of the second signal; and

[0025] a subtractor configured to determine a difference between the first output value and the second output value;

[0026] Each of the first signal path and the second signal path includes a self-oscillating time-encoded modulator and a time-decoded converter.

[0027] The multiplication circuit may further include a signal combiner configured to receive the first input value and the second input value and generate the first signal and the second signal.

[0028] In another aspect, there is provided a processing circuit comprising:

[0029] a signal combiner configured to receive a first input signal and a second input signal and to generate a first combined signal corresponding to a sum of the first input signal and the second input signal and a second combined signal corresponding to a difference between the first input signal and the second input signal;

[0030] A first time coded modulator and a second time coded modulator configured to receive the first combined signal and the second combined signal, respectively, and generate a corresponding first cyclic signal and a second cyclic signal having a cyclic frequency, wherein the cyclic frequency is substantially the same as (1-R 2 ), where R is the value of the corresponding input of the corresponding time coded modulator normalized to the range of -1 to +1 with respect to the input range of the time coded modulator; and

[0031] a first counter and a second counter, the first counter and the second counter being configured to receive the first cycle signal and the second cycle signal, respectively, and to generate a first count value and a second count value; and

[0032] A subtractor is configured to determine a difference between the first count value and the second count value.

[0033] In some examples, the first counter and the second counter are each configured to generate a count value of a number of cycles of the first cycle signal or the second cycle signal in a count period defined by a reference clock signal.

[0034] Any of the various features of the various implementations discussed herein may be implemented with any one or more of the other described features in any suitable combination, unless explicitly indicated to the contrary.

[0035] In order to better understand examples of the present disclosure and to more clearly show the manner in which the examples may be practiced, reference will now be made, by way of example only, to the following drawings, in which:

[0036] Figure 1 An example of a processing circuit according to an embodiment is shown;

[0037] Figure 2a shows an example of a time encoding modulator and a time decoding converter suitable for use in a processing circuit according to one embodiment, and Figure 2b An example of a time coded modulator is shown in more detail;

[0038] Figure 3 shows the form of the output signal from the time coded modulator;

[0039] Figure 4 Generally shows the manner in which a combined signal for a time coded modulator may be generated;

[0040] Figure 5 shows an example of a combinational circuit; and

[0041] Figure 6 Another example of a time coded modulator is shown.

[0042] Embodiments relate to methods and apparatus for processing of signals, and in particular to multiplying two signals together. Embodiments of the present disclosure are suitable for multiplying analog signals and can provide digital outputs.

[0043] Figure 1 A processing circuit 100 for multiplication according to an embodiment is generally shown. The processing circuit 100 receives a first input signal S1 and a second input signal S2 at input terminals 101a and 101b, respectively. The signals S1 and S2 may be analog signals, for example, analog voltage signals in which the voltage level of the signal may be regarded as the value of the signal, or analog current signals in which the magnitude of the current represents the magnitude of the signal value. In some embodiments, the input signals S1 and S2 may represent signal values ​​that are desired to be multiplied, for example, the first signal S1 may have a value X and the second signal S2 may have a value Y, and it may be desired to generate a value corresponding to X multiplied by Y. In this case, the input signals S1 and S2 may be input to a signal combiner 102, which generates a first combined signal S corresponding to the sum of the first signal and the second signal (i.e., S1+S2). C1 Therefore, the first combined signal S C1has a value corresponding to X+Y. The signal combiner 102 also generates a second combined signal S corresponding to the difference between the first signal and the second signal (ie, S1-S2). C2 Therefore, the second combined signal S C2 has a value corresponding to XY. As will be described in more detail below, the combiner 102 may be implemented to combine the signal S C1 and S C2 Provided as an analog circuit for analog signals, for example, if the input signals S1 and S2 are received or converted into analog current signals, the combiner 102 may be used to combine the signal S C1 The currents are combined in an additive manner and will be used to combine the signal S C2 The currents are combined in a subtractive manner.

[0044] The first combined signal S C1 and the second combined signal S C2 The TEMs 103a and 103b are input to corresponding time coded modulators (TEMs) 103a and 103b (collectively or generally referred to as 103). The TEMs 103a and 103b are based on the corresponding combined signals S input to the TEMs. C1 or S C2 Each generates a corresponding time-coded signal. In an embodiment of the present disclosure, each TEM 103 generates a repetitive or cyclic pulse width modulation (PWM) signal S PWM1 or S PWM2 , where the PWM cycle frequency is essentially dependent on the input of the TEM (i.e., the first combined signal S c1 Or the second combined signal S c2 ) squared.

[0045] As will be described in more detail below, various different types of TEMs may be implemented in which the PWM duty cycle and thus the overall PWM cycle frequency vary depending on the value of the input to the TEM, and in which the cycle frequency depends substantially on the square of the value of the input to the TEM, such as as follows:

[0046] F PWM =F0(1-R 2 ) (Equation 1)

[0047] where F PWM is the cycle frequency of the PWM signal output from TEM 103, F0 is the PWM cycle frequency when the input is zero magnitude (i.e., the limit cycle frequency), and R is the normalized value of the input within the input range, for example, normalized by some appropriate value to have a value in the range of -1 to +1, where -1 and +1 correspond to the lower and upper limits of the value of the input signal (i.e., the input signal levels that will asymptotically result in an output signal with zero frequency).

[0048] PWM signal SPWM1 and S PWM2 The digital signals D1 and D2 are input to corresponding time decoded converters (TDCs) 104a and 104b (collectively or generally referred to as 104), which generate digital signals D1 or D2 having values ​​(e.g., count values) based on the period or frequency of the corresponding PWM signal. The digital signals D1 and D2 from each TDC 104 are then subtracted from each other by a subtractor 105 to generate a digital output signal D OUT .

[0049] Therefore, the digital output signal D OUT has a value based on the difference between two count values ​​D1 and D2:

[0050] D OUT =D2-D1 (Equation 2)

[0051] As noted above, the values ​​D1 and D2 depend on the associated PWM signal S PWM1 or S PWM2 The cycle frequency F PWM In the case where the count value generated by the TDC 104 directly represents the cycle frequency of the associated PWM signal, then:

[0052] D OUT =F PWM2 -F PWM1 (Equation 3)

[0053] where F PWM1 and F PWM2 is the respective cycle frequency of the first PWM signal and the second PWM signal. As can be seen from equation 1 above, the difference between the PWM cycle frequencies depends on the values ​​of the respective inputs of TEMs 103a and 103b (i.e., the first combined signal S C1 and the second combined signal S C2 The difference between the squares of the values ​​of

[0054] As discussed above, the first combined signal S C1 is arranged to have a value corresponding to X+Y, and the second combined signal S C2 Arranged to have values ​​corresponding to XY. Therefore:

[0055] D OUT =D2-D1=F0(1-(XY) 2 )-F0(1-(X+Y) 2 )

[0056] =-F0(XY) 2 +F0(X+Y) 2 (Equation 4)

[0057] therefore:

[0058] D OU丁 =4F0XY (Equation 5)

[0059] Therefore, it can be seen that the digital output D OUT The value of is related to the product of the values ​​X and Y in a known manner.

[0060] Thus, the processing circuit 100 may receive input signals S1 and S2 having values ​​X and Y, and generate a digital value corresponding to the product of X and Y. The input signals S1 and S2 may be analog signals, and thus the processing circuit 100 may be used to multiply the analog signals. The output value may be digital, and thus the multiplication of the analog signals may be implemented as part of a process of converting from analog to digital, for example to allow further downstream processing. The arrangement of two TEMs 103 and a corresponding TDC 104 may be implemented as a relatively small and low power circuit, and thus embodiments of the present invention do not require complex analog circuits or a large number of logic gates for digital processing to implement multiplication.

[0061] Figure 2a An example of a suitable TEM 103 and an example of a suitable TDC 104 that can be used in the processing circuit 100 are shown. In this example, the TEM 103 comprises a comparator 201 arranged to receive an input analog signal S C , for example, the first combined signal S C1 Or the second combined signal S C2 The input signal S for TEM C Provided to a first comparator input terminal of the comparator 201 .

[0062] The comparator 201 converts the signal S at the first comparator input terminal into C is compared with the signal received at the second comparator input and an output PWM signal S is generated based on the comparison PWM The feedback path also extends from the output terminal of the comparator 201 to the second comparator input terminal for providing a feedback signal S to the second comparator input terminal. FB The filter arrangement 202 is arranged to apply filtering to the feedback path to provide a feedback signal S FB . Thus, the TEM 103 is a self-oscillating TEM, as will be understood by those skilled in the art.

[0063] In some embodiments, comparator 201 may be a hysteresis comparator. Figure 2bThe self-oscillating TEM 103 based on a hysteresis comparator is shown in more detail. In this example, the comparator 201 is a hysteresis comparator, and the filter arrangement includes an RC-type passive filter having an impedance (in this case a resistor 204) connected in series in the feedback path and a capacitor 205 coupled between a node of the feedback path and a defined voltage (e.g., ground). Although the filter arrangement 202 can be implemented using resistors and capacitors as shown, other RC components, such as FET-based resistors and / or capacitors, can be used in some implementations.

[0064] The hysteresis comparator 201 compares the signal at the first comparator input terminal and the signal at the second comparator input terminal (ie, the signal S C and feedback signal S FB ), and outputs either of two output states according to the result of the comparison, the two output states may be, for example, a high voltage state V H and low voltage state V L The hysteresis comparator 201 is operable to apply hysteresis to the comparison so that the signal S at the first comparator input C The signal S at the second comparator input FB The differential voltage between the output states must be greater than a first threshold (i.e., more positive or less negative than the first threshold) to transition from one output state to another (for example, from output state V L Transition to output state V H ), but must be below a second different threshold (i.e., less positive or more negative than the second different threshold) to make the opposite transition (e.g., to change from output state V H Switch to output state V L ). The difference between these first and second thresholds corresponds to the amount of hysteresis applied. In some implementations, the first and second thresholds may be equal in magnitude and opposite in polarity, i.e., signal S C With the feedback signal S FB The difference between them must be greater than the value required to transition to one state (for example, V H ) and must be less than -H for transitioning to another state. In this example, the magnitude of H can be considered a measure of the hysteresis applied by the hysteresis comparator 201.

[0065] In some embodiments, the output state V H and V LThe output states V may be, for example, positive and negative voltages, respectively, and may be, for example, voltages of equal magnitude but opposite polarity to each other, but states of unequal magnitude may be achieved. In some embodiments, one of the output states may correspond to zero voltage (i.e., ground), while the other output state corresponds to a positive or negative voltage of non-zero magnitude. In some examples, the output states may be voltages of the same polarity but different non-zero magnitudes. Output state V H and V L It may be derived from any suitable reference voltage or power supply and may be designed to provide a relatively low noise or accurate voltage that is independent of any supply voltage, such as a well-decoupled power supply or a low noise reference voltage generator.

[0066] Therefore, the signal S input to the TEM 103 C According to the output PWM signal S PWM The derived feedback signal S FB For comparison. Feedback signal S FB Corresponding to the output signal S PWM The filter arrangement 202 provides a certain delay and signal averaging over time. Therefore, if the output PWM signal S PWM Transitions to a high state V H , then the feedback signal S FB will be lower than the PWM signal S PWM The current value of and will start to increase within a certain period of time, i.e. become more positive. If the signal S at the first comparator input C If the signal S is relatively constant within the time period, C With the feedback signal S FB The difference between will decrease, i.e. become less positive / more negative, until the relevant threshold is reached and the comparator output transitions to the other output state V L At this time, the feedback signal S FB The value of will begin to decrease. The hysteresis comparator 201 maintains its output at a low state V L , until the signal S C With the feedback signal S FB The difference between increases until it reaches a second threshold (ie, less negative / more positive).

[0067] Therefore, if the signal S applied to the first comparator input C Maintaining a relatively constant level, the output of the hysteresis comparator 201 will be in the first output state V H With the second output state V L The time spent in each output state will depend on the feedback signal S FB Change the amount defined by hysteresis (e.g., from equal to S C-H value changes to S C +H, or vice versa). This will depend on the amount of hysteresis and the feedback signal S FB However, the feedback signal S FB The rate of change will depend on the feedback signal S FB The current value, especially the level of the output state and the feedback signal S FB which in turn depends on the signal S at the first comparator input C As noted above, Figure 2a The effect of the feedback loop of the TEM 103 shown means that the feedback signal S FB Will be in S C -H and S C +H, in other words, the feedback signal S FB will basically follow the input signal S C The waveform of the voltage ripple is ±H.

[0068] For example, consider that at the first transition, the comparator output changes from a low state V L Transition to high state V H To transition back to the low state V L , signal S C With the feedback signal S FB The difference between the values ​​of will have to decrease to a relevant threshold value defined by the amount of hysteresis, for example the difference must decrease to -H. C The level of the feedback signal S at the transition point is relatively high. FB The value of will also be relatively high. Therefore, the high output state V H The level of the feedback signal S FB The difference between the current values ​​of will be relatively small. Therefore, the feedback signal S FB The value of will increase only relatively slowly, and it will take a relatively long time for the difference to decrease to the relevant threshold. Therefore, the comparator output will remain in the high state V for a relatively long duration. H , which results in the PWM signal S PWM The pulses in the medium-high state are relatively long. However, if the signal S C The level of is relatively low at the first transition, so the feedback signal S FB The value of will also be relatively low. Therefore, in the high output state V H The level of the feedback signal S FB This would mean that the feedback signal S FB will increase faster, the feedback signal S FB With signal S CThe difference between will therefore decrease faster and will reach the threshold sooner. Therefore, the comparator output will remain in the high state V H shorter duration. The opposite will apply to the low state V L The subsequent duration in .

[0069] Therefore, corresponding to the PWM signal S PWM Medium to high status V H The duration of the pulse (and correspondingly the PWM signal S PWM Low to medium state V L The duration of the pulse depends on the input of the TEM (i.e., the signal S C ) level. The time code modulator 103 converts the analog input S C Linearly encoded into a PWM signal S PWM The duty cycle of the first output state (for example, V H ) is the duration of the pulse and the duration of the cycle period (i.e., the pulse of the first output state and the second output state (e.g., V L ) is the ratio between the total duration of temporally adjacent pulses. However, the total cyclic PWM cycle period and therefore the frequency (i.e., the high state V H and low state V L The duration of the two pulses of () also varies nonlinearly with the value of the input, and in such a way that the PWM cycle frequency varies significantly with the square of the value of the input. Therefore, the embodiments of the present disclosure utilize this square function.

[0070] about Figure 2b The TEM shown can be implemented in a relatively very small circuit area and has a relatively low power requirement in use, and may therefore be particularly advantageous in some embodiments. Thus, providing two such TEMs requires neither significant circuit area nor significant power requirements, and therefore means that multiplication can be achieved with a small and low power circuit.

[0071] Figure 3 Shown are suitable for use in embodiments of the present disclosure (e.g., such as in Figure 2a or Figure 2b The PWM signal S output by the time code modulator 103 is shown in PWM The PWM signal S PWM In both output states V H With V L High state V H The duration of the pulse is represented by α, and the low state V LThe duration of the pulse is represented by β. The cycle period T is equal to α + β. The cycle period T can also be viewed as the period between an instance of transitioning from one output state to another output state and the next instance of the same transition.

[0072] As mentioned above, as the low state V L The pulse duration is the same as the high state V H The duration of the pulse α depends on the TEM input (i.e., the signal S C ) level. For zero magnitude (assuming symmetrical hysteresis + / -H, this corresponds to a value equal to V H With V L The intermediate voltage signal between the reference voltage value) signal, the pulse cycle of each state (which is Figure 3 0 and β0) will be symmetrically equal to each other, that is, each equal to T0 / 2, where T0 is the PWM cycle period at zero magnitude. C As the size of increases, the duration of the pulse in one state will increase, while the duration of the pulse in the other state will decrease according to the following equation in first order:

[0073] α=T0 / 2.(1-R)β=T0 / 2.(1+R) (Equation 6)

[0074] where R is the level of the input signal normalized in the range -1 to +1, where +1 and -1 represent the upper and lower limits of the input signal level that asymptotically gives zero frequency, respectively. Figure 2b As shown in the TEM, the TEM output voltage state V H or V L And applying symmetrical hysteresis, the normalized level of the input signal is given by:

[0075] R=S C / S LIM (Equation 7)

[0076] Where S C Indicates the size of the input signal (referenced to the intermediate voltage V MID =(V H +V L ) / 2), and S LIM is the magnitude limit of the TEM input, which in this example is equal to (V H -V L ) / 2. It will be appreciated that an increase in the duration of one pulse is not equivalent to a decrease in the duration of the other pulse, and the total cycle period T will change:

[0077] T=α+β=T0 / (1-R 2 ) (Equation 8)

[0078] Therefore, the input (ie, signal S C Any increase in the size of ) will result in an increase in the cycle period, such as Figure 3 In the example, the durations α1 and β1 at non-zero input signal magnitudes and the duration T1 of the cycle period are shown. Therefore, the cycle period T0 (equal to α0+β0) corresponding to an input signal of zero magnitude will be the cycle period with the shortest duration. This condition is called the limit cycle, and period T0 is the limit cycle period. This corresponds to the fastest cycle frequency F0=1 / T0, which is called the limit cycle frequency. For a signal such as Figure 2b The TEM shown, the limit cycle frequency depends on the amount of hysteresis applied, as well as the time constant of the filter, i.e. the values ​​of the resistor and capacitor.

[0079] Therefore, the PWM signal S OUT The analog input S C The level of is encoded as the duty cycle of one of the pulses of the output state, i.e., as represented by α / (α+β). However, what is of interest to the present disclosure is that, according to Equation 6, the total cycle period T depends on the square of the normalized value of the input R of the TEM. Therefore, the cycle period is related to 1-R 2 Therefore, the PWM cycle frequency F PWM has a frequency that depends on the input of TEM as described in Equation 1 above. Therefore, the two PWM signals S PWM1 and S PWM2 The difference between the frequencies is proportional to the difference between the squares of the values ​​of the corresponding inputs.

[0080] Thus, each TDC 104 is arranged to provide a digital output indicative of the frequency or period of the associated PWM signal. Figure 2a In this example, each TDC 104 includes receiving a related PWM signal S PWM and a counter 203 of the reference clock signal CLK.

[0081] In some embodiments, the counter may be configured to determine a frequency value that will increase for higher frequencies and decrease for lower frequencies. In such embodiments, the TDC 104 may effectively count the number of PWM cycles within each of a consecutive number of count periods defined by the reference clock signal CLK. For example, the counter 203 may be arranged to count the number of PWM cycles for the associated PWM signal S PWM The counter 203 is clocked by the reference clock signal CLK so as to output a count value and reset for each cycle of the reference clock signal CLK. Therefore, the count value output from the counter 203 is an indication of the number of PWM cycles within each counting cycle.

[0082] In this case, the count value C output from the counter is proportional to the frequency of PWM, that is,

[0083] C=F PWM / F CLK (Equation 9)

[0084] where F CLK is the frequency of the counting cycles as defined by the reference clock signal.

[0085] The count value C from each count cycle can be output as a digital signal D, thereby providing a digital output at a sampling rate defined by the count cycle (e.g., the clock cycle of the reference clock signal). The same reference clock signal CLK can be supplied to TDCs 104a and 104b to synchronize their outputs, and obviously, the reference clock can be used to clock the digital subtractor 105.

[0086] However, in some embodiments, the count values ​​from each of the plurality of count cycles may be summed or averaged to minimize the effects of any quantization errors. In some embodiments, the count values ​​may be relatively easily scaled by a desired scaling factor using bit shifting or bit shifting and addition if desired before being output from the TDC. The resulting digital output value may be used as digital signal D1 or D2, as described above.

[0087] Therefore, providing a count value of the number of PWM cycles has the advantage of providing a value that can be used directly as a frequency value without any significant processing. In this example, the count period defined by the reference clock signal should be defined relative to the minimum PWM cycle frequency expected in use, so that there are a sufficient number of PWM cycles in each count period. Therefore, the frequency of the reference clock signal may be lower, and may be significantly lower, than the minimum expected PWM cycle frequency. Advantageously, this means that a relatively slow clock can be used for the TDC, which avoids the need for a fast clock and associated power requirements.

[0088] In some embodiments, the counter 203 of the TDC may alternatively be arranged to provide an indication of the PWM signal S PWM For example, in some embodiments, the reference clock signal CLK may be a relatively fast clock signal having a frequency significantly greater than the PWM cycle period. In this case, the counter 203 of the TDC 104 may be arranged to count the number of PWM cycles (e.g., in the PWM signal S PWMThe counter 203 may be arranged to count the number of clock cycles of the reference clock signal CLK (in the period defined between consecutive rising edges of the reference clock signal CLK). For example, the counter 203 may be arranged to increment for each rising edge of the reference clock signal CLK. The counter 203 is timed by, for example, rising edges of the received PWM signal clock signal to output a count value. Thus, the count value output from the counter 203 is an indication of the number of reference clock cycles within a PWM cycle period.

[0089] In this case, the count value C output from the counter 203 is proportional to the PWM cycle period T. PWM is proportional to, and therefore inversely proportional to, the PWM cycle frequency,

[0090] Right now:

[0091] C=T PWM / T CLK =F CLK / F PWM (Equation 10)

[0092] Therefore, each count value is related to the normalized value R of the TEM input as follows:

[0093] C=(F C LK / f0).[1 / (1-R 2 )] (Equation 11)

[0094] However, it should be noted that when the R value is relatively small, 1 / (1-R 2 ) is approximately equal to (1+R 2 ). Therefore, in some embodiments, the processing circuit can be configured to make the first combined signal S C1 and the second combined signal S C2 The value of is constrained so that the normalized value of each signal is relatively small, for example, not more than half, that is, the processing circuit can be configured so that R≤0.5 for each combined signal, so that the PWM cycle frequency is reduced by less than 25%. Therefore, the processing circuit can be configured so that the value of each of the first combined signal and the second combined signal is limited to not more than half of the maximum input signal level of the corresponding first time-coded modulator or the second time-coded modulator. In this case:

[0095] C≈(F C LK / F0).(1+R 2 ) (Equation 12)

[0096] In this case, if the count value from the TDC 104 is used as the digital values ​​D1 and D2, the digital output D OUT Can be viewed as:

[0097] D OuT=D2-D1≈(F CLK / F0).[(1+(XY) 2 )-(1+(X+Y) 2 )]

[0098] ≈(F CLK / F0).[(XY) 2 -(X+Y) 2 ] (Equation 13)

[0099] therefore:

[0100] D OUT ≈-(F CLK / F0).(4XY) (Equation 14)

[0101] Thus, the difference in the count values ​​can again provide a value related to the product of the values ​​one wishes to multiply with reasonable accuracy.

[0102] It will be appreciated that in such an embodiment, the counters effectively count count periods which may vary with the PWM cycle period, and therefore each counter will have a variable sampling rate. To provide synchronization between the outputs of the two TDCs 104a and 104b, the TDCs may be arranged to retime their outputs to some external clock, and / or the TDCs may combine count values ​​from several consecutive PWM cycles in a defined frame period to, for example, output an average count value for the frame period.

[0103] Using a fast reference clock and counting the number of cycles of the fast reference clock in a period defined by the fast reference clock means that the TDC can effectively provide a sample count value for each PWM cycle period with a time resolution determined by the frequency of the fast clock signal. This therefore allows the output of the TDC (i.e., D1 and D 2) Having a relatively fast effective sampling rate, but the sampling rate is variable, and subtracting these values ​​from each TDC provides an approximation to the desired multiplication value. In contrast, an alternative approach of counting the number of PWM cycle periods in a count period defined by a slower clock signal provides a fixed sampling rate and count value that can be used to give a more accurate representation of the desired multiplication, but since the sampling period more often corresponds to multiple PWM cycle periods, the update rate is much slower, and it may be necessary to average the results from several count periods to provide the desired level of accuracy.

[0104] In some applications, TEMs 103a and 103b may be configured to provide PWM signals having a limiting cycle frequency f0 of a few megahertz (say, 3 MHz in one example). PWMIf the TDC counts the number of clock cycles or periods of a relatively fast clock signal in a period defined by a slower clock signal, the fast clock may have a frequency of several hundred megahertz (say, 300 MHz). Alternatively, if the TDC counts the number of cycles of a PWM signal in a count period defined by a slower clock signal, the clock signal may have a frequency of several hundred kilohertz (e.g., 300 kHz). Those skilled in the art will be able to determine the appropriate method for a given application.

[0105] In some examples, TDCs 104a and 104b may be selectively operable to operate using either of these two methods to provide two modes of operation. Thus, each TDC 104 may be operable in a first mode to counteract the PWM signal S in a count period defined by a clock signal CLK having a relatively slow frequency. PWM The number of cycles of the PWM signal S is counted and the PWM signal S can be operated in the second mode to PWM The number of cycles of a clock signal with a relatively fast frequency in a defined period is counted. This allows the processing circuit 100 to selectively provide two operating modes. The second mode using a faster clock signal can provide a faster update rate and lower latency, but may consume more power due to the faster clock. The first mode provides a slower update rate but consumes less power, and thus can be advantageously used in a system standby or "always online" mode where signal multiplication may be required as part of the system detecting signal activity from a microphone or other sensor.

[0106] In any case, TDC 104 may be implemented by relatively simple, small, and low-power circuitry.

[0107] Therefore, the multiplication of two values ​​X and Y can be efficiently achieved in terms of power and circuit area by using two TEMs 103 and corresponding TDCs 104 .

[0108] Of course, it will be understood that the above-mentioned specific type of TEM is only a specific type of TEM, and other types of TEM are known. For example, a conventional asynchronous sigma delta modulator (ASDM) is a known type of self-oscillating TEM, which can receive an input and output a PWM signal with a PWM frequency, which is substantially dependent on the square of the value of the input. A conventional ASDM can receive an input and combine it with a feedback signal at the input to an integrator. The output from the integrator (which can be regarded as a loop filter) is input to a comparator input of a comparator (which can be a hysteresis comparator). The output from the integrator will ramp up or down at a rate defined by the input and feedback signal, and thus cause a PWM output signal whose duty cycle depends on the level of the input of the ASDM. The PWM cycle frequency will also be a function of the square of the value of the input. In some instances, instead of applying hysteresis in the comparison, a delay can be applied in the feedback loop of the feedback signal. Therefore, the embodiments of the present disclosure can be implemented as TEM103 with any suitable type of TEM (e.g., any suitable self-oscillating TEM, such as an ASDM). Likewise, while a small size and low power TDC may be implemented through the use of a simple counter, any suitable type of TDC may be implemented.

[0109] In any case, to provide the desired multiplication, the input of the first TEM 103a is arranged to have a value corresponding to the sum of the values ​​desired to be multiplied (i.e., X+Y), and the input of the second TEM 103 is arranged to have a value corresponding to the difference between these values ​​(i.e., XY). In some examples, the first signal S1 and the second signal S2 may already have the desired relationship through the operation of some upstream module, which may or may not be part of the same integrated circuit as the processing circuit 100. However, in some embodiments, the received first signal S1 and the second signal S2 may each indicate one of the values ​​desired to be multiplied, in which case there may be a difference as described above with respect to Figure 1 The signal combiner 102 is discussed to generate a combined signal S C1 and S C2 For input to TEM 103.

[0110] Figure 4 The principle of an example of a suitable signal combiner is shown. The combiner 102 receives input signals S1 and S2 having values ​​corresponding to X and Y, respectively. A first combiner element 401a (e.g., an adder) combines the values ​​of the first signal and the second signal together in an additive manner and outputs a first combined signal S C1 The second combiner element 402a (eg, a subtractor) combines the values ​​of the first signal and the second signal in a subtractive manner to provide a subtraction, and outputs a second combined signal S C2The form of the first and second combiner elements 401a, 401b may depend on the type of input signals. The analog voltage signals may be combined in any convenient way, for example by conversion to corresponding current signals that can be combined relatively easily for addition or subtraction.

[0111] Figure 5 A specific example of the signal combiner 102 is shown in more detail. The first combiner element 401a includes two current sources 5011 and 5012 (collectively or generally referred to as 501) configured to provide current to charge the capacitor 502a. The current sources 5011 and 5012 are driven by control signals derived from the first input signal S1 and the second input signal S2, respectively, so as to provide currents corresponding to values ​​X and Y. For example, the current source can be a programmable current source or an output stage of a voltage-to-current converter. In the first combiner element 401a, the current sources 5011 and 5022 are arranged to provide current to the output node of the first combiner element 401a in an additive manner, that is, the two current sources provide currents of the same polarity to the output node. This provides a first combined signal S having a value corresponding to X+Y that can be supplied to the TEM 103a. C1 Depending on the type of TEM, the current signal may be supplied directly to the TEM or may be converted into a voltage signal, for example by being applied to a defined impedance (not shown).

[0112] The second combiner element 401 b also comprises two current sources 5013 and 5014 which are driven by control signals derived from the first input signal S1 and the second input signal S2 respectively so as to provide currents corresponding to the values ​​X and Y. However, in this arrangement, the current source 5013 sources current and the current source 5013 sinks current, i.e. the current sources drive currents of opposite polarities at the output node. This arrangement provides a second combined signal S having a value corresponding to XY. C2 .

[0113] Of course, you will understand, Figure 4 and Figure 5 The arrangements shown are merely some examples of the ways in which two signals may be combined, and those skilled in the art will appreciate that a variety of other ways may be chosen to combine the signals without departing from the scope of the present disclosure.

[0114] Figure 6 An alternative arrangement for TEM 103 is shown, which is similar to Figure 2b The arrangement shown in FIG. 2 is different from the arrangement shown in FIG. 2 , but in which the filter arrangement 202 comprises a current generator 601 configured to generate a current signal having a current that varies according to the output state of the hysteresis comparator 201. Figure 6In the example shown, the current generator includes: a first current source 6011 for generating a defined positive current +i; and a second current source 6022 for generating a defined negative current -i, that is, the second current source 6022 acts as a current sink. The first current source 6021 and the second current source 6022 are controlled to generate a positive current or a negative current according to the output state of the comparator 201, that is, when the output signal S OUT In one state, a positive current +i is generated, and when the output signal S OUT The current signal output from the current generator 601 is supplied to a node coupled to the feedback capacitor 603, which is also biased to the reference voltage V through the impedance 604. R Thus, depending on the polarity of the feedback capacitor 603, the current signal charges or discharges it. The rate of charging and discharging depends on the magnitude of the current generated by the current generator, but also on the current through the impedance 604, which in turn depends on the voltage of the feedback capacitor and the reference voltage V R The difference between the reference voltage V R It may conveniently correspond to a voltage of a zero magnitude input signal, such as a midpoint voltage. Thus, the voltage of the feedback capacitor provides a filtered feedback signal S for the hysteresis comparator 201. FB .

[0115] A practical advantage of using a current generator is that it avoids the need for a voltage buffer to provide an accurate voltage level V H and V L , in order to avoid the effects of supply voltage variations, for example. Such buffers need to be well designed in order to avoid the effects of the feedback load from V H Switch to V L The current source filter embodiment also provides the following additional advantages: total harmonic distortion is reduced due to the improved linear rise and fall of the voltage input into the second inverting comparator input terminal.

[0116] exist Figure 6 In a variation of the arrangement, the input signal S C can be applied to impedance 604, and the reference signal V R can be applied to the non-inverting input of comparator 201. It should be remembered that the signal S C The general operation is similar with respect to the PWM cycle frequency changing slowly, and the voltage at the node coupled to the ungrounded terminal of feedback capacitor 603 is now referenced to voltage V RThe reduction in the range of the common-mode input voltage of the comparator 201 may simplify its design or allow for a lower supply voltage.

[0117] Thus, embodiments provide processing circuits that can provide multiplication of signals. By using TEM and TDC, a small and low power circuit can be realized that can therefore form part of a functional circuit without requiring significant space. The processing circuit can multiply two analog signals together.

[0118] Some embodiments involve multiplying the received analog signal by a variable as an initial stage of some processing, and applying further processing downstream. Such further processing may be difficult or complex to implement in the analog domain, and may therefore be conveniently implemented as digital processing. Such an arrangement will require an analog-to-digital converter (ADC) at some part of the processing path, and typically the received analog signal will be supplied to the ADC, and all processing (including multiplication) applied in the digital domain. Embodiments of the present invention provide multiplication as part of the conversion process from analog to digital, and therefore save space and power compared to providing a separate ADC and digital multiplication arrangement.

[0119] Thus, the embodiments may be advantageously applied to the multiplication of analog signals. However, the same principles may be applied to the multiplication of digital signals or values, and in some embodiments, the input signals S1 and S2 may be digital. For example, referring to Figure 5 , current source 501 may be a digitally programmable current source, and thus values ​​X and Y may be digital values ​​for programming the output current. In some applications, it may be beneficial to implement this multiplication arrangement rather than conventional digital multiplication for size and / or power benefits.

[0120] Thus, the skilled person will recognize that some aspects of the above-described apparatus and methods may be embodied as, for example, processor control code on a non-volatile carrier medium such as a disk, CD-ROM or DVD-ROM, a programmed memory such as a read-only memory (firmware) or a data carrier such as an optical or electrical signal carrier. For many applications, embodiments of the present invention will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit) or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode or, for example, code for setting up a control ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device such as a reprogrammable logic gate array. Similarly, the code may include code for a hardware description language such as Verilog TM or VHDL. As the skilled person will appreciate, the code may be distributed between multiple coupled components that communicate with each other. Where appropriate, the embodiments may also be implemented using code that runs on a field (re)programmable analog array or similar device to configure analog hardware.

[0121] Some embodiments of the present invention may be arranged as part of an audio processing circuit (e.g., an audio circuit that may be provided in a host device). Circuits according to embodiments of the present invention may be implemented as an integrated circuit. In use, one or more microphones may be connected to the integrated circuit.

[0122] Embodiments of the present invention may be implemented in a host device, particularly a portable and / or battery-powered host device. The device may be a communication device, such as a mobile phone, a cellular phone, or a smart phone. The device may be, for example, a computing device, such as a laptop, notebook, or tablet computer, or a gaming device. The device may be, for example, a personal media player, such as an audio player or a video player. The device may be a wearable device, such as a smart watch, and / or may be a voice-controlled or voice-activated device.

[0123] It should be noted that the above embodiments illustrate rather than limit the present invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude pluralities, and a single feature or other unit may perform the functions of several units recited in the claims. Any reference numerals in the claims should not be interpreted as limiting the scope of the claims. Terms such as amplification or gain include the possibility of applying a scaling factor or a scaling factor less than 1 to a signal.

Claims

1. A processing circuit, comprising: a first time coded modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first PWM signal having a cyclic frequency that depends substantially on the square of a value of the first combined signal; a second time coded modulator configured to receive a second combined signal corresponding to a difference between the first input signal and the second input signal and to generate a second PWM signal having a cyclic frequency that depends substantially on the square of a value of the second combined signal; a first time-decoding converter configured to receive the first PWM signal and provide a first count value based on a first parameter of the first PWM signal; a second time-decoding converter configured to receive the second PWM signal and provide a second count value based on a second parameter of the second PWM signal; as well as a subtractor configured to determine a difference between the first count value and the second count value and to output an output signal based on the difference between the first count value and the second count value; The first time-decoding converter and the second time-decoding converter each include a counter configured to receive a reference clock signal and count the number of PWM cycles in each of consecutive counting periods defined by the reference clock signal to provide a count value. 2 . The processing circuit of claim 1 , wherein the first parameter is a PWM cycle frequency of the first PWM signal, and the second parameter is a PWM cycle frequency of the second PWM signal. 3 . The processing circuit according to claim 1 , wherein the first parameter is a PWM cycle period of the first PWM signal, and the second parameter is a PWM cycle period of the second PWM signal.

4. The processing circuit of any preceding claim, wherein each of the first time coded modulator and the second time coded modulator comprises: a forward signal path configured to receive the first combined signal or the second combined signal, respectively, at a first input; a feedback path, the feedback path forming a feedback loop with at least a portion of the forward signal path; a comparator located in the forward signal path within the feedback loop; and A filter arrangement is located within the feedback loop. The processing circuit of claim 4 , wherein the comparator is a hysteresis comparator.

6. The processing circuit of claim 4, wherein the filter arrangement comprises a resistor-capacitor filter.

7. The processing circuit of claim 4, wherein the time coded modulator comprises: a current generator configured to receive a corresponding one of the first PWM signal or the second PWM signal output from the comparator and to generate a first controlled current signal having a first defined current during a period of a first voltage state of the PWM signal and to generate a second controlled current signal during a period of a second voltage state of the PWM signal; as well as A capacitor is configured to be charged and discharged by the first controlled current signal.

8. The processing circuit according to any one of claims 1 to 3, further comprising: A signal combiner having a first combiner element configured to combine the first input signal and the second input signal additively to generate the first combined signal and a second combiner element configured to combine the first input signal and the second input signal subtractively to generate the first combined signal.

9. The processing circuit according to claim 8, wherein: the first combiner element comprising a first current source and a second current source, the first current source and the second current source being configured to provide currents defined by the first input signal and the second input signal, respectively, wherein the first current source and the second current source are configured to supply currents having the same polarity as each other to an output node of the first combiner element; and The second combiner element includes a third current source and a fourth current source, the third current source and the fourth current source are configured to provide currents defined by the first input signal and the second input signal, respectively, wherein the third current source and the fourth current source are configured to supply currents of opposite polarities to an output node of the second combiner element.

10. The processing circuit according to any one of claims 1 to 3, implemented as an integrated circuit.

11. A processing circuit comprising: a first time coded modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first PWM signal having a cyclic frequency that depends substantially on the square of a value of the first combined signal; a second time coded modulator configured to receive a second combined signal corresponding to a difference between the first input signal and the second input signal and to generate a second PWM signal having a cyclic frequency that depends substantially on the square of a value of the second combined signal; a first time-decoding converter configured to receive the first PWM signal and provide a first count value based on a first parameter of the first PWM signal; a second time-decoding converter configured to receive the second PWM signal and provide a second count value based on a second parameter of the second PWM signal; as well as a subtractor configured to determine a difference between the first count value and the second count value and to output an output signal based on the difference between the first count value and the second count value; The first time-decoding converter and the second time-decoding converter each include a counter, which is configured to receive a reference clock signal and count the number of cycles of the reference clock signal in a PWM cycle period defined by a corresponding one of the first PWM signal or the second PWM signal to provide a corresponding first count value or a second count value.

12. The processing circuit of claim 11 , wherein the processing circuit is configured such that the value of each of the first combination signal and the second combination signal is limited to be no greater than a defined limit such that a maximum change in a cycle frequency of the corresponding first PWM signal or the second PWM signal is no greater than 25%.

13. A processing circuit comprising: a first time coded modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first PWM signal having a cyclic frequency that depends substantially on the square of a value of the first combined signal; a second time coded modulator configured to receive a second combined signal corresponding to a difference between the first input signal and the second input signal and to generate a second PWM signal having a cyclic frequency that depends substantially on the square of a value of the second combined signal; a first time-decoding converter configured to receive the first PWM signal and provide a first count value based on a first parameter of the first PWM signal; a second time-decoding converter configured to receive the second PWM signal and provide a second count value based on a second parameter of the second PWM signal; as well as a subtractor configured to determine a difference between the first count value and the second count value and to output an output signal based on the difference between the first count value and the second count value; wherein the first time-decoding converter and the second time-decoding converter each include a respective counter configured to receive a reference clock signal, and wherein the processing circuit is capable of selectively operating in a first operating mode or a second operating mode, wherein: In the first operation mode, the first parameter and the second parameter are PWM cycle frequencies of the first PWM signal and the second PWM signal, respectively, and the counters of the first time-decoding converter and the second time-decoding converter are each configured to count the number of PWM cycles in each of consecutive count periods defined by the reference clock signal to provide a count value; in the second operation mode, the first parameter and the second parameter are PWM cycle periods of the first PWM signal and the second PWM signal, respectively, and the counters of the first time-decoding converter and the second time-decoding converter are each configured to count the number of cycles of the reference clock signal in the PWM cycle period defined by a corresponding one of the first PWM signal or the second PWM signal to provide a count value; and The frequency of the reference clock signal is greater in the second operating mode than in the first operating mode.

14. An electronic device comprising a processing circuit according to any preceding claim.

15. The electronic device of claim 14, wherein the device is a battery powered device.

16. The electronic device of claim 14, wherein the device is a portable device.

17. The electronic device of claim 14, wherein the device is a communication device.

18. The electronic device of claim 14, wherein the device is a mobile phone.

19. The electronic device of claim 14, wherein the device is a smart phone.

20. The electronic device of claim 14, wherein the device is a computing device.

21. The electronic device of claim 14, wherein the device is a notebook or tablet computer.

22. The electronic device of claim 14, wherein the device is a gaming device.

23. The electronic device of claim 14, wherein the device is a personal media player.

24. The electronic device of claim 14, wherein the device is a wearable device.

25. The electronic device of claim 14, wherein the device is a voice controlled device.

26. A processing circuit comprising: a signal combiner configured to receive a first input signal and a second input signal and to generate a first combined signal corresponding to a sum of the first input signal and the second input signal and a second combined signal corresponding to a difference between the first input signal and the second input signal; A first time coded modulator and a second time coded modulator configured to receive the first combined signal and the second combined signal, respectively, and generate a first cyclic signal and a second cyclic signal having a cyclic frequency, wherein the cyclic frequency is substantially the same as (1-R 2 ), where R is the value of the corresponding input of the corresponding time coded modulator normalized in the range -1 to +1 with respect to the input range of said time coded modulator; as well as a first counter and a second counter, the first counter and the second counter being configured to receive the first cycle signal and the second cycle signal, respectively, and to generate a first count value and a second count value; as well as a subtractor configured to determine a difference between the first count value and the second count value; The first counter and the second counter are each configured to generate a count value of the number of cycles of the first cycle signal or the second cycle signal in a counting period defined by a reference clock signal.

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