Voltage level shifting device and method of operating the same

Abstract

A voltage level shifter for an SRAM element includes a level shifter input and provides a second voltage level. A voltage input terminal receives a first signal at a first voltage level, and an inverter has an input and an output, with the voltage input terminal connected to the inverter input. A first voltage selector selectively applies an intermediate voltage to the gate of a PMOS transistor in a first complementary pair when the voltage of a complementary level shifted output voltage rises to a logic 1, and a second voltage selector applies the intermediate voltage to the gate of a PMOS transistor in a second complementary pair when the voltage of a level shifted output voltage node rises to a logic 1. Current through the PMOS transistors is thereby reduced, resulting in lower energy dissipation and supporting greater voltage separation between the first and second voltage levels. A method of operation of a voltage level shifting device is also disclosed.

Description

Technical Field

[0001] This case relates to a voltage level offset device and its operating method, and more particularly to a voltage level offset device and its operating method used in SRAM in multiple voltage domains. Background Technology

[0002] A common type of integrated circuit memory is the static random access memory (SRAM) element. A typical SRAM memory element consists of an array of memory cells, where each memory cell has six transistors connected between an upper reference potential and a lower reference potential (usually ground). Each memory cell has two storage nodes that can store information. The first node stores the required information, while supplementary information is stored in the second storage node.

[0003] A "dual-track" SRAM architecture refers to an SRAM arrangement in which some memory logic operates in a low-voltage domain, while the memory array operates in a high-voltage domain. By operating the SRAM array in the high-voltage domain, static noise tolerance is improved, allowing individual memory cells to maintain the required logic state when exposed to noise. Furthermore, memory leakage power is significantly reduced. The leakage power gain increases with the difference between the high and low voltage values. Summary of the Invention

[0004] One embodiment of this invention relates to a voltage level offset device, and includes a voltage input terminal for receiving a first signal operating at a first voltage level, and an inverter having an input and an output, the voltage input terminal being connected to the input of the inverter; a first complementary pair of P-type metal-oxide-semiconductor (MOSFET) transistors and N-type MOSFETs, the drains of the P-type MOSFETs and N-type MOSFETs of the first complementary pair being connected together, the connected drains establishing a complementary level offset output voltage node, and the voltage input terminal being connected to the gate of the N-type MOSFET in the first complementary pair; a second complementary pair of P-type MOSFETs and N-type MOSFETs, the drains of the P-type MOSFETs and N-type MOSFETs of the second complementary pair being connected together, the connected drains establishing a level offset output voltage node, and the output of the inverter being connected to the second complementary pair. The system includes: a gate of an N-type metal-oxide-semiconductor transistor; a first voltage selector connected between a level-offset output node and the gate of a P-type metal-oxide-semiconductor transistor in a first complementary pair; the first voltage selector including a selector input connected to the complementary level-offset output voltage node; and a second voltage selector connected between the complementary level-offset output node and the P-type metal-oxide-semiconductor transistor in a second complementary pair; the second voltage selector including a selector input connected to the level-offset output voltage node. When the voltage of the complementary level-offset output voltage node rises to a logic 1, the first voltage selector selectively applies an intermediate voltage to the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair, and when the voltage of the level-offset output node rises to a logic 1, the second voltage selector selectively applies an intermediate voltage to the gate of the P-type metal-oxide-semiconductor transistor in the second complementary pair. Multiple input signals and corresponding multiple level-offset devices exist, wherein the input signals are offset from a first voltage level to a second voltage level greater than the first voltage level to establish a high-voltage domain in which multiple static random access memory cells operate.

[0005] One embodiment of this invention relates to a voltage level offset device, and includes a voltage input terminal for receiving a first signal operating at a first voltage level; an inverter having an input terminal and an output terminal, the voltage input terminal being connected to the input terminal of the inverter; a first N-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor, the first N-type metal-oxide-semiconductor transistor having a drain and a gate connected to the first voltage level, the second N-type metal-oxide-semiconductor transistor having a drain and a gate connected to the output terminal of the inverter; a first P-type metal-oxide-semiconductor transistor having a gate and a drain connected to the drain of the first N-type metal-oxide-semiconductor transistor, wherein the drain of the first N-type metal-oxide-semiconductor transistor and the drain of the first P-type metal-oxide-semiconductor transistor form a complementary level offset output node; and a second P-type metal-oxide-semiconductor transistor having a gate and a drain connected to the drain of the second N-type metal-oxide-semiconductor transistor, wherein the drain of the first N-type metal-oxide-semiconductor transistor and the drain of the second P-type metal-oxide-semiconductor transistor form a level offset output node, the level offset output node and the complementary level offset output node being connected to the first N-type metal-oxide-semiconductor transistor. A second voltage level operation greater than a first voltage level; a voltage selector connected between a level offset output node and the gate of a second P-type metal-oxide-semiconductor transistor and between a complementary level offset output node and the gate of a first P-type metal-oxide-semiconductor transistor, wherein the voltage selector has a first selector input and a second selector input, the first selector input being directly connected to the level offset output node through a first amplifier, and the second selector input being directly connected to the complementary level offset output node through a second amplifier; when the level offset output node rises to logic 1, the voltage selector applies a third voltage to the gate of the second P-type metal-oxide-semiconductor transistor, and when the complementary level offset output node rises to logic 1, the voltage selector applies a third voltage to the gate of the first P-type metal-oxide-semiconductor transistor, wherein there is an input signal and a corresponding level offset device, wherein the input signal is offset from the first voltage level to the second voltage level; and a memory array having static random access memory elements, the memory array being operatively connected to the level offset device and operating at the second voltage level to improve the operation of the memory array having static random access memory elements.

[0006] One embodiment of this invention relates to an operation method of a voltage level offset device, comprising: configuring a voltage input terminal to receive a first signal operating at a first voltage level and inverting the first signal; connecting the drains of the P-type metal-oxide-semiconductor transistors and the drains of the N-type metal-oxide-semiconductor transistors of a first complementary pair together, the drains of the P-type metal-oxide-semiconductor transistors and the drains of the N-type metal-oxide-semiconductor transistors of the first complementary pair forming a complementary level offset output voltage node, and connecting the voltage input terminal to the gate of the N-type metal-oxide-semiconductor transistor in the first complementary pair; connecting the drains of the P-type metal-oxide-semiconductor transistors and the drains of the N-type metal-oxide-semiconductor transistors of a second complementary pair together, the drains of the P-type metal-oxide-semiconductor transistors and the drains of the N-type metal-oxide-semiconductor transistors of the second complementary pair establishing a level offset output voltage node, and connecting the inverted first signal to the gate of the N-type metal-oxide-semiconductor transistor in the second complementary pair; and connecting the level offset output node to the P-type metal-oxide-semiconductor transistor in the first complementary pair. A first voltage selector is connected between the gates of the complementary level offset output node, the first voltage selector including a selector input directly connected to the complementary level offset output node through a first amplifier, and a second voltage selector is connected between the complementary level offset output node and the P-type metal-oxide-semiconductor transistor in the second complementary pair, the second voltage selector including a selector input directly connected to the complementary level offset output node through a second amplifier; when the voltage of the complementary level offset output voltage node rises to logic 1, an intermediate voltage is selectively applied to the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair; when the voltage of the level offset output voltage node rises to logic 1, an intermediate voltage is selectively applied to the gate of the P-type metal-oxide-semiconductor transistor in the second complementary pair; and multiple input signals of the operation at the first voltage level are offset to a second voltage level higher than the first voltage level, and the input signals of the operation at the second voltage level are connected to a memory array having multiple static random access memory elements, thereby improving the operation of the memory array having static random access memory elements. Attached Figure Description

[0007] The various aspects of one embodiment of this invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased:

[0008] Figure 1 This is a circuit diagram illustrating various states of an exemplary low-voltage level offset according to one embodiment;

[0009] Figure 2This is a simulation timing diagram according to one embodiment, illustrating the effect of the level offset input signal (LSIN) decreasing as... Figure 1 The representative voltage levels at each node of the level offset device as time progresses;

[0010] Figure 3 This is a simulation timing diagram according to one embodiment, illustrating the effect of the level offset input signal (LSIN) rising as the level offset input signal (LSIN) increases. Figure 1 The representative voltage levels at each node of the level offset device as time progresses;

[0011] Figure 4 This is a circuit diagram of a representative PMOS diode that can be used to generate voltage Vm according to some embodiments;

[0012] Figure 5 This is a block diagram according to one embodiment, illustrating the... Figure 1 Examples of low-voltage level offsets are shown, along with representative relationships between level offsets and memory arrays, word line drivers, local inputs / outputs, and local controls operating in the VDDM domain.

[0013] Figure 6 This is a representative block diagram of a method that can be employed by a level offsetter according to one embodiment.

[0014] [Symbol Explanation]

[0015] 10,50: Level offsetter / Level offset block / Level offset circuit

[0016] 21,MN1,22,MN2: NMOS transistors

[0017] 23, MP1, 24, MP2: PMOS transistors

[0018] 25: Inverter

[0019] 26: First Amplifier

[0020] 27: Second Amplifier

[0021] 28: First Multiplexer

[0022] 29: Second Multiplexer

[0023] VDD,VM,VDDM: Voltage

[0024] LSIN: Level Offset Input Signal

[0025] LSINB: Level Offset Input Signal B

[0026] LSOUT, LSOUTB: Nodes

[0027] MUX_OUT_MP1,MUX_OUT_MP2,SELECT,SELECTB: signal

[0028] 50: Level offset

[0029] 51,54: VDD domain

[0030] 52,53:VDDM domain

[0031] 60: Output latch

[0032] 600: Method

[0033] 601, 602, 603, 604: Squares Detailed Implementation

[0034] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the content of one embodiment of this application. These are, of course, merely examples and are intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of an embodiment of this application. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0035] Furthermore, spatial relative terms such as “below,” “below,” “lower,” “above,” “upper,” etc., may be used herein to simplify the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device / element in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0036] Some electrical components and circuits operate in multiple voltage domains. For example, Static Random Access Memory (SRAM) elements have an array of memory cells, each including a transistor connected between an upper reference potential and a lower reference potential, such that one of the two storage nodes can be occupied by information to be stored, with supplementary information stored at the other storage node. For example, a typical SRAM memory cell arrangement includes six transistors. Each bit in the SRAM cell is stored in four transistors, which form two cross-coupled inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the cell to its bit line.

[0037] For example, during a read operation, the memory cell bit lines are pre-charged to a predetermined threshold voltage. When the word lines are enabled, a sense amplifier connected to the bit lines senses and outputs the stored information.

[0038] A "dual-track" SRAM architecture refers to an SRAM arrangement in which some memory logic operates in a low-voltage domain, while the memory array operates in a high-voltage domain. Known dual-track SRAM arrangements can reduce memory leakage power, but may adversely affect memory access time. Furthermore, as the voltage difference between the high and low voltage domains increases, leakage and noise may increase.

[0039] Therefore, for on-chip system environments and other circuits operating in multiple voltage domains (such as dual-track SRAM), there is a need for level offsetters with low power dissipation over a wide voltage range. Embodiments constructed according to the principles of the present invention provide improved voltage separation between a first supply voltage level VDD and a second supply voltage level VDDM. For example, previous level offsetters typically supported a maximum separation of 350mV between VDD and VDDM, while embodiments of the present invention can support a separation of 500mV. Therefore, in some embodiments, the voltage difference between the first supply voltage level VDD and the second supply voltage level VDDM is 350mV to 500mV. Other advantages include improved delay at low VDD and reduced power dissipation for larger separations between VDD and VDDM.

[0040] Now go to Figure 1An embodiment of a low-voltage level offsetter according to the principles of the present invention is disclosed. The level offsetter (level offset block) is generally illustrated as 10. A level offset input signal (LSIN) is provided to the gate of an N-type metal-oxide-semiconductor (NMOS) transistor 21 and an inverter 25. The NMOS transistor 21 is connected to a PMOS transistor 23 using a node corresponding to the level offset output signal B (LSOUTB) between the two transistors. The node LSOUTB is an input to a first amplifier 26 and one of the two input signals to a first multiplexer 28. The output of the first amplifier 26 is the signal SELECTB. This signal is provided as a selector signal between the two inputs LSOUTB and Vm to a second multiplexer 29. In short, Vm is a reduced supply voltage having a level between a first supply voltage VDD and a second supply voltage VDDM. Therefore, it is referred to herein as an intermediate or third voltage level. Representative ways in which Vm can be generated are further presented below.

[0041] The complementary arrangement of transistors and components is configured opposite to the circuit described in the previous paragraph, and the output of inverter 25 (designated LSINB) is provided to the gate of NMOS transistor 22. Node LSOUT is located between NMOS transistor 22 and P-type metal-oxide-semiconductor (PMOS) transistor 24. The LSOUT signal is provided to the input of second amplifier 27 and is one of the two input signals of second multiplexer 29. The output of second amplifier 27 is the signal SELECT. This signal is provided to first multiplexer 28 as a selector signal between the two inputs LSOUT and Vm.

[0042] The first multiplexer 28 and the second multiplexer 29 each include two input signals and a selector signal. The first input signals are LSOUTB for the first multiplexer 28 and LSOUT for the second multiplexer 29. These input signals are selected when the selector signal is logic 0. The second input signal for both the first multiplexer 28 and the second multiplexer 29 is Vm. Input signal Vm is selected when the selector signal is logic 1. The output of the first multiplexer 28 is the signal MUX_OUT_MP2, which is applied to the gate of the PMOS transistor 24. The output of the second multiplexer 29 is the signal MUX_OUT_MP1, which is applied to the gate of the PMOS transistor 23.

[0043] The first multiplexer 28 and the second multiplexer 29 are used as voltage selectors and employ similar logic. More specifically, the logic 1 selector signal selects the Vm input, and the logic 0 selector signal selects the LSOUTB input (for the first multiplexer 28) and the LSOUT input (for the second multiplexer 29). The resulting logic selection of the inputs is summarized in the following two tables.

[0044] Table 1

[0045]

[0046] Table 2

[0047]

[0048] As can be seen from Tables 1 and 2, multiplexers 28 and 29 select between a high voltage present at the LSOUT and LSOUTB voltage nodes and Vm. Therefore, during the rise and fall of the LSIN signal, a high voltage is applied to the gates of the two PMOS transistors 23 and 24 to assist transistors 23 and 24 in maintaining a high-resistance state or quickly returning to a high-resistance state. This reduces the current in the PMOS transistors, thus making this circuit faster than the previous level offset circuit.

[0049] Furthermore, in the previous level offset circuit, the PMOS transistor current was relatively high when VDDM > VDD. In some embodiments, by including multiplexers 28 and 29 in the circuit and selectively applying Vm to the PMOS transistor gate, power consumption is reduced by 43%. For example, compared to the previous level offset circuit with VDD = 0.6V and VDDM = 0.950V, VDD can be reduced from 0.6V to 0.45V by using the level offsetter constructed according to the principles of the present invention. Although adding the multiplexer requires some additional wafer area, it is estimated that this additional area is small compared to the total area of ​​the memory circuit and should not exceed 0.5%.

[0050] Now we turn to a more detailed discussion of the operation of level offset 10, as described above, providing at least one input signal LSIN to level offset 10. It should be understood that this signal can be a rising signal from logic state 0 to logic state 1, or a falling signal from logic state 1 to logic state 0. The operation of level offset 10 will be described first with respect to the falling LSIN signal, and then in conjunction with the rising LSIN signal.

[0051] Now for reference Figure 1 and Figure 2 As described above, the LSIN signal is initially applied to the gate of NMOS transistor 21 and inverter 25. When the LSIN signal decreases, NMOS transistor 21 turns off, and the voltage at node LSOUTB rises. This rising voltage is applied to the first amplifier 26, and the resulting high SELECTB voltage is provided as a selector to the second multiplexer 29. As shown in Table 1 above, since the selector voltage is logic high, the output signal MUX_OUT_MP1 from the second multiplexer 29 is a voltage Vm, and this voltage is applied to the gate of PMOS transistor 23.

[0052] After being inverted to LSINB by inverter 25 (e.g., LSINB is a rising signal), the LSIN signal is also provided to the complementary component of level offset 10. The LSINB signal is applied to the gate of NMOS transistor 22, causing the transistor to turn on and the voltage at the LSOUT node to drop. This dropped voltage is applied to the second amplifier 27, and a low logic SELECT voltage is provided as a selector to the first multiplexer 28. As shown in Table 2 above, since the selector voltage is logic low, the output signal MUX_OUT_MP2 from the first multiplexer 28 is a high voltage appearing at node LSOUTB, and this voltage is applied to the gate of PMOS transistor 24.

[0053] exist Figure 2 The diagram illustrates a simulation of the voltage levels at various nodes of the time-shifting level offset unit 10 in relation to the falling LSIN signal. As can be seen in the timing diagram, the voltage applied to the gate of the PMOS transistor 24 changes from logic 1 to logic 0. Since LSOUTB is initially low, the SELECTB selector is also low, and the output of the second multiplexer 29 (MUX_OUT_MP1) is the LSOUT signal. As the voltage level of LSOUT decreases and LSOUTB increases, the MUX_OUT_MP1 level decreases along with the falling LSOUT signal until the SELECTB signal rises to logic 1. At this point, the output of the second multiplexer 29 switches to output to Vm.

[0054] The output (MUX_OUT_MP2) of the first multiplexer 28 is initially Vm with a high LSOUT level. When LSOUT drops to logic 0, the first multiplexer 28 selects the LSOUTB level as the output to the gate of the PMOS transistor 24.

[0055] Next reference Figure 3 The operation of level offset 10 is shown as an analog waveform with respect to the rising LSIN signal at the node and combined with the above. Figure 1 The output is described. For example... Figure 3 As shown, various voltages and waveforms with a rising LSIN input signal are complementary to a falling LSIN signal. Therefore, for a rising LSIN signal, the MUX_OUT_MP1 signal takes the form of the MUX_OUT_MP2 voltage level as described above with a rising LSIN signal, and the MUX_OUT_MP2 signal takes the form of the MUX_OUT_MP1 voltage level.

[0056] As mentioned above, voltage Vm is an intermediate or third voltage level and can be established at a level between the first supply voltage VDD and the second supply voltage VDDM. When VDD is the lower limit supply voltage, it can be considered as voltage Vm. However, a higher voltage may be required for level offset 10 to operate according to design and component requirements. Therefore, Vm can be established according to the following formula (1):

[0057] Vm~MAX[VDD,VDDM-n*|VTp|](1)

[0058] In formula (1), Vm is approximately equal to the maximum value of VDD or VDDM minus the threshold voltage (e.g., Vtp) of the PMOS diode used to generate Vm. In this representative formula, the value of "n" is equal to the number of diodes used. For example, if a single diode is used, the value of n = 1; if two diodes are used, the value of n = 2; and so on. Figure 4 The diagram illustrates a representative structure of a PMOS diode circuit that can be used to generate Vm. Figure 4 In the example diode structure shown, Vm = VDDM - VTp. However, it should be understood that many other diode types and configurations can be used to generate Vm from VDDM. Furthermore, other structures and methods for generating Vm from VDDM are also possible. Therefore, the term VTp, as used herein, is defined to include such other threshold voltages and other voltage drops (collectively referred to herein as “threshold voltages”) associated with alternative diode types, diode configurations, structures, and methods.

[0059] Go to Figure 5 The transition from VDD domain 51 to VDDM domain 52 is illustrated according to some embodiments. Various level offset signal inputs from the VDD domain to the VDDM domain, indicated by 53, include, for example, clock signals, chip enable (CE), write enable (WE), addresses, and VDD. Additionally, VDDM is provided to level offset block 10. Therefore, although a single level offset block 10 is illustrated and described above, it should be understood that multiple level offset circuits 10 exist within the level offset block 10—each level offset circuit handles the level offset of a single bit during the transition between the VDD and VDDM domains.

[0060] Still referencing Figure 5 The diagram also illustrates a second level offset block 10, which receives data from the VDD field (illustrated at reference 54) as input to the level offset block 10. Since the data can be in the form of an address or a value of several bits, there are multiple level offset circuits 10 within the level offset block 10. An output latch 60 provides the data back to the VDD field. Figure 5The diagram also illustrates at least one memory array (e.g., multiple SRAM elements forming the memory array), word line drivers, local input-output, and local control blocks within the VDDM domain. In other embodiments, each of these blocks may be multiple.

[0061] Although not explicitly illustrated and as stated above, however Figure 5 The memory array may include one or more SRAM elements. Each SRAM element may be formed as a six-transistor SRAM memory cell. However, other SRAM memory cell arrangements may be used in other embodiments.

[0062] As an alternative embodiment, instead of a multiplexer, combinational logic can be used to apply Vm to the PMOS gate, based on the logic described above in Tables 1 and 2.

[0063] refer to Figure 6 Generally, at block 600, a method for a low-voltage level offset element for a dual-track SRAM architecture according to some embodiments is disclosed. First, at block 601, first and second complementary pairs of PMOS and NMOS transistors are connected by connecting their drains together. The connected drains form complementary level offset output voltage nodes and level offset output voltage nodes for the first and second complementary pairs of transistors, respectively. At block 602, a first voltage selector is connected between the level offset output voltage node and the gate of the PMOS transistor in the first complementary pair, and a second voltage selector is connected between the complementary level offset output node and the PMOS transistor in the second complementary pair. Figure 1 The diagram illustrates an example circuit according to some embodiments. A voltage Vm is established at block 603. As described above... Figure 4 In some embodiments, Vm may be VDD or some other intermediate voltage between the values ​​of the first power supply voltage VDD and the second power supply voltage VDDM.

[0064] At block 604, when the voltage of the complementary level offset output voltage node (LSOUTB) rises to logic 1, a voltage Vm is applied to the gate of PMOS transistor 23 in the first complementary pair, and when the voltage of the level offset output voltage node (LSOUT) rises to logic 1, a voltage Vm is applied to the gate of PMOS transistor 24 in the second complementary pair. By applying Vm to the gate of PMOS transistor 23 or 24, the corresponding PMOS transistor current decreases as it turns off and exhibits high resistance.

[0065] At block 605, when the voltage of the complementary level offset output voltage node (LSOUTB) drops to logic 0, the voltage of the level offset output voltage node (LSOUT) is applied to the gate of the PMOS transistor 23 in the first complementary pair, and when the voltage of the level offset output voltage node (LSOUT) drops to logic 0, the voltage of the complementary level offset output voltage node (LSOUTB) is applied to the gate of the PMOS transistor 24 in the second complementary pair. This method can be used, for example, with multiple level offsetters 50 (in... Figure 5 (Best seen in the middle) Combined for multiple input signals 53 operating from the first level (VDD) to the second higher voltage level (VDDM), and connecting the multiple higher voltage level signals to elements and circuits operating in multiple voltage domains, such as memory arrays of SRAM elements.

[0066] The disclosed embodiments include a level offsetter of the type used in multiple voltage domains, and include at least one level offsetter input, and provide a second voltage level according to a first voltage level. A voltage input terminal receives a first signal operating at the first voltage level (VDD). The voltage input terminal is also connected to the input of an inverter, which also includes an output. The drains of first and second complementary pairs of PMOS and NMOS transistors are connected together, establishing complementary level offset output voltage nodes and level offset output voltage nodes, respectively. A first voltage selector is connected between the level offset output node and the gate of the PMOS transistor in the first complementary pair, and a second voltage selector is connected between the complementary level offset output node and the PMOS transistor in the second complementary pair. When the voltage of the complementary level offset output voltage node rises to logic 1, the first voltage selector selectively applies an intermediate voltage (Vm) to the gate of the PMOS transistor in the first complementary pair, and when the voltage of the level offset output voltage node rises to logic 1, the second voltage selector applies an intermediate voltage (Vm) to the gate of the PMOS transistor in the second complementary pair.

[0067] In some embodiments, the voltage level offset device includes an intermediate voltage equal to a first voltage level.

[0068] In some embodiments, the voltage level offset device includes an intermediate voltage generated by a PMOS diode and equal to VDDM-n*|VTp|, where n is equal to the number of elements used to generate the intermediate voltage, VTp is the threshold voltage of one of the elements, and VDDM is a second voltage level applied to the source of the first and second complementary pairs of PMOS transistors.

[0069] In some embodiments, the voltage level offset device includes a first voltage selector that applies the voltage of the level offset output voltage node to the gate of the PMOS transistor of the first complementary pair when the voltage at the complementary level offset output node drops to a logic 0, and a second voltage selector that applies the voltage at the complementary level offset output node to the gate of the second PMOS transistor when the voltage at the level offset output voltage node drops to a logic 0.

[0070] In some embodiments, the voltage level offset device includes a first voltage selector and a second voltage selector, which are multiplexers.

[0071] In some embodiments, the voltage level offset device includes each of the multiplexers comprising two inputs and a selector input.

[0072] In some embodiments, the voltage level offset device includes a plurality of input signals and a corresponding plurality of level offset devices, wherein the input signals are offset from a first voltage level to a second voltage level, the second voltage level being greater than the first voltage level.

[0073] In some embodiments, the voltage level offset device has a voltage difference of 350mV to 500mV between a first voltage level and a second voltage level.

[0074] In some embodiments, the voltage level offset device also includes a memory array of SRAM elements, the memory array being operatively connected to a plurality of level offset devices and operating at a voltage level higher than a first voltage level.

[0075] According to a further disclosed embodiment, the voltage level offset device includes a voltage input terminal for receiving a first signal operating at a first voltage level (VDD). An inverter having an input and an output is also connected to the voltage input terminal. A first NMOS transistor having a drain and a gate is connected to the first voltage level, and a second NMOS transistor having a drain and a gate is connected to the output of the inverter. A first PMOS transistor having a gate and a drain is connected to the drain of the first NMOS transistor, wherein the connected drains form a complementary level offset output node. The second PMOS transistor having a gate and a drain is connected to the drain of the second NMOS transistor, wherein the connected drains form a level offset output node. The level offset output node and the complementary level offset output node operate at a second voltage level (VDDM) greater than the first voltage level (VDD). A voltage selector is connected between the level offset output node and the gate of the second PMOS transistor, and between the complementary level offset output node and the first PMOS transistor. When the level offset output node rises to logic 1, the voltage selector applies a third voltage (Vm) to the gate of the second PMOS transistor, and when the complementary level offset output node rises to logic 1, the voltage selector applies a third voltage (Vm) to the gate of the first PMOS transistor.

[0076] In some embodiments, the voltage level offset device includes a third voltage level equal to a first voltage level.

[0077] In some embodiments, the voltage level offset device includes a third voltage generated by a PMOS diode and equal to [VDDM-n*|VTp|], where VDDM is equal to the second voltage level, n is equal to the number of PMOS diodes, and VTp is the threshold voltage of a PMOS transistor forming the PMOS diode.

[0078] In some embodiments, the voltage level offset device includes a voltage selector that selects and applies a voltage at the complementary level offset output node to the gate of a second PMOS transistor when the voltage at the level offset output node drops to a logic 0, and a voltage selector that selects and applies a voltage at the level offset output node to the gate of a first PMOS transistor when the complementary level offset output node drops to a logic 0.

[0079] In some embodiments, the voltage level offset device includes a voltage selector comprising two multiplexers.

[0080] In some embodiments, the voltage level offset device includes two inputs and a selector for each of the two multiplexers.

[0081] In some embodiments, the voltage level offset device includes a plurality of input signals and a corresponding plurality of level offset devices, wherein these signals are offset from a first voltage level to a second voltage level.

[0082] In some embodiments, the voltage level offset device also includes a memory array of SRAM elements, the memory array being operatively connected to a plurality of level offset devices and operating at a second voltage level.

[0083] According to a further disclosed embodiment, there is a method for a voltage level offset device, the method comprising: configuring a voltage input terminal to receive a first signal operating at a first voltage level (VDD) and inverting the first signal; connecting the drains of a first complementary pair of PMOS and NMOS transistors together, the drains forming a complementary level offset output voltage node, and connecting the voltage input terminal to the gate of the NMOS transistor in the first complementary pair; connecting a second complementary pair of PMOS and NMOS transistors together with their drains, the drains establishing a level offset output voltage node, and connecting the inverted signal to the gate of the second complementary pair of PMOS and NMOS transistors; connecting a second complementary pair of PMOS and NMOS transistors together with their drains, the drains establishing a level offset output voltage node, and connecting the inverted signal to the gate of the second complementary pair of PMOS and NMOS transistors; and connecting the second complementary pair of PMOS and NMOS transistors together with their drains, the drains establishing a level offset output voltage node. The gate of the NMOS transistor in the complementary pair; a first voltage selector is connected between the level offset output node and the gate of the PMOS transistor in the first complementary pair, and a second voltage selector is connected between the complementary level offset output node and the PMOS transistor in the second complementary pair; when the voltage of the complementary level offset output voltage node rises to logic 1, an intermediate voltage (Vm) is selectively applied to the gate of the PMOS transistor in the first complementary pair; and when the voltage of the level offset output voltage node rises to logic 1, an intermediate voltage (Vm) is selectively applied to the gate of the PMOS transistor in the second complementary pair.

[0084] In some embodiments, the method for a voltage level offset device also includes: selectively applying a voltage at the level offset output voltage node to the gate of a PMOS transistor in a first complementary pair when the voltage of the complementary level offset output voltage node drops to a logic 0; and selectively applying a voltage at the complementary level offset output voltage node to the gate of a PMOS transistor in a second complementary pair when the voltage of the level offset output voltage node drops to a logic 0.

[0085] In some embodiments, the method for a voltage level offset device also includes: offsetting a plurality of input signals operating at a first level to a second higher voltage level, and connecting the higher voltage level signals to a memory array of SRAM elements.

[0086] The features of several embodiments have been outlined above to enable those skilled in the art to better understand the various aspects of one embodiment of this application. Those skilled in the art should understand that they can readily use one embodiment of this application as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of this application, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of one embodiment of this application.

Claims

1. A voltage level offset device, characterized in that, include: A voltage input terminal for receiving a first signal operating at a first voltage level, and An inverter having an input terminal and an output terminal, wherein the voltage input terminal is connected to the input terminal of the inverter; A first complementary pair of P-type metal-oxide-semiconductor transistors and N-type metal-oxide-semiconductor transistors, the drains of the first complementary pair of P-type metal-oxide-semiconductor transistors and N-type metal-oxide-semiconductor transistors are connected together, the connected drains establish a complementary level offset output voltage node, and the voltage input terminal is connected to the gate of the N-type metal-oxide-semiconductor transistor in the first complementary pair. A second complementary pair of P-type metal-oxide-semiconductor transistors and N-type metal-oxide-semiconductor transistors, the drains of the P-type metal-oxide-semiconductor transistors and N-type metal-oxide-semiconductor transistors of the second complementary pair are connected together, the connected drains establish a quasi-offset output voltage node, and the output terminal of the inverter is connected to the gate of the N-type metal-oxide-semiconductor transistor in the second complementary pair. A first voltage selector is connected between the level offset output node and the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair. The first voltage selector includes a selector input connected to the complementary level offset output voltage node. A second voltage selector is connected between the complementary level offset output node and the P-type metal-oxide-semiconductor transistor in the second complementary pair. The second voltage selector includes a selector input connected to the level offset output voltage node. When the voltage of the complementary level offset output voltage node rises to a logic 1, the first voltage selector selectively applies an intermediate voltage to the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair; and when the voltage of the level offset output node rises to a logic 1, the second voltage selector selectively applies the intermediate voltage to the gate of the P-type metal-oxide-semiconductor transistor in the second complementary pair. The system contains multiple input signals and corresponding multiple level offset devices, wherein the multiple input signals are offset from the first voltage level to a second voltage level greater than the first voltage level to establish a high voltage domain in which multiple static random access memory units operate.

2. The voltage level offset device as claimed in claim 1, wherein the intermediate voltage is equal to the first voltage level.

3. The voltage level offset device of claim 1, wherein the intermediate voltage is generated by a P-type metal-oxide-semiconductor diode and is equal to VDDM-n*|VTp|, where n is equal to the number of the plurality of elements used to generate the intermediate voltage, VTp is the threshold voltage of one of the plurality of elements, and VDDM is the second voltage level applied to the source of the P-type metal-oxide-semiconductor transistors of the first complementary pair and the second complementary pair.

4. The voltage level offset device of claim 1, wherein when the voltage at the complementary level offset output node drops to a logic 0, the first voltage selector applies the voltage of the level offset output voltage node to the gate of the P-type metal-oxide-semiconductor transistor of the first complementary pair, and wherein when the voltage at the level offset output voltage node drops to the logic 0, the second voltage selector applies the voltage at the complementary level offset output node to the gate of the P-type metal-oxide-semiconductor transistor of the second complementary pair.

5. The voltage level offset device as claimed in claim 4, wherein the first voltage selector and the second voltage selector are multiplexers.

6. The voltage level offset device of claim 5, wherein each of the plurality of multiplexers includes two inputs and a selector input.

7. The voltage level offset device as claimed in claim 1, wherein the voltage difference between the first voltage level and the second voltage level is 350mV to 500mV.

8. The voltage level offset device of claim 1, wherein the plurality of static random access memory units comprise a memory array having a plurality of static random access memory elements, the memory array being operatively connected to the plurality of level offset devices and operating at the second voltage level.

9. The voltage level offset device of claim 1, further comprising a memory array having a plurality of static random access memory elements, the memory array being operatively connected to the plurality of level offset devices and operating at a voltage level higher than the first voltage level. Each of the plurality of level offset devices includes its own voltage input terminal, and The plurality of first signals applied to the plurality of voltage input terminals include a clock signal, a wafer enable signal, and a write enable signal.

10. A voltage level offset device, characterized in that, include: A voltage input terminal is used to receive a first signal that operates at a first voltage level; An inverter having an input terminal and an output terminal, wherein the voltage input terminal is connected to the input terminal of the inverter; A first N-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor, the first N-type metal-oxide-semiconductor transistor having a drain and a gate connected to the first voltage level, and the second N-type metal-oxide-semiconductor transistor having a drain and a gate connected to the output terminal of the inverter; A first P-type metal-oxide-semiconductor transistor has a gate and a drain connected to the drain of a first N-type metal-oxide-semiconductor transistor, wherein the drain of the first N-type metal-oxide-semiconductor transistor and the drain of the first P-type metal-oxide-semiconductor transistor form a complementary level offset output node. A second P-type metal-oxide-semiconductor transistor has a gate and a drain connected to the drain of the second N-type metal-oxide-semiconductor transistor, wherein the drain of the second N-type metal-oxide-semiconductor transistor and the drain of the second P-type metal-oxide-semiconductor transistor form a level offset output node. The level offset output node and the complementary level offset output node operate at a second voltage level greater than the first voltage level; A voltage selector is connected between the level offset output node and the gate of the second P-type metal-oxide-semiconductor transistor, and between the complementary level offset output node and the gate of the first P-type metal-oxide-semiconductor transistor. The voltage selector has a first selector input and a second selector input. The first selector input is directly connected to the level offset output node through a first amplifier, and the second selector input is directly connected to the complementary level offset output node through a second amplifier. When the level offset output node rises to logic 1, the voltage selector applies a third voltage to the gate of the second P-type metal-oxide-semiconductor transistor, and when the complementary level offset output node rises to logic 1, the voltage selector applies the third voltage to the gate of the first P-type metal-oxide-semiconductor transistor. The system includes multiple input signals and corresponding multiple level offset devices, wherein the multiple input signals are offset from the first voltage level to the second voltage level; as well as A memory array having a plurality of static random access memory elements, the memory array being operatively connected to the plurality of level offset devices and operating at the second voltage level to improve the operation of the memory array having the plurality of static random access memory elements.

11. The voltage level offset device of claim 10, wherein the third voltage is equal to the first voltage level.

12. The voltage level offset device of claim 10, wherein the third voltage is generated by a P-type metal-oxide-semiconductor diode and is equal to [VDDM-n*|VTp|], wherein VDDM is equal to the second voltage level, n is equal to the number of P-type metal-oxide-semiconductor diodes, and VTp is the threshold voltage of a P-type metal-oxide-semiconductor transistor forming the P-type metal-oxide-semiconductor diode.

13. The voltage level offset device of claim 10, wherein when the voltage at the level offset output node drops to a logic 0, the voltage selector selects and applies the voltage at the complementary level offset output node to the gate of the second P-type metal-oxide-semiconductor transistor, and When the complementary level offset output node drops to logic 0, the voltage selector selects and applies the voltage at the level offset output node to the gate of the first P-type metal-oxide-semiconductor transistor.

14. The voltage level offset device of claim 10, wherein the voltage selector comprises two multiplexers.

15. The voltage level offset device of claim 14, wherein each of the two multiplexers includes two inputs and a selector.

16. The voltage level offset device of claim 10, wherein the voltage selector includes combinational logic.

17. The voltage level offset device of claim 10, wherein each of the plurality of level offset devices includes a respective voltage input terminal, and wherein the plurality of first signals applied to the plurality of voltage input terminals includes a clock signal, a wafer enable signal, and a write enable signal.

18. An operating method for a voltage level offset device, characterized in that, include: Configure the voltage input terminal to receive a first signal operating at a first voltage level and invert the first signal; The drains of the P-type metal-oxide-semiconductor transistor and the drains of the N-type metal-oxide-semiconductor transistor in the first complementary pair are connected together, and the drains of the P-type metal-oxide-semiconductor transistor and the drains of the N-type metal-oxide-semiconductor transistor in the first complementary pair form a complementary level offset output voltage node, and the voltage input terminal is connected to the gate of the N-type metal-oxide-semiconductor transistor in the first complementary pair. The drains of the P-type metal-oxide-semiconductor transistor and the drains of the N-type metal-oxide-semiconductor transistor in the second complementary pair are connected together, and the drains of the P-type metal-oxide-semiconductor transistor and the drains of the N-type metal-oxide-semiconductor transistor in the second complementary pair are used to establish a level offset output voltage node, and the inverted first signal is connected to the gate of the N-type metal-oxide-semiconductor transistor in the second complementary pair. A first voltage selector is connected between the level offset output node and the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair. The first voltage selector includes a selector input that is directly connected to the complementary level offset output node through a first amplifier. A second voltage selector is connected between the complementary level offset output node and the P-type metal-oxide-semiconductor transistor in the second complementary pair. The second voltage selector includes a selector input that is directly connected to the complementary level offset output node through a second amplifier. When the voltage of the complementary level offset output voltage node rises to logic 1, an intermediate voltage is selectively applied to the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair. When the voltage of the level offset output voltage node rises to logic 1, the intermediate voltage is selectively applied to the gate of the P-type metal-oxide-semiconductor transistor in the second complementary pair. as well as The offset operation moves multiple input signals at a first voltage level to a second voltage level higher than the first voltage level, and connects the multiple input signals operating at the second voltage level to a memory array having multiple static random access memory elements, thereby improving the operation of the memory array having the multiple static random access memory elements.

19. The method of operating the voltage level offset device as described in claim 18, further comprising: When the voltage of the complementary level offset output voltage node drops to a logic 0, the voltage at the level offset output voltage node is selectively applied to the gate of the P-type metal-oxide-semiconductor transistor in the first complementary pair. as well as When the voltage at the quasi-offset output voltage node drops to logic 0, the voltage at the complementary quasi-offset output voltage node is selectively applied to the gate of the P-type metal-oxide-semiconductor transistor in the second complementary pair.

20. The method of operating the voltage level offset device as claimed in claim 18, wherein the voltage selector includes combinational logic.

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