Semiconductor device having a semiconductor package and a thermally conductive layer for heat dissipation

Abstract

A semiconductor device includes a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a conductive label that is flexible and disposed on the semiconductor package, the conductive label including a first adhesive layer in contact with the semiconductor package; a thermally conductive layer attached to the semiconductor package by the first adhesive layer and having a second length in the first horizontal direction that is greater than the first length; and a second adhesive layer in contact with a portion of a surface of the thermally conductive layer that does not vertically overlap the semiconductor package; a thermal interface material (TIM) disposed on the thermally conductive layer to vertically overlap the semiconductor package; and an enclosure including a first enclosure portion and a second enclosure portion, the first enclosure portion vertically overlapping the semiconductor package and in contact with the TIM, the thermally conductive layer attached to the second enclosure portion by the second adhesive layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0116366, filed September 20, 2019, and Korean Patent Application No. 10-2020-0027214, filed March 4, 2020, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a semiconductor package. BACKGROUND

[0004] A semiconductor package can generate a large amount of heat due to its high performance and implementation of various functions. Accordingly, heat dissipation performance of a semiconductor device including the semiconductor package is crucial to securing operational stability and product reliability of semiconductor chips in the semiconductor package. Therefore, structures of semiconductor devices capable of effectively discharging heat generated from the semiconductor package in a limited space provided by a housing of the semiconductor device have been actively researched. SUMMARY

[0005] The present inventive concept provides a semiconductor device capable of rapidly discharging heat generated from a semiconductor package to the outside of the semiconductor device.

[0006] The present inventive concept also provides a semiconductor device capable of inhibiting a short circuit defect.

[0007] According to an aspect of the inventive concept, a semiconductor device includes a system substrate, a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction, a conductive label that is flexible and disposed on the semiconductor package, the conductive label including a first adhesive layer in contact with the semiconductor package, a thermally conductive layer attached to the semiconductor package through the first adhesive layer and having a second length in the first horizontal direction that is greater than the first length of the semiconductor package, and a second adhesive layer in contact with a portion of a surface of the thermally conductive layer that does not vertically overlap the semiconductor package, a thermal interface material (TIM) disposed on the thermally conductive layer to vertically overlap the semiconductor package, and a housing including a first housing portion that vertically overlaps the semiconductor package and is in contact with the TIM, and a second housing portion to which the thermally conductive layer is attached through the second adhesive layer.

[0008] According to another aspect of the inventive concept, a semiconductor device includes a system substrate, a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction, a housing disposed such that a top surface of the semiconductor package is not covered by the housing and the housing surrounds a side surface of the semiconductor package, and a conductive label connecting the semiconductor package to the housing, the conductive label including a first adhesive layer in contact with the semiconductor package, and a thermally conductive layer disposed on the first adhesive layer and having a second length in the first horizontal direction that is greater than the first length of the semiconductor package.

[0009] According to still another aspect of the inventive concepts, a semiconductor device includes a first system substrate, a second system substrate vertically separated from the first system substrate, a flexible substrate connecting the first system substrate to the second system substrate, a housing surrounding the first system substrate, the second system substrate, and the flexible substrate, a first semiconductor package mounted on the first system substrate and having a first length in a first horizontal direction, a second semiconductor package mounted on the second system substrate and having a second length in the first horizontal direction, a first conductive label between the first semiconductor package and the housing, the first conductive label including a first adhesive layer in contact with the first semiconductor package, a first thermally conductive layer disposed on the first adhesive layer and having a third length in the first horizontal direction greater than the first length of the first semiconductor package in the first horizontal direction, and a second adhesive layer disposed on the first thermally conductive layer to contact the housing and attach the first thermally conductive layer to an inner surface of the housing, and a second conductive label between the second semiconductor package and the housing, the second conductive label including a third adhesive layer in contact with the second semiconductor package, a second thermally conductive layer disposed on the third adhesive layer and having a fourth length in the first horizontal direction greater than the second length of the second semiconductor package in the first horizontal direction, and a fourth adhesive layer disposed on the second thermally conductive layer to contact the housing and attach the second thermally conductive layer to the inner surface of the housing. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view of a first conductive label according to an example embodiment of the inventive concepts;

[0012] Figure 2 is a cross-sectional view of a second conductive label according to an example embodiment of the inventive concepts;

[0013] Figure 3 is a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concepts;

[0014] Figure 4 is a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concepts taken along line IV-IV' of Figure 3 Figure 3 ​a cross-sectional view of a conductive layer of a semiconductor device;

[0015] Figure 5 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0016] Figure 6 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0017] Figure 7 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0018] Figure 8 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0019] Figure 9 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0020] Figure 10 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0021] Figure 11 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept; Figure 10 a plan view of a region A of a semiconductor device;

[0022] Figure 12 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0023] Figure 13 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0024] Figure 14 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0025] Figure 15 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept; and

[0026] Figure 16 a cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] In the following, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 a cross-sectional view of a first conductive label 100a according to an example embodiment of the inventive concept.

[0029] With reference to Figure 1A first conductive label 100a, according to an exemplary embodiment of the present invention, includes a first adhesive layer 110 and a conductive layer 120. This conductive label may also be described as a conductive strip or conductive sheet. Although described as conductive label 100a, conductive label 100a need not include any printing or other markings.

[0030] In an example embodiment, the first conductive tag 100a may be a flexible, bendable tag that will be removed from a semiconductor package (e.g., Figure 3 The heat generated by (20) is transferred to the outer casing (e.g., Figure 3 (30). In addition, the first conductive label 100a may be a label with adhesive properties. For example, the first conductive label 100a may have a plate shape that is attached to the top surface of the semiconductor package 20 and the inner surface of the housing 30, and transfers heat generated from the semiconductor package 20 to the housing 30.

[0031] In the example embodiment, the vertical length (i.e., thickness) T1 of the first conductive label 100a can be significantly smaller than its horizontal length L1. For example, the vertical length T1 of the first conductive label 100a can be approximately 10 times to approximately 100,000 times smaller than its horizontal length L1. As described above, because the vertical length T1 of the first conductive label 100a can be significantly smaller than its horizontal length L1, the first conductive label 100a can be flexible, bendable, and conformal. For example, based on its thin profile, the first conductive label 100a has the characteristic of bending under its own weight without perforations or pre-defined edges.

[0032] In an example embodiment, the vertical length T1 of the first conductive tag 100a can range from approximately 0.10 mm to approximately 0.50 mm. More specifically, the vertical length T1 of the first conductive tag 100a can range from approximately 0.20 mm to approximately 0.35 mm. In these cases, according to some examples, the first conductive tag 100a is in a direction such as the X direction (see...). Figure 3The horizontal length in one direction of the first conductive label 100a can be longer than the length P1 of the semiconductor package, and can be, for example, in a range from about 1 cm to 2.5 times to 10 times the length of the semiconductor package in the X direction, or in a range from about 1 cm to the length as long as the length of the semiconductor device in the X direction that accommodates the semiconductor package. These horizontal lengths can apply to any of the different vertical lengths T1 described above (e.g., to any vertical length T1 between about 0.10 mm to about 0.50 mm), and can apply to the various embodiments described herein. Other examples will be described below. However, the inventive concepts are not limited to these examples, and the vertical length T1 and the horizontal length L1 of the first conductive label 100a can have various values according to the size of the semiconductor device (e.g., the semiconductor package 20, the semiconductor device 10, or the semiconductor device 10a) that includes the semiconductor package 20. In addition, terms such as "about" or "approximately" can reflect a quantity, size, direction, or layout that varies in a relatively small way and / or in a way that does not significantly change the operation, function, or structure of certain elements. For example, a range of "about 0.1 to about 1" can include a range such as 0.1 plus or minus 0-5% deviation and 1 plus or minus 0-5% deviation, particularly if such deviations maintain the same effect as the listed range. Figure 3

[0033] The first adhesive layer 110 of the first conductive label 100a can attach the conductive layer 120 to the semiconductor package 20. For example, the first adhesive layer 110 can be directly connected to both the conductive layer 120 and the semiconductor package 20. The first adhesive layer 110 can be a non-conductive film (NCF). For example, the first adhesive layer 110 can be a film including an insulating polymer. The first adhesive layer 110 can be non-conductive, but can be thermally conductive. The term non-conductive film or NCF is used herein to refer to a component that is not conductive. In addition, the first adhesive layer 110 can be a film that has adhesive properties by itself. For example, the first adhesive layer 110 can be a double-sided adhesive film.

[0034] The conductive layer 120 of the first conductive label 100a can be disposed on the first adhesive layer 110, and can transfer heat generated from the semiconductor package 20 to the housing 30. The thickness of the conductive layer 120 can be greater than the thickness of the first adhesive layer 110.

[0035] The conductive layer 120 can include a material having excellent thermal conductivity. In an example embodiment, the conductive layer 120 can include a metallic material having excellent thermal conductivity. For example, the conductive layer 120 can include a metallic material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), or nickel (Ni).

[0036] ​In example embodiments, the conductive layer 120 can include a carbon-based material having excellent thermal conductivity. For example, the conductive layer 120 can include graphite, diamond, carbon fiber, etc. In addition, the conductive layer 120 can include a polymer material having excellent thermal conductivity. However, the conductive layer 120 is not limited to the above-described materials, and can include a combination of the above-described materials or include other materials not mentioned above.

[0037] The conductive layer 120 can be formed of a thermally conductive material or a heat-conducting material, such as one of the materials listed above. Based on the material used, it can be electrically conductive or non-conductive. The term "heat-conducting" or "thermally conductive" does not apply to a particular material merely because it provides incidental heat conduction, but is intended to mean a material that is generally referred to as a good thermal conductor or is known to have a heat transfer effect, or a component having similar heat conduction properties to those materials. Also, components described as being thermally connected or in thermal communication are arranged so that heat will travel along the path between the components to allow heat to pass from a first component to a second component. Merely because two components are part of the same device or the same package does not make them thermally connected. In general, a component that is thermally conductive and is directly connected to (or connected to other thermally conductive or heat-generating components by intermediate thermally conductive components or in a manner that is in close proximity to allow substantial heat transfer) other thermally conductive or heat-generating components will be described as being thermally connected to those components, or in thermal communication with those components. Conversely, two components with an insulating material therebetween that significantly prevents heat transfer between the two components or only allows incidental heat transfer are not described as being thermally connected or in thermal communication with each other.

[0038] Figure 2 is a cross-sectional view of a second conductive label 100b according to an example embodiment of the inventive concept.

[0039] Referring to Figure 2 , the second conductive label 100b according to an example embodiment of the inventive concept can include a first adhesive layer 110, a conductive layer 120, a second adhesive layer 130, and an insulating layer 140. For example, the second conductive label 100b can have a structure in which the first adhesive layer 110, the conductive layer 120, the second adhesive layer 130, and the insulating layer 140 are sequentially stacked in order. The description of the first adhesive layer 110 and the conductive layer 120 of the second conductive label 100b is substantially the same as that given with respect to the first conductive label 100a, and thus will be omitted.

[0040] The second conductive label 100b can be a flexible label that transfers heat generated from the semiconductor package 20 to the housing 30. In addition, the second conductive label 100b can be a label having an adhesive property.

[0041] In the example embodiment, the vertical length (i.e., thickness T2) of the second conductive label 100b can be significantly smaller than its horizontal length L2. For example, the vertical length T2 of the second conductive label 100b can be approximately 10 times to approximately 100,000 times smaller than its horizontal length L2. Because the vertical length T2 of the second conductive label 100b can be significantly smaller than its horizontal length L2, the second conductive label 100b can be flexible, bendable, and conformal.

[0042] In an example embodiment, the vertical length T2 of the second conductive tag 100b can range from approximately 0.10 mm to approximately 3.00 mm. More specifically, the vertical length T2 of the second conductive tag 100b can range from approximately 0.20 mm to approximately 0.50 mm. In these cases, according to some examples, the horizontal length of the second conductive tag 100b in one direction can be longer than the length of the semiconductor package to which the second conductive tag 100b is attached, and for example, can range from approximately 1 cm to a length that is 2.5 to 10 times the length of the semiconductor package in the X direction, or from approximately 1 cm to a length that is the same as the length of the semiconductor device housing the semiconductor package. Other examples will be described below. However, the inventive concept is not limited thereto, and the vertical length T2 of the second conductive tag 100b can be determined based on the semiconductor package (e.g., Figure 3 Semiconductor devices (e.g., 20) Figure 3 The size of 1) in the figure has various values.

[0043] In an example embodiment, the second adhesive layer 130 of the second conductive tag 100b can attach the insulating layer 140 to the conductive layer 120. The second adhesive layer 130 can be a non-conductive film. For example, the second adhesive layer 130 can be a film comprising an electrically insulating polymer. Alternatively, the second adhesive layer 130 can be a film that inherently possesses adhesive properties. For example, the second adhesive layer 130 can be a double-sided adhesive film. Furthermore, the second adhesive layer 130 can comprise substantially the same material as the first adhesive layer 110.

[0044] In an example embodiment, the insulating layer 140 (which may be an electrically insulating layer) of the second conductive tag 100b can prevent the conductive layer 120 from contacting the system substrate (e.g., outside the area occupied by a semiconductor package) in areas such as those occupied by a semiconductor package. Figure 3The second conductive tag 100b has an insulating layer 140 that electrically insulates the conductive layer 120 from the system substrate 10. For example, the insulating layer 140 may be a layer used to suppress short circuits by preventing contact between the conductive layer 120 and the system substrate 10, for example, due to warping or physical stress applied outside the area occupied by the semiconductor package. It should be noted that unless the context clearly indicates otherwise, the term "contact" refers to a direct connection (e.g., touching).

[0045] For example, insulating layer 140 may include at least one selected from epoxy resin, polybenzobisoxazole (PBO), benzocyclobutene (BCB), polyimide, and polyimide derivatives. However, the inventive concept is not limited thereto, and insulating layer 140 may include various insulating materials.

[0046] and Figure 2 Unlike other conductive labels, although the second conductive label 100b includes a first adhesive layer 110, a conductive layer 120, and a second adhesive layer 130, the second conductive label 100b may not include an insulating layer 140. For example, in order to arrange the conductive layer 120 between the first component and the second component, the second conductive label 100b may include a first adhesive layer 110 and a second adhesive layer 130 respectively attached to the two surfaces of the conductive layer 120, and may not include an insulating layer 140.

[0047] The following will describe in more detail a semiconductor device that can rapidly dissipate heat generated by a semiconductor package to the outside of the semiconductor device by using a conductive tag having a structure substantially the same as or similar to that of the first conductive tag 100a and the second conductive tag 100b described above.

[0048] Figure 3 This is a cross-sectional view of a semiconductor device 1 according to an exemplary embodiment of the present invention. The semiconductor device 1 according to an exemplary embodiment of the present invention may include a system substrate 10, a semiconductor package 20, a housing 30, a conductive label 100, and a thermal interface material 150.

[0049] The system substrate 10 can be a substrate for connecting the semiconductor package 20 to an external device (e.g., one or more components of the semiconductor device 1). The system substrate 10 can include substrate pads 101 (e.g., a plurality of substrate pads 101) in contact with the package connection terminals 250 (e.g., a plurality of respective package connection terminals 250) of the semiconductor package 20. In an example embodiment, the system substrate 10 can be a single-sided printed circuit board (PCB) including the substrate pads 101 on only one surface thereof. However, the inventive concept is not limited thereto, and the system substrate 10 can be a double-sided PCB including the substrate pads 101 on both surfaces thereof. The system substrate 10 is not limited to the structure and material of the PCB, and may, for example, include various substrates such as a ceramic substrate.

[0050] The semiconductor package 20 can be mounted on the system substrate 10, and can include a semiconductor chip 200 connected to the substrate pads 101 of the system substrate 10. In an example embodiment, the semiconductor package 20 can include the semiconductor chip 200, a molding layer 230, a wiring structure 240, and the package connection terminals 250. The semiconductor package 20 can have a first length P1 in a horizontal direction (e.g., an X direction). The horizontal direction can be defined as a direction substantially parallel to an extension direction of a top surface of the semiconductor chip 200. Although Figure 3 The semiconductor package 20 can have a second length in a second horizontal direction (e.g., a Y direction), although not shown in FIG. 1.

[0051] Although Figure 3 Although the semiconductor package 20 is shown to include one semiconductor chip 200, the semiconductor package 20 can include two or more semiconductor chips 200. The semiconductor chips 200 included in the semiconductor package 20 can be of the same type or different types. In an example embodiment, the semiconductor package 20 can be a system-in-package (SIP) in which different types of semiconductor chips 200 are electrically connected to each other to operate as one system.

[0052] The semiconductor chip 200 can include a semiconductor device layer (not shown), also described as an active layer, and the semiconductor device layer can be formed in a lower portion of the semiconductor chip 200. A plurality of individual devices of various types can be formed in the semiconductor device layer. In an example embodiment, the plurality of individual devices can include various microelectronic devices, e.g., complementary metal-oxide semiconductor (CMOS) transistors, metal-oxide semiconductor field-effect transistors (MOSFETs), system large-scale integrated circuits (system LSIs), imaging sensors (e.g., CMOS imaging sensors (CISs)), micro electro mechanical systems (MEMS), active elements, passive elements, etc.

[0053] The semiconductor chip 200 can include a memory semiconductor chip. For example, the memory semiconductor chip can include a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), and can include a non-volatile memory semiconductor chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0054] In addition, the semiconductor chip 200 can include a logic semiconductor chip. The logic semiconductor chip, for example, can include a logic semiconductor chip such as a central processing unit (CPU), a micro processing unit (MPU), a graphic processing unit (GPU), or an application processor (AP). As used herein, the term "semiconductor device" may, for example, be used to refer to a device such as a semiconductor chip (e.g., a memory chip and / or a logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a package-on-package device including a plurality of packages.

[0055] In an example embodiment, the semiconductor chip 200 can include silicon (Si). However, the inventive concept is not limited thereto, and the semiconductor chip 200 can include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0056] In an example embodiment, the semiconductor chip 200 can include a chip pad 210 (e.g., a plurality of chip pads 210). The chip pad 210 can be electrically connected to a plurality of various types of individual devices described above.

[0057] In an example embodiment, the semiconductor chip 200 can include a passivation layer 220 surrounding a side surface of the chip pad 210 and exposing one surface of the chip pad 210. The passivation layer 220 can include an insulating material. In addition, the passivation layer 220 can have a thickness of about 2 micrometers (μm) to about 100 μm. More specifically, the passivation layer 220 can have a thickness of about 3 μm to about 50 μm. However, the inventive concept is not limited thereto, and the passivation layer 220 can have various thicknesses.

[0058] The molding layer 230 can surround at least a portion of the side surface of the semiconductor chip 200 on the wiring structure 240. In an example embodiment, the molding layer 230 can surround both the top surface and the side surface of the semiconductor chip 200. However, the inventive concept is not limited thereto, and as described below, the molding layer 230 can expose the top surface of the semiconductor chip 200 while surrounding the side surface of the semiconductor chip 200.

[0059] In an example embodiment, the molding layer 230 can include an epoxy molding compound (EMC). However, the inventive concept is not limited thereto, and the molding layer 230 can include various electrically insulating materials such as epoxy-based materials, thermosetting materials, thermoplastic materials, and ultraviolet (UV) treated materials.

[0060] In an example embodiment, the wiring structure 240 can be a structure for electrically connecting the semiconductor chip 200 to the package connection terminal 250. For example, the wiring structure 240 can be a redistribution structure including a redistribution pattern and an insulating material surrounding the redistribution pattern. However, the inventive concept is not limited thereto, and the wiring structure 240 can be a PCB configured to electrically connect the semiconductor chip 200 to the package connection terminal 250.

[0061] The semiconductor package 20 is not limited to the above-described structure, and can include various structures of semiconductor packages. For example, as shown in FIG. 2, the semiconductor package 20 can be, but is not limited to, a fan-out wafer level package (FOWLP), and can be a fan-in wafer level package (FIWLP). In addition, the semiconductor package 20 can be a panel level package (PLP). Figure 3

[0062] The conductive label 100 can be attached to both the top surface of the semiconductor package 20 and the inner surface of the housing 30. More specifically, although there is a height difference between the top surface of the semiconductor package 20 and the inner surface of the housing 30, the conductive label 100 can be attached to both the top surface of the semiconductor package 20 and the inner surface of the housing 30 due to the flexibility and bendability of the conductive label 100, even though they are located at different heights above the surface of the system substrate 10.

[0063] The conductive label 100 can include a first adhesive layer 110, a conductive layer 120, and a second adhesive layer 130. The first adhesive layer 110 can contact the top surface of the semiconductor package 20. More specifically, the first adhesive layer 110 can be disposed between the semiconductor package 20 and the conductive layer 120. The first adhesive layer 110 can attach a portion of the conductive layer 120 to the top surface of the semiconductor package 20.

[0064] ​The conduction layer 120 can transfer heat generated from the semiconductor package 20 to the housing 30. In an example embodiment, the conduction layer 120 can be in the form of a sheet, and can have a plate shape with a vertical (Z-directional) length thereof being significantly smaller than a horizontal (X-directional) length thereof. For example, a thickness of the conduction layer 120 in a direction away from (e.g., perpendicular to) a surface on which the conduction layer 120 is disposed can be significantly smaller than a length of the conduction layer 120 along the surface on which the conduction layer 120 is disposed (e.g., can be 1 / 10 to 1 / 100,000 of the length). Due to the above structure of the conduction layer 120, the conduction layer 120 can be flexible. In addition, a horizontal (X-directional) length C1 of the conduction layer 120 can be greater than a horizontal (X-directional) length P1 of the semiconductor package 20. Accordingly, the conduction layer 120 can be disposed partially above the semiconductor package 20, and can be disposed partially below the housing 30 in which the semiconductor package 20 is not disposed.

[0065] The second adhesive layer 130 can contact an inner surface of the housing 30. More specifically, the second adhesive layer 130 can be disposed between the housing 30 and the conduction layer 120. The second adhesive layer 130 can attach a portion of the conduction layer 120 to the inner surface of the housing 30.

[0066] In an example embodiment, the conduction layer 120 can include a first conduction portion 120a, a second conduction portion 120b, and a third conduction portion 120c. For example, these portions can be thermally conductive portions. The first conduction portion 120a can be a portion of the conduction layer 120 vertically overlapping (e.g., as viewed from a top view) the semiconductor package 20 and disposed between the first adhesive layer 110 and the thermal interface material 150. The first conduction portion 120a can transfer heat generated from the semiconductor package 20 to a lower portion of the thermal interface material 150.

[0067] The second conduction portion 120b can be a portion of the conduction layer 120 curved upward from the first conduction portion 120a and surrounding a side surface of the thermal interface material 150. In an embodiment, the second conduction portion 120b can extend vertically, and can have a vertically extending surface in contact with the side surface of the thermal interface material 150. The second conduction portion 120b can transfer heat generated from the semiconductor package 20 to a side portion of the thermal interface material 150.

[0068] The third conductive portion 120c can be a portion of the conductive layer 120 that is laterally bent from the second conductive portion 120b and attached to the inner surface of the housing 30 by the second adhesive layer 130. Also, the third conductive portion 120c does not vertically overlap (from a top view) the semiconductor package 20. The third conductive portion 120c can be located outside an area occupied by the semiconductor package 20 from a top view. The third conductive portion 120c can transfer heat generated from the semiconductor package 20 to a portion of the housing 30 that does not vertically overlap (from a top view) the semiconductor package 20.

[0069] The thermal interface material 150 can be disposed between the semiconductor package 20 and the housing 30 and transfer heat generated from the semiconductor package 20 to the housing 30.

[0070] In an example embodiment, the thermal interface material 150 can be disposed on the conductive layer 120 to vertically overlap (from a top view) the semiconductor package 20. More specifically, the thermal interface material 150 can be disposed between the housing 30 and the first conductive portion 120a. Also, a bottom surface and side surfaces of the thermal interface material 150 can be surrounded by the first conductive portion 120a and the second conductive portion 120b, respectively, and a top surface of the thermal interface material 150 can be surrounded by the housing 30.

[0071] The thermal interface material 150 can include a thermally conductive material. In an example embodiment, the thermal interface material 150 can include mineral oil, grease, caulk, phase change gel, phase change material pad, particle-filled epoxy, etc. However, the inventive concept is not limited thereto, and the thermal interface material 150 can include various materials having excellent thermal conductivity.

[0072] The housing 30 can cover the semiconductor package 20 to protect the semiconductor package 20 from external impact. As Figure 3 shown, the housing 30 can surround a top surface of the semiconductor package 20. However, the inventive concept is not limited thereto, and the housing 30 can cover all surfaces of the semiconductor package 20, side surfaces and the top surface, and a bottom surface of the system substrate 10.

[0073] In an example embodiment, the housing 30 can be a case that forms an exterior of the semiconductor device 1, or can be a case for packaging the semiconductor package 20. For example, the case can surround at least the top surface and the bottom surface of the semiconductor package 20, and can additionally surround 2-4 other side surfaces. However, the inventive concept is not limited thereto, and the housing 30 can be a heat dissipation member for heat dissipation of the semiconductor package 20.

[0074] In an example embodiment, the housing 30 can include a material having excellent thermal conductivity to rapidly discharge heat generated from the semiconductor package 20 to the outside of the semiconductor device 1. For example, the housing 30 can include a metallic material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), or nickel (Ni). However, the inventive concept is not limited thereto, and the housing 30 can include a carbon-based material having excellent thermal conductivity, such as graphite, diamond, or carbon fiber.

[0075] The housing 30 can include a first housing portion 30a and a second housing portion 30b. The first housing portion 30a can be a portion of the housing 30 that vertically overlaps the semiconductor package 20 and is in contact with the thermal interface material 150, as seen in a top view. Also, the second housing portion 30b can be a portion of the housing 30 that does not vertically overlap the semiconductor package 20 and is in contact with the second adhesive layer 130, as seen in a top view.

[0076] The semiconductor device 1 according to an example embodiment of the inventive concept can be an electronic device such as a solid state disk device. Also, the housing 30 can be a case that forms the outside of the solid state disk device. For example, the housing 30 can surround the system substrate 10 and the outside of the semiconductor package 20. However, the semiconductor device 1 is not limited thereto, and in some embodiments, the semiconductor device 1 can also be an electronic device such as a mobile phone, a tablet device, a laptop computer, a music player device, or other personal electronic device, or an external hard disk drive or other computer component.

[0077] The thermal interface material 150 included in a general semiconductor device can be located within an area defined by the top surface of the semiconductor package 20. For example, when the thermal interface material 150 is viewed from a planar perspective (i.e., when the thermal interface material 150 is viewed from above the X-Y plane), the area of the top surface of the thermal interface material 150 can be equal to or less than the area of the top surface of the semiconductor package 20, and the thermal interface material 150 can not extend beyond the outer boundary of the semiconductor package 20. Thus, in this case, the thermal interface material 150 actually transfers heat generated from the semiconductor package 20 only to the portion of the housing 30 that vertically overlaps the semiconductor package 20.

[0078] Because the semiconductor device 1 according to an example embodiment of the inventive concept includes the conductive label 100, the semiconductor package 20 can be thermally coupled to the second housing portion 30b of the housing 30 that does not vertically overlap the semiconductor package 20 through the conductive label 100, and the thermal coupling between the semiconductor package 20 and the housing 30 can be enhanced. Thus, heat generated from the semiconductor package 20 can be transferred to the portion of the housing 30 that does not vertically overlap the semiconductor package 20, and can be rapidly discharged to the outside of the semiconductor device 1.

[0079] Figure 4 is a cross-sectional view of a first conductive portion 120a of the semiconductor device 1 taken along the line IV-IV' of Figure 3 Figure 3

[0080] Referring to FIGS. 1 and 2 together, Figure 3 and Figure 4 a first hole H1 (e.g., a plurality of first holes H1) can be formed in the first conductive portion 120a. More specifically, a plurality of first holes H1 in a mesh shape can be formed in the conductive layer 120 vertically overlapping the semiconductor package 20. The thermal interface material 150 can be disposed in the first holes H1 so that the first holes H1 are filled with the thermal interface material 150. In this embodiment, the side surface (e.g., a vertically extending surface) of the first conductive portion 120a of the conductive layer 120 is in contact with the thermal interface material 150 in addition to the side surface of the conductive label 100 including the side surface of the first conductive portion 120a of the conductive layer 120. These side surfaces of the conductive label 100 or the conductive layer 120 can be described as vertically extending surfaces.

[0081] In addition, a second hole (e.g., a plurality of second holes, not shown) can be formed in the first adhesive layer 110, which vertically overlaps the first hole H1 of the first conductive portion 120a. Since the thermal interface material 150 can be disposed in the first hole H1 and the second hole, a portion of the thermal interface material 150 can contact the top surface of the semiconductor package 20. Each combined first hole H1 and second hole can be generally described as a hole in the conductive label 100.

[0082] More specifically, the thermal interface material 150 can include a phase change material as described above, and thus the thermal interface material 150 can be disposed in the first hole H1 and the second hole. For example, the thermal interface material 150 can flow into the first hole H1 and the second hole while being in a liquid state. After the thermal interface material 150 flows into the first hole H1 and the second hole, the thermal interface material 150 can solidify into a solid state.

[0083] Since a portion of the thermal interface material 150 can contact the top surface of the semiconductor package 20, some heat generated from the semiconductor package 20 can be quickly transferred to the housing 30 overlapping the semiconductor package 20 in a plan view, and some heat can still be transferred to the area of the housing 30 located outside the semiconductor package 20 in the plan view. Thus, heat dissipation performance of the semiconductor device 1 can be improved. Figure 4 The hole structure shown can also be applied to other embodiments herein including a thermal interface material connected to a conductive layer, such as Figure 5 , Figure 6 and Figures 13 to 16 ​​described above.

[0084] Figure 5 is a cross-sectional view of a semiconductor device 2 according to an example embodiment of the inventive concept. Hereinafter, repeated descriptions between the semiconductor device 1 of Figure 3 and the semiconductor device 2 of Figure 5 will be omitted, and differences between them will be mainly described.

[0085] Referring to Figure 5 , the conductive tag 100 of the semiconductor device 2 according to an example embodiment of the inventive concept can further include a third adhesive layer 135 and an insulating layer 140.

[0086] In an example embodiment, the third adhesive layer 135 can attach the insulating layer 140 to the third conductive portion 120c. The third adhesive layer 135 can be disposed between the third conductive portion 120c and the insulating layer 140.

[0087] The insulating layer 140 can be a layer attached to a lower portion of the third conductive portion 120c by the third adhesive layer 135 and including an electrically insulating material. The insulating layer 140 can be attached to a portion of the conductive layer 120 that does not vertically overlap the semiconductor package 20.

[0088] In addition, the insulating layer 140 can be attached to a portion of the conductive layer 120 facing the system substrate 10. Accordingly, the insulating layer 140 can suppress occurrence of a short circuit by preventing contact between the third conductive portion 120c of the conductive layer 120 and the system substrate 10.

[0089] Figure 6 is a cross-sectional view of a semiconductor device 3 according to an example embodiment of the inventive concept. Hereinafter, repeated descriptions between the semiconductor device 2 of Figure 5 and the semiconductor device 3 of Figure 6 will be omitted, and differences between them will be mainly described.

[0090] Referring to Figure 6 , a top surface of the semiconductor chip 200 of the semiconductor device 3 can be at substantially the same level as a top surface of the molding layer 230. Terms such as "same," "equal," "planar," or "coplanar" as used herein encompass being exactly the same or nearly exactly the same including variations that can occur, for example, due to manufacturing processes. Unless otherwise indicated by context or other statement, the term "substantially" can be used herein to emphasize this meaning. The top surface of the semiconductor chip 200 can be exposed with respect to the molding layer 230 and can contact the conductive tag 100. Accordingly, since heat generated from the semiconductor chip 200 can be rapidly transferred to the conductive tag 100, heat dissipation performance of the semiconductor device 3 can be improved. Although Figure 6 is shownFigure 5 the insulating layer 140 and the third adhesive layer 135, but Figure 6 the package configuration in can be used for embodiments that do not include the insulating layer 140 or the third adhesive layer 135, or for other embodiments among the various embodiments described herein.

[0091] Figure 7 is a cross-sectional view of a semiconductor device 4 according to an example embodiment of the inventive concept.

[0092] Referring to Figure 7 , a semiconductor device 4 according to an example embodiment of the inventive concept can include a system substrate 10, a semiconductor package 20, a housing 30, and a conductive label 100.

[0093] In an example embodiment, a top surface of the semiconductor package 20 can not be covered by the housing 30 and can be exposed with respect to the housing 30, and the housing 30 can surround a side surface of the semiconductor package 20. In an example embodiment, an inner surface of the housing 30 can be located at a lower level than a top surface of the semiconductor package 20 (e.g., located at a lower height from a top surface of the system substrate 10 in a direction perpendicular to the top surface of the system substrate 10 than the top surface of the semiconductor package 20). In addition, an outer surface of the housing 30 can be at substantially the same level as the top surface of the semiconductor package 20. However, the inventive concept is not limited thereto.

[0094] In an example embodiment, a horizontal (e.g., in the X direction) length C2 of the conductive label 100 can be greater than a horizontal (e.g., in the X direction) length P2 of the semiconductor package 20. In addition, the conductive label 100 can be attached to a top surface of the semiconductor package 20 and an outer surface of the housing 30. Unlike the curved plate shape described in connection with Figures 3 to 6 , the conductive label 100 in this embodiment can have a flat plate shape.

[0095] More specifically, the conductive label 100 can include a first adhesive layer 110 and a conductive layer 120. In an example embodiment, the first adhesive layer 110 can contact a top surface of the semiconductor package 20 and an outer surface of the housing 30. In addition, the first adhesive layer 110 can attach the conductive layer 120 to the top surface of the semiconductor package 20 and the outer surface of the housing 30.

[0096] In an example embodiment, the conductive layer 120 can transfer heat generated from the semiconductor package 20 to the housing 30. The conductive layer 120 can be disposed on the first adhesive layer 110 and can be exposed to the outside of the semiconductor device 4. The conductive layer 120 can discharge heat transferred from the semiconductor package 20 to the outside of the semiconductor device 4.

[0097] The heat generated from the semiconductor package 20 can be transferred through the conductive layer 120 to a portion of the housing 30 that does not vertically overlap the semiconductor package 20. Accordingly, heat dissipation performance of the semiconductor device 4 can be improved.

[0098] In an example embodiment, a vent hole H2 can be formed in a portion of the conductive label 100 that vertically overlaps a horizontal separation space between the semiconductor package 20 and the housing 30 (e.g., a gap between the semiconductor package 20 and the housing 30). The vent hole H2 can be formed in a portion of the conductive label 100 that does not vertically overlap the semiconductor package 20 and the housing 30. Two or more vent holes H2 can be formed. The vent hole H2 can form a combined hole with the separation space between the semiconductor package 20 and the housing 30 (e.g., can vertically overlap the separation space). The vent hole H2 can have equal long sides (e.g., it can be circular, square, etc.), or an elongated shape. For example, a portion of the housing 30 can contact a side surface of the semiconductor package 20, while the portion is separated from the side surface of the semiconductor package 20 by one or more vent holes H2.

[0099] Air flowing into the semiconductor device 4 through the vent hole H2 of the conductive label 100 can circulate around the semiconductor package 20, and then be discharged from the semiconductor device 4 through the vent hole H2. Due to the thermal convection of the air, heat generated from the semiconductor package 20 can be quickly discharged from the semiconductor device 4. Accordingly, heat dissipation performance of the semiconductor device 4 can be improved.

[0100] Figure 8 is a cross-sectional view of a semiconductor device 5 according to an example embodiment of the inventive concept. Hereinafter, repeated descriptions of the semiconductor device 4 of Figure 7 and the semiconductor device 5 of Figure 8 will be omitted, and mainly differences between them will be described.

[0101] Referring to Figure 8 , the conductive label 100 of the semiconductor device 5 according to an example embodiment of the inventive concept can further include a second adhesive layer 130. The second adhesive layer 130 can attach the heat spreader 310 to the conductive layer 120.

[0102] The heat spreader 310 can be a heat dissipation member that receives heat generated from the semiconductor package 20 and discharges the heat from the semiconductor device 5. The heat spreader 310 can be attached to the conductive layer 120 by the second adhesive layer 130, and can be exposed to the outside of the semiconductor device 5.

[0103] In an example embodiment, the horizontal (e.g., in the X direction) length S1 of the heat spreader 310 can be greater than the horizontal (e.g., in the X direction) length P2 of the semiconductor package 20. For example, the horizontal (e.g., in the X direction) length S1 of the heat spreader 310 can be greater than the horizontal (e.g., in the X direction) length P2 of the semiconductor package 20 and less than the horizontal (e.g., in the X direction) length of the conductive layer 120. However, the inventive concept is not limited thereto, and the horizontal (e.g., in the X direction) length S1 of the heat spreader 310 can be greater than the horizontal (e.g., in the X direction) length P2 of the semiconductor package 20 and substantially equal to the horizontal (e.g., in the X direction) length of the conductive layer 120. Although only the horizontal X direction is illustrated in various embodiments herein, the same length relationships described herein in connection with the X direction can occur in the Y direction between the semiconductor package 20, the conductive layer 120 (and the heat spreader 310 in embodiments of the inventive concept). Figure 8

[0104] The heat spreader 310 can include a material having excellent thermal conductivity. In an example embodiment, the heat spreader 310 includes a metallic material having excellent thermal conductivity. For example, the heat spreader 310 can include a metallic material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), or nickel (Ni).

[0105] In addition, the heat spreader 310 can include a carbon-based material having excellent thermal conductivity. For example, the heat spreader 310 can include graphite, diamond, carbon fiber, etc. In addition, the heat spreader 310 can include a polymer material having excellent thermal conductivity. However, the heat spreader 310 is not limited to the above-described materials and can include a combination of the above-described materials or include other materials not mentioned above.

[0106] In an example embodiment, the heat spreader 310 can have a concave-convex structure to increase the surface area thereof exposed to the outside of the semiconductor device 5. Accordingly, the semiconductor device 5 can rapidly discharge heat generated from the semiconductor package 20 to the outside of the semiconductor device 5.

[0107] ​In addition, information of the semiconductor package 20 can be marked on the surface of the heat spreader 310. For example, the following pieces of information of the semiconductor package 20, such as a type of the semiconductor chip 200, a number of the semiconductor chip 200 (for example, whether there is a stack of the semiconductor chip 200 in the semiconductor package 20, or an array or a row of the semiconductor chip 200 arranged in a horizontal direction in one package or in a plurality of packages), a performance of the semiconductor chip 200, a name and / or a logo of a manufacturer thereof, a manufacturing date thereof, and a serial number thereof, can be marked on the surface of the heat spreader 310. For example, the pieces of information of the semiconductor package 20 can be marked on the surface of the heat spreader 310 by a laser etching method. However, the inventive concept is not limited thereto, and the pieces of information of the semiconductor package 20 can be marked on the surface of the heat spreader 310 by a pad printing method.

[0108] Figure 9 is a cross-sectional view of a semiconductor device 6 according to an example embodiment of the inventive concept. Hereinafter, repeated descriptions of the semiconductor device 4 of Figure 7 and the semiconductor device 6 of Figure 9 will be omitted, and mainly differences between them will be described.

[0109] Referring to Figure 9 , a bottom surface of the housing 30 can be located at a lower level than a top surface of the semiconductor package 20. In addition, the top surface of the semiconductor package 20 can be located at a higher level than a top surface of the housing 30. That is, the semiconductor package 20 can protrude from an outer surface of the housing 30.

[0110] The conductive label 100 can include a first adhesive layer 110a, a second adhesive layer 110b, a conductive layer 120, a third adhesive layer 137, and an insulating layer 140. In an example embodiment, the first adhesive layer 110a can contact a top surface of the semiconductor package 20. In addition, the first adhesive layer 110a can attach the conductive layer 120 to the top surface of the semiconductor package 20. The first adhesive layer 110a can vertically overlap the semiconductor package 20.

[0111] The second adhesive layer 110b can contact a surface of the conductive layer 120 that does not vertically overlap the semiconductor package 20 and an inner surface of the housing 30. The second adhesive layer 110b can attach the conductive layer 120 to the inner surface of the housing 30.

[0112] A horizontal (e.g., in the X direction) length C3 of the conductive layer 120 can be greater than a horizontal (e.g., in the X direction) length P3 of the semiconductor package 20. The conductive layer can be partially disposed above the semiconductor package 20 and partially disposed below the housing 30. Heat generated from the semiconductor package 20 can be transferred to the housing 30 through the conductive layer 120.

[0113] In an example embodiment, the conductive layer 120 can include a first conductive portion 120d, a second conductive portion 120e, and a third conductive portion 120f. The first conductive portion 120d can be a portion of the conductive layer 120 attached to a top surface of the semiconductor package 20 by the first adhesive layer 110a. Also, the first conductive portion 120d can be a portion of the conductive layer 120 vertically overlapped with the semiconductor package 20.

[0114] The second conductive portion 120e can be a portion of the conductive layer 120 bent downward from the first conductive portion 120d and covering a separation space between the semiconductor package 20 and the housing 30. As one example, the second conductive portion 120e can be inclined between the semiconductor package 20 and the housing 30.

[0115] The third conductive portion 120f can be a portion of the conductive layer 120 extending laterally from the second conductive portion 120e and attached to an inner surface of the housing 30 by the second adhesive layer 110b. Also, the third conductive portion 120f can be a portion of the conductive layer 120 not vertically overlapped with the semiconductor package 20.

[0116] In an example embodiment, a third adhesive layer 137 can attach the insulating layer 140 to a portion of the conductive layer 120 facing the system substrate 10. More specifically, the third adhesive layer 137 can contact the third conductive portion 120f and can attach the insulating layer 140 to the third conductive portion 120f.

[0117] In an example embodiment, the insulating layer 140 can be a layer for suppressing short circuit occurrence by preventing contact between the conductive layer 120 and the system substrate 10. The insulating layer 140 can be attached to the third conductive portion 120f by the third adhesive layer 137. Also, the insulating layer 140 can not be vertically overlapped with the semiconductor package 20 and can face the system substrate 10.

[0118] Figure 10 is a cross-sectional view of a semiconductor device 7 according to an example embodiment of the inventive concept. Also, Figure 11 is a top view of a region A of the semiconductor device 7 of Figure 10 Referring to

[0119] and Figure 10 Figure 11 ​The semiconductor device 7 of the present inventive concept can further include a heat spreader 310. The heat spreader 310 can be a heat dissipation member that receives heat generated from the semiconductor package 20 and discharges the heat to the outside of the semiconductor device 7.

[0120] In an example embodiment, the fourth adhesive layer 320 can contact a top surface of the first conductive portion 120d, and can attach the heat spreader 310 to the first conductive portion 120d. The heat spreader 310 can be attached to the first conductive portion 120d by the fourth adhesive layer 320, and can be exposed to the outside of the semiconductor device 7.

[0121] In an example embodiment, a horizontal (e.g., in the X direction) length S2 of the heat spreader 310 can be substantially equal to a horizontal (e.g., in the X direction) length P4 of the semiconductor package 20. However, the present inventive concept is not limited thereto, and the horizontal (e.g., in the X direction) length S2 of the heat spreader 310 can be less than the horizontal (e.g., in the X direction) length P4 of the semiconductor package 20.

[0122] The description of the material and shape of the heat spreader 310 is the same as that given with reference to the heat spreader 310 of the semiconductor device 7 of FIG. 1, and thus the description thereof will be omitted. Figure 8 The description of the material and shape of the heat spreader 310 is the same as that given with reference to the heat spreader 310 of the semiconductor device 7 of FIG. 1, and thus the description thereof will be omitted.

[0123] In an example embodiment, a vent hole H3 that allows air to flow into or out of the semiconductor device 7 can be formed in the conductive layer 120. The vent hole H3 is formed in a portion of the conductive layer 120 that vertically overlaps with the partition space between the semiconductor package 20 and the case 30. For example, the vent hole H3 can be formed in the second conductive portion 120e. Two or more vent holes H3 can be formed.

[0124] Air flowing into the semiconductor device 7 through the vent hole H3 of the conductive label 100 can circulate around the semiconductor package 20, and then be discharged from the semiconductor device 7 through the vent hole H3. Due to the thermal convection of the air, heat generated from the semiconductor package 20 can be quickly discharged from the semiconductor device 7. Accordingly, heat dissipation performance of the semiconductor device 7 can be improved.

[0125] Figure 12 is a cross-sectional view of a semiconductor device 8a according to an example embodiment of the present inventive concept.

[0126] Referring to Figure 12 The semiconductor device 8a according to an example embodiment of the present inventive concept can include a first system substrate 10a, a second system substrate 10b, a flexible substrate 11, a first semiconductor package 20a, a second semiconductor package 20b, a case 30, a first conductive label 100c, and a second conductive label 100d.

[0127] The first system substrate 10a can be a substrate on which the first semiconductor package 20a is mounted. The first system substrate 10a can include first substrate pads 101a that contact the respective first package connection terminals 250a of the first semiconductor package 20a. In an example embodiment, the first system substrate 10a can be a double-sided PCB that includes substrate pads on both surfaces thereof. However, the inventive concept is not limited thereto, and the first system substrate 10a can be a single-sided PCB that includes the first substrate pads 101a on only one surface thereof.

[0128] In an example embodiment, the first system substrate 10a can include a first mounting surface 105 and a second mounting surface 107 opposite the first mounting surface 105. The first mounting surface 105 can be a surface of the first system substrate 10a that faces the inner surface of the housing 30 closest to the first system substrate 10a, and the first semiconductor package 20a can be mounted on the first mounting surface 105. In addition, the second mounting surface 107 can be a surface of the first system substrate 10a that faces the second system substrate 10b, and a plurality of first electronic modules 410 can be mounted on the second mounting surface 107. For example, the first electronic modules 410 can include passive elements, active elements, etc.

[0129] Generally, heat emitted from the first semiconductor package 20a mounted on the first mounting surface 105 of the first system substrate 10a can be greater than heat emitted from the first electronic modules 410 mounted on the second mounting surface 107 of the first system substrate 10a. Accordingly, when the first semiconductor package 20a is mounted on the first mounting surface 105, heat emitted from the first semiconductor package 20a can be quickly dissipated from the semiconductor device 8a through the housing 30.

[0130] However, the inventive concept is not limited thereto, and when heat emitted from the first electronic modules 410 is greater than heat emitted from the first semiconductor package 20a, the first electronic modules 410 can be mounted on the first mounting surface 105 of the first system substrate 10a, and the first semiconductor package 20a can be mounted on the second mounting surface 107 of the first system substrate 10a.

[0131] The second system substrate 10b can be a substrate on which the second semiconductor package 20b is mounted. The second system substrate 10b can include second substrate pads 101b that contact the respective second package connection terminals 250b of the second semiconductor package 20b. In an example embodiment, the second system substrate 10b can be a double-sided PCB that includes substrate pads on both surfaces thereof. However, the inventive concept is not limited thereto, and the second system substrate 10b can be a single-sided PCB that includes the second substrate pads 101b on only one surface thereof.

[0132] In an example embodiment, the second system substrate 10b can include a third mounting surface 106 and a fourth mounting surface 108 opposite the third mounting surface 106. The third mounting surface 106 can be a surface of the second system substrate 10b facing the inner surface of the second system substrate 10b closest to the housing 30, and the second semiconductor package 20b can be mounted on the third mounting surface 106. Also, the fourth mounting surface 108 can be a surface of the second system substrate 10b facing the first system substrate 10a, and a plurality of second electronic modules 420 can be mounted on the fourth mounting surface 108. For example, the second electronic modules 420 can include passive elements, active elements, etc. Also, the second mounting surface 107 of the first system substrate 10a and the fourth mounting surface 108 of the second system substrate 10b can face each other.

[0133] Generally, heat emitted from the second semiconductor package 20b mounted on the third mounting surface 106 of the second system substrate 10b can be greater than heat emitted from the second electronic modules 420 mounted on the fourth mounting surface 108 of the second system substrate 10b. Accordingly, when the second semiconductor package 20b is mounted on the third mounting surface 106, heat emitted from the second semiconductor package 20b can be quickly discharged from the semiconductor device 8a through the housing 30.

[0134] However, the inventive concept is not limited thereto, and when heat emitted from the second electronic modules 420 is greater than heat emitted from the second semiconductor package 20b, the second electronic modules 420 can be mounted on the third mounting surface 106 of the second system substrate 10b, and the second semiconductor package 20b can be mounted on the fourth mounting surface 108 of the second system substrate 10b.

[0135] In an example embodiment, the flexible substrate 11 can be a substrate physically and / or electrically connecting the first system substrate 10a to the second system substrate 10b. Also, the flexible substrate 11 can be a substrate having flexibility.

[0136] In an example embodiment, the flexible substrate 11 can have a thickness of about 300 µm or less to secure its flexibility. However, the inventive concept is not limited thereto, and the flexible substrate 11 can have various thicknesses. Also, the flexible substrate 11 can have a curved shape to connect the first system substrate 10a to the second system substrate 10b in a limited internal space provided by the housing 30.

[0137] In an example embodiment, the flexible substrate 11 can include at least one of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyether ether ketone (PEEK), and prepreg.

[0138] The housing 30 can surround the first system substrate 10a, the second system substrate 10b, the flexible substrate 11, the first semiconductor package 20a, and the second semiconductor package 20b to protect the first system substrate 10a, the second system substrate 10b, the flexible substrate 11, the first semiconductor package 20a, and the second semiconductor package 20b from external impact.

[0139] In an example embodiment, the housing 30 can be a case for packaging the first system substrate 10a, the second system substrate 10b, the flexible substrate 11, the first semiconductor package 20a, and the second semiconductor package 20b. However, the inventive concept is not limited thereto, and the housing 30 can be a heat dissipation member for dissipating heat generated from the first semiconductor package 20a and the second semiconductor package 20b. Although not shown, the housing 30 can have an opening through which the first semiconductor package 20a and the second semiconductor package 20b communicate to be electrically connected to an external device or system.

[0140] In an example embodiment, the housing 30 can include a material having excellent thermal conductivity to rapidly dissipate heat generated from the first semiconductor package 20a and the second semiconductor package 20b to the outside of the semiconductor device 8a. For example, the housing 30 can include a metallic material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), or nickel (Ni). However, the inventive concept is not limited thereto, and the housing 30 can include a carbon-based material having excellent thermal conductivity, for example, graphite, diamond, or carbon fiber.

[0141] The first semiconductor package 20a can be a package including a first semiconductor chip (not shown). For example, the first semiconductor package 20a can include two or more first semiconductor chips. The first semiconductor chips included in the first semiconductor package 20a can have the same type or different types. In addition, the first semiconductor package 20a can include first package connection terminals 250a that contact the first system substrate 10a. Furthermore, the first semiconductor package 20a can have a first length P5 in a horizontal direction (for example, an X direction).

[0142] In an example embodiment, the first semiconductor chip can include a first semiconductor device layer, and a plurality of various types of individual devices can be formed in the first semiconductor device layer. The first semiconductor device layer can be connected to the first system substrate 10a via the first package connection terminals 250a.

[0143] The second semiconductor package 20b can be a package including a second semiconductor chip (not shown). For example, the second semiconductor package 20b can include two or more second semiconductor chips. The second semiconductor chips included in the second semiconductor package 20b can have the same type or different types. Also, the second semiconductor package 20b can include second package connection terminals 250b that contact the second system substrate 10b. Further, the second semiconductor package 20b can have a second length P6 in a horizontal direction (e.g., the X direction).

[0144] In an example embodiment, the first semiconductor package 20a and the second semiconductor package 20b can be electrically connected to each other and can operate as one system. More specifically, the first semiconductor package 20a and the second semiconductor package 20b can be electrically connected to each other via the first system substrate 10a, the second system substrate 10b, and the flexible substrate 11, and thus operate as one system.

[0145] The first semiconductor chip included in the first semiconductor package 20a can have a different type from the second semiconductor chip included in the second semiconductor package 20b. For example, the first semiconductor chip can include a memory semiconductor chip. For example, the first semiconductor chip can include a volatile memory semiconductor chip such as a DRAM or an SRAM, and can include a non-volatile memory semiconductor chip such as a PRAM, an MRAM, a FeRAM, or an RRAM.

[0146] Also, the second semiconductor chip included in the second semiconductor package 20b can include a logic semiconductor chip. The second semiconductor chip can include, for example, a logic semiconductor chip such as a CPU, an MPU, a GPU, or an AP.

[0147] In an example embodiment, the first conductive tag 100c can be disposed between the first semiconductor package 20a and the housing 30. Also, a horizontal (e.g., in the X direction) length C4 of the first conductive tag 100c can be greater than a first length P5 of the first semiconductor package 20a in the horizontal direction (e.g., the X direction). Thus, the first conductive tag 100c can even be attached to an inner surface of the housing 30 that does not vertically overlap the first semiconductor package 20a. The length C4 of the first conductive tag 100c can be greater than 1.1 times the first length P5 and less than a length of the semiconductor device 8a in the X direction. In some embodiments, the length C4 of the first conductive tag 100c is greater than 1.2 times the first length P5 and less than 5 times the first length P5.

[0148] The first conductive label 100c can include a first adhesive layer 110a, a first conductive layer 123, and a second adhesive layer 130a. The first adhesive layer 110a can contact a top surface of the first semiconductor package 20a and can vertically overlap the first semiconductor package 20a. The first adhesive layer 110a can attach the first conductive layer 123 to the top surface (e.g., a passive surface) of the first semiconductor package 20a.

[0149] The first conductive layer 123 can be attached to the top surface of the first semiconductor package 20a by the first adhesive layer 110a. In a horizontal direction, a length C4 of the first conductive layer 123 (e.g., can be the same as a length of the first conductive label 100c) can be greater than a first length P5 of the first semiconductor package 20a.

[0150] In an example embodiment, the first conductive layer 123 can be disposed between the first adhesive layer 110a and the second adhesive layer 130a. Heat generated from the first semiconductor package 20a can be transferred upwardly through the first conductive layer 123 to an inner surface of the housing 30, a portion of which does not vertically overlap the first semiconductor package 20a.

[0151] The second adhesive layer 130a can be disposed between the housing 30 and the first conductive layer 123. The second adhesive layer 130a can attach the first conductive layer 123 to the inner surface of the housing 30.

[0152] In an example embodiment, the second conductive label 100d can be disposed between the second semiconductor package 20b and the housing 30. Additionally, a fourth length C5 of the second conductive label 100d in a horizontal direction (e.g., X direction) can be greater than a second length P6 of the second semiconductor package 20b in the horizontal direction (e.g., X direction). Thus, the second conductive label 100d can even be attached to an inner surface of the housing 30 that does not vertically overlap the second semiconductor package 20b. In the X direction, the length C5 of the second conductive label 100d can be greater than 1.1 times the second length P6 and less than a length of the semiconductor device 8a. In some embodiments, in the X direction, the length C5 of the second conductive label 100d is greater than 1.2 times the second length P6 and less than 5 times the second length P6. A portion of the second conductive label 100d can also extend vertically to connect to a sidewall of the housing 30, as shown in Figure 12

[0153] The second conductive label 100d can include a third adhesive layer 110b, a second conductive layer 125, and a fourth adhesive layer 130b. The third adhesive layer 110b can contact a top surface of the second semiconductor package 20b and can vertically overlap the second semiconductor package 20b. The third adhesive layer 110b can attach the second conductive layer 125 to the top surface of the second semiconductor package 20b.​

[0154] The second conductive layer 125 can be attached to a top surface (e.g., a passive surface) of the second semiconductor package 20b through the third adhesive layer 110b. In a horizontal direction, a length C5 of the second conductive layer 125 can be greater than a second length P6 of the second semiconductor package 20b.

[0155] In an example embodiment, the second conductive layer 125 can be disposed between the third adhesive layer 110b and the fourth adhesive layer 130b. Heat generated from the second semiconductor package 20b can be transferred upward to an inner surface of the housing 30, a portion of which does not vertically overlap the second semiconductor package 20b, through the second conductive layer 125.

[0156] The fourth adhesive layer 130b can be disposed between the housing 30 and the second conductive layer 125. The fourth adhesive layer 130b can attach the second conductive layer 125 to the inner surface of the housing 30.

[0157] Because the semiconductor device 8a according to an example embodiment of the inventive concept can include the first conductive label 100c between the first semiconductor package 20a and the housing 30 and the second conductive label 100d between the second semiconductor package 20b and the housing 30, heat emitted from the first semiconductor package 20a and the second semiconductor package 20b can be quickly transferred to the housing 30. Accordingly, heat dissipation performance of the semiconductor device 8a can be improved.

[0158] For ease of description, spatially relative terms, such as "top", "bottom", "lower", "below", "bottom", "lower", "upper", "above", "upper", and the like, can be used herein for describing one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0159] Figure 13 is a cross-sectional view of a semiconductor device 8b according to an example embodiment of the inventive concept. Hereinafter, repeated descriptions between the semiconductor device 8a of Figure 12 and the semiconductor device 8b of Figure 13 will be omitted, and mainly differences between them will be described.

[0160] Referring to Figure 13The thermal interface material 150 can be disposed over at least one of the first semiconductor package 20a and the second semiconductor package 20b. For example, as shown in FIG. 10, the thermal interface material 150 can be disposed over the first semiconductor package 20a, and the thermal interface material 150 can not be disposed over the second semiconductor package 20b. However, the inventive concept is not limited thereto, and the thermal interface material 150 can be disposed over both the first semiconductor package 20a and the second semiconductor package 20b. Figure 13 The thermal interface material 150 can be disposed over at least one of the first semiconductor package 20a and the second semiconductor package 20b. For example, as shown in FIG. 10, the thermal interface material 150 can be disposed over the first semiconductor package 20a, and the thermal interface material 150 can not be disposed over the second semiconductor package 20b. However, the inventive concept is not limited thereto, and the thermal interface material 150 can be disposed over both the first semiconductor package 20a and the second semiconductor package 20b.

[0161] In an example embodiment, the thermal interface material 150 can be disposed between the first conductive layer 123 and the housing 30. The description of the thermal interface material 150 is the same as that given with reference to Figure 3 the first semiconductor package 20a can be the same as the semiconductor package 20 discussed previously, and thus a detailed description thereof will be omitted. Figures 13 to 16 the first semiconductor package 20a can be the same as the semiconductor package 20 discussed previously, and thus a detailed description thereof will be omitted.

[0162] In an example embodiment, the first conductive layer 123 can include a first conductive portion 123a, a second conductive portion 123b, and a third conductive portion 123c. The first conductive portion 123a can be a portion of the first conductive layer 123 that vertically overlaps the first semiconductor package 20a and is disposed between the first adhesive layer 110a and the thermal interface material 150.

[0163] The second conductive portion 123b can be a portion of the first conductive layer 123 that is curved upward from the first conductive portion 123a and surrounds a side surface of the thermal interface material 150. In addition, the third conductive portion 123c can be a portion of the first conductive layer 123 that is curved laterally from the second conductive portion 123b and is attached to an inner surface of the housing 30 that does not vertically overlap the first semiconductor package 20a by the second adhesive layer 130a.

[0164] In an example embodiment, the first conductive label 100c can optionally include a first insulating layer 143 under the third conductive portion 123c. More specifically, the first conductive label 100c can further include a fifth adhesive layer 141 in contact with one surface of the third conductive portion 123c, and the first insulating layer 143 attached to the third conductive portion 123c by the fifth adhesive layer 141. The first insulating layer 143 can be attached to the third conductive portion 123c to face the first mounting surface 105 of the first system board 10a.

[0165] In an example embodiment, the second conductive label 100d can optionally include a second insulating layer 147 positioned above the second conductive layer 125. More specifically, the second conductive label 100d can further include a sixth adhesive layer 145 in contact with the second conductive layer 125, and the second insulating layer 147 attached to the second conductive layer 125 by the sixth adhesive layer 145. The second insulating layer 147 can be attached to the second conductive layer 125 to face the third mounting surface 106 of the second system substrate 10b.

[0166] In an example embodiment, the semiconductor device 8b can further include a third conductive label 100e. The third conductive label 100e can include a seventh adhesive layer 171, a third conductive layer 173, and an eighth adhesive layer 175. The third conductive label 100e can be attached to at least one of the first electronic module 410 and the second electronic module 420, which have been described above.

[0167] In an example embodiment, the seventh adhesive layer 171 can contact a top surface of the first electronic module 410. The seventh adhesive layer 171 can attach the third conductive layer 173 to the top surface of the first electronic module 410.

[0168] The third conductive layer 173 can transfer heat generated from the first electronic module 410 to the housing 30. For example, the third conductive layer 173 can include a fourth conductive portion 173a extending in a horizontal direction, and a fifth conductive portion 173b vertically bent from the fourth conductive portion 173a and attached to an inner surface (e.g., an inner side surface) of the housing 30. More specifically, the fifth conductive portion 173b can be attached to the inner surface of the housing 30 by the eighth adhesive layer 175.

[0169] In an example embodiment, the third conductive label 100e can further include a third insulating layer 177 and a fourth insulating layer 179. The third insulating layer 177 can be attached to one surface of the third conductive layer 173 facing the first system substrate 10a by a ninth adhesive layer 181. The third insulating layer 177 can suppress a short defect due to contact between the third conductive layer 173 and the first system substrate 10a.

[0170] In addition, the fourth insulating layer 179 can be attached to one surface of the third conductive layer 173 facing the second system substrate 10b by a tenth adhesive layer 183. The fourth insulating layer 179 can suppress a short defect due to contact between the third conductive layer 173 and the second system substrate 10b.

[0171] Figure 14 is a cross-sectional view of a semiconductor device 8c according to an example embodiment of the inventive concept. Hereinafter, the semiconductor device 8b of Figure 13 will be omitted Figure 14The repeated descriptions of the semiconductor device 8c will be omitted, and only the differences between them will be mainly described.

[0172] Referring to Figure 14 The first conductive tag 100c and the second conductive tag 100d can be connected to each other and attached to the inner surface of the housing 30. In other words, the first conductive tag 100c and the second conductive tag 100d can be attached to the inner surface of the housing 30 while being integrated.

[0173] In an example embodiment, the second adhesive layer 130a, the first conductive layer 123, the fifth adhesive layer 141, and the first insulating layer 143 of the first conductive tag 100c can be connected to the fourth adhesive layer 130b, the second conductive layer 125, the sixth adhesive layer 145, and the second insulating layer 147 of the second conductive tag 100d, respectively, and thus be integrated.

[0174] In an example embodiment, the first conductive tag 100c and the second conductive tag 100d can include the first insulating layer 143 and the second insulating layer 147, respectively, to prevent an electrical short from occurring due to contact between each of the first conductive layer 123 and the second conductive layer 125 and each of the first system substrate 10a, the second system substrate 10b, and the flexible substrate 11.

[0175] However, the inventive concept is not limited thereto, and the fifth adhesive layer 141 and the first insulating layer 143 can be omitted from the first conductive tag 100c and the sixth adhesive layer 145 and the second insulating layer 147 can be omitted from the second conductive tag 100d.

[0176] In an example embodiment, the third conductive layer 173 of the third conductive tag 100e can be connected to the first conductive layer 123 of the first conductive tag 100c and attached to the inner surface of the housing 30.

[0177] More specifically, the eighth adhesive layer 175 and the third conductive layer 173 of the third conductive tag 100e can be connected to the second adhesive layer 130a and the first conductive layer 123 of the first conductive tag 100c, respectively, and thus be integrated.

[0178] In addition, the third conductive layer 173 of the third conductive tag 100e can be connected to the second conductive layer 125 of the second conductive tag 100d and attached to the inner surface of the housing 30.

[0179] More specifically, the eighth adhesive layer 175 and the third conductive layer 173 of the third conductive tag 100e can be connected to the fourth adhesive layer 130b and the second conductive layer 125 of the second conductive tag 100d, respectively, and thus be integrated.

[0180] In an example embodiment, the third conductive label 100e can be connected to at least one of the first conductive label 100c and the second conductive label 100d. As Figure 14 illustrated, the third conductive label 100e can be connected to both the first conductive label 100c and the second conductive label 100d. However, the inventive concept is not limited thereto, and the third conductive label 100e can be connected to only one of the first conductive label 100c and the second conductive label 100d.

[0181] In an example embodiment, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e can be connected to each other and attached to the entire inner surface of the housing 30. For example, the inner surface of the housing 30 can not be exposed by the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e. Although the lengths of the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e in the Y direction are not illustrated, in one embodiment, these lengths can extend in the Y direction from one side surface of the semiconductor device 8c to the opposite side surface. However, in other embodiments, the lengths of these components in the Y direction can be, for example, the same length or longer than the length of one or both of the semiconductor packages 20a or 20b in the Y direction. This same length or length option can apply to other embodiments described herein.

[0182] With the above-described structure of the semiconductor device 8c of the inventive concept, heat generated due to the operation of at least one of the first semiconductor package 20a, the second semiconductor package 20b, and the first electronic module 410 can be transferred to the inner surface of the housing 30. Accordingly, heat dissipation performance of the semiconductor device 8c of the inventive concept can be improved.

[0183] Figure 15 is a cross-sectional view of a semiconductor device 8d according to an example embodiment of the inventive concept. Hereinafter, repeated descriptions of the semiconductor device 8b of Figure 13 and the semiconductor device 8d of Figure 15 will be omitted, and mainly the differences between them will be described.

[0184] Referring to Figure 15 , a first heat transfer hole H4 through which the first conductive label 100c can pass can be formed in the housing 30. In addition, a second heat transfer hole H5 through which the second conductive label 100d can pass can be formed in the housing 30.

[0185] In an example embodiment, as described above, the second adhesive layer 130a of the first conductive label 100c can contact the inner surface of the housing 30. In addition, the second adhesive layer 130a can pass through the first heat transfer hole H4 and thus contact the outer surface of the housing 30.

[0186] In addition, the first conductive layer 123 can pass through the first heat transfer hole H4 of the case 30 through the second adhesive layer 130a, and extend to be attached to the outer surface of the case 30 through the second adhesive layer 130a, as described above. The first heat transfer hole H4 can have edges of equal length (for example, it can be circular, square, etc.) or can be an elongated shape.

[0187] In an example embodiment, the fourth adhesive layer 130b of the second conductive label 100d can contact the inner surface of the case 30, as described above. In addition, the fourth adhesive layer 130b can pass through the second heat transfer hole H5 and thus contact the outer surface of the case 30.

[0188] In addition, the second conductive layer 125 can pass through the second heat transfer hole H5 of the case 30 through the fourth adhesive layer 130b, so that it can be attached to the outer surface of the case 30 through the fourth adhesive layer 130b, as described above.

[0189] In an example embodiment, the first conductive label 100c and the second conductive label 100d can partially cover the outer surface of the case 30 and partially expose the outer surface of the case 30. However, the inventive concept is not limited thereto, and the first conductive label 100c and the second conductive label 100d can cover the entire outer surface of the case 30.

[0190] In an example embodiment, a vent hole H6 can be formed in a portion of the case 30 to which the first conductive label 100c and the second conductive label 100d are not attached. Air flowing into the semiconductor device 8d through the vent hole H6 can circulate around the first semiconductor package 20a and the second semiconductor package 20b, and then be discharged to the outside of the semiconductor device 8d through the vent hole H6. Due to the thermal convection of the air, heat generated from the first semiconductor package 20a and the second semiconductor package 20b can be quickly discharged from the semiconductor device 8d. Accordingly, heat dissipation performance of the semiconductor device 8d can be improved.

[0191] Figure 16 is a cross-sectional view of a semiconductor device 8e according to an example embodiment of the inventive concept. Hereinafter, repetitive descriptions of the semiconductor device 8d of Figure 15 and the semiconductor device 8e of Figure 16 will be omitted, and mainly the differences between them will be described.

[0192] Referring to Figure 16The first conductive label 100c, the second conductive label 100d, and the third conductive label 100e can be connected to each other and attached to the inner surface of the housing 30. For example, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e can be attached to the inner surface of the housing 30 while being integrated. For example, the inner surface of the housing 30 can not be exposed by the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e.

[0193] In addition, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e can be connected to each other and attached to the outer surface of the housing 30. For example, the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e can be attached to the outer surface of the housing 30 while being integrated. For example, the outer surface of the housing 30 can not be exposed by the first conductive label 100c, the second conductive label 100d, and the third conductive label 100e.

[0194] With the above-described structure of the semiconductor device 8e according to the present inventive concept, heat generated due to the operation of at least one of the first semiconductor package 20a, the second semiconductor package 20b, and the first electronic module 410 can be transferred to both the inner surface and the outer surface of the housing 30. Accordingly, heat dissipation performance of the semiconductor device 8e can be improved.

[0195] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a conductive label that is flexible and disposed on the semiconductor package, the conductive label including: a first adhesive layer in contact with the semiconductor package; a thermally conductive layer attached to the semiconductor package through the first adhesive layer and having a second length in the first horizontal direction greater than the first length of the semiconductor package; and a second adhesive layer in contact with a portion of a surface of the thermally conductive layer among surfaces of the thermally conductive layer, wherein the portion is less than an entire surface of the thermally conductive layer, the portion not vertically overlapping the semiconductor package; a thermal interface material disposed on the thermally conductive layer to vertically overlap the semiconductor package; and a housing including: a first housing portion vertically overlapping the semiconductor package and in contact with the thermal interface material; and a second housing portion to which the thermally conductive layer is attached through the second adhesive layer.

2. The semiconductor device according to claim 1, wherein the thermally conductive layer includes: a first thermally conductive portion extending horizontally and vertically overlapping the semiconductor package and disposed between the first adhesive layer and the thermal interface material; a second thermally conductive portion curved upward from the first thermally conductive portion and surrounding a side surface of the thermal interface material; and a third thermally conductive portion not vertically overlapping the semiconductor package, the third thermally conductive portion curved from the second thermally conductive portion to extend horizontally and attached to the second housing portion through the second adhesive layer.

3. The semiconductor device according to claim 2, wherein the thermal interface material is disposed between the first thermally conductive portion and the first housing portion.

4. The semiconductor device according to claim 2, wherein the conductive label further includes: a third adhesive layer in contact with a bottom surface of the third thermally conductive portion; and an insulating layer attached to the third thermally conductive portion to face the system substrate through the third adhesive layer.

5. The semiconductor device according to claim 2, wherein the first thermally conductive portion includes a plurality of first holes filled with a mesh of the thermal interface material.

6. The semiconductor device according to claim 5, wherein the first adhesive layer includes second holes vertically overlapping the first holes, and the thermal interface material is disposed in the second holes and contacts a top surface of the semiconductor package. 7.The semiconductor device of claim 1, further comprising: a second system substrate; a second semiconductor package mounted on the second system substrate and having a third length in the first horizontal direction; and ​ a second conductive label between the second semiconductor package and the housing, the second conductive label including: a third adhesive layer in contact with the second semiconductor package; a second thermally conductive layer disposed on the third adhesive layer and having a fourth length in the first horizontal direction that is greater than the third length of the second semiconductor package in the first horizontal direction; and a fourth adhesive layer disposed on the second thermally conductive layer to contact the housing and attach the second thermally conductive layer to an inner surface of the housing.

8. A semiconductor device, comprising: a system substrate; a semiconductor package mounted on the system substrate and having a first length in a first horizontal direction; a housing disposed such that a top surface of the semiconductor package is not covered by the housing and the housing surrounds a side surface of the semiconductor package, an outer surface of the housing being at substantially the same horizontal level as the top surface of the semiconductor package; and a conductive label connecting the semiconductor package to the housing, the conductive label including: a first adhesive layer in contact with the semiconductor package; and a thermally conductive layer disposed on the first adhesive layer and having a second length in the first horizontal direction that is greater than the first length of the semiconductor package. the thermally conductive layer is attached to the top surface of the semiconductor package and an outer surface of the housing through the first adhesive layer. the conductive label includes a vent hole penetrating the first adhesive layer and the thermally conductive layer, and 9. The semiconductor device according to claim 8, wherein the vent hole vertically overlaps a separation space between the semiconductor package and the housing.

10. The semiconductor device according to claim 9, wherein an inner surface of the housing is at a lower horizontal level than the top surface of the semiconductor package, the conductive label further includes a second adhesive layer attached to a portion of a top surface of the thermally conductive layer that does not vertically overlap the semiconductor package, and 11. The semiconductor device according to claim 8, wherein the thermally conductive layer includes: a first thermally conductive portion that vertically overlaps the semiconductor package and is attached to the top surface of the semiconductor package through the first adhesive layer; a second thermally conductive portion that is bent downward from the first thermally conductive portion and covers a separation space between the semiconductor package and the housing; and a third thermally conductive portion that is bent laterally from the second thermally conductive portion and is attached to a portion of an inner surface of the housing that does not vertically overlap the semiconductor package through the second adhesive layer. the second thermally conductive portion includes a vent hole penetrating the thermally conductive layer. the conductive label further includes:

12. The semiconductor device according to claim 11, wherein a third adhesive layer in contact with a bottom surface of the third thermally conductive portion; and 13. The semiconductor device according to claim 11, wherein an insulating layer attached to the third thermally conductive portion through the third adhesive layer and facing the system substrate.

14. A semiconductor device, comprising: a first system substrate; a second system substrate vertically separated from the first system substrate; ​ ​ a flexible substrate connecting the first system substrate to the second system substrate; a housing surrounding the first system substrate, the second system substrate, and the flexible substrate; a first semiconductor package mounted on the first system substrate and having a first length in a first horizontal direction; a second semiconductor package mounted on the second system substrate and having a second length in the first horizontal direction; a first conductive label between the first semiconductor package and the housing, the first conductive label including a first adhesive layer in contact with the first semiconductor package, a first thermally conductive layer disposed on the first adhesive layer and having a third length in the first horizontal direction greater than the first length of the first semiconductor package in the first horizontal direction, and a second adhesive layer disposed on the first thermally conductive layer; a thermal interface material between the first thermally conductive layer and an inner surface of the housing, the second adhesive layer in contact with a portion of a surface of the first thermally conductive layer among surfaces of the first thermally conductive layer, wherein the portion is less than an entire surface of the first thermally conductive layer, the portion not vertically overlapping the first semiconductor package, and a second conductive label between the second semiconductor package and the housing, the second conductive label including a third adhesive layer in contact with the second semiconductor package, a second thermally conductive layer disposed on the third adhesive layer and having a fourth length in the first horizontal direction greater than the second length of the second semiconductor package in the first horizontal direction, and a fourth adhesive layer disposed on the second thermally conductive layer to contact the housing and attach the second thermally conductive layer to the inner surface of the housing.

15. The semiconductor device according to claim 14, wherein the first thermally conductive layer includes: a first thermally conductive portion vertically overlapping the first semiconductor package and disposed between the first adhesive layer and the thermal interface material; a second thermally conductive portion curved upward from the first thermally conductive portion and surrounding a side surface of the thermal interface material; and a third thermally conductive portion curved laterally from the second thermally conductive portion and attached to a portion of the inner surface of the housing not vertically overlapping the first semiconductor package through the second adhesive layer.

16. The semiconductor device of claim 14, further comprising: a first electronic module mounted on the first system substrate; and a third conductive label connecting the first electronic module to the housing, the third conductive label including a fifth adhesive layer in contact with a top surface of the first electronic module and the inner surface of the housing. ​ a third thermally conductive layer arranged on the fifth adhesive layer and attached to the top surface of the first electronic module and the inner surface of the housing by the fifth adhesive layer.

17. The semiconductor device according to claim 16, wherein The first system substrate includes: a first mounting surface facing the inner surface of the housing; and a second mounting surface opposite the first mounting surface, and wherein, the first semiconductor package is mounted on the first mounting surface, and the first electronic module is mounted on the second mounting surface.

18. The semiconductor device according to claim 14, wherein The housing includes a heat transfer aperture, and at least one of the first conductive label and the second conductive label extends to an outer surface of the housing through the heat transfer aperture of the housing.

19. The semiconductor device according to claim 18, wherein a venting aperture that penetrates the housing is arranged in a portion of the housing to which the first conductive label and the second conductive label are not attached.

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