Semiconductor memory device and method for manufacturing the semiconductor memory device

Abstract

This invention provides a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device includes a stacked structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region, and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures penetrating the stacked structure, a first vertical structure on the cell array region, and a second vertical structure on the extension region. Each vertical structure includes a channel layer and a tunneling insulating layer, a charge storage layer, and a barrier insulating layer sequentially stacked on the sidewalls of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to the top surface of the substrate, with horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along the sidewalls of the horizontal electrodes and the sidewalls of the horizontal insulating layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices, and more specifically, to three-dimensional (3D) non-volatile memory devices and methods for manufacturing such 3D non-volatile memory devices. Background Technology

[0002] Semiconductor devices have become highly integrated to provide improved performance and generally lower manufacturing costs. The integration density of a semiconductor device directly impacts its cost, leading to a typically high demand for highly integrated devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be determined by the area per unit memory cell. Therefore, the integration density of a typical 2D or planar semiconductor device can be influenced by the technology used to form intricate patterns. However, because the equipment used to form intricate patterns can be expensive, the integration density of 2D semiconductor devices continues to increase, but is limited. Three-dimensional (3D) semiconductor memory devices, incorporating memory cells arranged in three dimensions, have been developed to overcome these limitations. Summary of the Invention

[0003] Embodiments of the present invention can provide a semiconductor memory device with improved reliability and a method for manufacturing the semiconductor memory device.

[0004] In some embodiments, a semiconductor memory device may include a stacked structure comprising horizontal electrodes and horizontal insulating layers sequentially stacked on a substrate including a cell array region and an extension region. The semiconductor memory device may also include vertical structures penetrating the stacked structure, a first vertical structure on the cell array region and a second vertical structure on the extension region. Each vertical structure may include a channel layer and a tunneling insulating layer, a charge storage layer, and a barrier insulating layer sequentially stacked on the sidewalls of the channel layer. The charge storage layer of the first vertical structure may include charge storage patterns spaced apart from each other in a direction perpendicular to the top surface of the substrate, with horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure may extend along the sidewalls of the horizontal electrodes and the sidewalls of the horizontal insulating layer.

[0005] In some embodiments, a semiconductor memory device may include a stacked structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region, and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may also include vertical structures penetrating the stacked structure. Each vertical structure may include a channel layer and a tunneling insulating layer, a charge storage layer, and a barrier insulating layer sequentially stacked on the sidewalls of the channel layer. Each horizontal electrode may include a cell portion on the cell array region and an extension portion on the extension region. The top surface of the extension portion may be located at a height higher than the top surface of the cell portion relative to the top surface of the substrate, which serves as a reference, and the bottom surface of the extension portion may be located at a height lower than the bottom surface of the cell portion relative to the top surface of the substrate, which serves as a reference.

[0006] In some embodiments, a semiconductor memory device may include: stacked structures, each stacked structure including horizontal electrodes extending in a first direction and sequentially stacked on a substrate including a cell array region and an extended region, and horizontal insulating layers between the horizontal electrodes, the stacked structures being spaced apart from each other in a second direction perpendicular to the first direction; a separation pattern between the stacked structures; vertical structures penetrating the stacked structures, the vertical structures including a first vertical structure on the cell array region and a second vertical structure on the extended region; contacts connected to the upper portion of the vertical structures; and bit lines on the contacts. Each vertical structure may include: a fill layer; a channel layer on the sidewalls of the fill layer; a tunneling insulating layer, a charge storage layer, and a barrier insulating layer sequentially stacked on the sidewalls of the channel layer; and a pad pattern on the top surface of the channel layer. The charge storage layer of the first vertical structure may include charge storage patterns, the charge storage patterns being spaced apart from each other in a direction perpendicular to the top surface of the substrate and with horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure may extend along the sidewalls of the horizontal electrodes and the sidewalls of the horizontal insulating layer.

[0007] In some embodiments, a method of manufacturing a semiconductor memory device may include: forming a molded structure by stacking a first layer and a second layer in an alternating sequence on a substrate including a cell array region and an extension region; forming vertical structures penetrating the molded structure, wherein a first vertical structure is on the cell array region and a second vertical structure is on the extension region, each vertical structure including a channel layer and a tunneling insulating layer, a charge storage layer, and a barrier insulating layer sequentially stacked on the sidewalls of the channel layer. The method further includes: forming a first trench penetrating the molded structure and extending in a first direction parallel to the top surface of the substrate; removing a first layer from the cell array region through the first trench to form a gap region; etching the charge storage layer of the first vertical structure in the vertical structure through the gap region to divide each charge storage layer into a charge storage pattern; forming a separation pattern in the first trench and the gap region; forming a second trench extending from the cell array region to the extension region and penetrating the molded structure; and replacing the second layer with a horizontal electrode through the second trench. Attached Figure Description

[0008] The inventive concept will become more apparent from the accompanying drawings and detailed description.

[0009] Figure 1 This is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the concept of the present invention.

[0010] Figure 2 This is a top view illustrating some embodiments of a semiconductor memory device according to the present invention.

[0011] Figure 3A and Figure 3B They are along Figure 2 The cross-sectional views taken along lines I-I' and II-II' illustrate semiconductor memory devices according to some embodiments of the concept of the present invention.

[0012] Figure 4 yes Figure 3B A magnified view of region 'R'.

[0013] Figure 5 yes Figure 2 An enlarged view of region 'S' to show the hierarchy of one of the horizontal electrodes.

[0014] Figure 6 , Figure 8 and Figure 15 This is a top view illustrating a method for manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention.

[0015] Figure 7A , Figure 9A , Figure 10A , Figure 12A , Figure 14A and Figure 16A It is along Figure 6 , Figure 8 and Figure 15 A sectional view taken from line I-I'.

[0016] Figure 7B , Figure 9B , Figure 10B , Figure 12B , Figure 14B and Figure 16B It is along Figure 6 , Figure 8 and Figure 15 The sectional view taken from line II-II'.

[0017] Figure 11 , Figure 13A , Figure 13B and Figure 13C yes Figure 10B and Figure 12B A magnified view of region 'R'.

[0018] Figure 17 yes Figure 15 A magnified view of region 'S'.

[0019] Figure 18A and 18B They are along Figure 2 The cross-sectional views taken along lines I-I' and II-II' illustrate semiconductor memory devices according to some embodiments of the concept of the present invention.

[0020] Figure 19 yes Figure 18B A magnified view of region 'R'.

[0021] Figure 20A and Figure 21A It is along Figure 2 The image is a cross-sectional view taken along line I-I' to illustrate a method for manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention.

[0022] Figure 20B and Figure 21B It is along Figure 2 The cross-sectional view taken along line II-II' illustrates a method for manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention.

[0023] Figure 22A and Figure 22B They correspond to Figure 11 and Figure 13B A magnified view.

[0024] Figure 23 It is along Figure 2The cross-sectional view taken along line II-II' is used to illustrate a semiconductor memory device according to some embodiments of the concept of the present invention. Detailed Implementation

[0025] Figure 1 This is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the concept of the present invention.

[0026] Reference Figure 1 According to some implementations, a semiconductor memory device may include a common source line CSL, multiple bit lines BL0 to BL2, and multiple cell strings CSTRs provided between the common source line CSL and the bit lines BL0 to BL2.

[0027] The common source line (CSL) can be a conductive layer disposed on a semiconductor substrate or a doped region formed in the semiconductor substrate. Bit lines BL0 to BL2 can be conductive patterns (e.g., metal lines) spaced perpendicularly to the semiconductor substrate (i.e., in the Z direction). Bit lines BL0 to BL2 can be arranged in two dimensions, and multiple cell strings (CSTRs) can be connected in parallel with each of the bit lines BL0 to BL2. Therefore, cell strings (CSTRs) can be arranged in two dimensions on the common source line (CSL) or the semiconductor substrate.

[0028] Each cell string (CSTR) may include a ground select transistor (GST) connected to a common source line (CSL), a string select transistor (SST) connected to one of the bit lines BL0 to BL2, and multiple memory cell transistors (MCTs) providing space between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the memory cell transistors (MCTs), and the string select transistors (SSTs) may be connected in series with each other. The ground select line (GSL), multiple word lines (WL0 to WL3), and string select lines (SSL0, SSL1, or SSL2) located between the common source line (CSL) and the bit lines BL0 to BL2 may be used as the gate electrodes of the ground select transistor (GST), the memory cell transistors (MCTs), and the string select transistors (SSTs), respectively.

[0029] The ground select transistor (GST) can be positioned at substantially equal distances from the semiconductor substrate, and the gate electrodes of the GST can be connected to the ground select line (GSL) to achieve equipotentiality. For this purpose, the ground select line (GSL) can be a plate-shaped or comb-shaped conductive pattern positioned between the common source line (CSL) and the memory cell transistor (MCT) closest to the common source line (CSL). Similarly, the gate electrodes of the memory cell transistors (MCTs) positioned at substantially equal distances from the common source line (CSL) can be connected to one of the word lines (WL0 to WL3) to achieve equipotentiality. For this purpose, each of the word lines (WL0 to WL3) can be a plate-shaped or comb-shaped conductive pattern arranged parallel to the top surface of the semiconductor substrate. Because a single cell string (CSTR) comprises multiple memory cell transistors (MCTs) located at different heights from the common source line (CSL), the word lines (WL0 to WL3) at different heights can be positioned between the common source line (CSL) and the bit lines (BL0 to BL2).

[0030] Each cell string (CSTR) may include a channel structure extending perpendicularly (i.e., in the Z direction) from the common source line (CSL) to connect to one of the bit lines BL0 to BL2. The channel structure may penetrate the ground select line (GSL), word lines (WL0 to WL3), and string select lines (SSL0, SSL1, or SSL2). Additionally, the channel structure may include a body portion and doped regions formed at one or both ends of the body portion. For example, a drain region may be formed at the top of the body portion.

[0031] The data storage layer can be disposed between the channel structure and the word lines WL0 to WL3. In some embodiments, the data storage layer may include a charge storage layer.

[0032] The dielectric layer of the gate insulating layer used as the ground select transistor GST and / or the string select transistor SST can be disposed between the ground select line GSL and the channel structure and / or between the string select lines SSL0, SSL1 or SSL2 and the channel structure. The gate insulating layer of at least one of the ground select transistor GST and the string select transistor SST can be formed of the same material as the data storage layer of the memory cell transistor MCT, or it can be the gate insulating layer (e.g., silicon oxide layer) used for general transistors (MOSFETs).

[0033] The ground select transistor (GST), string select transistor (SST), and memory cell transistor (MCT) can be metal-oxide-semiconductor (MOS) field-effect transistors that use a channel structure as the channel region. In some embodiments, the channel structure can form a MOS capacitor together with the ground select line (GSL), word lines (WL0 to WL3), and string select lines (SSL0, SSL1, or SSL2). In this example, the ground select transistor (GST), memory cell transistor (MCT), and string select transistor (SST) can share an inversion layer generated by an edge field, which is generated by lines GSL, WL0 to WL3, and SSL0 to SSL2. Therefore, the transistors GST, MCT, and SST included in each cell string (CSTR) can be electrically connected to each other.

[0034] Figure 2 This is a top view illustrating some embodiments of a semiconductor memory device according to the present invention. Figure 3A and Figure 3B They are along Figure 2 The cross-sectional views taken along lines I-I' and II-II' illustrate semiconductor memory devices according to some embodiments of the concept of the present invention. Figure 4 This is an enlarged view of region 'R' in Figure 3.

[0035] Reference Figure 2 , Figure 3A , Figure 3B and Figure 4 Semiconductor memory devices according to some embodiments of the present invention may include a cell array region CR and an extension region ER provided at the ends of the cell array region CR. For example, the extension regions ER may be provided at both ends of the cell array region CR. Hereinafter, the cell array region CR and the extension regions ER will be described based on a substrate 100. A plurality of stacked structures ST may be disposed on the substrate 100 including the cell array region CR and the extension regions ER. The stacked structures ST may extend in a first direction D1 parallel to the top surface of the substrate 100 and may be spaced apart from each other in a second direction D2 parallel to the top surface of the substrate 100 and perpendicular to the first direction D. The substrate 100 may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, and / or a single-crystal epitaxial layer grown on a single-crystal silicon substrate.

[0036] Source region SR (see example) Figure 3B The source region SR can be disposed in the substrate 100. In a top view, the source region SR can be disposed between the stacked structures ST and can extend in the first direction Dl. The source region SR can be a doped region having a conductivity type different from that of the substrate 100.

[0037] Each stacked structure ST may include horizontal electrodes GP stacked on a third direction D3 perpendicular to the top surface of the substrate 100. The bottommost horizontal electrode in the horizontal electrodes GP may be Figure 1 The ground selection line GSL, the uppermost horizontal electrode in the horizontal electrode GP can be Figure 1 The serial select line SSL. The horizontal electrode GP between the bottommost horizontal electrode and the topmost horizontal electrode can be the word line WL. In other embodiments, multiple horizontal electrodes GP can be used as the serial select line SSL. For example, the horizontal electrodes GP can include doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and / or transition metals (e.g., titanium or tantalum).

[0038] A second horizontal insulating layer 105 can be disposed between horizontal electrodes GP on the cell array region CR. A first horizontal insulating layer 101 can be disposed between horizontal electrodes GP on the extension region ER. For example, the first horizontal insulating layer 101 and horizontal electrodes GP can be stacked alternately and repeatedly on the extension region ER, and the second horizontal insulating layer 105 and horizontal electrodes GP can be stacked alternately and repeatedly on the cell array region CR. Figure 4 As shown, a second horizontal insulating layer 105 may be connected to the first horizontal insulating layer 101 near the boundary between the cell array region CR and the extended region ER. Depending on the characteristics of the semiconductor memory device, the first horizontal insulating layer 101 and the second horizontal insulating layer 105 may have different thicknesses in the D3 direction. Horizontal insulating layers 101 and 105 may include, for example, silicon oxide. A buffer layer 110 may be provided between the lowermost horizontal electrode GP and the substrate 100. The buffer layer 110 may include silicon oxide. A first separator pattern 133 may be provided on the cell array region CR on the uppermost horizontal electrode GP. The first separator pattern 133 may include silicon oxide.

[0039] The ends (i.e., pads) of the horizontal electrodes GP can be exposed in a stepped shape on the extension region ER (i.e., without other layers or materials). Each pad can be defined as the end of each horizontal electrode GP exposed by another horizontal electrode GP directly disposed thereon. Contacts for applying voltage to the horizontal electrodes GP can be connected to the ends (i.e., pads) of the horizontal electrodes GP. On the extension region ER, the sidewalls of the ends of each first horizontal insulating layer 101 can be aligned with the sidewalls of the ends of the horizontal electrodes GP directly disposed therebelow. A first interlayer insulating layer 131 can be provided on the extension region ER as a cover pad. A second interlayer insulating layer 132 can be provided on the extension region ER on top of the first interlayer insulating layer 131. The top surface of the second interlayer insulating layer 132 can be located at the same height as the top surface of the first separating pattern 133. The first interlayer insulating layer 131 and the second interlayer insulating layer 132 can comprise silicon oxide.

[0040] like Figure 4 As shown, each horizontal electrode GP may include a cell portion CG on the cell array region CR and an extension portion EG on the extension region ER. Some horizontal electrode GPs (e.g., the uppermost horizontal electrode) may not include the extension portion EG. The top surface TS2 of the extension portion EG may be at a higher height in the D3 direction than the top surface TS1 of the cell portion CG. The bottom surface BS2 of the extension portion EG may be at a lower height in the D3 direction than the bottom surface BS1 of the cell portion CG. For example, the thickness T2 of the extension portion EG may be greater than the thickness T1 of the cell portion CG. Due to the height difference and / or thickness difference, the horizontal electrode GP may have a stepped structure at the boundary between the extension portion EG and the cell portion CG.

[0041] Vertical structures VS1 and VS2 can be provided as penetrating the stacked structure ST. Vertical structures VS1 and VS2 can be provided in the vertical holes CH penetrating the stacked structure ST. Vertical structures VS1 and VS2 can include a first vertical structure VS1 provided on the cell array region CR and a second vertical structure VS2 provided on the extension region ER. The first vertical structure VS1 and its adjacent horizontal electrode GP can constitute... Figure 1 The cell string CSTR. The second vertical structure VS2 may not constitute a memory cell transistor, but may be a dummy structure used to support the molded structure during manufacturing. For example, the second vertical structure VS2 may not be connected to the upper interconnect via a contact. When viewed from above, the first vertical structure VS1 may be arranged in a zigzag pattern in the second direction D2.

[0042] Each of the vertical structures VS1 and VS2 may include a fill layer 139, a channel layer CS, a data storage layer DS1 or DS2, and a pad pattern 128. The channel layer CS and the data storage layer DS1 or DS2 may be stacked sequentially on the sidewall of the fill layer 139. For example, the channel layer CS may be disposed between the fill layer 139 and the data storage layer DS1 or DS2. The pad pattern 128 may be disposed in the upper part of each of the vertical structures VS1 and VS2, and may be on and at least partially cover the top surface of the data storage layer DS1 or DS2.

[0043] The channel layer CS may include a polycrystalline silicon layer, an organic semiconductor layer, or a carbon nanostructure. Each of the data storage layers DS1 and DS2 may include a tunneling insulating layer TL, a charge storage layer CL, and a barrier insulating layer BL. The tunneling insulating layer TL may be adjacent to the sidewall of the channel layer CS and may extend along the sidewall of the channel layer CS in a third direction D3. The tunneling insulating layer TL may include, for example, a silicon oxide layer.

[0044] For example, the charge storage layer CL may include a silicon nitride layer. For example, the barrier insulating layer BL may include a silicon oxide layer.

[0045] The first data storage layer DS1 of the first vertical structure VS1 and the second data storage layer DS2 of the second vertical structure VS2 can have different structures from each other. For example, the structure of the charge storage layer and the barrier insulating layer of the first data storage layer DS1 can be different from the structure of the charge storage layer CL and the barrier insulating layer BL of the second data storage layer DS2. The charge storage layer CL of the second data storage layer DS2 can extend continuously along the sidewall of the horizontal electrode GP and the sidewall of the first horizontal insulating layer 101 in the third direction D3. In other words, the charge storage layer CL of the second data storage layer DS2 can be provided in the region between the channel layer CS and the first horizontal insulating layer 101 and in the region between the channel layer CS and the horizontal electrode GP. In contrast, the charge storage layer of the first data storage layer DS1 can include charge storage patterns CP that are spaced apart from each other in the third direction D3 and the second horizontal insulating layer 105 is interposed therebetween. In other words, the charge storage patterns CP of the first data storage layer DS1 can be arranged intermittently along the third direction D3. When viewed in top view, each charge storage pattern CP can be annular.

[0046] The charge storage pattern CP can be disposed in the region between the channel layer CS and the horizontal electrode GP, but may not be disposed in the region between the channel layer CS and the second horizontal insulating layer 105. Therefore, the charge contained in each charge storage pattern CP may not move or diffuse into other charge storage patterns CP. Due to the structure in which the charge storage patterns CP are perpendicularly separated from each other, the data retention characteristics of the semiconductor memory device can be improved.

[0047] Similar to the charge storage layer, the structure of the barrier insulating layer of the first data storage layer DS1 can differ from the structure of the barrier insulating layer BL of the second data storage layer DS2. The barrier insulating layer BL of the second data storage layer DS2 can extend continuously along the sidewalls of the horizontal electrode GP and the sidewalls of the first horizontal insulating layer 101 in the third direction D3. In contrast, the barrier insulating layer of the first data storage layer DS1 can include barrier insulating patterns BP spaced apart from each other in the third direction D3, with the second horizontal insulating layer 105 interposed therebetween. When viewed in top view, each barrier insulating pattern BP can be annular.

[0048] The width T3 of each blocking insulating pattern BP in the third direction D3 can be greater than the thickness T1 of the adjacent portion (i.e., the unit portion CG) of the horizontal electrode GP. The width T3 of each charge storage pattern CP in the third direction D3 can be greater than the thickness T1 of the adjacent portion (i.e., the unit portion CG) of the horizontal electrode GP.

[0049] Unlike the charge storage layer and the barrier insulating layer, the tunneling insulating layer TL of the first data storage layer DS1 can have a shape substantially the same as that of the tunneling insulating layer TL of the second data storage layer DS2. In other embodiments, similar to the charge storage layer and the barrier insulating layer, the structure of the tunneling insulating layer TL of the first data storage layer DS1 can differ from the structure of the tunneling insulating layer TL of the second data storage layer DS2. For example, as... Figure 13C As shown, the tunneling insulation layer of the first data storage layer DS1 may include tunneling insulation patterns TP spaced apart from each other on the third-direction D3. Referring below... Figure 4 Example embodiments of the present invention are described.

[0050] Semiconductor pillars (SPs) can be disposed between the substrate 100 and the vertical structures VS1 and VS2. The semiconductor pillars (SPs) can be formed by performing a selective epitaxial growth (SEG) process using the substrate 100 as a seed. For example, the semiconductor pillars (SPs) can include intrinsic semiconductor materials or P-type semiconductor materials.

[0051] Barrier insulating layer 160 may be disposed between the horizontal electrode GP and the horizontal insulating layers 105 and 101, and may extend between the barrier insulating layer BL and the horizontal electrode GP. Barrier insulating layer 160 may be in physical contact with barrier insulating layer BL. Barrier insulating layer 160 may comprise a single layer or multiple layers. For example, barrier insulating layer 160 may comprise a metal oxide layer and / or a metal nitride layer. For example, barrier insulating layer 160 may be part of the barrier insulating layer of a charge trap type non-volatile storage transistor.

[0052] The pad pattern 128 can be in physical contact with and electrically connected to the channel layer CS. The pad pattern 128 can comprise polysilicon doped with a dopant of a different conductivity type than that of the dopant on the substrate 100 (e.g., a P-type dopant). For example, the pad pattern 128 can comprise an N-type dopant.

[0053] Source lines SL can be positioned between stacked structures ST and can be connected to source regions SR. When viewed in a top view, source lines SL can have a linear or rectangular shape extending along the source regions SR in a first direction D1 (see example). Figure 2 In other embodiments, the source lines SL may include contacts that are separated from each other in the first direction D1. For example, the source lines SL may be formed of a metal (e.g., tungsten, copper, or aluminum) and / or a transition metal (e.g., titanium or tantalum). A second separation pattern 134 may be disposed between the source lines SL and the stacked structure ST. The second separation pattern 134 may extend in the first direction D1. For example, the second separation pattern 134 may include an insulating material (e.g., silicon oxide or silicon nitride).

[0054] Figure 5 yes Figure 2 A magnified view of region 'S' to show the hierarchy of one of the horizontal electrodes. (As shown) Figure 5 As shown, a second trench TH2 can be provided between adjacent stacked structures ST, and a source line SL and a second separator pattern 134 can be provided in the second trench TH2. The second separator pattern 134 can be provided on the cell array region CR and the extended region ER. A protruding separator pattern 138 can protrude from the second separator pattern 134 toward the horizontal electrode GP in a second direction D2 and / or in a direction opposite to the second direction D2. The protruding separator pattern 138 can be provided in the first trench TH1. The protruding separator pattern 138 can be part of a layer formed simultaneously and / or synchronously with the first separator pattern 133. The first trench TH1 and the second trench TH2 can expose the top surface of the substrate 100. The protruding separator pattern 138 can be locally provided on the cell array region CR, but may not extend to the extended region ER. The first separator pattern 133 and the second separator pattern 134 can comprise silicon oxide.

[0055] A third interlayer insulating layer 135 may be provided on and at least partially covering the second interlayer insulating layer 132 and the first separator pattern 133. For example, the third interlayer insulating layer 135 may include at least one of a silicon oxide layer, a silicon nitride layer, and / or a silicon oxide nitride layer. A contact plug CT may penetrate the third interlayer insulating layer 135 and may contact the pad pattern 128. The contact plug CT may include doped silicon and / or a metallic material (e.g., tungsten (W), copper (Cu), or aluminum (Al)). A bit line 176 may be disposed on the third interlayer insulating layer 135. The bit line 176 may be electrically connected to the first vertical structure VS1 via the contact plug CT. The bit line 176 may include a conductive material.

[0056] Figure 6 , Figure 8 and Figure 15 This is a top view illustrating a method for manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention. Figure 7A , Figure 9A , Figure 10A , Figure 12A , Figure 14A and Figure 16A It is along Figure 6 , Figure 8 and Figure 15 A sectional view taken from line I-I'. Figure 7B , Figure 9B , Figure 10B , Figure 12B , Figure 14B and Figure 16B It is along Figure 6 , Figure 8 and Figure 15 The sectional view taken from line II-II'. Figure 11 , Figure 13A , Figure 13B and Figure 13C yes Figure 10B and Figure 12B A magnified view of region 'R'. Figure 17 yes Figure 15 A magnified view of region 'S'.

[0057] Reference Figure 6 , Figure 7A and Figure 7BA molded structure MS can be formed on a substrate 100 including a cell array region CR and an extension region ER. The molded structure MS may include a first layer and a second layer alternately and repeatedly stacked on the substrate 100. For example, the first layer may be a first horizontal insulating layer 101, and the second layer may be a sacrificial layer 102. The first horizontal insulating layer 101 may include a material with etch selectivity relative to the sacrificial layer 102. For example, the first horizontal insulating layer 101 may be a silicon oxide layer, and the sacrificial layer 102 may be a silicon nitride layer. A buffer layer 110 may be formed at the bottom of the molded structure MS. The buffer layer 110 may be a silicon oxide layer.

[0058] A patterned molding structure MS can be used to form a stepped structure on the extended region ER. The stepped structure can be formed by a mask patterning process and an etching process. A first interlayer insulating layer 131 can be formed on the stepped structure and at least partially cover the stepped structure.

[0059] A vertical hole CH can be formed as a through-molded structure MS. The vertical hole CH can expose the substrate 100, meaning that a portion of the substrate 100 may not have the molded structure MS. For example, the vertical hole CH can be formed using an anisotropic etching process. A mask pattern can be formed on the molded structure MS, and the vertical hole CH can be formed by etching the molded structure MS exposed by the mask pattern. The etching process for forming the vertical hole CH can be performed until a portion of the top surface of the substrate 100 is exposed, i.e., until a portion of the top surface of the substrate 100 is free of the molded structure. Through over-etching in the etching process, the top surface of the substrate 100 can be recessed.

[0060] Vertical holes CH can be formed on both the cell array region CR and the extended region ER. Semiconductor pillars SP can be formed or grown from the top surface of the substrate 100 exposed by the vertical holes CH. For example, the semiconductor pillars SP can include intrinsic semiconductor material or P-type semiconductor material. In some embodiments, the semiconductor pillars SP can be omitted.

[0061] Vertical structures VS1 and VS2 can be formed on semiconductor pillars SP within a vertical via CH. The first vertical structure VS1 on the cell array region CR and the second vertical structure VS2 on the extended region ER can be formed having substantially the same layers and the same shape. Each of the vertical structures VS1 and VS2 may include a fill layer 139, a channel layer CS, a data storage layer DS, and a pad pattern 128. The channel layer CS can penetrate the data storage layer DS and thus be connected to the semiconductor pillar SP. More specifically, the data storage layer DS can be formed on the inner surface of the vertical via CH. Subsequently, the lower portion of the data storage layer DS can be etched using a dry etching process to expose the top surface of the semiconductor pillar SP; that is, the top surface of the semiconductor pillar SP may be free of the data storage layer DS. Next, the channel layer CS can be formed on the sidewalls of the data storage layer DS. The lower portion of the channel layer CS can be connected to the semiconductor pillar SP. Subsequently, a fill layer 139 can be formed in the vertical via CH on the sidewalls of the channel layer CS and at least partially covering the sidewalls of the channel layer CS. The fill layer 139 can be formed using, for example, spin-coated glass (SOG) technology. The fill layer 139 may include an insulating material, such as a silicon oxide layer or a silicon nitride layer. The data storage layer DS, the channel layer CS, and the top portion of the fill layer 139 may be removed to form an empty region in the vertical via CH. A pad pattern 128 may then be formed in the empty region using a conductive material. A second interlayer insulating layer 132 may be formed on and at least partially covers the vertical structures VS1 and VS2. The second interlayer insulating layer 132 may include silicon oxide.

[0062] Reference Figure 8 , Figure 9A and Figure 9B The first trench TH1 can be formed as a through-molded structure MS. The first trench TH1 can expose the top surface of the substrate 100, for example, providing an entrance to the top surface of the substrate 100. The first trench TH1 can be formed using an ion beam etching process. The first trench TH1 can be formed on the cell array region CR, and when viewed in a top view, the two ends of each first trench TH1 can be provided in the cell array region CR (see, for example...). Figure 8 The first trench TH1 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2.

[0063] Reference Figure 10A and Figure 10BThe first horizontal insulating layer 101 exposed or revealed by the first trench TH1 can be removed from the cell array region CR. The first horizontal insulating layer 101 of the cell array region CR can be removed using an isotropic etching process. The first horizontal insulating layer 101 can be removed using an etching formulation (e.g., hydrofluoric acid (HF)) that has etch selectivity relative to the sacrificial layer 102. Therefore, the etching of the sacrificial layer 102 can be reduced or minimized during the etching process of the first horizontal insulating layer 101. At least a portion of the second interlayer insulating layer 132 on the cell array region CR can be removed together with the first horizontal insulating layer 101. Due to the distance from the first trench TH1, the first horizontal insulating layer 101 and the second interlayer insulating layer 132 on the extension region ER may not be removed. By removing the first horizontal insulating layer 101 of the cell array region CR, a data storage layer DS exposing the sacrificial layers 102 and a first gap region GR1 connected to the first trench TH1 can be formed. Because the first trench TH1 is confined to the cell array region CR and not formed on the extension region ER, the loss or damage of the second interlayer insulating layer 132 and the first interlayer insulating layer 131 on the extension region ER can be reduced or minimized. As a result, the process for manufacturing semiconductor memory devices can be simplified, and the dispersion of subsequent processes for forming horizontal electrodes can be reduced.

[0064] Figure 11 yes Figure 10B A magnified view of region 'R'. (Refer to...) Figure 11 The first gap region GR1 may be locally formed on the cell array region CR. The first horizontal insulating layer 101 may be on and at least partially cover the data storage layer DS of the second vertical structure VS2 disposed on the extension region ER.

[0065] Reference Figure 12A and Figure 12B An etching process can be performed on the data storage layer DS (hereinafter referred to as the first data storage layer DS1) of the first vertical structure VS1. Figure 13A , Figure 13B and Figure 13C yes Figure 12B A magnified view of region 'R'.

[0066] Reference Figure 12A , Figure 12B and Figure 13AThe barrier insulating layer of the first data storage layer DS1 can be etched to form barrier insulating patterns BP separated from each other on the third direction D3. The barrier insulating layer BL of the data storage layer DS of the second vertical structure VS2 (hereinafter referred to as the second data storage layer DS2) can be at least partially covered by the first horizontal insulating layer 101 and therefore can be left unetched. The etching process for forming the barrier insulating pattern BP can be performed using an etching formulation (e.g., hydrofluoric acid (HF)) that has etch selectivity relative to the sacrificial layer 102 and the charge storage layer CL. Therefore, the etching of the sacrificial layer 102 and the charge storage layer CL can be reduced or minimized during the formation of the barrier insulating pattern BP. The portion of the sacrificial layer 102 exposed by the first gap region GR1 can have substantially the same thickness (e.g., a first thickness T6) as the portion of the sacrificial layer 102 covered by the first horizontal insulating layer 101. The portion of the first horizontal insulating layer 101 exposed by the first gap region GR1 and the portion of the second interlayer insulating layer 132 on the extension region ER can also be removed. As a result, the top surface of the second interlayer insulating layer 132 can be compared to Figure 10B The top surface of the second interlayer insulation layer 132 is lower in the D3 direction.

[0067] Reference Figure 12A , Figure 12B and Figure 13B The charge storage layer CL exposed between the barrier insulating patterns BP of the first data storage layer DS1 can be etched to form charge storage patterns CP separated from each other on the third direction D3. The charge storage layer CL of the second data storage layer DS2 of the second vertical structure VS2 can be at least partially covered by the first horizontal insulating layer 101 and therefore can be left unetched. The etching process for forming the charge storage pattern CP can be performed using an etching formulation (e.g., phosphoric acid (H3PO4)) that has etch selectivity relative to the barrier insulating pattern BP and the tunneling insulating layer TL. The difference in etching rate between the charge storage layer CL and the sacrificial layer 102 can be smaller than the difference in etching rate between the charge storage layer CL and the barrier insulating pattern BP (and the tunneling insulating layer TL). As a result, the top and bottom surfaces of the portion of the sacrificial layer 102 exposed or revealed by the first gap region GR1 can be etched simultaneously with the etching of the charge storage layer CL, so that the etched portion of the sacrificial layer 102 can have a second thickness T7 less than the first thickness T6. The first thickness T6 of the portion of the sacrificial layer 102 at least partially covered by the first horizontal insulating layer 101 can be maintained. As a result, a stepped structure can be formed at the top and bottom of the sacrificial layer 102.

[0068] In some implementations, such as Figure 13CIn one implementation, the tunneling insulating layer TL exposed or revealed between the charge storage patterns CP of the first data storage layer DS1 can be etched to form tunneling insulating patterns TP separated from each other on the third direction D3. In some implementations, the tunneling insulating layer TL of the second data storage layer DS2 of the second vertical structure VS2 can be at least partially covered by the first horizontal insulating layer 101, and therefore can be left unetched. Referring below... Figure 13B Example embodiments of the present invention are described.

[0069] Reference Figure 14A and Figure 14B A gap-filling insulating layer (hereinafter referred to as the first separator pattern) 133 may be formed to fill the first trench TH1 and the first gap region GR1 extending from the first trench TH1. Hereinafter, the portion of the first separator pattern 133 in the first gap region GR1 may be referred to as the second horizontal insulating layer 105. For example, the first separator pattern 133 may comprise silicon oxide.

[0070] Reference Figure 15 , Figure 16A , Figure 16B and Figure 17 The second trench TH2 can be formed as a through-molded structure MS. The second trench TH2 can expose the top surface of the substrate 100, i.e., at least a portion of the top surface of the substrate is free of the molded structure MS. For example, the second trench TH2 can be formed using an ion beam etching process. Each second trench TH2 can be formed on the cell array region CR and the extended region ER. In other words, each second trench TH2 can intersect with the cell array region CR and the extended region ER. The second trenches TH2 can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. The second trenches TH2 can overlap with the first trench TH1 respectively. In some embodiments, a portion of the sidewall of the second trench TH2 may not be aligned with the first trench TH1, thus a portion of the first trench TH1 and the protruding partition pattern 138 in that portion of the first trench TH1 can be retained. The protruding partition pattern 138 corresponding to a portion of the remaining first partition pattern 133 can contact the sidewall of the sacrificial layer 102 between the second horizontal insulating layers 105.

[0071] The sacrificial layer 102 exposed or exposed through the second trench TH2 can be replaced with a horizontal electrode GP. For example, the sacrificial layer 102 exposed through the second trench TH2 can be selectively removed to form a second gap region, and the horizontal electrode GP can be formed separately in the second gap region. The formation of the horizontal electrode GP may include: forming a conductive layer in the second gap region; and performing an etching process on the conductive layer to remove the conductive layer formed in the second trench TH2 and locally retain portions of the conductive layer in the respective second gap regions.

[0072] Formation can be performed before the formation of the horizontal electrode GP. Figure 4 The process of the barrier insulating layer 160 is shown. The barrier insulating layer 160 may be formed on the top and bottom surfaces of the second horizontal insulating layer 105 exposed by the second gap region to at least partially conformally cover the top and bottom surfaces of the second horizontal insulating layer 105 exposed by the second gap region. The barrier insulating layer 160 may comprise a single layer or multiple layers. For example, the barrier insulating layer 160 may be part of the barrier insulating layer of a charge trap type non-volatile storage transistor. The barrier insulating layer 160 may be a dielectric layer (e.g., a high-k material, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium aluminum oxide (HfAlO), and / or hafnium silicon oxide (HfSiO)). By forming the horizontal electrode GP, a stacked structure ST including the horizontal electrode GP and the horizontal insulating layers 105 and 101 can be formed.

[0073] Refer again Figure 2 , Figure 3A and Figure 3B A source region SR can be formed in the substrate 100 exposed or exposed through the second trench TH2. The source region SR can be formed using an ion implantation process. The source region SR can have a different conductivity type than that of the substrate 100. A second partition pattern 134 and a source line SL can be sequentially formed in each second trench TH2. For example, the second partition pattern 134 can be formed on the sidewalls of the second trench TH2 and at least partially cover the sidewalls of the second trench TH2. The formation of the second partition pattern 134 may include: forming an insulating layer (not shown) on the sidewalls and bottom surface of the second trench TH2 and at least partially covering the sidewalls and bottom surface of the second trench TH2; and etching a portion of the insulating layer (not shown) on the bottom surface of the second trench TH2 and at least partially covering the bottom surface of the second trench TH2 to expose or expose the top surface of the substrate 100, i.e., the portion of the top surface of the substrate may not have an insulating layer. The second partition pattern 134 can be formed of, for example, silicon oxide or silicon nitride. Source lines SL can be formed in each second trench TH2 in which the second separation pattern 134 is formed. Source lines SL can be formed using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD) processes. For example, source lines SL can be formed from metals (e.g., tungsten, copper, and / or aluminum) and / or transition metals (e.g., titanium and / or tantalum).

[0074] A third interlayer insulating layer 135 may be formed after the source line SL is formed. The third interlayer insulating layer 135 may be on the top surface of the first separation pattern 133 and the top surface of the second interlayer insulating layer 132, and at least partially cover the top surfaces of the first separation pattern 133 and the second interlayer insulating layer 132. The third interlayer insulating layer 135 may include an insulating material, such as a silicon oxide layer, a silicon nitride layer, and / or a silicon nitride layer.

[0075] The contact plug CT can be formed to penetrate the third interlayer insulating layer 135. The contact plug CT can be in physical contact with the pad pattern 128. The contact plug CT can include doped silicon and / or conductive materials (e.g., tungsten (W), copper (Cu), and / or aluminum (Al)).

[0076] Bit lines 176 that physically contact the contact plug CT can be formed on the third interlayer insulating layer 135. Bit lines 176 may intersect with the stack structure ST, and each bit line 176 may be connected to a first vertical structure VS1 arranged in the second direction D2. Bit lines 176 may include conductive materials (e.g., tungsten (W), aluminum (Al), and / or copper (Cu)).

[0077] Figure 18A and 18B They are along Figure 2 The cross-sectional views taken along lines I-I' and II-II' illustrate semiconductor memory devices according to some embodiments of the concept of the present invention. Figure 19 yes Figure 18B An enlarged view of region 'R'. In the following text, for the sake of convenience and ease of explanation, descriptions of the same components as in the above embodiments will be omitted.

[0078] Reference Figure 18A , Figure 18B and Figure 19 According to some embodiments, the semiconductor memory device may include a protective semiconductor pattern 166 provided on the sidewall of the second vertical structure VS2. The protective semiconductor pattern 166 may be provided partially on the extension region ER, but may not be provided on the sidewall of the first vertical structure VS1 disposed on the cell array region CR. The protective semiconductor patterns 166 may be spaced apart from each other with horizontal electrodes GP interposed therebetween. In other words, the protective semiconductor patterns 166 disposed on the sidewall of one of the second vertical structures VS2 may be separated from each other by the horizontal electrodes GP. For example, when viewed in top view, each of the protective semiconductor patterns 166 separated from each other by the horizontal electrodes GP may have an annular shape. The protective semiconductor pattern 166 may be provided between the barrier insulating layer BL of the second data storage layer DS2 and the first horizontal insulating layer 101. The protective semiconductor pattern 166 may include a semiconductor material such as polysilicon.

[0079] Figure 20A and Figure 21A It is along Figure 2 The image is a cross-sectional view taken along line I-I' to illustrate a method for manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention. Figure 20B and Figure 21B It is along Figure 2 The cross-sectional view taken along line II-II' illustrates a method for manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention. Figure 22A and Figure 22B They correspond to Figure 11 and 13B A magnified view.

[0080] Reference Figure 20A and Figure 20B A molded structure MS can be provided on the substrate 100, the molded structure MS comprising alternating and repeating stacked first horizontal insulating layers 101 and sacrificial layers 102. The molded structure MS may include a stepped structure on the extended region ER. A first interlayer insulating layer 131 may be provided on the stepped structure and at least partially covering the stepped structure.

[0081] After forming the vertical vias CH through the molded structure MS to expose or reveal portions of the substrate 100 surface, portions of the first horizontal insulating layer 101 exposed or revealed by the vertical vias CH can be removed to form recessed regions RS on the cell array region CR and the extended region ER. Each recessed region RS can be a region defined by an adjacent sacrificial layer 102 and the sidewalls of the first horizontal insulating layer 101 between the adjacent sacrificial layers 102. The recessed regions RS can be formed using an etching formulation (e.g., hydrofluoric acid (HF)) that has etch selectivity relative to the sacrificial layer 102. The first interlayer insulating layer 131 can be etched together with the first horizontal insulating layer 101.

[0082] The protective semiconductor layer 165 in the recessed region RS can be formed in the vertical via CH. In some embodiments, the protective semiconductor layer 165 can be formed of a material that has etch selectivity relative to the first horizontal insulating layer 101 and the sacrificial layer 102. For example, the protective semiconductor layer 165 can be a polysilicon layer. Due to the recessed region RS, the protective semiconductor layer 165 can have a curved or uneven inner surface.

[0083] Reference Figure 21A and Figure 21B A process for trimming the protective semiconductor layer 165 can be performed to form separate protective semiconductor patterns 166 in the recessed region RS. For example, the trimming process may include a wet etching process. Thereafter, it can be performed as described with reference to... Figure 6 , Figure 7A and Figure 7BThe ground forms semiconductor pillars SP and vertical structures VS1 and VS2 in the vertical hole CH.

[0084] Figure 22A It corresponds to Figure 11 A magnified view of the area to show how the view is achieved through... Figure 21A and Figure 21B The resulting structure is executed by reference. Figure 8 , Figure 9A , Figure 9B , Figure 10A and Figure 10B The structure obtained by the described example process. (Refer to...) Figure 22A While removing the first horizontal insulating layer 101 exposed or revealed by the first trench TH1 from the cell array region CR, the data storage layer DS on the cell array region CR can be protected by the protective semiconductor pattern 166. As a result, damage to the data storage layer DS on the cell array region CR can be reduced or prevented.

[0085] Figure 22B It corresponds to Figure 13B A magnified view of the area to show how the view is achieved through... Figure 22A The resulting structure is executed by reference. Figure 12A , Figure 12B , Figure 13A and Figure 13B The structure is obtained through the example process described. The protective semiconductor pattern 166 on the cell array region CR can be obtained by referring to... Figure 12A , Figure 12B , Figure 13A and Figure 13B The described process is removed, but the protective semiconductor pattern 166 on the extended region ER can be at least partially covered by the first horizontal insulating layer 101 and the interlayer insulating layers 131 and 132, and therefore can be retained. As a result, according to some embodiments, the semiconductor memory device may include the protective semiconductor pattern 166 provided on the sidewall of the second vertical structure VS2. Thereafter, execution can be performed... Figure 14A , Figure 14B , Figure 16A and Figure 16B Example process for manufacturing according to reference Figure 18A and Figure 18B Semiconductor memory devices according to the described embodiments.

[0086] Figure 23 It is along Figure 2 The cross-sectional view taken along line II-II' is used to illustrate a semiconductor memory device according to some embodiments of the concept of the present invention.

[0087] exist Figure 23In this embodiment, the semiconductor memory device may include a peripheral circuit structure PS and a cell array structure CS disposed on the peripheral circuit structure PS. When viewed in a top view, the cell array structure CS may overlap with the peripheral circuit structure PS. The peripheral circuit structure PS may include a peripheral logic circuit PTR integrated on the semiconductor substrate 1, and a lower interlayer insulating layer 50 on and at least partially covering the peripheral logic circuit PTR.

[0088] Semiconductor substrate 1 may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, and / or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Semiconductor substrate 1 may include an active region defined by device isolation layer 11.

[0089] The peripheral logic circuit PTR may include row and column decoders, page buffers, and control circuitry, and may include NMOS and PMOS transistors, low-voltage and high-voltage transistors, and resistors integrated on the semiconductor substrate 1. Peripheral circuit interconnects 33 can be electrically connected to the peripheral logic circuit PTR via peripheral contact plugs 31. For example, peripheral contact plugs 31 and peripheral circuit interconnects 33 can be connected to NMOS and PMOS transistors.

[0090] The lower interlayer insulating layer 50 may be on and at least partially cover the peripheral gate electrode, peripheral contact plug 31, and peripheral circuit interconnect 33. The lower interlayer insulating layer 50 may include multiple stacked insulating layers. For example, the lower interlayer insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and / or a low-k dielectric layer.

[0091] An etch stop layer 60 and an intermediate interlayer insulating layer 65 may be sequentially stacked on the lower interlayer insulating layer 50. The etch stop layer 60 may be formed of an insulating material that has etch selectivity relative to the lower interlayer insulating layer 50. For example, the etch stop layer 60 may include a silicon nitride layer and / or a silicon oxide nitride layer. For example, the intermediate interlayer insulating layer 65 may include the same material as the lower interlayer insulating layer 50.

[0092] The cell array structure CS may include a stacked structure ST on the substrate layer 100a. The substrate layer 100a may be formed of a semiconductor material. For example, the substrate layer 100a may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or any mixture thereof. For example, the substrate layer 100a may be formed of a polycrystalline silicon layer doped with an N-type dopant.

[0093] Figure 23 The region 'R' can be similar to Figure 4 or Figure 19Apart from the third horizontal insulating layer 99 included in the stacked structure ST, other components of the stacked structure ST may be the same as or similar to those described in the above embodiments. The third horizontal insulating layer 99 may be provided on the extended region, but may not be provided on the cell array region.

[0094] The distance between a pair of horizontal electrodes GPs spaced apart and with a third horizontal insulating layer 99 inserted therebetween can be greater than the distance between other adjacent horizontal electrodes GPs. The stacked structure ST may include a first stacked structure and a second stacked structure spaced apart and with a third horizontal insulating layer 99 inserted therebetween. Each of the vertical structures VS1 and VS2 may have a stepped structure at a height adjacent to the third horizontal insulating layer 99. This stepped structure can be produced because the vertical holes providing the vertical structures VS1 and VS2 are formed by etching multiple patterning processes of the first and second molded structures, respectively, spaced apart and with the third horizontal insulating layer 99 inserted therebetween, and are provided for forming the first and second stacked structures.

[0095] In some embodiments of the semiconductor memory device conceived according to the present invention, charge storage patterns may be separated from each other in a direction perpendicular to the top surface of the substrate. Therefore, the charge contained in each charge storage pattern may not move or diffuse into other charge storage patterns, or the movement or diffusion of charge may be reduced.

[0096] In some embodiments of the present invention, methods for manufacturing semiconductor memory devices can reduce or minimize the loss or damage of interlayer insulating layers over extended regions.

[0097] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Consequently, the scope of the inventive concept will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be constrained or limited by the foregoing description.

[0098] This application claims priority to Korean Patent Application No. 10-2019-0116373, filed on September 20, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device comprising: a stack structure including: horizontal electrodes stacked in sequence on a substrate including a cell array region and an extension region; and horizontal insulating layers between the horizontal electrodes; and vertical structures penetrating the stack structure, a first one of the vertical structures being on the cell array region, a second one of the vertical structures being on the extension region; wherein each of the vertical structures includes: a channel layer; and tunnel insulating layers, charge storage layers, and barrier insulating layers stacked in sequence on sidewalls of the channel layer, wherein the charge storage layers of the first vertical structure include charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween; and wherein the charge storage layers of the second vertical structure extend along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers, wherein each of the horizontal electrodes has a first thickness in the direction perpendicular to the top surface of the substrate on the cell array region and a second thickness in the direction perpendicular to the top surface of the substrate on the extension region, and wherein the second thickness is greater than the first thickness.

2. The semiconductor memory device according to claim 1, wherein the barrier insulating layers of the first vertical structure include barrier insulating patterns spaced apart from each other in a direction perpendicular to the top surface of the substrate with the horizontal insulating layers interposed therebetween; and wherein the barrier insulating layers of the second vertical structure extend along the sidewalls of the horizontal electrodes and the sidewalls of the horizontal insulating layers.

3. The semiconductor memory device according to claim 2, wherein, each of the barrier insulating patterns has a width in the direction perpendicular to the top surface of the substrate that is greater than a thickness of the horizontal electrode adjacent to each of the barrier insulating patterns in the direction perpendicular to the top surface of the substrate.

4. The semiconductor memory device according to claim 1, wherein the tunnel insulating layers of the first vertical structure and the tunnel insulating layers of the second vertical structure extend along the sidewalls of the horizontal electrodes and the sidewalls of the horizontal insulating layers.

5. The semiconductor memory device according to claim 1, wherein each of the charge storage patterns has a width in the direction perpendicular to the top surface of the substrate that is greater than a thickness of the horizontal electrode adjacent to each of the charge storage patterns in the direction perpendicular to the top surface of the substrate.

6. The semiconductor memory device according to claim 1, wherein each of the horizontal electrodes has a step structure near a boundary between the cell array region and the extension region in which a thickness in the direction perpendicular to the top surface of the substrate changes discontinuously.

7. The semiconductor memory device according to claim 1, further comprising: guard semiconductor patterns spaced apart perpendicularly from each other on sidewalls of the barrier insulating layers of the second vertical structure with the horizontal electrodes interposed therebetween.

8. The semiconductor storage device according to claim 7, wherein the protective semiconductor pattern includes polysilicon.

9. The semiconductor storage device according to claim 7, wherein the protective semiconductor pattern is confined to the extended region.

10. The semiconductor storage device according to claim 1, wherein the stack structure includes a plurality of stack structures that extend in a first direction parallel to the top surface of the substrate and are separated from each other in a second direction perpendicular to the first direction, the semiconductor storage device further comprising: a partition pattern that extends between the plurality of stack structures adjacent to each other; and a protruding partition pattern that protrudes from the partition pattern in the second direction.

11. The semiconductor storage device according to claim 10, wherein the protruding partition pattern is on the cell array region.

12. A semiconductor storage device comprising: a stack structure including: horizontal electrodes that are stacked in order on a substrate including a cell array region and an extended region; and horizontal insulating layers between the horizontal electrodes; and a vertical structure that penetrates the stack structure, wherein each of the vertical structures includes: a channel layer; and a tunnel insulating layer, a charge storage layer, and a barrier insulating layer that are stacked in order on a sidewall of the channel layer, wherein each of the horizontal electrodes includes: a cell portion on the cell array region; and an extended portion on the extended region, wherein, with respect to a top surface of the substrate as a reference, a top surface of the extended portion is located at a higher level than a top surface of the cell portion, and wherein, with respect to the top surface of the substrate as a reference, a bottom surface of the extended portion is located at a lower level than a bottom surface of the cell portion.

13. The semiconductor storage device according to claim 12, wherein a thickness of the extended portion in a direction perpendicular to the top surface of the substrate is greater than a thickness of the cell portion in the direction perpendicular to the top surface of the substrate.

14. The semiconductor storage device according to claim 12, wherein each of the horizontal electrodes has a step structure in which a thickness in a direction perpendicular to the top surface of the substrate changes discontinuously near a boundary between the cell array region and the extended region.

15. The semiconductor storage device according to claim 12, wherein the vertical structure includes: first vertical structures on the cell array region; and second vertical structures on the extended region, wherein the charge storage layer of the first vertical structures includes charge storage patterns that are spaced apart from each other in a direction perpendicular to the top surface of the substrate with the horizontal insulating layers interposed therebetween; and wherein the charge storage layer of the second vertical structures extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers. ​ ​ 16. The semiconductor memory device according to claim 15, wherein the barrier insulating layer of the first vertical structure includes barrier insulating patterns spaced apart from each other in the direction perpendicular to the top surface of the substrate with the horizontal insulating layer interposed therebetween; and wherein the barrier insulating layer of the second vertical structure extends along the sidewalls of the horizontal electrodes and the sidewalls of the horizontal insulating layer.

17. The semiconductor memory device according to claim 15, further comprising: guard semiconductor patterns spaced apart from each other perpendicularly on sidewalls of the barrier insulating layer of the second vertical structure with the horizontal electrodes interposed therebetween.

18. The semiconductor memory device according to claim 17, wherein the guard semiconductor patterns are confined in the extended region.

19. A semiconductor memory device, comprising: stacked structures, each of the stacked structures including: horizontal electrodes extending in a first direction and stacked in series on a substrate, the substrate including a cell array region and an extended region; and horizontal insulating layers between the horizontal electrodes, the stacked structures being spaced apart from each other in a second direction perpendicular to the first direction; a separation pattern between the stacked structures; vertical structures penetrating the stacked structures, the vertical structures including first vertical structures on the cell array region and second vertical structures on the extended region; contacts connected to upper portions of the vertical structures; and bit lines on the contacts, wherein each of the vertical structures includes: a fill layer; a channel layer on sidewalls of the fill layer; tunnel insulating layers, charge storage layers, and barrier insulating layers stacked in series on sidewalls of the channel layer; and pad patterns on a top surface of the channel layer, wherein the charge storage layers of the first vertical structures include charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween; and wherein the charge storage layers of the second vertical structures extend along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers, wherein each of the horizontal electrodes has a step structure near a boundary between the cell array region and the extended region in which a thickness in the direction perpendicular to the top surface of the substrate changes discontinuously.

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