Floating power supply for a driver circuit configured to drive a high-side switching transistor

Abstract

Various embodiments of the present disclosure describe a floating power supply for a driver circuit configured to drive a high-side switching transistor. The high-side switching transistor of a rectifier circuit is driven by a high-side driver circuit to supply current to an output node. The high-side driver circuit is powered between a capacitive bootstrap node and the output node. A startup charging circuit charges a bootstrap capacitor by supplying current to the bootstrap node. The startup charging circuit includes: a first current path that selectively supplies a first charging current to the bootstrap node when the rectifier circuit operates in a switching mode; and a second current path that selectively supplies a second charging current to the bootstrap node when the rectifier circuit operates in a reset mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 904,038, filed on September 23, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to power supply circuits, and in particular to a bootstrap power supply for use in transistor drive circuits. Background Art

[0004] Rectifiers, inverters, and buck / boost / buck-boost converters are widely used circuits in AC-DC and DC-AC conversion. Such circuits typically have low-side and high-side transistor switches that are turned on and off based on some control signal. Low-side switches are typically implemented using n-channel metal oxide semiconductor (NMOS) field-effect transistors (FETs), and these switches are easy to control because they are typically referenced to the system ground. To save area, high-side switches are also typically implemented using NMOS FETs. However, NMOS high-side switches are not referenced to ground and are therefore more complex to control. Typically, a bootstrap technique is used to drive the high-side switch, whereby a bootstrap capacitor (CBOOT) is recharged when the low-side transistor is turned on, and when the output is very high, the energy stored in the capacitor is used to control the gate-to-source voltage (Vgs) of the high-side NMOS transistor switch. In order to provide a stable power supply to the driver of the high-side transistor switch, a robust and accurately charged bootstrap capacitor is required.

[0005] Now see Figure 1 , Figure 1 A schematic diagram of a prior art circuit 10 for charging a bootstrap capacitor CBOOT is shown. A diode-connected bipolar transistor Q1 and a Zener diode Z1 (connected in series) respond to bias current IBIAS to create a reference voltage at node Vgate1. When the voltage at node AC1 is zero, bootstrap capacitor CBOOT is charged to the Zener voltage via transistors M1 and M2 in response to a control signal at node Vgate2. When the voltage at node AC1 subsequently rises, voltage VBOOT is bootstrapped to a higher value.

[0006] Figure 1The primary challenge with this circuit is the variation in the generated boost supply voltage VBOOT1-VAC1 across process corners, temperature, and variations in the input rectified voltage V RECT . The reference voltage Vgate1 generated by Zener diode Z1 also depends on the bias current IBAIS . When V REC is less than 6V, the boost supply voltage VBOOT1-VAC1 will always be lower than the rectified voltage V RECT . Therefore, it is clear that circuit 10 requires a higher rectified voltage V RECT to initiate charging. The boost supply voltage VBOOT1-VAC1 also depends on the mode of the rectifier generating the input rectified voltage V RECT , as the emitter of transistor Q1 is always at zero volts (ground), while voltage VAC1 can be -0.7V or 0V depending on whether the rectifier is operating in diode mode or synchronous mode. Because the boost supply voltage VBOOT1-VAC1 is the power supply for the high-side switch driver circuit, it will be different from the power supply for the low-side switch driver circuit, resulting in asymmetric on-resistances (R DS_ON ) for the high-side and low-side transistor switches.

[0007] Figures 2A to 2C A prior art circuit 20 is shown comprising a half-bridge circuit 22 and a driver circuit 24 with bootstrapping. Figure 2A shows the operation of circuit 20 in update mode, Figure 2B shows the operation of circuit 20 in bootstrap mode, and Figure 2C The operation of circuit 20 in drive mode is shown. This circuit solution shows some limitations when the technology node moves higher and the drive voltage moves lower. One challenge is to ensure diode threshold compensation. This is particularly noteworthy when an external capacitor is used as a bootstrap capacitor CBoot. In this case, there will be a chip pin that generates the boost voltage VBOOT. With a pin for the regulated input voltage VREG and a pin for the boost voltage VBOOT, appropriate electrostatic discharge (ESD) protection is required, and the diode must therefore be sized to cope with ESD. If the bootstrap capacitor CBoot is overcharged, in some cases this can cause the drive voltage of the high-side transistor to exceed the safe operating area (SOA) of the process (i.e., when the maximum allowed Vgs of the high-level node is as low as 2.5V).

[0008] Therefore, there is a need in the art to address the deficiencies of prior art circuits. In particular, there is a need to ensure that the charge voltage of the bootstrap capacitor is well controlled over the full range of circuit operation. Summary of the Invention

[0009] In an embodiment, a circuit includes a rectifier circuit including a high-side switching transistor configured to supply current to an output node; and a high-side driver circuit configured to drive a control terminal of the high-side switching transistor, wherein the high-side driver circuit is powered between a bootstrap node and the output node; wherein the rectifier circuit is operable in a switching mode and a reset mode. The circuit also includes a bootstrap capacitor coupled between the bootstrap node and the output node; and a startup charging circuit configured to charge the bootstrap capacitor by supplying current to the bootstrap node. The startup charging circuit includes a first current path configured to selectively supply a first charging current to the bootstrap node, the first current path being activated in response to operation of the rectifier circuit in the switching mode; and a second current path configured to selectively supply a second charging current to the bootstrap node, the second current path being activated in response to operation of the rectifier circuit in the reset mode.

[0010] In one embodiment, a circuit includes: a high-side switching transistor coupled between a first node and a second node; a high-side driver circuit configured to drive a control terminal of the high-side switching transistor, wherein the high-side driver circuit is powered between a bootstrap node and the first node. The circuit also includes: a bootstrap capacitor coupled between the bootstrap node and an input node; and a startup charging circuit configured to charge the bootstrap capacitor by supplying current to the bootstrap node. The startup charging circuit includes: a first current path configured to selectively supply a first charging current to the bootstrap node, the first current path being activated when the high-side switching transistor is driven by the high-side driver circuit in a switching mode of operation; and a second current path configured to selectively supply a second charging current to the bootstrap node, the second current path being activated when the high-side switching transistor is driven by the high-side driver circuit in a reset mode of operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a better understanding of these embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram of a prior art circuit for charging a bootstrap capacitor;

[0013] Figures 2A to 2C A prior art circuit comprising a half-bridge circuit and a driving circuit with bootstrapping is shown;

[0014] Figure 3 A circuit diagram showing a bridge circuit with bootstrapped high-side drive; and

[0015] Figure 4A and Figure 5A Each shows the Figure 3 Circuit diagram of the starting charging circuit in the circuit;

[0016] Figure 4B and Figure 5B Each shows the Figure 3 A circuit diagram of a startup charging circuit having an alternative configuration in a circuit of

[0017] Figures 6 and 7 The operating waveforms of the circuit are shown. DETAILED DESCRIPTION

[0018] Now see Figure 3 , which shows a circuit diagram of a rectifier circuit 30 including a rectifier bridge circuit 32 with a bootstrapped high-side drive. A rectified voltage, VRECT, is generated from the A / C input. A low-dropout voltage regulator circuit 34 receives the rectified voltage, VRECT, and generates a regulated low-dropout voltage, VLDO. Bridge circuit 32 is a full-bridge type, comprising a first half-bridge formed by a series connection of a high-side switching transistor Q1 and a low-side switching transistor Q3, connected at an A / C input node AC1 between the rectified voltage, VRECT, and a reference / ground node. The second half-bridge is formed by a series connection of a high-side switching transistor Q2 and a low-side switching transistor Q4, connected at an A / C input node AC2 between the rectified voltage, VRECT, and the reference / ground node. The gate of high-side switching transistor Q1 is driven by a high-side driver circuit HSD1 (using a drive voltage, Vgate1) in response to a control signal D1 generated by a rectifier control circuit. The gate of high-side switching transistor Q2 is driven by high-side driver circuit HSD2 (using drive voltage Vgate2) in response to control signal D2 generated by the rectifier control circuit. The gate of low-side switching transistor Q3 is driven by low-side driver circuit LSD1 (using drive voltage Vgate3) in response to control signal D3 generated by the rectifier control circuit. The gate of low-side switching transistor Q4 is driven by low-side driver circuit LSD2 (using drive voltage Vgate4) in response to control signal D4 generated by the rectifier control circuit. The power supply for high-side driver circuit HSD1 is between bootstrap voltage node BOOT1 and the voltage at the first half-bridge A / C input node AC1. The power supply for high-side driver circuit HSD2 is between bootstrap voltage node BOOT2 and the voltage at the second half-bridge A / C input node AC2. The power supply for low-side driver circuit LSD1 and low-side driver circuit LSD2 is between low dropout voltage VLDO and reference / ground voltage. A first bootstrap capacitor CBOOT1 is connected between bootstrap voltage node BOOT1 and the first half-bridge output node AC1. The second bootstrap capacitor CBOOT2 is connected between the bootstrap voltage node BOOT2 and the second half-bridge output node AC2 .

[0019] The charging voltage at the bootstrap voltage node BOOT1 is generated from the low dropout voltage VLDO by the first bootstrap charging circuit 40, and the charging voltage at the bootstrap voltage node BOOT2 is generated from the low dropout voltage VLDO by the second bootstrap charging circuit 42. The first bootstrap charging circuit 40 and the second bootstrap charging circuit 42 have the same circuit configuration. Figures 4A to 4B An embodiment of a first startup charging circuit 40 is shown, and Figures 5A to 5B An embodiment for the second startup charging circuit 42 is shown.

[0020] Now refer to Figure 4A To describe the circuit 40 and its connections. For the sake of brevity, the detailed description will not be given. Figure 5A It will be appreciated that the circuit 42 shown in FIG. 1 operates generally the same as the circuit 40 but with the addition of Figure 3 The startup charging circuit 40 has two current paths (path 1 and path 2) to charge the bootstrap capacitor CBOOT1, which is connected between the bootstrap node BOOT1 and the first half-bridge voltage node AC1.

[0021] Path 1 is defined by a series connection of n-channel transistors M1 and M2, with their sources connected together and their drains connected to the low dropout voltage VLDO and the bootstrap node BOOT1, respectively. The gate of transistor M1 is driven by the signal at node X, and the gate of transistor M2 is driven by the signal at node Y. A first buffer B1 has an input that receives the LS_COMP signal output by a comparator COMP. This comparator operates to compare a reference / ground voltage (received at its non-inverting input) with the voltage at the first A / C input node AC1 (received at its inverting input). The output of buffer B1 is connected to the first plate of capacitor C1, with the second plate of capacitor C1 connected to node X. A second buffer B2 has an input that receives the voltage Vgate3 at the gate of low-side transistor Q3 in the first half-bridge. The output of buffer B2 is connected to the first plate of capacitor C2, with the second plate of capacitor C2 connected to node Y. A first diode D1 is connected in series with an NMOS transistor M3 between a low dropout voltage VLDO and a node X. The gate of transistor M3 is driven by an enable signal EN generated by the rectifier control circuit. A second diode D2 is connected in series with an NMOS transistor M5 between a low dropout voltage VLDO and a node Y. The gate of transistor M5 is driven by an enable signal EN. A first resistor R1 is connected in series with an NMOS transistor M4 between node X and a reference / ground voltage. The gate of transistor M4 is driven by a delayed and logically inverted version of the enable signal EN, referred to as ENB, generated by the rectifier control circuit. A second resistor R2 is connected in series with an NMOS transistor M6 between node Y and the reference / ground voltage. The gate of transistor M6 is driven by a delayed and logically inverted enable signal ENB.

[0022] Path 1 has the following operation during normal rectifier / inverter operation (e.g., when drive signals Vgate1 and Vgate3, and drive signals Vgate2 and Vgate4, alternate under the control of the rectifier control circuit, Vgate1 and Vgate2 are never in the same state at the same time, and Vgate3 and Vgate4 are never in the same state at the same time). In response to current flowing through diode D1 / transistor M3 (enabled by signal EN) and diode D1 / transistor M5 (enabled by signal EN), a low dropout voltage VLDO is stored across capacitors C1 and C2. This operation occurs during the period when low-side transistor Q3 in the first half-bridge is off and transistor Q1 is on. In response to the assertion of voltage Vgate3 at the gate of low-side transistor Q3 in the first half-bridge (i.e., a logical 1), transistor Q3 turns on (and transistor Q1 turns off), and the voltage at output node AC1 decreases. Comparator COMP senses when the AC1 voltage drops below the reference / ground voltage and, in response, asserts the LS_COMP signal to a logic 1. At this point in time, both the voltage Vgate3 and the LS_COMP signal are logic 1. The voltages at nodes X and Y are then bootstrapped by the low-dropout voltage VLDO stored across capacitors C1 and C2, respectively, ensuring that both transistors M1 and M2 are fully conductive. The activated transistors M1 and M2 of path 1 pass current to charge the bootstrap capacitor CBOOT1 to the level of the low-dropout voltage VLDO. Comparator COMP then senses when the AC1 voltage rises above the reference / ground voltage as the current direction reverses. In response, the LS_COMP signal is asserted to a logic 0. At this point in time, both the voltage Vgate3 and the LS_COMP signal transition from 1 to 0. Then, the voltages at nodes X and Y are each bootstrapped down by the stored low dropout voltage VLDO across capacitors C1 and C2 to ensure that both transistors M1 and M2 are completely turned off. Transistors M1 and M2 in path 1 are turned off, and the path from VLDO to VBOOT1 is completely removed.

[0023] The rectifier control circuit generates an EN signal at logic 0 when the VLDO voltage output from low-dropout regulator 24 is not ready. Nodes X and Y are fully discharged to ground. Once the VLDO voltage output is ready, the EN signal changes state from logic 0 to logic 1, enabling operation of circuit 40 or circuit 42 to ensure that signals X and Y can be charged to VLDO-Vth (M3 or M5). When nodes X and Y are bootstrapped during operation, diodes D1 and D2 protect nodes X and Y from leaking current to VLDO and discharging.

[0024] Path 2 is defined by p-channel transistors M7 and M8 connected in series, with their sources connected together and their drains connected to the low dropout voltage VLDO and the bootstrap node BOOT1. The gates of transistors M7 and M8 are both driven by the signal at node Z. Resistor R3 is connected between node Z and the common source of transistors M7 and M8. Zener diode Z1 is connected between node Z (at the Zener anode) and the common source of transistors M7 and M8 (at the Zener cathode). NMOS transistor M9 has its drain connected to node Z and its source connected to the reference / ground voltage. The gate of transistor M9 is driven by a logic signal output by a logic circuit (in this case, a three-input AND gate) that logically combines the voltage Vgate3 at the gate of the low-side transistor Q3 in the first half-bridge, the voltage Vgate4 at the gate of the low-side transistor Q4 in the second half-bridge, and a startup charging enable signal (Boot_EN).

[0025] Path 2 operates as follows during rectifier / inverter reset operation. During the rectifier reset period, both transistors Q3 and Q4 are turned on (and both transistors Q1 and Q2 are turned off) in response to voltages Vgate3 and Vgate4, respectively, generated by the rectifier control circuit. In this reset mode of operation, no switching is performed. In response to the assertion of a logic high on the startup charge enable signal Boot_EN, with both Vgate3 and Vgate4 also logic high, the AND gate asserts its output signal logic high and turns on transistor M9. This pulls node Z to the reference / ground voltage, which is then applied to the gates of p-channel transistors M7 and M8. Both transistors M7 and M8 are turned on. The activated transistors M7 and M8 of path 2 pass current to charge the bootstrap capacitor CBOOT1 to the level of the low dropout voltage VLDO. When the rectifier is released from the reset state and operation in the normal switching mode resumes with switching controlled by the signal generated by the rectifier control circuit, both transistor Q3 and transistor Q4 are never on at the same time, and the output of the AND gate is driven to logic low, causing both p-channel transistor M7 and p-channel transistor M8 to turn off to block path 2. The Z point voltage in this case will follow the voltage at the bootstrap node BOOT1.

[0026] It should be noted that path 1 must be designed with transistors M1 and M2 to recharge the bootstrap capacitor CBOOT at twice the maximum frequency of the rectifier / inverter switching operation. The size of the transistors depends on the Ron required to handle the maximum load on the bootstrap node BOOT1. In order to ensure that the voltage difference between the bootstrap node BOOT1 voltage and the output node AC1 voltage is always less than or equal to the low dropout voltage VLDO, the diode drop on path 1 must be greater than the rectifier diode drop during diode operation mode.

[0027] In one embodiment, path 1 can include only transistor M2 (i.e., transistor M1 is missing or bypassed). This circuit solution is just as effective as a solution that includes both M1 and M2 under normal operation. However, transistor M2 must be sized to meet ESD requirements because a path exists from the external pad of the bootstrap node BOOT1 (which supports the connection to the external bootstrap capacitor CBOOT1) to the external pad of the low dropout voltage VLDO through the parasitic diode of transistor M2. Including back-to-back transistor switches M1 and M2 provides circuit designers with the flexibility to size the transistor switches based on the aforementioned recharge and diode voltage drop requirements without encountering the design headaches of ESD constraints. In practice, for the preferred circuit solution, there is no direct ESD path from VLDO to BOOT1, and therefore another solution for ESD protection can be used. As an example, the pad of VLDO can be self-protected (e.g., using a local ESD clamp), and the pad of BOOT1 can be self-protected (e.g., using an appropriate diode or HV ESD clamp on the ESD floating rail).

[0028] It will also be noted that path 2 must be designed with transistors M7 and M8 based on the reset time available to charge the bootstrap capacitor CBOOT1. Many practical situations have very relaxed reset times, which will allow the designer to choose relatively small devices for transistors M7 and M8.

[0029] exist Figure 4B and Figure 5B In an alternative circuit embodiment, resistor R1 is omitted if transistor M4 is directly connected to node X, and resistor R2 is omitted if transistor M5 is directly connected to node Y. Figure 4A and Figure 5A Compared to the circuit configuration of FIG, this circuit configuration has the advantage that, since resistors R1 and R2, which can occupy a considerable area on the die, are omitted, the circuit occupies a smaller integrated circuit area. However, the removal of resistors R1 and R2 raises concerns about leakage current through M3-M4 (and M5-M6) during the logic transitions of signals EN and ENB. To address this issue, a logic circuit is provided to generate signals EN and ENB in ​​a non-overlapping manner.

[0030] Referring now to the circuit's operating waveforms, which show Figure 6 and Figure 7 The voltages VX and VY at the X and Y nodes are bootstrapped according to the comparator output signal and the gate input signal. Even if the rectifier enters diode mode, the voltage difference between the nodes BOOT1 and AC1 will always be maintained at or below the VLDO voltage, which is lower than the SOA threshold.

[0031] This circuit presents several advantages including: a) variations in the power supply for the high-side driver are reduced; b) operation is supported even if the rectified voltage VRECT decreases; and c) both the high-side switch and the low-side switch have the same Vgs.

[0032] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: A rectifier circuit capable of operating in a switching mode and a reset mode, wherein the rectifier circuit comprises: a high-side switching transistor coupled between the input node and the output node; and a high-side driver circuit configured to drive a control terminal of the high-side switching transistor, wherein the high-side driver circuit is powered between a bootstrap node and the input node; a bootstrap capacitor coupled between the bootstrap node and the input node; a startup charging circuit configured to charge the bootstrap capacitor by supplying current to the bootstrap node, wherein the startup charging circuit comprises: a first current path configured to selectively supply a first charging current to the bootstrap node, the first current path being activated in response to the rectifier circuit operating in the switching mode; and A second current path is configured to selectively supply a second charging current to the bootstrap node, the second current path being activated in response to the rectifier circuit operating in the reset mode.

2. The circuit according to claim 1, wherein The input node receives an AC signal, and wherein the output node generates a DC signal.

3. The circuit according to claim 1, wherein The rectifier circuit comprises a series connection of a low-side switching transistor coupled to the high-side switching transistor at the input node, wherein the high-side switching transistor and the low-side switching transistor are coupled between the output node and a ground node, and wherein in the switching mode, the high-side switching transistor and the low-side switching transistor are alternately actuated, and wherein in the reset mode, the high-side switching transistor is off and the low-side switching transistor is on.

4. The circuit according to claim 1, wherein The output node generates a DC signal, and the circuit further includes a voltage regulation circuit powered by the DC signal and configured to generate a regulated voltage.

5. The circuit according to claim 4, wherein The startup charging circuit is powered by the regulated voltage.

6. The circuit according to claim 4, wherein The rectifier circuit comprises a series of low-side switching transistors coupled to the high-side switching transistor at the input node, and wherein the first current path comprises a first transistor and a second transistor coupled in series with each other between the regulated voltage and the bootstrap node, the circuit further comprising: a first gate control circuit configured to generate a first gate signal applied to a gate of the first transistor, wherein the first gate signal is boosted in response to a comparison of a signal at the input node with a reference; and A second gate control circuit is configured to generate a second gate signal applied to a gate of the first transistor, wherein the second gate signal is boosted in response to actuation of the low-side switching transistor.

7. The circuit according to claim 6, wherein The signal at the input node is an A / C signal.

8. The circuit according to claim 6, wherein The output node generates a DC signal, the circuit further comprising a voltage regulation circuit powered by the DC signal and configured to generate a regulated voltage, and wherein the first gate control circuit is enabled for operation in response to the generated regulated voltage.

9. The circuit according to claim 6, wherein The output node generates a DC signal, the circuit further comprising a voltage regulation circuit powered by the DC signal and configured to generate a regulated voltage, and wherein the second gate control circuit is enabled for operation in response to the generated regulated voltage.

10. The circuit according to claim 4, wherein The second current path includes a first transistor and a second transistor coupled in series with each other between the regulated voltage and the bootstrap node, the circuit further comprising: The gate control circuit is configured to generate gate signals applied to the first transistor and the second transistor in response to the rectifier circuit operating in the reset mode.

11. The circuit of claim 10 , wherein the rectifier circuit comprises a series connection of a low-side switching transistor coupled to the high-side switching transistor at the input node, and wherein, The gate control circuit generates the gate signal in response to actuation of the low-side switching transistor during the reset mode.

12. A circuit comprising: a high-side switching transistor coupled between the first node and the second node; a high-side driver circuit configured to drive a control terminal of the high-side switching transistor, wherein the high-side driver circuit is powered between a bootstrap node and the first node; a bootstrap capacitor coupled between the bootstrap node and an input node; a startup charging circuit configured to charge the bootstrap capacitor by supplying current to the bootstrap node, wherein the startup charging circuit comprises: a first current path configured to selectively supply a first charging current to the bootstrap node, the first current path being activated when the high-side switching transistor is driven by the high-side driver circuit in a switching operation mode; and A second current path is configured to selectively supply a second charging current to the bootstrap node, the second current path being activated when the high-side switching transistor is driven by the high-side driver circuit in a reset operation mode.

13. The circuit of claim 12 further comprising a series connection of a low-side switching transistor coupled to the high-side switching transistor at the first node, and wherein In the switching operation mode, the high-side switching transistor and the low-side switching transistor are alternately actuated, and wherein, in a reset mode, the high-side switching transistor is off and the low-side switching transistor is on.

14. The circuit according to claim 13, wherein The first current path includes a first transistor and a second transistor coupled in series with each other between a regulated voltage and the bootstrap node, the circuit further comprising: a first gate control circuit configured to generate a first gate signal applied to a gate of the first transistor, wherein the first gate signal is boosted in response to a comparison of a signal at the first node with a reference; and A second gate control circuit is configured to generate a second gate signal applied to a gate of the first transistor, wherein the second gate signal is boosted in response to actuation of the low-side switching transistor.

15. The circuit of claim 14, wherein: The first gate control circuit is enabled for operation in response to the regulated voltage.

16. The circuit of claim 14, wherein: The second gate control circuit is enabled for operation in response to the regulated voltage.

17. The circuit of claim 14, wherein: The second current path includes a first transistor and a second transistor coupled in series with each other between the regulated voltage and the bootstrap node, the circuit further comprising: The gate control circuit is configured to generate gate signals applied to the first transistor and the second transistor in response to the reset operation mode.

18. The circuit of claim 17 further comprising a series connection of a low-side switching transistor coupled to the high-side switching transistor at the input node, and wherein The gate control circuit generates the gate signal in response to actuation of the low-side switching transistor during the reset mode.

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