Semiconductor device and method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for forming the same. In the embodiment of the present invention, by forming an arc-shaped fin with both sides of the lower end recessed inward, the size of the lower end of the fin is smaller than the size of the upper end, so that when the semiconductor device is turned on, the current on the fin can be evenly distributed to avoid the formation of leakage current. At the same time, the arc-shaped fin can increase the distance between adjacent fins, thereby increasing the area of ​​the non-channel region, avoiding the formation of current between the fins, and further reducing the leakage current. Therefore, the reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a forming method thereof. Background Art

[0002] With the continuous development of semiconductor manufacturing technology, the integration of semiconductor devices is getting higher and higher, and the characteristic size of semiconductor devices is gradually shrinking. However, the reliability of semiconductor devices still needs to be improved. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a semiconductor device and a method for forming the same, so as to improve the reliability of the semiconductor device.

[0004] In a first aspect, a method for forming a semiconductor device provided by an embodiment of the present invention includes:

[0005] Providing a front-end device layer, the front-end device layer comprising a plurality of mutually separated fins and an isolation layer covering a portion of the sidewalls of the fins;

[0006] forming a first oxide layer on the surface of each of the fins and the isolation layer;

[0007] removing the first oxide layer located in the epitaxial layer growth region of each of the fins;

[0008] forming an epitaxial layer on the epitaxial layer growth region of each of the fins;

[0009] The first oxide layer below the epitaxial layer growth region and a portion of the sidewalls of each of the fins are etched so that the size of the region of each of the fins below the epitaxial layer growth region is smaller than the size of the fin in the epitaxial layer growth region.

[0010] Furthermore, the epitaxial layer growth region is a region extending downward from the top of the fin by a predetermined distance.

[0011] Further, the step of forming an epitaxial layer on the epitaxial layer growth region of each of the fins is specifically as follows:

[0012] An epitaxial layer is formed on the epitaxial layer growth region by using an epitaxial process.

[0013] Furthermore, the material of the epitaxial layer is a semiconductor material.

[0014] Furthermore, the thickness of the epitaxial layer is 0.5nm-10nm.

[0015] Further, removing the first oxide layer located in the epitaxial layer growth region of each of the fins includes:

[0016] forming a protective layer on the first oxide layer, wherein the protective layer covers an area below an epitaxial layer growth area of ​​each of the fins;

[0017] removing the first oxide layer not covered by the protective layer;

[0018] The protective layer is removed.

[0019] Further, removing the first oxide layer located in the epitaxial layer growth region of each of the fins includes:

[0020] forming a second oxide layer covering the fin on the first oxide layer;

[0021] The second oxide layer and a portion of the first oxide layer in the epitaxial layer growth region are etched back.

[0022] Furthermore, the material of the first oxide layer is the same as the material of the second oxide layer.

[0023] Further, the etching of the first oxide layer below the epitaxial layer growth region and a portion of the sidewalls of each of the fins is specifically:

[0024] The first oxide layer in the predetermined area and a portion of the fin are etched by an etching process in which an etching rate of the first oxide layer is greater than an etching rate of the fin and the epitaxial layer.

[0025] Further, after etching the first oxide layer below the epitaxial layer growth region and a portion of each of the fins, the method further includes:

[0026] Annealing treatment.

[0027] Furthermore, the size of each of the fins below the epitaxial layer growth region is 0.5 nm-5 nm; the size of each of the fins in the epitaxial layer growth region is 7 nm-10 nm.

[0028] On the other hand, an embodiment of the present invention provides a semiconductor device, the semiconductor device comprising:

[0029] A front-end device layer, the front-end device layer comprising a plurality of mutually discrete fins and an isolation layer covering a portion of the sidewalls of each of the fins, wherein the size of the area of ​​each of the fins below the epitaxial layer growth area is smaller than the size of the fin in the epitaxial layer growth area;

[0030] An epitaxial layer covers the epitaxial layer growth region of each of the fins.

[0031] Furthermore, the epitaxial layer growth region is a region extending downward from the top of the fin by a predetermined distance.

[0032] Furthermore, the material of the epitaxial layer is a semiconductor material.

[0033] Furthermore, the thickness of the epitaxial layer is 0.5nm-10nm.

[0034] Furthermore, the size of each of the fins below the epitaxial layer growth region is 0.5 nm-5 nm; the size of each of the fins in the epitaxial layer growth region is 7 nm-10 nm.

[0035] In the embodiment of the present invention, by forming an arc-shaped fin with both sides of the lower end recessed inward, the size of the lower end of the fin is made smaller than the size of the upper end, so that the current on the fin can be evenly distributed during the conduction of the semiconductor device, avoiding the formation of leakage current. At the same time, the arc-shaped fin can increase the distance between adjacent fins, thereby increasing the area of ​​the non-channel region, avoiding the formation of current between the fins, and further reducing the leakage current. Therefore, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0037] Figure 1-Figure 2 is a schematic cross-sectional view of a fin portion of a semiconductor device of a comparative example;

[0038] Figure 3 is a schematic diagram of the structure of a semiconductor device of a comparative example;

[0039] Figure 4 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0040] Figure 5-Figure 14 is a schematic diagram of a structure formed by each step of a method for forming a semiconductor device according to an embodiment of the present invention;

[0041] Fig.15 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0043] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0044] Unless the context clearly requires otherwise, the words "include", "comprises" and the like throughout the specification should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the present invention, unless otherwise specified, "multi-layer" means two or more layers.

[0045] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For ease of description, spatial relationship terms such as "under," "below," "below," "above," "on," and the like may be used herein to describe the relationship between one element or feature and another element or features as shown in the accompanying drawings.

[0046] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in association with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not necessarily all refer to the same aspect. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

[0047] References throughout the specification to an integrated circuit are generally intended to include integrated circuit components built on a semiconductor substrate, whether or not the components are coupled together into a circuit or are capable of being interconnected. Throughout the specification, the term "layer" is used in its broadest sense to include a film, a capping layer, or the like, and a layer may include multiple sublayers. In addition, references to conventional techniques for thin film formation may include growing films in situ. For example, in some embodiments, controlled growth of an oxide to a desired thickness may be obtained by exposing the silicon surface to oxygen or to moisture in a heated chamber.

[0048] Throughout the specification, conventional etching techniques known in the field of semiconductor manufacturing for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials include, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing (CMP) and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques can be interchangeable. For example, stripping the photoresist can include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly on the sample.

[0049] Semiconductor devices are electronic devices with conductivity between good conductors and insulators. They use the special electrical properties of semiconductor materials to complete specific functions. They can be used to generate, control, receive, transform, amplify signals and perform energy conversion. Commonly used semiconductor devices include field effect transistors (FETs). Field effect transistors have high input resistance (10 8 ~10 9 Ω), low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and wide safe working area.

[0050] As a new type of field effect transistor, Fin Field-Effect Transistor (FinFET) can improve circuit control and further increase the integration of semiconductor devices. The characteristic size of existing FinFETs can reach 7nm. However, the shape of the fins in existing FinFETs leads to uneven current distribution in the fins and large leakage current, resulting in insufficient reliability of semiconductor devices.

[0051] Figure 1 and Figure 2 Schematic diagram of the cross section of the fin of a semiconductor device of a comparative example. Figure 1 and Figure 2 The cross-sectional shape of the fin 1 of the comparative example is a rectangle or a trapezoid that is narrow at the top and wide at the bottom. Figure 3 Schematic diagram of a semiconductor device of a comparative example. Figure 3 As shown, the semiconductor device includes a fin and a gate structure 2 located on the fin, wherein the gate structure covers a portion of the top and sidewalls of the fin. The semiconductor device also includes sidewalls 3 located on both sides of the gate structure and a source region 1a and a drain region 1b in the fin 1 located on both sides of the gate structure 2.

[0052] exist Figure 3In the semiconductor device shown, when it is in the on state, a current is formed in the fin between the source region 1a and the drain region 1b. Since the upper end of the fin is close to the gate, and the upper and lower ends of the fin are similar in size or the upper end of the fin is smaller than the lower end of the fin, the resistance of the upper end of the fin is smaller than the resistance of the lower end of the fin. Therefore, the current is easily concentrated on the upper end of the fin between the source region 1a and the drain region 1b. However, since the current is excessively concentrated on the upper end of the fin, a large leakage current will be caused, reducing the reliability of the semiconductor device. At the same time, the mobility of carriers in the channel region of the existing semiconductor device is relatively small.

[0053] In view of this, in order to improve the reliability of semiconductor devices. An embodiment of the present invention provides a method for forming a semiconductor device. In the embodiment of the present invention, the formation of a fin field effect transistor is used as an example for explanation. Further, the method of the embodiment of the present invention is applied to form a fin field effect transistor below a 7nm process node. It should be understood that the embodiment of the present invention can also be used to form other semiconductor devices. Figure 4 FIG. 1 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the method for forming a semiconductor device according to an embodiment of the present invention comprises the following steps:

[0054] Step S100: providing a front-end device layer, wherein the front-end device layer includes a plurality of mutually separated fins and an isolation layer covering a portion of sidewalls of the fins.

[0055] Step S200: forming a first oxide layer on the surfaces of each of the fins and the isolation layer.

[0056] Step S300 , removing the first oxide layer located in the epitaxial layer growth region of each of the fins.

[0057] Step S400: forming an epitaxial layer on the epitaxial layer growth region of each of the fins.

[0058] Step S500, etching the first oxide layer below the epitaxial layer growth region and part of the sidewalls of each of the fins, so that the size of the region of each of the fins below the epitaxial layer growth region is smaller than the size of the fin in the epitaxial layer growth region.

[0059] In an optional implementation, after step S500, the method for forming a semiconductor device according to an embodiment of the present invention further includes the following steps:

[0060] Step S600: annealing treatment.

[0061] Figure 5-Figure 14 Schematic diagram of the structure formed by each step of the method for forming a semiconductor device according to an embodiment of the present invention. Figure 5As shown, in step S100, a front-end device layer 10 is provided. The front-end device layer 10 includes a plurality of mutually separated fins 11 and an isolation layer 12 covering part of the sidewalls of the fins. Optionally, the front-end device layer 10 also includes a hard mask layer 13 covering the top of the fins 11.

[0062] The front-end device layer 10 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the front-end device layer 10 may also be a silicon on insulator (SOI) substrate, a stacked silicon on insulator (SSOI), a stacked silicon germanium on insulator (S-SiGeOI), a silicon germanium on insulator (SiGeOI), a germanium on insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer or an alloy front-end device layer. The compound front-end device layer includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium, the alloy front-end device layer includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof, the SOI substrate includes a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer or a germanium layer) disposed on an insulating material layer, the semiconductor layer has active devices and passive devices, and the insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. A number of epitaxial interface layers or strained layers and other structures may also be formed on the surface of the front-end device layer to improve the electrical performance of the semiconductor device.

[0063] In an optional implementation, the fins 11 are a plurality of discrete substantially parallel rectangular structures. The material of the fins 11 may be silicon single crystal.

[0064] The material of the isolation layer 12 may be silicon oxide formed by a flow chemical vapor deposition process (FCVD). The isolation layer 12 is used to protect the sidewalls of the covered fin 11 and the surface of the front-end device layer 10 in subsequent processes to prevent the fin 11 and the surface of the front-end device layer 10 from being etched and damaged, thereby ensuring the reliability of the semiconductor device.

[0065] The material of the hard mask layer 13 can be one or more of silicon nitride, silicon oxide spin on carbon (SOC) or spin on hard mask (SOH). The hard mask layer 13 is used as a mask in the process of forming the fin 11 to form the patterned fin 11.

[0066] refer to Figure 6 In step S200 , a first oxide layer 20 is formed on the surfaces of each of the fins 11 and the isolation layer 12 .

[0067] Furthermore, the first oxide layer 20 may be silicon dioxide (SiO2). The first oxide layer may be deposited by atomic layer deposition (ALD) or rapid thermal oxidation (RTO).

[0068] The first oxide layer 20 covers the fin 11 and the isolation layer 12 to protect the fin 11 and the isolation layer 12 .

[0069] refer to Figure 7-Figure 11 In step S300 , the first oxide layer 20 located in the epitaxial layer growth region S of each of the fins 11 is removed.

[0070] The epitaxial layer growth region S is a region extending downward from the top of the fin 11 by a predetermined distance. Further, the predetermined distance is smaller than the distance from the top of the fin to the upper surface of the isolation layer. Further, the predetermined distance may be one third to four fifths of the distance from the top of the fin to the upper surface of the isolation layer.

[0071] In an optional implementation, removing the first oxide layer located in the epitaxial layer growth region of each of the fins comprises the following steps:

[0072] Step S301 : forming a protective layer on the isolation layer, wherein the protective layer covers an area below the epitaxial layer growth region of each of the fins.

[0073] Step S302: removing the first oxide layer not covered by the protective layer.

[0074] Step S303: removing the protective layer.

[0075] refer to Figure 7 In step S301 , a protection layer 21 is formed on the first oxide layer 20 , and the protection layer 21 covers the area below the epitaxial layer growth region S of each of the fins 11 .

[0076] Specifically, the material of the protection layer 21 may be spin-on carbon. The method for forming the protection layer 21 specifically includes first forming a protection material layer covering the sidewall and top of the fin 11, and then etching the protection material layer to expose the epitaxial layer growth region S by an etch-back process.

[0077] The etch-back process may be dry etching or wet etching, and the etch-back rate of the protective layer 21 is greater than the etch-back rate of the first oxide layer 20 .

[0078] refer to Figure 8 In step S302 , the first oxide layer 20 not covered by the protective layer 21 is removed.

[0079] Specifically, a stripping process or an etching process may be used to remove the first oxide layer 20 that is not covered by the protection layer 21 .

[0080] refer to Fig. 9 In step S303, the protective layer 21 is removed.

[0081] The protective layer 21 is removed by a stripping process. The stripping process is to use gas to blow onto the end surface of the substrate to reduce the bonding between the layer and the substrate. Optionally, the gas can be nitrogen or carbon dioxide. Since using oxygen as a stripping gas will damage the first oxide layer, the stripping process does not use oxygen as a stripping gas.

[0082] In another optional implementation, as shown in the figure, removing the first oxide layer located in the epitaxial layer growth region of each of the fins 11 includes the following steps:

[0083] Step S304 , forming a second oxide material layer 40 on the first oxide layer 20 to cover the fin 11 .

[0084] Step S305 , etching back the second oxide material layer 40 and a portion of the first oxide layer 20 above the predetermined region of each of the fins 11 .

[0085] refer to Fig.10 In step S304 , a second oxide layer 40 is formed on the first oxide layer 20 to cover the fin 11 .

[0086] The material of the first oxide layer 20 is the same as the material of the second oxide layer 40. Optionally, the material of the second oxide layer is silicon dioxide.

[0087] Forming the second oxide layer 40 may include first forming a second oxide material layer and then planarizing the second oxide material layer. Optionally, a chemical mechanical polishing process is used to planarize the second oxide material layer.

[0088] The second oxide layer 40 can be formed by a spin coating process, or by a chemical vapor deposition (CVD) method, such as low temperature chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), and fluid chemical vapor deposition (FCVD).

[0089] In an optional implementation, the second oxide layer 40 is formed by a fluid chemical vapor deposition process.

[0090] In another optional implementation, the second oxide layer 40 is formed by a spin coating process. Specifically, tetraethyl orthosilicate (TEOS) is spin coated and baked to form the second oxide layer 40 .

[0091] Forming the second oxide layer by spin coating or fluid chemical vapor deposition process has the advantages of high formation efficiency and good filling effect, and the second oxide layer can be easily removed in subsequent processes.

[0092] refer to Fig.11 In step S305, the second oxide layer 40 and a portion of the first oxide layer 20 in the epitaxial layer growth region S are etched back.

[0093] The second oxide layer 40 is etched back by an etching process in which the etching rate of the first oxide layer 20 and the second oxide layer 40 is greater than the etching rate of the fin 11. Since the first oxide layer 20 and the second oxide layer 40 are made of the same material, the first oxide layer 20 is also partially removed while the second oxide layer 40 is etched back. Specifically, the first oxide layer 20 and the second oxide layer 40 on the epitaxial layer growth region S are etched back and removed.

[0094] The etch-back process may be wet etching. In an optional implementation, the first oxide layer 20 and the second oxide layer 40 may be etched with a hydrofluoric acid aqueous solution.

[0095] Optionally, after removing the protective layer 21 , a plasma reduction process is used to clean the structure formed by the above process to remove surface impurity ions and improve cleanliness to ensure that the epitaxial layer and the fin 11 have better bonding performance in the subsequent epitaxial growth process.

[0096] The cleaning process may include: placing the workpiece under a vacuum condition of 3Pa (the vacuum degree can be less than 4Pa, only 3Pa is taken here for illustration), introducing 100 to 400 ml of inorganic gas per minute, and under the action of the radio frequency power supply, the inorganic gas is decomposed into high-speed ions that impact the surface of the workpiece, forming a gas phase cleaning under vacuum conditions, and the cleaning time is 180 to 360s. The inorganic gas is selected from one or more of O2, H2, N2, Ar2, but is not limited to these gases.

[0097] Optionally, when the material of the hard mask layer 13 is the same as that of the protective layer 21, the hard mask layer 13 is removed while removing the protective layer 21. When the material of the hard mask layer 13 is different from that of the protective layer 21, an etching process in which the etching rate of the hard mask layer 13 is greater than the etching rate of the fin portion can be used to remove the hard mask layer 13.

[0098] refer to Fig.12 and Fig.13 In step S400 , an epitaxial layer 30 is formed on the epitaxial layer growth region S of each of the fins 11 .

[0099] The material of the epitaxial layer 30 is a semiconductor material. The forming of the epitaxial layer on the epitaxial layer growth region S of each of the fins 11 is specifically to form the epitaxial layer 30 on the epitaxial layer growth region S using an epitaxial process. Optionally, a semiconductor material, such as silicon (Si), germanium (Ge) or silicon germanium (SiGe), is epitaxially grown in the epitaxial layer growth region S of each of the fins 11. In which, in-situ doping can be performed during epitaxial growth, such as doping with phosphorus (P) or boron (B). In an optional implementation, the material of the epitaxial layer 30 is germanium.

[0100] The epitaxial growth process may be an etching method known to those skilled in the art, such as vapor phase epitaxy (VPE), liquid phase epitaxy (Liquid-Phase Epitaxy), molecular beam epitaxy (MBE), and ion beam epitaxy (IBE). The epitaxial layer 30 formed by the epitaxial growth process has a good combination with the fin 11.

[0101] The thickness of the epitaxial layer 30 is 0.5 nm-10 nm. Optionally, the thickness of the epitaxial layer 30 is 5 nm.

[0102] In an optional implementation, a vapor phase epitaxy process is used to epitaxially grow an epitaxial layer 30 made of germanium on the epitaxial layer growth region S of the fin 11. The thickness of the epitaxial layer 30 is 6 nm.

[0103] In the embodiment of the present invention, an epitaxial layer 30 is formed on the epitaxial layer growth region S of the fin 11. The epitaxial layer 30 is used to form a channel layer at the upper end of the fin 11, which can improve the carrier migration rate. The epitaxial layer is equivalent to being integrated with the fin 11, so that the size of the upper end of the fin 11 is larger than the size of the bottom end of the fin 11. This is to facilitate the formation of a fin of a specific shape in the subsequent process, so as to improve the defect of excessive leakage current caused by the fin shape in the comparative example.

[0104] refer to Fig.14 In step S500, the first oxide layer 20 below the epitaxial layer growth region S and part of the sidewalls of each fin 11 are etched so that the size of the region below the epitaxial layer growth region S of each fin 11 is smaller than the size of the fin 11 in the epitaxial layer growth region S.

[0105] In another optional implementation, while etching the first oxide layer 20 below the epitaxial layer growth region S and a portion of the sidewalls of each of the fins 11 , the second oxide layer 40 is also etched.

[0106] An etching process with a much lower etching rate for the epitaxial layer than the etching rate for the first oxide layer is selected to protect the upper end of the fin and form the fin into a specific shape. At the same time, an etching process with a low etching selectivity for the first oxide layer 20 and the fin 11 is selected to remove the first oxide layer 20 and part of the fin 11 at the same time. A dry etching process can be used to etch the first oxide layer 20 below the epitaxial layer growth region S and part of the sidewalls of each of the fins 11. Further, a plasma etching process can be used. Specifically, the etching gas can be selected according to the selected material. Trifluoromethane (CHF3), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), carbon tetrafluoride (CF4) / oxygen (O2) and carbon tetrafluoride (CF4) / hydrogen (H2) can be selected as etching gases. In an embodiment of the present invention, sulfur hexafluoride is used as the etching gas, and the etching pressure can be 5 to 300 mTorr, preferably 8 to 10 mTorr.

[0107] After etching, Fig.11 As shown, an arc-shaped side surface concave inward is formed on the fin 11 in the area below the epitaxial layer growth area S. The size of each fin 11 in the area below the epitaxial layer growth area S can be 0.5nm-5nm; the size of each fin 11 in the epitaxial layer growth area S can be 7nm-10nm. Fig.11The width of the fin 11 at different positions in the cross section shown. In an optional implementation, the minimum size of each fin 11 below the epitaxial layer growth region S may be 4 nm; the size of each fin 11 in the epitaxial layer growth region S may be 8 nm.

[0108] The formation of the fin with curved side is mainly due to the fact that during the etching process, the positively charged ions are accelerated by the dark area electric field to achieve physical bombardment of the target. During the bombardment process, the plasma will reflect and other phenomena, so that the etching rates of the fins in different areas are different, especially in the middle part of the fin below the epitaxial layer, there will be a certain concentration of reflected plasma, so that the surface of the fin not covered by the epitaxial layer forms an arc with a more etched middle part. The curved fin can avoid the current of the semiconductor device mainly distributed at the upper end of the fin due to the fin shape in the comparative example during the conduction process of the semiconductor device, so that the current on the fin can be evenly distributed to avoid the formation of leakage current. At the same time, the curved fin can increase the distance between adjacent fins, thereby increasing the area of ​​the non-channel area, avoiding the formation of current between the fins, and further reducing the leakage current.

[0109] In another optional implementation, the etching process may also be wet etching. Specifically, a hydrofluoric acid aqueous solution may be used to etch the first oxide layer 20 and the second oxide layer 40. During the etching process, since the concentration of the etching solution changes in a gradient, the etching rates for different parts will also be different, and an inwardly concave arc structure will also be formed on the fin below the epitaxial layer.

[0110] It should be understood that the drawings of the present application use an arc shape as an example to illustrate the shape of the formed fin, but the shape actually formed may be an irregular shape or other different arc shapes.

[0111] In step S600, annealing treatment is performed.

[0112] Optionally, the structure formed by the above steps is annealed at 200° C.-600° C. Through the annealing process, the bonding performance between the epitaxial layer 30 and the fin 11 is improved.

[0113] In the subsequent process, the "gate first" or "gate last" (dummy gate replacement) technology is used to form a gate structure surrounding the two sides and the upper surface of the fin. And source and drain regions are formed in the fins on both sides of the gate structure. And an interconnection structure connecting the gate structure and the source and drain regions is formed to form a complete semiconductor device.

[0114] In the embodiment of the present invention, by forming an arc-shaped fin with both sides of the lower end recessed inward, the size of the lower end of the fin is made smaller than the size of the upper end, so that the current on the fin can be evenly distributed during the conduction of the semiconductor device, avoiding the formation of leakage current. At the same time, the arc-shaped fin can increase the distance between adjacent fins, thereby increasing the area of ​​the non-channel region, avoiding the formation of current between the fins, and further reducing the leakage current. Therefore, the reliability of the semiconductor device can be improved.

[0115] On the other hand, an embodiment of the present invention further provides a semiconductor device. Fig.15 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0116] like Fig.15 As shown, the semiconductor device includes: a front-end device layer 10 ′ and an epitaxial layer 30 ′.

[0117] The front-end device layer 10 ′ includes a plurality of mutually separate fins 11 ′, wherein the size of each fin 11 ′ below the epitaxial layer growth region S′ is smaller than the size of the fin 11 ′ in the epitaxial layer growth region S′.

[0118] The front-end device layer 10' may be a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the front-end device layer 10' may also be a silicon on insulator (SOI) substrate, a stacked silicon on insulator (SSOI), a stacked silicon germanium on insulator (S-SiGeOI), a silicon germanium on insulator (SiGeOI), a germanium on insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer or an alloy front-end device layer. The compound front-end device layer includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium, the alloy front-end device layer includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof, the SOI substrate includes a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer or a germanium layer) disposed on an insulating material layer, the semiconductor layer has active devices and passive devices, and the insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. A number of epitaxial interface layers or strained layers may also be formed on the surface of the front-end device layer 10 ′ to improve the electrical performance of the semiconductor device.

[0119] The epitaxial layer growth region S' is a region extending downward from the top of the fin 11' by a predetermined distance.

[0120] like Fig.15As shown, an arc-shaped side surface concave inward is formed on the fin 11' below the epitaxial layer growth region S'. The size of each fin 11' below the epitaxial layer growth region S' is 0.5nm-5nm; the size of each fin 11' in the epitaxial layer growth region S' is 7nm-10nm. Fig.11 The width of the fin at different positions in the cross section shown. In an optional implementation, the minimum size of each fin 11' below the epitaxial layer growth region S' may be 4nm; the size of each fin 11' in the epitaxial layer growth region S' may be 8nm.

[0121] The curved fins can avoid the current of the semiconductor device being mainly distributed on the upper end of the fins due to the fin shape in the comparative example during the conduction process, so that the current on the fins can be evenly distributed to avoid the formation of leakage current. At the same time, the curved fins can increase the distance between adjacent fins, thereby increasing the area of ​​the non-channel region, which can avoid the formation of current between the fins and further reduce the leakage current.

[0122] The epitaxial layer 30 ′ covers the epitaxial layer growth region S′ of each of the fins.

[0123] The epitaxial layer growth region S' is a region extending downward from the top of the fin by a predetermined distance.

[0124] The material of the epitaxial layer 30' is a semiconductor material. The material of the epitaxial layer 30' may include silicon (Si), germanium (Ge) or silicon germanium (SiGe). At the same time, the epitaxial layer 30' also includes doped ions, which may include phosphorus (P) or boron (B). In an optional implementation, the material of the epitaxial layer 30' is germanium.

[0125] The thickness of the epitaxial layer 30' is 0.5nm-10nm. Optionally, the thickness of the epitaxial layer 30' is 5nm.

[0126] In an optional implementation, the epitaxial layer 30' is made of germanium and has a thickness of 6 nm.

[0127] The epitaxial layer 30 ′ is used to form a channel layer at the upper end of the fin 11 , which can improve the migration rate of carriers.

[0128] In the embodiment of the present invention, by forming an arc-shaped fin with both sides of the lower end recessed inward, the size of the lower end of the fin is made smaller than the size of the upper end, so that the current on the fin can be evenly distributed during the conduction of the semiconductor device, avoiding the formation of leakage current. At the same time, the arc-shaped fin can increase the distance between adjacent fins, thereby increasing the area of ​​the non-channel region, avoiding the formation of current between the fins, and further reducing the leakage current. Therefore, the reliability of the semiconductor device can be improved.

[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: The method comprises: Providing a front-end device layer, the front-end device layer comprising a plurality of mutually separated fins and an isolation layer covering a portion of the sidewalls of the fins; forming a first oxide layer on the surface of each of the fins and the isolation layer; Removing a first oxide layer located in an epitaxial layer growth region of each of the fins, wherein the epitaxial layer growth region is a region extending downward from the top of the fin by a predetermined distance; forming an epitaxial layer on the epitaxial layer growth region of each of the fins; The first oxide layer below the epitaxial layer growth region and a portion of the sidewalls of each of the fins are etched so that the size of the region of each of the fins below the epitaxial layer growth region is smaller than the size of the fin in the epitaxial layer growth region.

2. The method for forming a semiconductor device according to claim 1, wherein: The step of forming an epitaxial layer on the epitaxial layer growth region of each of the fins specifically comprises: An epitaxial layer is formed on the epitaxial layer growth region by using an epitaxial process.

3. The method for forming a semiconductor device according to claim 1, wherein: The material of the epitaxial layer is semiconductor material.

4. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the epitaxial layer is 0.5nm-10nm.

5. The method for forming a semiconductor device according to claim 1, wherein: The removing of the first oxide layer located in the epitaxial layer growth region of each of the fins comprises: forming a protective layer on the first oxide layer, wherein the protective layer covers an area below an epitaxial layer growth area of ​​each of the fins; removing the first oxide layer not covered by the protective layer; The protective layer is removed.

6. The method for forming a semiconductor device according to claim 1, wherein: The removing of the first oxide layer located in the epitaxial layer growth region of each of the fins comprises: forming a second oxide layer covering the fin on the first oxide layer; The second oxide layer and a portion of the first oxide layer in the epitaxial layer growth region are etched back.

7. The method for forming a semiconductor device according to claim 6, wherein: The material of the first oxide layer is the same as the material of the second oxide layer.

8. The method for forming a semiconductor device according to claim 1, wherein: The etching of the first oxide layer below the epitaxial layer growth region and a portion of the sidewalls of each of the fins is specifically as follows: The first oxide layer in a predetermined area and a portion of the fin are etched by an etching process in which the etching rate of the first oxide layer is greater than the etching rate of the fin and the epitaxial layer.

9. The method for forming a semiconductor device according to claim 1, wherein: After etching the first oxide layer below the epitaxial layer growth region and a portion of each of the fins, the method further includes: Annealing treatment.

10. The method for forming a semiconductor device according to claim 1, wherein: The size of each fin below the epitaxial layer growth region is 0.5 nm-5 nm; the size of each fin in the epitaxial layer growth region is 7 nm-10 nm.

11. A semiconductor device, characterized in that: The semiconductor device comprises: A front-end device layer, the front-end device layer comprising a plurality of mutually discrete fins and an isolation layer covering a portion of the sidewalls of each of the fins, wherein the size of the area of ​​each of the fins below the epitaxial layer growth area is smaller than the size of the fin in the epitaxial layer growth area; An epitaxial layer, the epitaxial layer covers the epitaxial layer growth region of each of the fins, the epitaxial layer growth region is a region extending downward from the top of the fin by a predetermined distance, and the epitaxial layer is used to form a channel layer.

12. The semiconductor device according to claim 11, characterized in that The material of the epitaxial layer is semiconductor material.

13. The semiconductor device according to claim 11, characterized in that The thickness of the epitaxial layer is 0.5nm-10nm.

14. The semiconductor device according to claim 11, characterized in that The size of each fin below the epitaxial layer growth region is 0.5 nm-5 nm; the size of each fin in the epitaxial layer growth region is 7 nm-10 nm.

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