System, method and apparatus for executing instructions

Abstract

A system, apparatus, and method for sequencing a sequence of processing transactions. The method includes accessing a program sequence of operations to be performed from a memory. Instructions are received, some of which have identifiers or mnemonics for distinguishing those identified operations from other operations without identifiers or mnemonics. The mnemonics indicate assignment of execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonics to separate certain operations from other operations.

Description

Technical Field

[0001] The present disclosure relates to an instruction set architecture (ISA) for a programmable data processing apparatus. More particularly, the ISA includes barrier instructions that a processor uses to separate memory operations and enable merging of some memory operations while prohibiting merging of other memory operations. Background Art

[0002] In many instruction execution systems, it is desirable to coalesce memory accesses. However, while memory coalescing generally has certain efficiency advantages, in some cases instructions may be grouped such that coalescing is not desirable.

[0003] As computing systems have evolved, some existing barrier instruction techniques have been developed to restrict memory accesses to prevent unwanted memory accesses from occurring. Typically, existing barrier instruction techniques attempt to achieve instruction ordering by enforcing memory ordering, but such enforcement is too slow and places unnecessary burden on device memory. Attempting to change the memory system to participate in the semantics of existing barriers is extremely difficult and unreasonable. In addition, existing barriers for I / O memory accesses have a detrimental performance impact because they can cause pipeline stalls or delays while waiting for confirmation from a connection between a processor and memory (e.g., a PCI root complex). Summary of the invention

[0004] According to a first aspect of the present disclosure, a method for distinguishing memory operations in a programmable data processor is provided, comprising: accessing a program sequence of instructions to be executed by a processor from a memory, the instructions including a barrier instruction; identifying a mnemonic of the barrier instruction, the mnemonic indicating that there is a difference in the program sequence of the instructions; assigning a metadata tag to memory operations generated by a first group of instructions accessed before the barrier instruction; updating the metadata tag in response to executing the barrier instruction; assigning the updated metadata tag to memory operations generated by a second group of instructions accessed after the barrier instruction; and distinguishing between the first group of instructions and the second group of instructions based on the metadata tag, the distinction comprising allowing memory operations generated by instructions in at least one of the first group of instructions and the second group of instructions to be merged, while preventing memory operations generated by instructions in different groups from being merged.

[0005] According to a second aspect of the present disclosure, a method for distinguishing memory operations in a programmable data processor is provided, comprising: receiving a first group of one or more instructions; receiving a first instruction for distinguishing memory accesses; receiving a second group of one or more instructions; associating a first metadata value with a memory operation generated by an instruction in the first group of instructions, the first metadata value being based on a counter value; implementing the first instruction by incrementing the counter; associating a second metadata value with a memory operation generated by an instruction in the second group of instructions, the second metadata value being based on the incremented counter value; comparing metadata data values ​​of the first memory operation and the second memory operation, so that: when the metadata value of the first memory operation matches the metadata value of the second memory operation, the first memory operation and the second memory operation are merged with the matching metadata value; and when the metadata value of the first memory operation is different from the metadata value of the second memory operation, the first memory operation and the second memory operation are prevented from being merged with the mismatched metadata values.

[0006] According to a third aspect of the present disclosure, a programmable data processing device is provided, comprising: a memory; and a processor, coupled to the memory and configured to: access a program sequence of instructions to be executed from the memory, some of the instructions having mnemonics, the mnemonics indicating that the program sequence of the instructions is distinguished; identify instructions having the mnemonics; assign metadata tags to memory operations generated by a first group of instructions accessed before the instructions having the mnemonics; update the metadata tags in response to executing the instructions having the mnemonics; assign the updated metadata tags to memory operations generated by a second group of instructions accessed after the instructions having the mnemonics; and distinguish between the first group of instructions and the second group of instructions based on the metadata tags, the distinction comprising allowing memory operations generated by instructions in at least one of the first group of instructions and the second group of instructions to be merged, while preventing memory operations generated by instructions in different groups from being merged.

[0007] According to a fourth aspect of the present disclosure, a programmable data processing device is provided, comprising: a memory; and a processor, coupled to the memory and configured to: receive a first group of one or more instructions; receive a first instruction to distinguish memory access; receive a second group of one or more instructions; associate a first metadata value with a memory operation generated by an instruction in the first group of instructions, the first metadata value being based on a counter value; implement the first instruction by incrementing the counter; associate a second metadata value with a memory operation generated by an instruction in the second group of instructions, the second metadata value being based on the incremented counter value; compare metadata data values ​​of the first memory operation and the second memory operation, so that: when the metadata value of the first memory operation matches the metadata value of the second memory operation, the first memory operation and the second memory operation are merged with the matching metadata value; and when the metadata value of the first memory operation is different from the metadata value of the second memory operation, the first memory operation and the second memory operation are prevented from being merged with the mismatched metadata values. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a visual representation, which will be used to more fully describe the various representative embodiments and can be used by those skilled in the art to better understand the disclosed representative embodiments and their inherent advantages. In these drawings, the same reference numerals identify corresponding elements.

[0009] Figure 1 A block diagram of a system according to the present disclosure is shown.

[0010] Figure 2 An example of a flow chart that may be used in accordance with various representative embodiments is shown.

[0011] Figure 3 An example of a flow chart that may be used in accordance with various representative embodiments is shown.

[0012] Figure 4 An example of a flow chart that may be used in conjunction with hardware according to various representative embodiments is shown.

[0013] Figure 5 Examples of buffers are shown in accordance with various representative embodiments.

[0014] Figure 6 Examples of memory modules are shown in accordance with various representative embodiments.

[0015] Figure 7 A flow chart according to an embodiment is shown.

[0016] Although the present disclosure may be embodied in many different forms, specific embodiments are shown in the drawings and will be described in detail herein, it should be understood that the present disclosure is to be considered as an example of the principles described and is not intended to be limited to the specific embodiments shown and described. In the following description, the same reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings. DETAILED DESCRIPTION

[0017] In this document, relational terms such as first and second, top and bottom, etc. may be used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between those entities or actions. The terms "comprise," "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitations, an element beginning with "comprises..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0018] In this document, references to "one embodiment," "some embodiments," "an embodiment," or similar terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of such phrases throughout this specification or in various places are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0019] As used herein, the word "or" shall be interpreted as an inclusive or meaning any one or any combination. Thus, "A, B or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". An exception to this definition will only occur if the combination of elements, functions, operations or actions are inherently mutually exclusive in some way.

[0020] For simplicity and clarity of illustration, reference numerals may be repeated between the drawings to indicate corresponding or similar elements. Many details are set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other instances, well-known methods, processes, and components are not described in detail to avoid obscuring the embodiments. This description should not be considered to be limited to the scope of the embodiments described herein.

[0021] The following terms may be used in the description of various embodiments of the present disclosure.

[0022] Auxiliary: additional, supplementary.

[0023] Barrier instruction: An instruction that causes the CPU or compiler to distinguish between memory operations resulting from instructions accessed before and after the barrier instruction.

[0024] Buffer: A temporary storage area, usually in RAM. The purpose of most buffers is to act as a holding area, allowing the CPU to manipulate data before transferring it to the device.

[0025] Cache: Cache memory, also known as CPU memory, is random access memory (RAM) that can be accessed faster by a computer microprocessor than regular RAM. This memory is usually integrated directly with the CPU chip or is placed on a separate chip that is separated from the CPU by a bus interconnect. Cache memory is a small, volatile computer memory that provides high-speed data access to the processor and stores frequently used computer programs, applications, and data. It stores and retains data only until the computer is started.

[0026] Merge: Merge two instructions of similar type. The merge can be done when there are two similar instructions to execute and the block is freed, or it can be postponed to a later time (called a delayed merge), or it may not be done at all.

[0027] CPU: Central Processing Unit; an electronic circuit in a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic, control, and input / output (I / O) operations specified by the instructions.

[0028] Execution: The basic operating process of a computer. It is the process by which a computer retrieves program instructions from its memory, determines the actions indicated by the instructions, and performs those actions. The central processing unit (CPU) repeats this cycle continuously from the time the computer is turned on until it is shut down.

[0029] Flowchart: A type of diagram that represents an algorithm, workflow, or process. A flowchart shows the operations or actions of a method as various types of boxes and their sequence.

[0030] Granularity: The degree to which a system consists of independent components (such as particles). The more components a system has, or the greater its granularity, the more flexible it is.

[0031] Interface: A hardware connection or user interface. Interface can also be used as a verb to describe how two devices connect to each other. Hardware interfaces are used to connect two or more electronic devices together.

[0032] Load Queue: A sequence of work objects waiting to be processed.

[0033] Metadata: Additional data that usually summarizes basic information about the data and makes it easier to find and use a specific instance of the data.

[0034] Microarchitecture: Computer organization, the way a given instruction set architecture (ISA) is implemented in a specific processor.

[0035] Mnemonic: A name or identifier or code that is shorter in length but provides the same functionality as the original.

[0036] I / O: Input / Output, the transfer of data between the processor and peripheral devices in a data processing system. I / O devices may include keyboards, displays, pointing devices, etc., which may be coupled directly or through an intermediate I / O controller.

[0037] Module: A component or part of a program or device that may consist of hardware or software, or a combination of hardware and software. In a module that includes software, the software may consist of one or more routines or subroutines. One or more modules may make up a program and / or device.

[0038] Monotonic: Sorting schemes among ordered sets that preserve or reverse a given order.

[0039] Operation: A single action performed by the computer during the execution of a program.

[0040] Sort tag: A type of metadata that helps describe an item and allows it to be found again through browsing or searching.

[0041] Peripheral: A computer device, such as a keyboard or printer, that is not an integral part of the computer (i.e., memory and microprocessor). These auxiliary devices are usually intended to be connected to the computer.

[0042] Source code: Any collection of code written in a human-readable programming language, usually in plain text, possibly with comments. A program's source code is designed to facilitate the work of computer programmers, who write source code to specify actions for the computer to perform. Typically, the source code is converted by an assembler or compiler into binary machine code that the computer can understand. The machine code can then be stored for later execution. Alternatively, the source code can be interpreted and therefore executed immediately.

[0043] Storage Queue: A sequence of work objects being stored.

[0044] Embodiments of the present disclosure utilize a memory location for a storage operation. A new instruction is received at the memory location, the instruction having the mnemonic "SEP" (standing for "Separate"). The behavior of the instruction is to prevent memory accesses made before the instruction in a program order or program sequence from combining with memory accesses made after the instruction.

[0045] Although in some commercial CPU architectures, memory merging behavior is micro-architectural, i.e., not exposed to programming interfaces, some control over memory and instructions may help in efficient communication with I / O devices. This provides a degree of control over the execution of program sequences or instruction sequences and can reduce latency by an order of magnitude without causing any pipeline stalls. The embodiments described herein are particularly useful because performance is significantly improved with minimal or no implementation modifications to the memory system.

[0046] An embodiment of the present disclosure proposes a barrier instruction technology, which separates memory operations based on the efficiency of merging some memory operations or the efficiency of suppressing the merging of some memory operations.

[0047] This barrier instruction with a mnemonic (separate or "SEP") is implemented by specifying that a stage exists after the "execute" memory operation, during which memory interactions are buffered and possibly merged. This stage is designated as the memory stage ("MEM"). In practice, the stage memory or MEM can be architectural, micro-architectural, or non-architectural, depending on the memory model. For example, an architectural embodiment can be used for Total Store Ordering. Non-architectural embodiments can be used for other ordering models.

[0048] In any of the architectural, microarchitectural, or non-architectural embodiments, barrier instructions with a mnemonic may be enforced by assigning a metadata value to each memory operation, which barrier instruction may be identified as a separation or "SEP." The metadata may be a phase color or ordering tag, or an unsigned integer, or other suitable tag, identifier, or indicator.

[0049] In one embodiment, the mnemonic SEP increments a monotonically increasing counter that is used to assign sequential tags to memories / operations. The SEP itself does not perform any memory functions. Therefore, this tag can be applied immediately after the decode stage so that it does not affect potential out-of-order memory operations (i.e., the SEP mnemonic does not enforce ordering, so multiple memory operations after the SEP can be executed and merged before the SEP commits). In such an embodiment, the MEM stage only merges memory operations of the same metadata tag, thereby satisfying the required semantics, but the mnemonic SEP does not require micro-op generation, renaming, issuance, or execution.

[0050] This concept can be extended by one or more operands that restrict which memory operations the instruction affects, for example, only write / store instructions.

[0051] In addition, another embodiment disclosed herein is a memory operation, such as a "write" operation, or other operation performed on memory. In this embodiment, the programmer can control execution to stop at the memory stream. This can be implemented in the CPU by using a memory stage identifier that increases by "1" each time there is a command. Only operations that share the same identifier are combined.

[0052] Figure 1 A system 100 is shown that includes a first module 110 that is operably coupled to various peripheral / auxiliary modules 114(a)...(n) (where "n" is any suitable number commensurate with the system 100) via a bidirectional communication bus 112(a)...(n) (where "n" is any suitable number commensurate with the system 100). Each of these elements will be described in greater detail herein.

[0053] Module 110 includes memory 102 operatively coupled to processor 106 via interface 104. Processor 104 is operatively coupled to memory module 130(a), I / O module 130(b), and peripheral / auxiliary module 130(n) via associated interfaces 126(a), (b) ... (n), respectively, where "n" is any suitable number.

[0054] Memory module 102 is coupled to or includes additional memory locations or memory modules including, for example: buffer 116; load queue 118; store queue 120; and cache memory 122. Although four supplemental memory modules 116, 118, 120, and 122 are shown, any suitable number of supplemental memory modules may be used.

[0055] The buffer module 116 may be used to buffer various instructions received at the memory module 102. The buffer 116 acts as a holding area, enabling the CPU to manipulate data before transferring the data to a module or device.

[0056] The load queue module 118 is used to store instructions to be executed.

[0057] The storage queue 120 is used to store instructions that can be accessed and processed.

[0058] Memory module 102 is operatively coupled to processor 106 via interface 104 and may utilize memory modules 122, 116, 118, and 120. Interface 104 may be any suitable interface, such as an AXI interface, which is implemented by The interface 104 provides a hardware interface to connect the memory module 102 and the processor 106 so that information and data as well as communication and control signals can be exchanged.

[0059] The processor module 106 may be any suitable processor having a CPU with sufficient processing power to perform sorting based on a model, rule, or algorithm that may be stored in a memory such as a cache memory or may be accessed from a remote memory by the processor module 106. The processor module 106 is capable of storing instructions, codes, algorithms, models, and other operating and execution parameters.

[0060] As used herein, the term "processor" may include or utilize programmable hardware, such as: computers, microcontrollers, embedded microcontrollers, microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs). These hardware examples may be further combined to implement the desired functional controller modules. Computers, microcontrollers, and microprocessors may be programmed using languages ​​such as assembly, C, C++, C#, etc. FPGAs, ASICs, and CPLDs are typically programmed using hardware description languages ​​(HDLs) such as VHSIC Hardware Description Language (VHDL) or Verilog, which configure the connections between internal hardware modules on programmable devices with fewer functions.

[0061] The processor module 106 is operatively coupled to one or more modules 130(a)...(n) via an associated interface or bus 126(a)...(n), where "n" is any suitable number.

[0062] A first module 110, including a memory 102, a processor 106, and associated modules 130 (collectively), is operably coupled to a plurality of peripheral / auxiliary modules 114(a)...(n) (where "n" is any suitable number) via associated bidirectional interfaces or buses 112(a)...(n), respectively.

[0063] The peripheral / auxiliary module 114 may be any I / O (input / output), computer peripheral device, such as a mouse, keyboard, printer, port, etc., or auxiliary storage or auxiliary processor commensurate with the system 100 .

[0064] Figure 2 A flow chart 200 is shown according to an embodiment. The series of acts 200 may be stored in any suitable programming language in a non-volatile memory or other suitable storage or computer usable medium.

[0065] Figure 2 The series of actions shown in FIG. 1 are stored in the memory 102, such as Figure 2 As shown, and as Figure 2 As shown, it can be executed by the processor 106.

[0066] like Figure 2 As shown, the algorithm begins (202). A program order or sequence is accessed (204). An instruction is received or accessed, typically via an interface (206). The instruction is evaluated to determine whether the instruction includes a group change indicator (208), which can be a mnemonic or a "start / stop" command or symbol. The group change sequence indicator can be any one of a plurality of indicators. The group change indicator modifies the sequence of memory operations. One embodiment includes the indicator as a mnemonic, wherein the mnemonic is a command or metadata. As another embodiment, the indicator is a start / stop indicator.

[0067] Instructions with indicators are used to distinguish the allocation of memory to operations. The allocation is usually based on mnemonics or other identifiers. Such allocation of memory to operations usually involves grouping the operations, so that a first group consisting of one or more first operations is different from one or more second operations.

[0068] In fact, as an embodiment, the second group of operations may be an open group, in that these operations will be processed after the operations in the first group are processed.

[0069] If it is determined (208) that the instruction does not include a sequence change indicator (210), then operation (212) is performed. After operation (212) is performed, it is determined whether there is another instruction (216). If so (218), then the next instruction (206) is typically received from the interface. If there are no other instructions, then the algorithm ends (270).

[0070] If it is determined (208) that there is a sequence modification indicator (222) as part of the received instruction, then the sequence of program operations is modified (224). A command is issued (226) to perform any of the following operations: stop; start; insert a barrier; or modify the sequence of operations depending on the type of sequence modification indicator or the command associated with it. The indicator may or may not actually perform any command control function and may simply act as a pointer. For example, a "SEP" may not perform any memory function but simply update a counter so that subsequent memory operations obtain different metadata tags.

[0071] Modify the program sequence, which may generally be a memory manipulation (228). This memory manipulation or modification may include, for example, merging certain instructions, preventing certain instructions from merging, starting execution, stopping execution, or any other modification or change in the order of execution of instructions or other memory operations.

[0072] At this point in the algorithm, many different embodiments can be implemented. One embodiment is to assign a metadata tag or value to the memory operation (230). This metadata tag or value can be viewed as a phase color or sorting tag, or an unsigned integer assigned from a counter (such as a monotonically increasing counter). The tag is then applied to the memory operation (232).

[0073] Additionally, as described above, the value may be an unsigned integer assigned, for example, by a monotonically increasing counter (234). In this embodiment, the SEP does not actually perform any memory functions, but is simply used to increment a counter in order to assign a different metadata tag to subsequent memory operations. Thus, this tag may be applied immediately after the decode stage. Thus, the SEP does not enforce ordering, allowing multiple memory operations after the SEP to be executed and merged before the SEP commits. In this embodiment, the buffer stage or MEM stage will only merge memory operations with the same metadata tag. This satisfies the desired semantics, but the SEP does not need to generate micro-ops, nor rename, issue, or execute.

[0074] In yet another embodiment, a "start / stop" command (236) may be identified in a pipelined manner. In this pipelined process, the command is used to distinguish boundary conditions. This boundary condition is used to manipulate the processing sequence or order and can be used to identify or act as a barrier instruction.

[0075] Regardless of whether there is a tag (232), counter (234), or command (236), the identifier (232), (234), (236) is compared (238) to a predetermined criterion or other metric. For example, when metadata tags are used, the metadata tag of one operation can be compared to the metadata tag of another operation. In addition, the counter value of one operation can be compared to the counter value of another operation. In addition, the command "start" or "stop" can be recognized as starting an operation or stopping an operation.

[0076] Based on the results of the comparison (238), a match is determined, or an actuation or function is activated (248). If it is determined that there is a match or there is no barrier, memory merging may occur (252). If there is no match, or there is a barrier, memory merging does not occur (258).

[0077] After an operation has been performed, whether merged (252) or not merged (258), the operation may be renamed.

[0078] A determination is made as to whether there are further instructions (216). If so (218), then the next instruction is typically received from the interface (206). If there are no further instructions, then the algorithm ends (270).

[0079] Figure 3 An exemplary algorithm or flow chart 300 that may be used in accordance with embodiments of the present disclosure is shown. The flow chart 300 may be stored in any suitable programming language in a non-volatile memory or other suitable storage or computer usable medium.

[0080] The algorithm starts (302) and a first instruction is received at a processor, typically via an interface (304). A second instruction is received at the processor, typically via an interface (306). An indicator is associated with the first instruction (308). Typically, this indicator can be metadata, a metadata tag, a metadata value, a command ("start / stop"), or an incremental value.

[0081] The indicator associated with the first instruction may be modified, updated, or changed (308) such that the new indicator is associated with the second instruction (312). In one embodiment, the first indicator will be the same as the second indicator in some instances. In practice, the indicator associated with the second instruction may be such that it indicates a match between the instruction type of the first instruction and the instruction type of the second instruction.

[0082] The use of the indicator associated with the first instruction and the indicator associated with the second instruction allows the indicators to be compared or analyzed (314) to determine if a barrier instruction is present or if the indicator results in a change in program sequence or a change in the order in which operations are performed.

[0083] The comparison is used to determine whether the indicators match (316) or otherwise indicate whether the execution order should be changed. If the result of the determination (316) is that the indicators do not match, or an execution modification identifier is present (318), the memory operations are not merged (320).

[0084] If the result of the determination (316) is that the indicators match, or that the execution modification identifier (324) is not present, then the memory operations are merged (326).

[0085] After the memory is merged (326) or not merged (320), the indicator may be renamed for use in subsequent instructions.

[0086] A determination is made as to whether there are more instructions (330), and if so (334), another instruction is received (304). If there are no more instructions (336), the algorithm ends (340).

[0087] Figure 4 A flow chart is shown that references hardware components to implement an embodiment. Figure 4 The elements are collectively represented as 400, which components can be used in a computer processing environment of hardware, memory, processors, peripherals, auxiliary components, interfaces, and software. The software can be stored in any suitable programming language on a non-volatile memory or other suitable storage or computer usable medium.

[0088] Figure 4 An instruction cache (402) that may be accessed is shown. The instruction cache may be a memory module, a memory, or any suitable electronic storage medium, which may be local or remote. The instruction cache stores a plurality of instructions.

[0089] When the instruction cache is accessed, an instruction is fetched (406). This instruction can be any desired instruction for use by the processor, memory, or a combination thereof.

[0090] The instruction is decoded (410). The decoding of the instruction can be used to parse various aspects of the instruction, such as indicators, mnemonics, metadata tags, metadata values, counter values, commands (start / stop), or any other available information associated with the instruction for identification purposes. The identification helps determine whether the instruction includes an indicator indicating that the program order or execution sequence should be modified.

[0091] Once the instructions have been decoded and recognized, they are renamed 412. Renaming is performed to maintain control over those instructions that have been issued or executed. This renaming ensures that subsequent memory operations obtain different indicators, such as different metadata tags or different commands.

[0092] Then, the instructions are issued (414) to enable the execution of the operation.After the instructions are issued (414), other units or operations may be accessed (416).

[0093] Memory operations are performed (418). These memory operations (410) may be modified based on indicators or decoded instructions. Typically, memory operations access a memory module (420), which may include a load queue module (422) and a store queue module (424). Other memory registers or submodules may also be located in the memory module (420).

[0094] Figure 5 The storage queue (424) is shown in more detail. The storage queue (424) can be, for example, a buffer, such as a write combining buffer (WCB), and includes multiple registers, or storage areas, or memory locations that can be accessed. Although one buffer 424 is shown and described herein, it is within the scope of the present disclosure that the system can have any suitable number of buffers, including multiple WCBs.

[0095] Figure 6 A data cache memory module 522 is shown operatively coupled to the store queue 424 such that the store queue 424 can access data from the cache module 522. The data cache module 522 holds data and can access buffers and memory locations.

[0096] In one embodiment, the storage queue 424 may be a WCB, which is a weakly ordered memory type. The WCB may be operably coupled to a data cache module 522. This allows the WCB to react faster than slower control messages. The WCBs may be mapped to allow each WCB to operate independently of other WCB buffers in a processor or CPU core. The use of WCBs allows data to be combined and temporarily stored therein, and then the data may be put together rather than being written (immediately) as a single bit or chunk.

[0097] like Figure 5As shown, the memory registers of the buffer 424 have storage allocations 526, 528, 530, 532, 534, 536, and 538. These storage allocations are used to store data from the cache 522 having registers 552(a)...(n). The storage registers of the buffer 424 may or may not store data. In practice, the storage location of the data in the buffer may be manipulated so that memory operations that can be merged are valid, and when a barrier indicator such as a command or tag is recognized, the memory operation will not be merged. The storage capacity dimension 540 of the buffer 424 is shown. As shown in the buffer 424, the storage allocations 526, 528, 530, 532, 534, 536, and 538 may be smaller than the dimension 540.

[0098] Figure 6 A representation of a data cache 522 is shown. This data cache 522 has a set (generally shown as columns 552) of sub-registers 552(a)...(n) (where "n" is any suitable number). The width dimension 560 of the data cache 522 is shown. The data in the registers 552 (generally) can be accessed and manipulated and stored in the buffer 424. The data stored in the buffer 424 can be utilized in bursts, rather than in individual bits or smaller segments.

[0099] Figure 7 A flow chart 700 is shown according to an embodiment. The series of acts 700 may be stored in any suitable programming language in a non-volatile memory or other suitable storage or computer usable medium.

[0100] Figure 7 The series of actions shown in can be stored in the memory 102, such as Figure 7 As shown, and can be executed by the processor 106, such as Figure 7 shown.

[0101] like Figure 7 As shown, the algorithm begins (702). A program order or sequence of operations to be performed is accessed (704). Instructions are received or accessed, typically via an interface (706).

[0102] The instruction is evaluated to identify (208) a group change indicator or mnemonic as part of the instruction indicating that the sequence of operations is different. The indicator can be a mnemonic or a "start / stop" command or symbol. The group change sequence indicator can be any of a plurality of indicators. The group change indicator can be used to modify the sequence of memory operations. One embodiment includes the indicator as a mnemonic, which is a command or metadata. As another embodiment, the indicator is a start / stop indicator.

[0103] Instructions with indicators are used to distinguish the allocation of memory to operations. The allocation is usually based on mnemonics or other identifiers. Such allocation of memory to operations usually involves grouping the operations, so that a first group consisting of one or more first operations is different from one or more second operations.

[0104] In fact, as an embodiment, the second group of operations may be an open group in that these operations will be processed after the operations in the first group are processed.

[0105] If it is determined (708) that the instruction does not include a sequence change indicator, then the operations are assigned to the second group by default (709), and the second group is executed (720).

[0106] When the instruction includes a mnemonic indicating that the sequence of operations is distinct, the instruction is executed (710).

[0107] The allocation of operations is differentiated based on mnemonics or instructions with mnemonics (712). The operations are separated, separated, or grouped based on the distinction (714). Typically, the separation is performed on a first group that is not merged, or on operations that are performed in sequence based on the mnemonics. The second group may be an open group that may be merged. Alternatively, the first group may be differentiated by other processing operations that may not be related to memory merging.

[0108] like Figure 7 As shown, the operations classified into the first group are performed (716). Then, the operations in the second group are performed (720).

[0109] A determination is made as to whether additional operations exist (722). If yes (724), the sequence of operations is accessed (704). If no (726), the algorithm ends (730).

[0110] Any combination of one or more computer usable or computer readable media may be utilized. A computer usable or computer readable medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples of computer readable media (a non-exhaustive list) would include: an electrical connection with one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CDROM), an optical storage device, a transmission medium (such as a medium supporting the Internet or an Intranet), or a magnetic storage device.

[0111] A computer usable or computer readable medium may even be paper or other suitable medium on which the program is printed, since the program may be captured electronically, for example, by optically scanning the paper or other medium, and then compiled, interpreted, or otherwise processed in an appropriate manner as needed, and then stored in a computer memory. In the context of this document, a computer usable or computer readable medium may be any medium that can contain, store, communicate, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer usable medium may include a propagated data signal containing the computer usable program code, which data signal may be in baseband or as part of a carrier wave. The computer usable program code may be transmitted using any suitable medium (including but not limited to wireless, wired, optical cable, RF, etc.).

[0112] Computer program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, C++, C#, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or a connection may be established with an external computer (e.g., through the Internet using an Internet service provider).

[0113] The present disclosure is described below with reference to flowchart illustrations and / or block diagrams of methods, devices, systems, and computer program products according to embodiments of the present disclosure. It will be understood that each block in the flowchart illustrations and / or block diagrams and combinations of blocks in the flowchart illustrations and / or block diagrams can be implemented by computer program instructions.

[0114] These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in the flowchart and / or block diagram blocks. These computer program instructions can also be stored in a computer-readable medium, which can instruct a computer or other programmable data processing device to function in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture, which includes an instruction device for implementing the functions / actions specified in the flowchart and / or block diagram blocks.

[0115] The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in the flowchart and / or block diagram blocks.

[0116] As will be appreciated by those skilled in the art, embodiments may be described as systems, methods, or computer program products. Thus, the present disclosure may take the form of pure hardware embodiments, pure software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects, which are generally referred to herein as "circuits," "modules," or "systems." In addition, the present disclosure may take the form of a computer program product included in any tangible medium of expression, including computer usable program code.

[0117] It can be seen that the system and methodology proposed in this article have improved the existing technology.

[0118] Therefore, some disclosed embodiments are presented below:

[0119] One embodiment relates to a method ("the method") comprising the steps of: accessing a program sequence of operations to be performed from a memory; accessing one or more instructions, some of the one or more instructions having associated mnemonics; identifying one or more instructions having mnemonics, the mnemonics indicating that the program sequence of operations is distinct; executing the one or more identified instructions; and distinguishing an allocation of the memory to the operations, the allocation being based on the presence of the mnemonics, the allocation representing a first grouping of one or more first operations relative to one or more second operations, the first grouping being distinct from the one or more second operations.

[0120] The method also includes assigning a metadata tag to the selected operation based on the mnemonic.

[0121] The method, wherein the metadata tags determine the sequence of operations.

[0122] The method wherein the metadata tag indicates a difference in the allocation of operations.

[0123] The method, wherein the metadata tag includes a stage color.

[0124] The method, wherein the metadata tags include ranking tags.

[0125] The method also includes the steps of: renaming the mnemonics so that subsequent operations have different metadata tags; and merging operations based on the metadata tags.

[0126] The method, wherein the mnemonic comprises an integer.

[0127] The method, wherein receiving one or more instructions comprises receiving instructions via an interface.

[0128] The method also includes modifying a mnemonic associated with one or more subsequent instructions or operations.

[0129] The method further includes: executing one or more operations having the mnemonic after executing the previous instruction; and merging the one or more operations before executing the instruction having the mnemonic.

[0130] The method, wherein the selected operation is performed independent of the mnemonic.

[0131] The method also includes merging memory operations based on the matching mnemonics.

[0132] The method also includes merging operations based on the identified instructions independent of the mnemonics.

[0133] Another embodiment relates to a method comprising the following steps: receiving a first instruction that distinguishes memory accesses; accessing a second instruction, the second instruction accessing an input address; associating a first metadata value with the first instruction; implementing the first instruction by assigning the first metadata value to each memory operation; incrementing a counter so that subsequent memory operations are assigned a second metadata value; applying the second metadata value to a next decoding stage; comparing the first metadata value with the second metadata value so that: when the first metadata value matches the second metadata value, the associated operations are grouped with the matching metadata value; and when the first metadata value is different from the second metadata value, the associated operations are grouped with the non-matching metadata value.

[0134] The method as described above, wherein the second instruction provides access to memory operations with compatible metadata.

[0135] The method as described above, wherein the first instruction is assigned an execution state that is independent of execution but varies with the grouping of other instructions.

[0136] The method as described above, wherein the first instruction controls memory access before the first instruction and memory access after the first instruction.

[0137] A device comprises: a memory; and a processor coupled to the memory to execute instructions stored in the memory, the instructions comprising: accessing a program sequence of operations to be performed from the memory; accessing one or more instructions, wherein some of the one or more instructions have associated mnemonics; identifying one or more instructions having mnemonics, wherein the mnemonics indicate that the program sequence of operations is distinguished; executing the one or more identified instructions; and distinguishing an allocation of the memory to the operations, wherein the allocation is based on the presence of the mnemonics, wherein the allocation represents a first grouping of one or more first operations relative to one or more second operations, wherein the first grouping is distinguished from the one or more second operations.

[0138] Various representative embodiments have been described in detail herein by way of example and not limitation. It will be appreciated by those skilled in the art that various changes may be made in the form and details of the embodiments described so that equivalent embodiments are still within the scope of the appended claims.

Claims

1. A method for distinguishing memory operations in a programmable data processor, comprising: accessing from memory a program sequence of instructions to be executed by a processor, the instructions including a barrier instruction; identifying the barrier instruction; executing the barrier instruction; assigning metadata tags to memory operations resulting from a first set of instructions accessed prior to the barrier instruction; updating the metadata tag in response to executing the barrier instruction; assigning updated metadata tags to memory operations resulting from a second set of instructions accessed after the barrier instruction; as well as Distinguishing between the first group of instructions and the second group of instructions based on the metadata tag includes allowing memory operations generated by instructions in at least one of the first group of instructions and the second group of instructions to be merged, while preventing memory operations generated by instructions in different groups from being merged.

2. The method according to claim 1, wherein: The metadata tags determine a sequence of the memory operations.

3. The method according to claim 1, wherein: The metadata tags do not prevent out-of-order memory operations.

4. The method according to claim 1, wherein: The metadata tags include stage color.

5. The method according to claim 1, wherein: The metadata tags include an ordering tag indicating an order in which corresponding instruction groups are accessed.

6. The method of claim 1 , updating the metadata tag in response to executing the barrier instruction comprises: renaming the metadata tag so that subsequent memory operations have different metadata tags; And the method also includes: Memory operations are merged based on the metadata tags.

7. The method according to claim 1, wherein: The metadata tag comprises an integer.

8. The method according to claim 1, wherein: Accessing the one or more instructions includes receiving the instructions via an interface.

9. The method according to claim 1, further comprising: Metadata tags associated with memory operations resulting from one or more instructions in a program sequence accessed after the barrier instruction is accessed are modified.

10. The method according to claim 1, further comprising: executing one or more memory operations having the metadata tag after executing a previous barrier instruction; as well as The one or more memory operations are merged prior to executing the barrier instruction.

11. The method according to claim 1, wherein: The order in which memory operations are performed is independent of the barrier instructions.

12. The method according to claim 1, further comprising: Memory operations are merged based on matching metadata tags.

13. The method according to claim 1, further comprising: Merge operations based on recognized instructions independent of mnemonics.

14. A method for distinguishing memory operations in a programmable data processor, comprising: receiving a first set of one or more instructions; receiving a first instruction to distinguish memory accesses; receiving a second set of one or more instructions; associating a first metadata value with a memory operation produced by an instruction in the first set of instructions, the first metadata value being based on a counter value; implementing the first instruction by incrementing the counter; associating a second metadata value with a memory operation resulting from an instruction in the second set of instructions, the second metadata value being based on the incremented counter value; The metadata data values ​​of the first memory operation and the second memory operation are compared such that: When the metadata value of the first memory operation matches the metadata value of the second memory operation, merging the first memory operation and the second memory operation with the matching metadata value; as well as When the metadata value of the first memory operation is different from the metadata value of the second memory operation, the first memory operation and the second memory operation are prevented from being merged with the mismatching metadata values.

15. The method according to claim 14, further comprising: Decoding instructions of the first group of instructions or the second group of instructions in a decoding stage; as well as The metadata value is applied to memory operations immediately following the decoding stage.

16. The method according to claim 14, wherein: The first instruction does not enforce ordering of other instructions.

17. The method according to claim 14, wherein: The first instruction controls memory access before the first instruction and memory access after the first instruction so that memory operations generated by instructions before the first instruction are not merged with memory operations generated by instructions after the first instruction.

18. A programmable data processing device, comprising: Memory; and a processor, coupled to the memory, and configured to: Accessing a program sequence of instructions to be executed from the memory, the instructions comprising a barrier instruction, wherein the barrier instruction indicates that the program sequence of the instructions is distinguished, wherein the processor is configured to: identifying the barrier instruction; executing the barrier instruction; assigning metadata tags to memory operations resulting from a first set of instructions accessed prior to the barrier instruction; updating the metadata tag in response to executing the barrier instruction; assigning updated metadata tags to memory operations resulting from a second set of instructions accessed after the barrier instruction; and Distinguishing between the first group of instructions and the second group of instructions based on the metadata tag includes allowing memory operations generated by instructions in at least one of the first group of instructions and the second group of instructions to be merged, while preventing memory operations generated by instructions in different groups from being merged.

19. A programmable data processing device, comprising: Memory; and a processor, coupled to the memory, and configured to: receiving a first set of one or more instructions; receiving a first instruction to distinguish memory accesses; receiving a second set of one or more instructions; associating a first metadata value with a memory operation produced by an instruction in the first set of instructions, the first metadata value being based on a counter value; implementing the first instruction by incrementing the counter; associating a second metadata value with a memory operation resulting from an instruction in the second set of instructions, the second metadata value being based on the incremented counter value; The metadata data values ​​of the first memory operation and the second memory operation are compared such that: When the metadata value of the first memory operation matches the metadata value of the second memory operation, merging the first memory operation and the second memory operation with the matching metadata value; as well as When the metadata value of the first memory operation is different from the metadata value of the second memory operation, the first memory operation and the second memory operation are prevented from being merged with the mismatching metadata values.

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