AXI Bus Structure and Chip System

Abstract

The present invention provides an AXI bus structure and a chip system. The AXI bus structure includes: at least two master function unit groups, each of the master function unit groups including at least two master function units; at least two first routing units, the at least two master function unit groups corresponding to the at least two first routing units one by one, each of the first routing units being connected to each master function unit of the corresponding master function unit group through an AXI bus respectively; at least two second routing units, each of the second routing units being connected to each of the first routing units through an AXI bus respectively; at least two slave function unit groups, each of the slave function unit groups including at least two second slave function units, the at least two slave function unit groups corresponding to the at least two second routing units one by one, each of the second routing units being connected to each of the slave function units of the corresponding slave function unit group through an AXI bus respectively.

Description

Technical Field

[0001] This application relates to the technical field of chips, and particularly to an AXI bus structure and a chip system. Background Art

[0002] The Network On Chip (NoC) refers to the connection relationship between various systems or modules within a chip, mainly used to implement data exchange between subsystems or functional modules within the chip. In AI processing chips, the huge data throughput requirements pose many challenges to the design of the on-chip interconnect bus. For example, in a multi-core NPU (Neural network Processing Unit), the data interaction between multiple cores and the bandwidth requirements for data interaction with the OCM (On chip memory) are huge. To support high bandwidth, high clock frequencies and large bus widths have become the basic characteristics of the on-chip interconnect bus of AI processors. At the same time, multiple cores also make the number of interconnect bus lines start to become huge, bringing serious congestion problems to the chip backend implementation. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide an AXI bus structure and a chip system, which can reduce the number of interconnected AXI buses and eliminate congestion problems in the chip backend implementation.

[0004] The embodiments of this application provide an AXI bus structure, including:

[0005] At least two main functional unit groups, each of the main functional unit groups including at least two main functional units;

[0006] At least two first routing units, the at least two main functional unit groups corresponding to the at least two first routing units one by one, each of the first routing units being respectively connected to each of the main functional units of the corresponding main functional unit group through an AXI bus;

[0007] At least two second routing units, each of the second routing units being respectively connected to each of the first routing units through an AXI bus;

[0008] At least two slave functional unit groups, each of the slave functional unit groups including at least two second slave functional units, the at least two slave functional unit groups corresponding to the at least two second routing units one by one, each of the second routing units being respectively connected to each of the slave functional units of the corresponding slave functional unit group through an AXI bus.

[0009] Optionally, in the AXI bus structure described in the embodiments of the present application, each of the first routing units includes at least two first routing nodes connected in sequence through the AXI bus, and each of the second routing units includes at least two second routing nodes connected in sequence through the AXI bus;

[0010] At least two second routing nodes of each of the second routing units correspond to the at least two first routing units one by one, and each second routing node is connected to a first routing node of the corresponding first routing unit through the AXI bus.

[0011] Optionally, in the AXI bus structure described in the embodiments of the present application, each of the first routing nodes is connected to at least one of the second routing nodes.

[0012] Optionally, in the AXI bus structure described in the embodiments of the present application, the number of first routing nodes of the first routing unit is different from the number of second routing nodes in each of the second routing units.

[0013] Optionally, in the AXI bus structure described in the embodiments of the present application, the AXI bus includes a write address / data channel, a read address channel, a read data channel, and a write response channel;

[0014] Each of the first routing nodes includes: a first downstream sub-node on the write address / data channel, a second downstream sub-node on the read address channel, a first upstream sub-node on the read data channel, and a second upstream sub-node on the write response channel;

[0015] Within the same first routing unit, the first downstream sub-nodes of the at least two first routing nodes are connected in sequence, the second downstream sub-nodes of the at least two first routing nodes are connected in sequence, the first upstream sub-nodes of the at least two first routing nodes are connected in sequence, and the second upstream sub-nodes of the at least two first routing nodes are connected in sequence;

[0016] One end of the first downstream sub-node, the second downstream sub-node, the first upstream sub-node, and the second upstream sub-node is respectively connected to the corresponding main functional unit, and the other end is connected to the corresponding second routing node.

[0017] Optionally, in the AXI bus structure described in the embodiments of the present application, each of the second routing nodes includes: a third downstream sub-node on the write address / data channel, a fourth downstream sub-node on the read address channel, a third upstream sub-node on the read data channel, and a fourth upstream sub-node on the write response channel;

[0018] Within the same second routing unit, the third downstream child nodes of the at least two second routing nodes are connected in sequence, the fourth downstream child nodes of the at least two second routing nodes are connected in sequence, the third upstream child nodes of the at least two second routing nodes are connected in sequence, and the third downstream child nodes of the at least two second routing nodes are connected in sequence;

[0019] The input end of the third downstream child node is connected to the output end of the first downstream child node, the input end of the fourth downstream child node is connected to the output end of the second downstream child node, one end of the third upstream child node is connected to the first upstream child node, and the other end of the fourth upstream child node is connected to the second upstream child node; the other ends of the third downstream child node, the fourth downstream child node, the third upstream child node, and the fourth upstream child node are respectively connected to the corresponding slave functional units.

[0020] Optionally, in the AXI bus structure described in the embodiments of the present application, the first preset child node includes a master demultiplexer and a master arbiter;

[0021] The master demultiplexer is used to access the information sent by other nodes connected to it and send the information to the master arbiter or another other node connected to it;

[0022] The master arbiter is used to receive the information sent by the demultiplexer or the information sent by other first preset child nodes and output the information to other nodes connected to it;

[0023] The node type of the first preset child node is: the first upstream child node, the first downstream child node, the second upstream child node, the second downstream child node, the third upstream child node, the third downstream child node, the fourth upstream child node, or the fourth downstream child node, and the number of the same type of first preset child nodes connected to the first preset child node is one.

[0024] Optionally, in the AXI bus structure described in the embodiments of the present application, the second preset child node includes a master demultiplexer, a master arbiter, a bypass demultiplexer, and a bypass arbiter;

[0025] The master demultiplexer is used to access the information sent by other nodes connected to it and send the information to the master arbiter, the bypass arbiter, and / or another other node connected to it;

[0026] The master arbiter is used to receive the information sent by the demultiplexer, the bypass demultiplexer, and / or other child nodes and output the information to the nodes connected to it;

[0027] The bypass multi-way distributor is used to access the information sent by other nodes connected to it and send the information to the main arbiter or the bypass arbiter;

[0028] The bypass arbiter is used to access the information sent by the main multi-way distributor and the bypass multi-way distributor and send the information to other nodes connected to it;

[0029] The node type of the second preset sub-node is: the first upstream sub-node, the first downstream sub-node, the second upstream sub-node, the second downstream sub-node, the third upstream sub-node, the third downstream sub-node, the fourth upstream sub-node or the fourth downstream sub-node, and the number of the second preset sub-nodes of the same type connected to the second preset sub-node is at least two.

[0030] Optionally, in the AXI bus structure described in the embodiments of the present application, the main functional unit includes a processor, an accelerator, a coprocessor or a DMA controller.

[0031] Optionally, in the AXI bus structure described in the embodiments of the present application, the slave functional unit group is a memory, and the slave functional unit is a storage unit of the memory.

[0032] Optionally, in the AXI bus structure described in the embodiments of the present application, different first routing nodes are configured with different numbers of first-in-first-out queues FIFO, and the depths of the first-in-first-out queues FIFO on different first routing nodes are different.

[0033] Optionally, in the AXI bus structure described in the embodiments of the present application, different second routing nodes are configured with different numbers of first-in-first-out queues FIFO, and the depths of the first-in-first-out queues FIFO on different second routing nodes are different.

[0034] In a second aspect, an embodiment of the present application further provides a chip system, including the AXI bus structure described in any one of the above.

[0035] As can be seen from the above, the AXI bus structure provided by the embodiments of the present application divides a plurality of main functional units into a group, divides a plurality of slave functional units into a group, and a plurality of main functional units in a group share a routing network formed by a plurality of first routing units to interact with a routing network formed by a plurality of second routing units, so as to realize the access to each slave functional unit, which can reduce the number of interconnected AXI buses and eliminate the congestion problem in the chip backend implementation. Description of the Drawings

[0036] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present application, and thus should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0037] Figure 1 It is a schematic structural diagram of an AXI bus structure in some embodiments of the present application.

[0038] Figure 2 It is a schematic structural diagram of a first preset sub-node of an AXI bus structure in some embodiments of the present application.

[0039] Figure 3 It is a schematic diagram of the first connection structure of a first preset sub-node of an AXI bus structure in some embodiments of the present application.

[0040] Figure 4 It is a schematic diagram of the first connection structure of a first preset sub-node and a second preset sub-node of an AXI bus structure in some embodiments of the present application.

[0041] Figure 5 It is a schematic diagram of the second connection structure of a first preset sub-node and a second preset sub-node of an AXI bus structure in some embodiments of the present application.

[0042] Figure 6 It is a sub-node connection structure diagram of a channel of an AXI bus structure in some embodiments of the present application. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application.

[0044] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. In addition, terms such as "first", "second", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.

[0045] It should also be noted that, unless otherwise clearly specified or limited, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

[0046] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an AXI bus structure in some embodiments of the present application.

[0047] Among them, the AXI bus structure includes: at least two master function unit groups 10, at least two first routing units 20, at least two second routing units 30, and at least two slave function unit groups 40.

[0048] Among them, each master function unit group 10 includes at least two master function units 11. The at least two master function unit groups 10 and the at least two first routing units 20 are in one-to-one correspondence, and each first routing unit 20 is respectively connected to each master function unit 11 of the corresponding master function unit group 10 through an AXI bus 100. Each second routing unit 30 is respectively connected to each first routing unit 20 through an AXI bus 100; each slave function unit group 40 includes at least two second slave function units 41, the at least two slave function unit groups 40 and the at least two second routing units 30 are in one-to-one correspondence, and each second routing unit 30 is respectively connected to each slave function unit 41 of the corresponding slave function unit group 40 through an AXI bus 100.

[0049] In some embodiments, the master function units 11 of each master function unit group 10 can be different function units or the same function units. For example, the master function unit 11 can be a processor, a DMA (Direct Memory Access) controller, or a network processor (NPU), etc. Of course, it is not limited thereto. Among them, the number of master function units 11 in each master function unit group 10 can be 3, 4, or other numbers. Among them, the number of master function unit groups 10 is 2 in this embodiment. Of course, it can also be other numbers. In this embodiment, there are a total of two master function unit groups 10. One master function unit group 10 includes 3 master function units 11, and the other master function unit group 10 includes 4 master function units 11.

[0050] In some embodiments, the first routing unit 20 includes at least two first routing nodes 21. For example, the number of first routing nodes 21 can be 2, 3, or more than 3. Among them, the at least two first routing nodes 21 are connected in sequence. Of course, in some embodiments, the at least two first routing nodes 21 can also adopt other connection manners, such as star connection, etc.

[0051] Among them, the at least two first routing nodes 21 can be connected to at least two main functional units 11 of the corresponding main functional unit group 10 in a one-to-one correspondence; of course, they may not be in a one-to-one correspondence. For example, the number of first routing nodes 21 can be greater than the number of main functional units 11 of the corresponding main functional unit group 10. Or the number of first routing nodes 21 can be greater than the number of main functional units 11 of the corresponding main functional unit group 10. In this case, some first routing nodes 21 need to be connected to two or more main functional units 11.

[0052] Among them, the second routing unit 30 includes at least two second routing nodes 31. For example, the number of second routing nodes 31 can be 2, 3, or more than 3. The at least two second routing nodes 31 are connected in sequence. Of course, in some embodiments, the at least two second routing nodes 31 can also adopt other connection manners, such as star connection, etc.

[0053] Among them, the at least two second routing nodes 31 of the second routing unit 30 can be connected to the at least two slave functional units 11 in a one-to-one correspondence, that is, the number of second routing nodes 31 of the second routing unit 30 is equal to the number of slave functional units 11 of the corresponding slave functional unit group 10. Of course, the at least two second routing nodes 31 of the second routing unit 30 can also not be in a one-to-one correspondence with the at least two slave functional units 11. For example, the number of second routing nodes 31 can be greater than the number of slave functional units 41 of the corresponding slave functional unit group 40.

[0054] Among them, the at least two second routing nodes 31 of each second routing unit 30 are in a one-to-one correspondence with the at least two first routing units 20, and each second routing node 31 is connected to a first routing node 21 of the corresponding first routing unit 20. As Figure 1 shown, the number of second routing nodes 31 of each second routing unit 30 is two. Correspondingly, the number of first routing units 20 is two; of course, it is not limited thereto.

[0055] In some embodiments, the slave functional unit group 40 includes at least two slave functional units 41. At least two slave functional units 41 of each slave functional unit group 40 are connected to at least two second routing nodes 31 of the corresponding second routing unit 30 in a one-to-one correspondence, that is to say, the number of slave functional units 41 of each slave functional unit group 40 is equal to the number of second routing nodes 31 of the corresponding second routing unit 30. Of course, the number of slave functional units 41 of different slave functional unit groups 40 may be equal or unequal.

[0056] Among them, the at least two slave functional unit groups 40 may belong to the same memory or multiple memories, and each slave functional unit 41 is a storage unit of the memory.

[0057] In some embodiments, the AXI bus 100 includes a write address / data channel, a read address channel, a read data channel, and a write response channel.

[0058] Among them, each first routing node 21 and each second routing node 31 include four sub-nodes, and the four sub-nodes are respectively in one-to-one correspondence with the write address / data channel, the read address channel, the read data channel, and the write response channel.

[0059] Specifically, the first routing node 21 includes: a first downstream sub-node located on the write address / data channel, a second downstream sub-node located on the read address channel, a first upstream sub-node located on the read data channel, and a second upstream sub-node located on the write response channel; within the same first routing unit, the first downstream sub-nodes of the at least two first routing nodes are connected in sequence, the second downstream sub-nodes of the at least two first routing nodes are connected in sequence, the first upstream sub-nodes of the at least two first routing nodes are connected in sequence, and the second upstream sub-nodes of the at least two first routing nodes are connected in sequence; among them, within the same first routing unit, the first downstream sub-nodes of the at least two first routing nodes may be cascaded in sequence, or may be interconnected in pairs, or may adopt other star connection methods, and of course, cascading in sequence is the best. Of course, the second downstream sub-nodes within the same first routing unit may be cascaded in sequence, or may be interconnected in pairs, or may adopt other star connection methods, and of course, cascading in sequence is the best. The second upstream sub-nodes within the same first routing unit may be cascaded in sequence, or may be interconnected in pairs, or may adopt other star connection methods, and of course, cascading in sequence is the best. The second downstream sub-nodes within the same first routing unit may be cascaded in sequence, or may be interconnected in pairs, or may adopt other star connection methods, and of course, cascading in sequence is the best.

[0060] Among them, one end of the first downlink sub-node, the second downlink sub-node, the first uplink sub-node, and the second uplink sub-node are respectively connected to the corresponding main functional unit 11, and the other ends are respectively connected to the corresponding second routing node 31. Specifically, the input ends of the first downlink sub-node and the second downlink sub-node are connected to the main functional unit, and the inputs of the first downlink sub-node and the second downlink sub-node are connected to the corresponding second routing node. The input ends of the first uplink sub-node and the second uplink sub-node are connected to the second routing node, and the output ends of the first uplink sub-node and the second uplink sub-node are connected to the main functional unit.

[0061] Specifically, each second routing node 31 includes: a third downlink sub-node located on the write address / data channel, a fourth downlink sub-node located on the read address channel, a third uplink sub-node located on the read data channel, and a fourth uplink sub-node located on the write acknowledgment channel; within the same second routing unit, the third downlink sub-nodes of the at least two second routing nodes are connected in sequence, the fourth downlink sub-nodes of the at least two second routing nodes are connected in sequence, the third uplink sub-nodes of the at least two second routing nodes are connected in sequence, and the third downlink sub-nodes of the at least two second routing nodes are connected in sequence. Among them, within the same second routing unit, the third downlink sub-nodes of the at least two second routing nodes can be cascaded in sequence, or can be interconnected pairwise, or can adopt other star connection methods. Of course, cascading in sequence is the best. Of course, the third uplink sub-nodes within the same second routing unit can be cascaded in sequence, or can be interconnected pairwise, or can adopt other star connection methods. Of course, cascading in sequence is the best. The fourth uplink sub-nodes within the same second routing unit can be cascaded in sequence, or can be interconnected pairwise, or can adopt other star connection methods. Of course, cascading in sequence is the best. The fourth downlink sub-nodes within the same second routing unit can be cascaded in sequence, or can be interconnected pairwise, or can adopt other star connection methods. Of course, cascading in sequence is the best.

[0062] Among them, one end of the third downlink sub-node is connected to the output end of the first downlink sub-node, one end of the fourth downlink sub-node is connected to the output end of the second downlink sub-node, one end of the third uplink sub-node is connected to the input end of the first upper and lower sub-node, and one end of the fourth uplink sub-node is connected to the input end of the second uplink sub-node; the other ends of the third downlink sub-node, the fourth downlink sub-node, the third uplink sub-node, and the fourth uplink sub-node are respectively connected to the corresponding slave functional unit 41. Specifically, the output ends of the third downlink sub-node and the fourth downlink sub-node are respectively connected to the corresponding slave functional unit 41. The input ends of the third uplink sub-node and the fourth uplink sub-node are respectively connected to the corresponding slave functional unit 41.

[0063] Among them, in this application, "down" refers to the direction in which the data flow points from the main functional unit to the slave functional unit, and "up" refers to the direction in which the data volume points from the slave functional unit to the main functional unit.

[0064] Among them, as Figure 2 shown, the first preset sub-node a1 includes a main demultiplexer a11 and at least one main arbiter a12. Among them, the main demultiplexer a11 is used to access the information sent by other nodes connected to it and send the information to the main arbiter a12 or another other node connected to it. The main arbiter a12 is used to receive the information sent by the main demultiplexer a11 or other nodes and output the information to other nodes connected to it. For example, Figure 2 only includes one main arbiter a12. Figure 4 The rightmost first preset sub-node in

[0065] includes two main arbiters a12. Among them, the node type of the first preset sub-node a1 can be: the first up sub-node, the first down sub-node, the second up sub-node, the second down sub-node, the third up sub-node, the third down sub-node, the fourth up sub-node or the fourth down sub-node, and the number of the first preset sub-nodes of the same type connected to the first preset sub-node is one. For example, for the first up sub-node that is the first preset sub-node a1, the number of the first up sub-nodes connected to it is one. In Figure 2 , Figure 3 and Figure 4 the sub-nodes at both ends are only connected to one sub-node of the same type, so they are all first preset sub-nodes.

[0066] Of course, it can be understood that for some first preset sub-nodes a1 provided with two main demultiplexers a11, a bypass demultiplexer a13 needs to be set to receive the information sent by other nodes. Then send the information to the main arbiter so that the main arbiter can send out each received information in turn.

[0067] As Figure 3 shown, it is a node network composed of two first preset sub-nodes a1 of the same type. For example, the Figure 3 can correspond to Figure 1 the connection relationship of the sub-nodes of the same type of two second routing nodes in the second routing unit in

[0068] Among them, as Figure 4As shown, the second preset sub-node a2 includes a main multi-way distributor a11, at least one main arbiter a12, at least one bypass multi-way distributor a13, and at least one bypass arbiter a14. Among them, the main multi-way distributor a11 is used to access the information sent by other nodes connected to it, and send the information to the corresponding main arbiter a12, the bypass arbiter a14, and / or other sub-nodes; for example, in Figure 4 among them, the second sub-node from the left is a bypass multi-way distributor a13 in the coordinates of the second preset sub-node a2, which selectively distributes the information received from the first preset sub-node a1 to the main arbiter a12 or a bypass arbiter a14 on the right.

[0069] Among them, the main arbiter a12 is used to receive the information sent by the main multi-way distributor and the bypass multi-way distributor a13, and output the information to other nodes connected to the second preset sub-node.

[0070] Among them, the bypass multi-way distributor a14 is used to access the information sent by other sub-nodes, and send the information to the main arbiter a12 or the bypass arbiter a13;

[0071] Among them, the bypass arbiter a13 is used to access the information sent by the main multi-way distributor a11 and the bypass multi-way distributor a14, and send the information to other nodes connected to it.

[0072] Among them, the node type of the second preset sub-node is: the first up sub-node, the first down sub-node, the second up sub-node, the second down sub-node, the third up sub-node, the third down sub-node, the fourth up sub-node or the fourth down sub-node, and the number of the same type of first preset sub-nodes connected to the first preset sub-node is at least two. For example, Figure 3 the middle sub-node in it is connected to the two sub-nodes beside it, and is the second preset sub-node. Figure 4 the two middle sub-nodes in it are respectively connected to two sub-nodes, so the Figure 4 two middle sub-nodes in it are the second preset sub-nodes.

[0073] Among them, in this application, the arbiter is used to sequentially send at least two paths of received information to the next node. The multi-way distributor is used to distribute one path of received information to at least one node connected to it.

[0074] Such as Figure 6 shown, a connection relationship diagram of a sub-node of the second routing unit and the first routing unit in the downlink channel in this application. Of course, the connection relationship diagram of the corresponding uplink channel only needs to be adjusted adaptively.

[0075] Among them, different first routing nodes 21 and second routing nodes 31 are configured with different numbers of first-in-first-out (FIFO) queues, and the depths of the FIFO queues on different first routing nodes 21 are different. Also, the depths of the FIFO queues on different second routing nodes 31 are different.

[0076] Among them, each child node of the first routing node 21 has the function of splitting the burst length of the AXI bus into multiple segments, so that the burst length can be reduced.

[0077] It can be understood that the AXI bus 100 includes a write address channel, a write data channel, a read address channel, a read data channel, and a write response channel. That is, the write address / data channel is split into two channels: a write address channel and a write data channel.

[0078] Among them, in some embodiments, the signal transmission directions of the write address / data channel and the read address channel are the same, and the depths of the FIFOs configured on the same first routing node on different channels are the same. Therefore, the child nodes of the same first routing node or second routing node on the write address / data channel and the read address channel can adopt the same structure.

[0079] As can be seen from the above, the AXI bus structure provided by the embodiments of the present application groups multiple master functional units into one group and multiple slave functional units into one group, and multiple master functional units in one group share a routing network formed by multiple first routing units to interact with a routing network formed by multiple second routing units, thereby realizing access to each slave functional unit, reducing the number of interconnected AXI buses, and eliminating the congestion problem in the chip backend implementation.

[0080] The embodiments of the present application also provide a chip system, which includes an AXI bus structure according to any of the above embodiments.

[0081] The above descriptions are only for the embodiments of the present application and are not intended to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An AXI bus structure, characterized in that, Comprising: At least two main functional unit groups, each of the main functional unit groups comprising at least two main functional units; At least two first routing units, the at least two main functional unit groups corresponding one-to-one with the at least two first routing units, each of the first routing units being respectively connected to each of the main functional units of the corresponding main functional unit group through an AXI bus; At least two second routing units, each of the second routing units being respectively connected to each of the first routing units through an AXI bus; At least two slave functional unit groups, each slave functional unit group comprising at least two second slave functional units, the at least two slave functional unit groups corresponding one-to-one with the at least two second routing units, each of the second routing units being respectively connected to each of the slave functional units of the corresponding slave functional unit group through an AXI bus.

2. The AXI bus structure according to claim 1, characterized in that, Each of the first routing units comprises at least two first routing nodes connected in sequence through an AXI bus, and each of the second routing units comprises at least two second routing nodes connected in sequence through an AXI bus; At least two second routing nodes of each of the second routing units respectively correspond one-to-one with the at least two first routing units, and each of the second routing nodes is connected to one first routing node of the corresponding first routing unit through an AXI bus.

3. The AXI bus structure according to claim 2, characterized in that, Each of the first routing nodes is connected to at least one of the second routing nodes.

4. The AXI bus structure according to claim 2, characterized in that, The AXI bus comprises a write address / data channel, a read address channel, a read data channel and a write response channel; Each of the first routing nodes comprises: a first downstream sub-node located on the write address / data channel, a second downstream sub-node located on the read address channel, a first upstream sub-node located on the read data channel, and a second upstream sub-node located on the write response channel; Within the same first routing unit, the first downstream sub-nodes of the at least two first routing nodes are connected in sequence, the second downstream sub-nodes of the at least two first routing nodes are connected in sequence, the first upstream sub-nodes of the at least two first routing nodes are connected in sequence, and the second upstream sub-nodes of the at least two first routing nodes are connected in sequence; One end of the first downstream sub-node, the second downstream sub-node, the first upstream sub-node and the second upstream sub-node is respectively connected to the corresponding main functional unit, and the other end is connected to the corresponding second routing node.

5. The AXI bus structure according to claim 4, characterized in that, Each of the second routing nodes comprises: a third downstream sub-node located on the write address / data channel, a fourth downstream sub-node located on the read address channel, a third upstream sub-node located on the read data channel, and a fourth upstream sub-node located on the write response channel; Within the same second routing unit, the third downstream sub-nodes of the at least two second routing nodes are connected in sequence, the fourth downstream sub-nodes of the at least two second routing nodes are connected in sequence, the third upstream sub-nodes of the at least two second routing nodes are connected in sequence, and the fourth upstream sub-nodes of the at least two second routing nodes are connected in sequence; The input end of the third downlink sub-node is connected to the output end of the first downlink sub-node, the input end of the fourth downlink sub-node is connected to the output end of the second downlink sub-node, one end of the third uplink sub-node is connected to the first uplink sub-node, and the other end of the fourth uplink sub-node is connected to the second uplink sub-node; the other ends of the third downlink sub-node, the fourth downlink sub-node, the third uplink sub-node and the fourth uplink sub-node are respectively connected to corresponding slave functional units.

6. The AXI bus structure according to claim 5, characterized in that, The first preset sub-node includes a main demultiplexer and a main arbiter; The main demultiplexer is used to access the information sent by other nodes connected thereto and send the information to the main arbiter or another other node connected thereto; The main arbiter is used to receive the information sent by the demultiplexer or the information sent by other first preset sub-nodes and output the information to other nodes connected thereto; The node type of the first preset sub-node is: the first uplink sub-node, the first downlink sub-node, the second uplink sub-node, the second downlink sub-node, the third uplink sub-node, the third downlink sub-node, the fourth uplink sub-node or the fourth downlink sub-node, and the number of the same type of first preset sub-nodes connected by the first preset sub-node is one.

7. The AXI bus structure according to claim 5, characterized in that, The second preset sub-node includes a main demultiplexer, a main arbiter, a bypass demultiplexer and a bypass arbiter; The main demultiplexer is used to access the information sent by other nodes connected thereto and send the information to the main arbiter, the bypass arbiter and / or another other node connected thereto; The main arbiter is used to receive the information sent by the demultiplexer, the bypass demultiplexer and / or other sub-nodes and output the information to the nodes connected thereto; The bypass demultiplexer is used to access the information sent by other nodes connected thereto and send the information to the main arbiter or the bypass arbiter; The bypass arbiter is used to access the information sent by the main demultiplexer and the bypass demultiplexer and send the information to other nodes connected thereto; The node type of the second preset sub-node is: the first uplink sub-node, the first downlink sub-node, the second uplink sub-node, the second downlink sub-node, the third uplink sub-node, the third downlink sub-node, the fourth uplink sub-node or the fourth downlink sub-node, and the number of the same type of second preset sub-nodes connected by the second preset sub-node is at least two.

8. The AXI bus structure according to claim 1, characterized in that, The main functional unit includes a processor, an accelerator or a DMA controller.

9. The AXI bus structure according to claim 1, characterized in that, The slave functional unit group is a memory, and the slave functional unit is a storage unit of the memory.

10. The AXI bus structure according to claim 4, characterized in that, Different first routing nodes are configured with different numbers of first-in-first-out queues FIFO, and the depths of the first-in-first-out queues FIFO on different first routing nodes are different.

11. The AXI bus structure according to claim 4, wherein, Different second routing nodes are configured with different numbers of first-in-first-out queues FIFO, and the depths of the first-in-first-out queues FIFO on different second routing nodes are different.

12. A chip system, wherein, Including the AXI bus structure according to any one of claims 1-11.

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