Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a device includes providing a first fin in a first device type region and providing a second fin in a second device type region. Each of the first fin and the second fin includes a plurality of semiconductor channel layers. A two-step recess of an STI region is performed on opposite sides of each of the first fin and the second fin to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region, and a second gate structure is formed in the second device type region. The first gate structure is formed above a first fin having a first number of exposed semiconductor channel layers, and the second gate structure is formed above a second fin having a second number of exposed semiconductor channel layers. Embodiments of the present invention also relate to semiconductor devices and methods for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC sizes (e.g., minimum component size) and thereby increasing production efficiency and reducing associated costs. However, this scaling also increases the complexity of semiconductor manufacturing processes. Therefore, the realization of the continued development of semiconductor ICs and devices requires similar developments in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control, reduce off-state current, and reduce short channel effects (SCE) by increasing gate-channel coupling. One such multi-gate device that has been introduced is the fin field effect transistor (FinFET). FinFETs get their name from the fin-like structure that extends from the substrate on which the FinFET is formed and is used to form the FET channel. Another multi-gate device that was introduced in part to address the performance challenges associated with FinFETs is the all-around gate (GAA) transistor. The name of the GAA transistor comes from the gate structure that extends completely around the channel, providing better electrostatic control than the FinFET. FinFETs and GAA transistors are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCE.

[0004] Typically, GAA transistors are implemented, for example, where FinFETs are no longer able to meet performance requirements. However, semiconductor ICs may typically include a variety of different device types with different performance requirements. Therefore, providing multi-gate devices (e.g., such as GAA transistors) that can meet these different device performance requirements remains a challenge. Therefore, the prior art has not proven to be completely satisfactory in all respects. Summary of the invention

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a first fin in a first device type region and providing a second fin in a second device type region, wherein each of the first fin and the second fin includes a plurality of semiconductor channel layers; performing a two-step recess of a shallow trench isolation (STI) region on opposite sides of each of the first fin and the second fin to expose a first number of semiconductor channel layers among the plurality of semiconductor channel layers of the first fin in the first device type region and a second number of semiconductor channel layers among the plurality of semiconductor channel layers of the second fin in the second device type region; and forming a first gate structure in the first device type region and forming a second gate structure in the second device type region, wherein the first gate structure is formed above the first fin having the first number of exposed semiconductor channel layers, and wherein the second gate structure is formed above the second fin having the second number of exposed semiconductor channel layers.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a plurality of fins extending from a substrate, wherein each of the plurality of fins includes a stack of epitaxial layers, the stack of epitaxial layers having a plurality of first type layers and a plurality of second type layers; forming a plurality of shallow trench isolation (STI) features inserted into the plurality of fins; performing a first shallow trench isolation recess process to expose a first number of each of the first type layers and the second type layers within each of the plurality of fins, and wherein, after the first shallow trench isolation recess process, each of the second number of the first type layers and the second type layers remains embedded in the shallow trench isolation feature; and performing a second shallow trench isolation recess process to expose a second number of each of the first type layers and the second type layers in a first region of the semiconductor device, wherein, after the second shallow trench isolation recess process, each of the second number of the first type layers and the second type layers remains embedded in the shallow trench isolation feature in a second region of the semiconductor device.

[0007] Another embodiment of the present invention provides a semiconductor device, comprising: a first transistor located in a first device type region of a substrate, wherein the first transistor comprises a first gate structure and a first source / drain component adjacent to the first gate structure; and a second transistor located in a second device type region of the substrate, wherein the second transistor comprises a second gate structure and a second source / drain component adjacent to the second gate structure; wherein the first transistor comprises a first fin having a first number of semiconductor channel layers disposed above a first shallow trench isolation (STI) region and in laterally contact with the first source / drain component, wherein the second transistor comprises a second fin having a second number of semiconductor channel layers disposed above a second shallow trench isolation region and in laterally contact with the second source / drain component, and wherein the first number of semiconductor channel layers is different from the second number of semiconductor channel layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A simplified top-down layout diagram of a multi-gate device according to some embodiments is provided;

[0010] Figure 2 is a flow chart of a method of manufacturing a semiconductor device 300 according to one or more aspects of the present invention;

[0011] Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C and Fig. 8A , Figure 8B , Figure 8C Embodiments of a semiconductor device 300 according to some embodiments are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section BB' or section CC';

[0012] Fig. 9A , Fig. 9B , Fig. 9C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C and Fig.23A , Fig. 23B , Fig.23C Embodiments of a semiconductor device 300 according to some embodiments are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section CC';

[0013] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.14A , Fig. 14B , Fig. 14C , Fig.16A , Fig. 16B , Fig. 16C , Fig.18A , Fig.18B , Fig.18C , Fig. 20A , Fig. 20B , Fig. 20C and Fig.24A , Fig. 24B , Fig.24C Embodiments of a semiconductor device 300 according to some embodiments are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section AA'; and

[0014] Fig.11A , Fig. 11B , Fig. 11C , Fig.13A , Fig. 13B , Fig. 13C , Fig.15A , Fig. 15B , Fig. 15C , Fig.17A , Fig. 17B , Fig. 17C and Fig.19A , Fig.19B , Fig.19C Embodiments of a semiconductor device 300 according to some embodiments are provided along with Figure 1 The plane defined by section BB' is substantially parallel to the plane of the cross-section. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples of different components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or other) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of the channel region. These multi-gate devices may include P-type metal oxide semiconductor devices or N-type metal oxide semiconductor multi-gate devices. Due to its fin-like structure, a specific example may be presented and referred to herein as FinFET. Also presented herein is an embodiment of a multi-gate transistor referred to as a full-all-around gate (GAA) transistor. GAA transistors include any device having a gate structure or a portion thereof formed on 4 sides of the channel region (e.g., surrounding a portion of the channel region). The devices presented herein also include embodiments having a channel region disposed in a semiconductor channel layer. In various embodiments, the semiconductor channel layer may include (one or more) nanosheet channels, (one or more) nanowire channels, (one or more) strip channels, and / or other suitable channel configurations. Presented herein are embodiments of devices that may have one or more channel regions (e.g., semiconductor channel layers) associated with a single continuous gate structure. However, those skilled in the art will recognize that the teachings may be applied to a single channel (e.g., a single semiconductor channel layer) or any number of channels. Those of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from various aspects of the present disclosure.

[0018] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all advantages must be discussed herein, and specific advantages are not required for all embodiments. For example, the embodiments discussed herein include methods and structures for providing a multi-gate device (e.g., such as a GAA transistor) having a plurality of semiconductor channel layers selected based on the device type implemented by the multi-gate device. GAA transistors can be used for various device types, for example, for implementing core (logic) devices, static random access memory (SRAM) devices, and analog devices, etc. With respect to these various device types implemented using GAA transistors, and in some embodiments, core (logic) devices can be implemented using a smaller number of semiconductor channel layers compared to SRAM and analog devices, and both SRAM and analog devices can be implemented using a larger number of semiconductor channel layers compared to core (logic) devices. In some instances, core (logic) devices can be implemented using a smaller number of semiconductor channel layers to reduce the total device capacitance and provide an increased device speed. Alternatively, in various embodiments, SRAM devices can be implemented using a larger number of semiconductor channel layers to provide an increased cell current. In some embodiments, analog devices may be implemented using a greater number of semiconductor channel layers in order to provide increased cell capacitance. In some instances, the number of semiconductor channel layers for a core (logic) device may be less than or equal to three (3), and the number of semiconductor channel layers for both the SRAM and analog devices may be greater than or equal to four (4). Generally, by providing a multi-gate device having multiple semiconductor channel layers selected based on the type of device implemented (e.g., a core, SRAM, or analog device), embodiments of the present disclosure provide methods and device structures that can simultaneously meet different performance requirements of a variety of different device types. In addition, as described in more detail below, a single continuous process flow may be used to manufacture various embodiments of multi-gate devices disclosed herein and including having different numbers of semiconductor channel layers. Other embodiments and advantages will be apparent to those skilled in the art upon reading the present disclosure.

[0019] For the purpose of the following discussion, Figure 1A simplified top-down layout diagram of a multi-gate device 100 is provided. In various embodiments, the multi-gate device 100 may include a FinFET device, a GAA transistor, or other type of multi-gate device. The multi-gate device 100 may include a plurality of fin elements 104 extending from a substrate, a gate structure 108 disposed above and around the fin elements 104, and source / drain regions 105, 107, wherein the source / drain regions 105, 107 are formed in, above, and / or around the fins 104. A channel region of the multi-gate device 100, which may include a plurality of semiconductor channel layers (e.g., when the multi-gate device 100 includes a GAA transistor), is disposed within the fins 104, below the gate structure 108, and along a path connected to the fins 104 by a gate structure 108. Figure 1 The plane defined by the cross section AA' is substantially parallel to the plane. In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structure 108. Figure 2 Various other components of the multi-gate device 100 are discussed in greater detail in the method of FIG.

[0020] refer to Figure 2 , which shows a semiconductor manufacturing method 200 according to various embodiments, the method including manufacturing a semiconductor device 300 (e.g., including a multi-gate device) having different numbers of semiconductor channel layers on a single substrate, wherein the number of semiconductor channel layers of a given multi-gate device is selected based on the device type being implemented. The method 200 is discussed below with reference to the manufacture of GAA transistors for implementing various device types, including core (logic) devices, static random access memory (SRAM) devices, and analog devices. However, it should be understood that various aspects of the method 200 may be equally applied to other types of multi-gate devices, or to other types of devices implemented by the multi-gate device, without departing from the scope of the present disclosure. In some embodiments, the method 200 may be used to manufacture a multi-gate device 100, as described above with reference to FIG. Figure 1 Thus, one or more aspects discussed above with reference to the multi-gate device 100 may also be applied to the method 200. It should be appreciated that the method 200 includes steps that are characteristic of a complementary metal oxide semiconductor (CMOS) technology process flow, and therefore is only briefly described herein. In addition, additional steps may be performed before, after, and / or during the method 200.

[0021] Note that certain aspects of method 200 are described as being performed in a region of semiconductor device 300 that includes a particular device type (e.g., a core (logic) device, an SRAM device, and / or an analog device). However, if not described as being performed in a region that includes a particular device type, it can be assumed that the steps of method 200 described are performed across multiple regions that include multiple device types (e.g., across multiple device type regions). In addition, semiconductor device 300 may include various other devices and components, such as other types of devices (e.g., additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic circuits, etc.), but are simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, semiconductor device 300 includes multiple semiconductor devices (e.g., transistors), including PFETs, NFETs, etc. that may be interconnected. In addition, note that the process steps of method 200 (including any description given with reference to the accompanying drawings) are merely exemplary and are not intended to be limited beyond what is specifically recited in the appended claims.

[0022] The method 200 begins at block 202 where a substrate including fins is provided. Figure 3 In an example of block 202 , a substrate 302 including fins 304 is provided. Figure 3 An embodiment of a semiconductor device 300 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the cross section BB' or the cross section CC'. In some embodiments, the substrate 302 may be a semiconductor substrate, such as a silicon substrate. The substrate 302 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. As is well known in the art, the substrate 302 may include various doping configurations according to design requirements. The substrate 302 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 302 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 302 may optionally include an epitaxial layer (epi layer), may be strained to improve performance, may include a silicon on insulator (SOI) structure, and / or have other suitable enhancement components.

[0023] Fin 304 including layers 308 and 310 can be formed by growing epitaxial layers of a first composition (e.g., subsequently patterned to form layer 310) with epitaxial layers of a second composition interposed therebetween (e.g., subsequently patterned to form layer 308). In one embodiment, the epitaxial layers of the first composition (e.g., used to form layer 310) are SiGe, and the epitaxial layers of the second composition (e.g., used to form layer 308) are silicon (Si). However, other embodiments are possible, including those that provide first and second compositions with different oxidation rates and / or etching selectivities. For example, in some embodiments, either the epitaxial layer of the first composition or the epitaxial layer of the second composition may include other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations of the foregoing. For example, the epitaxial growth of the epitaxial layer of the first composition or the epitaxial layer of the second composition can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. It is also noted that although layers 308, 310 are shown as having a specific stacking order within fin 304, in which layer 308 is the topmost layer of the stack of layers 308, 310, other configurations are possible. For example, in some cases, layer 310 may alternatively be the topmost layer of the stack of layers 308, 310. In other words, the growth order of layers 308, 310, and thereby their stacking order, can be switched or otherwise different from the order shown in the figure while remaining within the scope of the present disclosure.

[0024] After forming an epitaxial layer of a first composition (e.g., to form layer 310) and an epitaxial layer of a second composition (e.g., to form layer 308), a hard mask (HM) layer may be formed over device 300. In some embodiments, the HM layer may then be patterned to form an HM layer 312, as described below, wherein the HM layer 312 includes an oxide layer 314 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 316 (e.g., a pad nitride layer that may include Si3N4) formed over the oxide layer 314. In some examples, the oxide layer 314 may include a thermally grown oxide, a CVD deposited oxide, and / or an ALD deposited oxide, and the nitride layer 316 may include a nitride layer deposited by CVD or other suitable technique. Generally, in some embodiments, the HM layer may include a nitride-containing material deposited by CVD, ALD, PVD, or other suitable process.

[0025] After forming the HM layer, fins 304 extending from the pad 302 are formed. The fins 304 may be fabricated using a suitable process including a lithography and an etching process. The lithography process may include forming a photoresist layer over the device 300, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a mask element including the resist. In some embodiments, an electron beam (e-beam) lithography process may be used to perform patterning of the resist to form a mask element. The mask element may then be used to protect areas of the substrate 302 and layers formed thereon, while an etching process forms trenches 307 through the HM layer, through the epitaxial layer of the first composition, and the epitaxial layer of the second composition in unprotected areas and into the substrate 302, thereby leaving a plurality of extended fins 304. The trenches 307 may be etched using dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes.

[0026] In various embodiments, each fin 304 includes a substrate portion 302A formed by a substrate 302, a layer 310 (e.g., including a first composition), a layer 308 (e.g., including a second composition), and a HM layer 312. In some embodiments, the HM layer 312 can be removed (e.g., by a CMP process) before forming the fin 304. In some instances, the HM layer 312 is used to mitigate material loss of the fin 304 during a subsequent gate etching process. In various embodiments, the epitaxial layer 308 (e.g., including the second composition) or a portion thereof can form a channel region of a GAA transistor of the device 300. For example, the layer 308 can be referred to as a semiconductor channel layer, which is used to form a channel region of a GAA transistor. In various embodiments, the semiconductor channel layer (e.g., layer 308 or a portion thereof) can include (one or more) nanosheet channels, (one or more) nanowire channels, (one or more) strip channels, and / or other suitable channel configurations. As described below, the semiconductor channel layer is also used to form a portion of the source / drain components of the GAA transistor.

[0027] Note that although the fin 304 is shown as including four (4) epitaxial layers 310 and four (4) epitaxial layers 308, this is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It will be appreciated that any number of epitaxial layers may be formed, where, for example, the number of epitaxial layers depends on the desired number of semiconductor channel layers for the GAA transistor. In some instances, the number of epitaxial layers, and thus the number of semiconductor channel layers, is selected based on the type of device implemented by the GAA transistor (e.g., such as a core (logic) device, an SRAM device, or an analog device, etc.). In some embodiments, the number of epitaxial layers 308, and therefore the number of semiconductor channel layers, is between 4 and 10.

[0028] In some embodiments, epitaxial layers 310 each have a thickness range of about 4-8 nanometers (nm). In some cases, epitaxial layers 308 each have a thickness range of about 4-8 nm. As described above, epitaxial layer 308 can be used as (one or more) channel regions of a subsequently formed multi-gate device (e.g., a GAA transistor), and its thickness can be selected at least in part based on device performance considerations. Epitaxial layer 310 can be used to define the gap distance between (one or more) adjacent channel regions of a subsequently formed multi-gate device, and its thickness can also be selected at least in part based on device performance considerations.

[0029] The method 200 then proceeds to block 204 where shallow trench isolation (STI) features are formed. Figure 3 and Figure 4 In an embodiment of block 204 , STI features 402 are formed to be interposed between fins 304 . Figure 4 An embodiment of a semiconductor device 300 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the cross section BB' or the cross section CC'. In some instances, after forming the fins 304, the trenches 307 inserted between the fins 304 may be filled with a dielectric material. In some embodiments, the dielectric material used to fill the trenches 307 may include SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations of the foregoing, and / or other suitable materials known in the art. In various instances, the dielectric material may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes.

[0030] In some examples, after depositing the dielectric material, a CMP process may be performed to remove excess portions of the dielectric material and planarize the top surface of the device 300 to form the STI feature 402, such as Figure 4 In some embodiments, the CMP process may also remove the HM layer 312 above each fin 304 to expose the topmost layer of the stack of layers 308, 310. In this example, the topmost layer of the stack of layers 308, 310 includes the epitaxial layer 308. However, as previously discussed, other stack configurations are possible.

[0031] The method 200 then proceeds to block 206 where a first STI recess process is performed. Figure 4 and Figure 5 In an embodiment of block 206, an STI recess process is performed to recess the STI feature 402, thereby forming a recessed STI feature 402A, such as Figure 5 shown. Figure 5An embodiment of a semiconductor device 300 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to a plane defined by a cross section BB' or a cross section CC' of the semiconductor device 300. In various embodiments, the recessed STI component 402A formed by the first STI recess process may be formed to span multiple regions of the semiconductor device 300, the multiple regions including multiple device types (e.g., core devices, SRAM devices, and analog devices). In various instances, the STI component 402A is recessed so that the fin 304 extends above the STI component 402A. In some embodiments, the recess process may include a dry etching process, a wet etching process, and / or a combination of the foregoing. In some embodiments, the recess depth of the first STI recess process is controlled (e.g., by controlling the etching time) to obtain a desired height "H1" of the exposed upper portion of the fin 304. In some embodiments, the height "H1" exposes a subset 502 of the epitaxial stack of layers 308, 310 of each fin 304. In various instances, the exposed subset 502 of the epitaxial stack of layers 308, 310 includes a first number of exposed epitaxial layers 308. In other words, the exposed subset 502 of the epitaxial stack of layers 308, 310 includes a first number of exposed semiconductor channel layers. The epitaxial layers 308, 310 (including at least one semiconductor channel layer) that are not exposed by the first STI recess process can remain embedded in the STI feature 402A. As described in more detail below, the first number of exposed semiconductor channel layers provided by the subset 502 can define a first number of semiconductor channel layers for a first device type, which is disposed within the first region of the semiconductor device 300. In the present example, the first device type corresponding to the first number of exposed semiconductor channel layers can include a core (logic) device. In addition, although the subset 502 is shown as including three (3) semiconductor channel layers, in some cases, the subset 502 may optionally include less than three (3) semiconductor channel layers.

[0032] The method 200 then proceeds to block 208 where a second STI recess process is performed. Figure 5 and Fig. 6A , Figure 6B , Figure 6C In an embodiment of block 208, an STI recess process is performed to further recess the STI feature 402A, thereby forming a recessed STI feature 402B, such as Fig. 6A and Figure 6C shown. Fig. 6A , Figure 6B , Figure 6C An embodiment of a semiconductor device 300 is provided along with Figure 1The cross-sectional view is a plane substantially parallel to the plane defined by the cross section BB' or the cross section CC'. In some embodiments, the recessed STI component 402B formed by the second STI recess process may be formed in the analog device region ( Fig. 6A ) and SRAM device area ( Figure 6C ), while the STI component 402A remains in the core device region ( Figure 6B ). For example, before forming the recessed STI component 402B, a resist layer is formed above the device 300 and patterned to form a patterned resist layer 602, which exposes the analog device region and the SRAM device region of the semiconductor device 300, while the patterned resist layer 602 remains disposed above the core device region. In some embodiments, after forming the patterned resist layer 602, a second STI recess process is performed to further recess the STI component 402A to form the STI component 402B in the analog device region and the SRAM device region, while the core device region remains masked by the patterned resist layer 602. In some embodiments, the recess process may include a dry etching process, a wet etching process, and / or a combination of the foregoing. After the second STI recess process, the patterned resist layer 602 may be removed, for example, by a solvent, a resist stripper, ashing, or other suitable techniques.

[0033] In some embodiments, the recess depth of the second STI recess process is controlled (e.g., by controlling the etching time) to obtain a desired height "H2" of the exposed upper portion of the fin 304 in the analog device region and the SRAM device region. In some embodiments, the height "H2" exposes one or more layers in the epitaxial stack of layers 308, 310 that were previously covered by the STI feature 402A. In various instances, the second STI recess process is used to expose one or more additional epitaxial layers 308, resulting in a total number of exposed epitaxial layers 308 greater than the first number of epitaxial layers 308 exposed by the first STI recess process. In other words, the second STI recess process is used to expose one or more additional semiconductor channel layers, resulting in a total number of exposed semiconductor channel layers greater than the first number of semiconductor channel layers exposed by the first STI recess process. Therefore, in various embodiments, the analog device region and the SRAM device region ( Fig. 6A and Figure 6C ) is larger than the amount of exposed semiconductor channel layer in the core device area ( Figure 6B). In at least some embodiments, the second STI recess process is used to expose all epitaxial layers 308 in the analog device region and the SRAM device region. As described in more detail below, the number of exposed epitaxial layers 308 in the analog device region and the SRAM device region can define the number of semiconductor channel layers for the analog device region and the SRAM device formed in the corresponding region of the semiconductor device 300. Although Fig. 6A and Figure 6C The example is shown as including four (4) semiconductor channel layers in the analog device region and the SRAM device region, respectively, but in some cases, the analog device region and the SRAM device region may alternatively include more than four (4) semiconductor channel layers.

[0034] The method 200 then proceeds to block 210 where a fin capping layer is formed. Fig. 6A , Figure 6B , Figure 6C and Fig. 7A , Figure 7B , Figure 7C In an embodiment of block 210 , a fin capping layer 702 may be formed over the fins 304 in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 . Fig. 7A , Figure 7B , Figure 7C An embodiment of a semiconductor device 300 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the cross section BB' or the cross section CC'. In some embodiments, the fin cover layer 702 includes an epitaxial SiGe layer. The fin cover layer 702 can be conformally deposited above each fin 304. For example, the fin cover layer 702 can be deposited by an MBE process, an MOCVD process, an ALD process and / or other suitable epitaxial growth process. In various embodiments, as described below, the fin cover layer 702 is a sacrificial layer that is removed in a subsequent processing stage. In addition, the fin cover layer 702 can be used to increase the gate area density of the GAA transistor formed on the semiconductor device 300. For example, in the gate region of the device (e.g., in the analog device region, the core device region, or the SRAM device region), the area occupied by the fin cover layer 702 can be subsequently replaced by a gate structure (e.g., including a dielectric layer and a metal gate layer). In some cases, the fin cover layer 702 has a thickness in the range of about 4-16nm. In various embodiments, the thickness of the fin cap layer 702 may be selected to provide a desired areal density for subsequently formed gate structures (eg, to provide lower gate resistance) while also providing a sufficient process window for fabrication of the semiconductor device 300 .

[0035] The method 200 then proceeds to block 212 where a dual layer dielectric is formed. Fig. 7A , Figure 7B , Figure 7C and Fig. 8A , Figure 8B , Figure 8C In the embodiment of block 212 , a dual-layer dielectric 802 may be formed in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 . Fig. 8A , Figure 8B , Figure 8C An embodiment of a semiconductor device 300 is provided along with Figure 1 804. In some embodiments, a double-layer dielectric 802 is formed by filling a trench adjacent to a fin cap layer 702 (deposited above each fin in the fin 304) with a first material 804 and a second material 806 disposed above the first material 804, thereby forming a double-layer dielectric 802. In various cases, the double-layer dielectric 802 may be deposited by a CVD process, an ALD process, a PVD process, and / or other suitable processes. In some instances, after depositing the first material 804 and the second material 806, a CMP process may be performed to remove excess material portions and planarize the top surface of the device 300 to provide the double-layer dielectric 802. In some embodiments, the first material 804 may include a low-K (LK) material including SiCN, SiOC, SiOCN, or another low-K material (e.g., having a dielectric constant "K" <7). In some examples, the second material 806 may include a high-K (HK) material including HfO2, ZrO2, HfAlO x 、HfSiO x , Al2O3 or another high-K material (e.g., having a dielectric constant "K" > 7). Therefore, in various cases, the double-layer dielectric 802 includes an HK upper portion (e.g., the second material 806) and a LK lower portion (e.g., the first material 804). In some instances, the ratio of the upper portion to the lower portion (i.e., the HK / LK ratio) is approximately 1 / 20-20 / 1. In some embodiments, the double-layer dielectric 802 is used to expand the cut metal gate (CMG) process window. In addition, in some cases, the double-layer dielectric 802 can be used to prevent undesirable lateral merging of source / drain epitaxial layers subsequently formed on adjacent fins 304.

[0036] The method 200 then proceeds to block 214 where a dummy gate structure is formed. Although the present discussion is directed to a replacement gate (gate last) process whereby a dummy gate structure is formed and subsequently replaced, other configurations are possible.

[0037] refer to Fig. 9A , Fig. 9B , Fig. 9C and Fig. 10A , Fig. 10B , Fig. 10C In an embodiment of block 214 , gate stacks 903 , 905 , 907 are formed over the fins 304 in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 . Fig. 9A , Fig. 9B , Fig. 9C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section CC' is substantially parallel to the cross-sectional view of the plane, and Fig. 10A , Fig. 10B , Fig. 10C An embodiment of a semiconductor device 300 is provided along with Figure 1 The cross-sectional view of the plane substantially parallel to the plane defined by the cross section AA' of the semiconductor device 300. In one embodiment, the gate stacks 903, 905, 907 are dummy (sacrificial) gate stacks, which are subsequently removed and replaced by the final gate stacks at a subsequent processing stage of the device 300, as described below. The gate stacks 903, 905, 907 may be replaced by a high-K dielectric layer (HK) and a metal gate electrode (MG) at a subsequent processing stage. In some embodiments, the gate stacks 903, 905, 907 are formed above the substrate 302 and are at least partially disposed above the fin 304 in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300. The portion of the fin 304 below the gate stacks 903, 905, 907 may be referred to as a channel region. The gate stacks 903, 905, 907 may also define the source / drain region of the fin 304, for example, the region where the fin 304 is adjacent to the channel region and on the opposite side of the channel region.

[0038] In some embodiments, the gate stacks 903, 905, 907 include a dielectric layer 904 and an electrode layer 906. The gate stacks 903, 905, 907 may also include one or more hard mask layers 908, 910. In some embodiments, the hard mask layer 908 may include an oxide layer, and the hard mask layer 910 may include a nitride layer. In some embodiments, the gate stacks 903, 905, 907 are formed by various process steps (e.g., layer deposition, patterning, etching, and other suitable process steps). In some examples, the layer deposition process includes CVD (including both low pressure CVD and plasma enhanced CVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or a combination of the foregoing. When forming the gate stacks 903, 905, 907, for example, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods.

[0039] In some embodiments, the dielectric layer 904 includes silicon oxide. Alternatively or additionally, the dielectric layer 904 may include silicon nitride, a high-K dielectric material, or other suitable material. In some embodiments, the electrode layer 906 may include polycrystalline silicon (polysilicon). In some embodiments, the oxide of the hard mask layer 908 includes a pad oxide layer, which may include SiO2. In some embodiments, the nitride of the hard mask layer 910 includes a pad nitride layer, which may include Si3N4, silicon oxynitride, or silicon carbide.

[0040] In some embodiments, and after forming the gate stacks 903, 905, 907, a spacer layer 1202 is deposited on the substrate. The spacer layer 1202 can be a conformal layer. For example, the spacer layer 1202 is shown in various figures, such as Fig. 12A , Fig. 12B , Fig. 12CAs shown. The spacer layer 1202 can be deposited above and on the sidewalls of the gate stacks 903, 905, and 907. In some cases, the spacer layer 1202 can have a thickness of about 2-10 nm. In some instances, the spacer layer 1202 can include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., having a dielectric constant "K" <7), and / or a combination of the foregoing. In some embodiments, the spacer layer 1202 includes multiple layers, such as a main spacer layer, a liner layer, and the like. For example, the spacer layer 1202 can be formed by conformally depositing a dielectric material over the device 300 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes.

[0041] The method 200 then proceeds to block 216 where a first source / drain etch process is performed. Fig.11A , Fig. 11B , Fig. 11C and Fig. 12A , Fig. 12B , Fig. 12C In an embodiment of block 216 , a first source / drain etching process is performed on the analog device region and the SRAM device region of the semiconductor device 300 . Fig.11A , Fig. 11B , Fig. 11C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section BB' is substantially parallel to the cross-sectional view of the plane, and Fig. 12A , Fig. 12B , Fig. 12C An embodiment of a semiconductor device 300 is provided along with Figure 1A cross-sectional view of a plane substantially parallel to the plane defined by the section AA' of the semiconductor device 300. In some embodiments, a resist layer is formed above the device 300 and patterned to form a patterned resist layer 1102, which exposes the analog device region and the SRAM device region of the semiconductor device 300, while the patterned resist layer 1102 remains disposed above the core device region. In some embodiments, after forming the patterned resist layer 1102, a first source / drain etching process is performed to remove the fin capping layer 702 and the exposed epitaxial layers 308, 310 in the source / drain regions of the analog device region and the SRAM device region to form a trench 1104, which exposes the substrate portion 302A below the fin 304 in the analog device region and the SRAM device region, while the core device region remains masked by the patterned resist layer 1102. For example, the first source / drain etch process may be used to remove portions of the epitaxial layers 308, 310 (in the source / drain regions of the analog device region and the SRAM device region) that were exposed during the second STI recess process of block 208 as described above. Fig. 12A and Fig. 12C As shown, the first source / drain etching process may also remove portions of the spacer layer 1202 (e.g., from the top surfaces of the gate stacks 903 and 907). In some embodiments, the first source / drain etching process may include a dry etching process, a wet etching process, and / or a combination of the foregoing. After the first source / drain etching process, the patterned resist layer 1102 may be removed, for example, by a solvent, a resist stripper, ashing, or other suitable techniques.

[0042] The method 200 then proceeds to block 218 where a second source / drain etch process is performed. Fig.13A , Fig. 13B , Fig. 13C and Fig.14A , Fig. 14B , Fig. 14C In an embodiment of block 218 , a second source / drain etching process is performed on a core device region of the semiconductor device 300 . Fig.13A , Fig. 13B , Fig. 13C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section BB' is substantially parallel to the cross-sectional view of the plane, and Fig.14A , Fig. 14B , Fig. 14C An embodiment of a semiconductor device 300 is provided along with Figure 1A cross-sectional view of a plane substantially parallel to the plane defined by the cross section AA' of the semiconductor device 300. In some embodiments, a resist layer is formed above the device 300 and patterned to form a patterned resist layer 1302, which exposes the core device region of the semiconductor device 300, while the patterned resist layer 1302 remains disposed above the analog device region and the SRAM device region. In some embodiments, after the patterned resist layer 1302 is formed, a second source / drain etching process is performed to remove the fin capping layer 702 and the exposed epitaxial layers 308, 310 in the source / drain region of the core device region to form a trench 1304, which exposes the underlying portion of the fin 304 in the core device region, while the analog device region and the SRAM device region remain masked by the patterned resist layer 1302. For example, the second source / drain etch process may be used to remove portions (in the source / drain regions of the core device area) of the epitaxial layers 308, 310 (e.g., a subset 502 of the epitaxial stack including the layers 308, 310) that were exposed during the first STI recess process described above at block 206. The epitaxial layers 308, 310 (including at least one semiconductor channel layer) that were not exposed by the first STI recess process may remain embedded within the STI features 402A below the trenches 1304, as shown. Fig. 13B Reference Fig. 14B , the second source / drain etching process may also remove portions of the spacer layer 1202 (e.g., from the top surface of the gate stack 905). In some embodiments, the second source / drain etching process may include a dry etching process, a wet etching process, and / or a combination of the foregoing. After the second source / drain etching process, the patterned resist layer 1302 may be removed, for example, by a solvent, a resist stripper, ashing, or other suitable technique.

[0043] The method 200 then proceeds to block 220 where an internal spacer is formed. Fig.15A , Fig. 15B , Fig. 15C and Fig.16A , Fig. 16B , Fig. 16C In the embodiment of block 220 , internal spacers 1602 are formed in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 . Fig.15A , Fig. 15B , Fig. 15C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section BB' is substantially parallel to the cross-sectional view of the plane, and Fig.16A , Fig. 16B , Fig. 16C An embodiment of a semiconductor device 300 is provided along with Figure 1 The cross-sectional view is a plane substantially parallel to the plane defined by the section AA' of FIG. In some embodiments, the formation of the internal spacer 1602 may include lateral etching of the epitaxial layer 310 (SiGe layer), followed by deposition and etching back of a dielectric material to form the internal spacer 1602. In some embodiments, the internal spacer 1602 includes amorphous silicon. In some instances, the internal spacer 1602 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., having a dielectric constant "k" <7) and / or a combination of the foregoing. In various instances, the internal spacer layer 1602 may extend below the spacer layer 1202 (formed on the sidewalls of the gate stacks 903, 905, 907) while abutting subsequently formed source / drain features, as described below.

[0044] The method 200 then proceeds to block 222 where source / drain features are formed. Fig.17A , Fig. 17B , Fig. 17C and Fig.18A , Fig.18B , Fig.18C In an embodiment of block 222 , source / drain features 1702 are formed in the analog device region and the SRAM device region of the semiconductor device 300 , and source / drain features 1802 are formed in the core device region of the semiconductor device 300 . Fig.17A , Fig. 17B , Fig. 17C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section BB' is substantially parallel to the cross-sectional view of the plane, and Fig.18A , Fig.18B , Fig.18C An embodiment of a semiconductor device 300 is provided along with Figure 1 AA' defined by the plane substantially parallel to the cross-sectional view. In some embodiments, the source / drain components 1702, 1802 are formed in the source / drain region, which is adjacent to and on either side of the gate stack 903, 905, 907. For example, the source / drain component 1702 can be formed in the trench 1104 of the analog device region and the SRAM device region, above the exposed substrate portion 302A and in contact with the adjacent internal spacer 1602 and the semiconductor channel layer (epitaxial layer 308). Similarly, the source / drain component 1802 can be formed in the trench 1304 of the core device region, above the epitaxial layers 308, 310 embedded with the STI component 402 and in contact with the adjacent internal spacer 1602 and the semiconductor channel layer (epitaxial layer 308).

[0045] In some embodiments, the source / drain components 1702, 1802 are formed by epitaxially growing a semiconductor material layer in the source / drain region. In various embodiments, the semiconductor material layer grown to form the source / drain components 1702, 1802 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain components 1702, 1802 may be formed by one or more epitaxial (epi) processes. In some embodiments, the source / drain components 1702, 1802 may be in-situ doped during the epitaxial process. For example, in some embodiments, the epitaxially grown SiGe source / drain components may be doped with boron. In some cases, the epitaxially grown Si epitaxial source / drain components may be doped with carbon to form Si:C source / drain components, doped with phosphorus to form Si:P source / drain components, or doped with both carbon and phosphorus to form SiCP source / drain components. In some embodiments, the source / drain features 1702, 1802 are not doped in situ, but an implantation process is performed to dope the source / drain features 1702, 1802. In some embodiments, the formation of the source / drain features 1702, 1802 may be performed in separate processing sequences for each of the N-type and P-type source / drain features. Fig.17A / Fig. 17B / Fig. 17C As shown, the double-layer dielectric 802 can effectively prevent undesired lateral merging of source / drain features 1702 , 1802 formed on adjacent fins 304 .

[0046] The method 200 then proceeds to block 224 where an interlayer dielectric (ILD) layer is formed. Fig.19A , Fig.19B , Fig.19C and Fig. 20A , Fig. 20B , Fig. 20C In an embodiment of block 224 , an ILD layer 1902 is formed in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 . Fig.19A , Fig.19B , Fig.19C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section BB' is substantially parallel to the cross-sectional view of the plane, and Fig. 20A , Fig. 20B , Fig. 20C An embodiment of a semiconductor device 300 is provided along with Figure 1AA' defined by the plane substantially parallel to the plane defined by the cross section. In some embodiments, before forming the ILD layer 1902, a contact etch stop layer (CESL) 1904 is formed over the device 300. In some examples, the CESL 1904 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 1904 can be formed by a plasma enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 1902 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)) and / or other suitable dielectric materials. The ILD layer 1902 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 1902 , a high thermal budget process may be performed on the device 300 to anneal the ILD layer 1902 .

[0047] In some examples, after depositing the ILD layer 1902 (and / or the CESL 1904 or other dielectric layer), a planarization process may be performed to expose the top surface of the gate stacks 903, 905, 907. For example, the planarization process includes a CMP process that removes portions of the ILD layer 1902 (and the CESL 1904, if present) overlying the gate stacks 903, 905, 907 and planarizes the top surface of the device 300. In addition, the CMP process may remove the hard mask layers 908, 910 overlying the gate stacks 903, 905, 907 to expose the underlying electrode layer 906 of the dummy gate, such as a polysilicon electrode layer.

[0048] The method 200 proceeds to block 226 where the dummy gate is removed. Fig. 20A , Fig. 20B , Fig. 20C and Fig.21A , Fig. 21B , Fig. 21C In the example of block 226 , the exposed electrode layer 906 of the gate stacks 903 , 905 , 907 may be removed by a suitable etching process. Fig.21A , Fig. 21B , Fig. 21C An embodiment of a semiconductor device 300 is provided along with Figure 1The cross-sectional view is a plane substantially parallel to the plane defined by the section CC'. In various embodiments, the electrode layer 906 can be etched using wet etching, dry etching, or a combination of the foregoing. In some embodiments, and as a result of removing the electrode layer 906, the underlying dielectric layer 904 is exposed.

[0049] The method 200 proceeds to block 228 where the gate stack dielectric layer and the underlying SiGe layer are removed. Fig.21A , Fig. 21B , Fig. 21C and Fig.22A , Fig. 22B , Fig. 22C In an example, in an embodiment of block 228, the exposed dielectric layer 904 of the gate stacks 903, 905, 907 may first be removed by a suitable etching process (eg, wet etching, dry etching, or a combination of the foregoing). Fig.22A , Fig. 22B , Fig. 22C An embodiment of a semiconductor device 300 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the cross section CC' of the semiconductor device 300. After removing the dielectric layer 904, and in another embodiment of frame 228, selectively removing the SiGe layer (including the fin cover layer 702 and the epitaxial layer 310) in the channel region of the GAA transistor in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 is performed. In some embodiments, the SiGe layer is removed from the fin 304 in the groove provided by removing the dummy gate electrode layer 906 and the dielectric layer 904. In various examples, the SiGe layer (including the fin cover layer 702 and the epitaxial layer 310) is removed from the exposed fin 304 using a selective wet etching process. In some embodiments, the selective wet etching includes ammonia and / or ozone. As just one example, the selective wet etching includes tetramethylammonium hydroxide (TMAH). In one embodiment, the fin cover layer 702 and the epitaxial layer 310 are SiGe, and the epitaxial layer 308 is silicon, thereby allowing the SiGe layer to be selectively removed. Note that after selectively removing the SiGe layer, a gap may be formed between adjacent semiconductor channel layers in the channel region (eg, gap 2202 between epitaxial layers 308). In some examples, as described above, selectively removing the SiGe layer may be referred to as a semiconductor channel layer release process.

[0050] The method 200 then proceeds to block 230 where a gate structure is formed. Fig.23A , Fig. 23B , Fig.23C and Fig.24A , Fig. 24B , Fig.24CIn an embodiment of block 230 , a gate structure is formed in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300 . Fig.23A , Fig. 23B , Fig.23C An embodiment of a semiconductor device 300 is provided along with Figure 1 The plane defined by section CC' is substantially parallel to the cross-sectional view of the plane, and Fig.24A , Fig. 24B , Fig.24C An embodiment of a semiconductor device 300 is provided along with Figure 1 The gate structure described herein may include a high-K / metal gate stack, but other compositions are also possible. In some embodiments, the gate structure may form a gate associated with a multi-channel provided by a plurality of exposed semiconductor channel layers (exposed epitaxial layer 308, now with gaps between them) in the channel region of the GAA transistor in each of the analog device region, the core device region, and the SRAM device region of the device 300. In some embodiments, a gate dielectric is formed in a trench of the GAA transistor in each of the analog device region, the core device region, and the SRAM device region of the device 300, the trench being provided by removing a dummy gate and / or by releasing the semiconductor channel layer, as described above. In various embodiments, the gate dielectric includes an interface layer (IL) 2302 and a high-K gate dielectric layer 2304 formed above the interface layer 2302. In some embodiments, the gate dielectric has a total thickness of about 1-5 nm. As used and described herein, a high-K gate dielectric includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide.

[0051] In some embodiments, the interface layer 2302 may include a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer 2302 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer 2304 may include a high-K dielectric layer, such as hafnium oxide (HfO2). Alternatively, the high-K gate dielectric layer 2304 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, silicon oxynitride (SiON), combinations of the foregoing, or other suitable materials. The high-K gate dielectric layer 2304 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0052] In another embodiment of block 230, a metal gate including a metal layer 2306 is formed over the gate dielectric (e.g., over the IL 2302 and the high-K gate dielectric layer 2304). The metal layer 2306 may include a metal, a metal alloy, or a metal silicide. Additionally, the formation of the gate dielectric / metal gate stack may include deposition to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate material and thereby planarize the top surface of the device 300.

[0053] In some embodiments, the metal layer 2306 may include a single layer or optionally a multilayer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the metal layer 2306 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or a combination of the foregoing. In various embodiments, the metal layer 2306 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, the metal layer 2306 may be formed for N-type and P-type transistors, respectively, and the N-type and P-type transistors may use different metal layers. In addition, the metal layer 2306 may provide an N-type or P-type work function, may be used as a transistor (e.g., a GAA transistor) gate electrode, and in at least some embodiments, the metal layer 2306 may include a polysilicon layer. With respect to the GAA transistor shown and discussed, the gate structure includes a portion inserted into each epitaxial layer 308 , each epitaxial layer 308 providing a semiconductor channel layer for the GAA transistor.

[0054] In various embodiments, the channel region formed by the epitaxial layer 308 and defining the semiconductor channel layer may have various sizes in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300. For example, from an end view of the epitaxial layer 308 (e.g., Fig.23A , Fig. 23B , Fig.23C ) Considering the general thickness dimension “T1” and the general width dimension “W1” of the epitaxial layer 308. In some embodiments, the epitaxial layer 308 may have a thickness dimension “T1” in the range of about 4-8 nm in each of the analog device region, the core device region, and the SRAM device region of the semiconductor device 300. In some examples, the width dimension “W1” of the epitaxial layer 308 in the analog device region ( Fig.23A ) can be greater than or equal to about 15nm, and in the core device area ( Fig. 23B ) can be in the range of about 10-60nm, in the SRAM device area ( Fig.23C ) can be in the range of about 6-20 nm. In addition, considering the general length dimension "L1" of the epitaxial layer 308 (e.g., reference Fig.24A , Fig. 24B , Fig.24C ), the length dimension “L1” of the epitaxial layer 308 is in the analog device region ( Fig.24A ) can be larger than about 20nm, and in the core device area ( Fig. 24B) can be less than or equal to about 20 nm, and in the SRAM device area ( Fig.24C ) can be less than or equal to about 20 nm. In some cases, the spacing / gap between adjacent semiconductor channel layers (epilayer 308) is equal to about 4-8 nm (eg, determined by the thickness of released epilayer 310).

[0055] In addition, due to the two-step STI recess process (boxes 206 and 208 of method 200), and the resulting epitaxial layers 308, 310 that remain embedded within the STI features 402A (e.g., within the core device region), there will be an STI offset "S1" between the STI features 402A in the core device region and the STI features 402B in the analog / SRAM device region. In some embodiments, the STI offset "S1" is greater than or equal to the thickness of the pair of epitaxial layers 308, 310. Typically, the STI offset "S1" can be equal to the total thickness of the epitaxial layers 308, 310 that remain embedded (or not released) within the STI features 402A in the core device region. In some cases, the STI offset "S1" is in the range of about 8-16nm. In some examples, the number of embedded (unreleased) epitaxial layers 308, 310 (e.g., indicated by line 2308) in the core device region may be greater than or equal to one (1) pair of epitaxial layers 308, 310. In various embodiments, there may be no embedded (unreleased) epitaxial layers 308, 310 in the analog device region or the SRAM device region of the semiconductor device 300.

[0056] Similarly, and again due to the two-step STI recess process, there will be a source / drain offset "S2" between the source / drain features 1802 in the core device area and the source / drain features 1702 in the analog / SRAM device area. In some embodiments, the source / drain offset "S2" is greater than or equal to the thickness of the pair of epitaxial layers 308, 310. Typically, the source / drain offset "S2" can be equal to the total thickness of the epitaxial layers 308, 310 that remain embedded (or not released) within the STI features 402A in the core device area (during the second source / drain etch process of block 218). In some cases, the source / drain offset "S2" is in the range of approximately 8-16nm. In some examples, the number of unetched epitaxial layers 308 , 310 (eg, indicated by line 2408 ) in the source / drain regions of the core device area and beneath the source / drain features 1802 can be greater than or equal to one (1) pair of epitaxial layers 308 , 310 .

[0057] The method 200 then proceeds to block 232 where a metal gate cutting process is performed. Fig.23A , Fig. 23B , Fig.23C In the embodiment of block 232 and after forming the metal layer 2306, a cut metal gate process may be performed to isolate the metal layer 2306 of adjacent structures. As an example, a photolithography and etching process may be first performed to remove the portion of the metal layer 2306 in the cut metal gate region 2310. In some embodiments, removing the portion of the metal layer 2306 in the cut metal gate region 2310 may form a trench that exposes the second material 806 below the double-layer dielectric 802. Thereafter, in various examples, a cut metal gate material 2312 may be deposited within the trench to electrically isolate the metal layer 2306 of adjacent structures. In some embodiments, the cut metal gate material 2312 includes a nitride-based material deposited by ALD, CVD, PVD, or other suitable process. In some cases, after depositing the cut metal gate material 2312, a CMP process may be performed to remove excess material and planarize the top surface of the device 300.

[0058] In some embodiments, contact components may also be formed. For example, in some embodiments, a portion of the metal layer 2306 may be etched back, and a tungsten (W) layer or a fluorine-free W (FFW) layer may be deposited over the etched back metal layer 2306. In various instances, the W layer or the FFW layer may be used as an etch stop layer, and may also provide a reduced contact resistance (e.g., to the metal layer 2306). In some cases, a self-aligned contact layer may be formed over the W layer or the FFW layer, wherein the self-aligned contact layer may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a combination of the foregoing, or other suitable materials. In various embodiments, source / drain contacts are formed to provide contact with the source / drain components 1702, 1802, and vias may be formed to provide electrical connection to the source / drain contacts. In some embodiments, a metal contact etch stop layer (MCESL) and an ILD layer may also be formed.

[0059] Typically, the semiconductor device 300 may be further processed to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) on the substrate 302, which are configured to connect various components to form functional circuits, which may include one or more multi-gate devices (e.g., one or more GAA transistors). In a further development of this example, the multilayer interconnects may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect components may be made of various conductive materials, including copper, tungsten and / or silicide. In one example, inlay and / or dual inlay processes are used to form copper-related multilayer interconnect structures. In addition, additional process steps may be implemented before, during, and after the method 200, and some of the process steps described above may be replaced or eliminated according to various embodiments of the method 200. In addition, although the method 200 has been shown and described as including a device 300 having a GAA transistor, it should be understood that other device configurations are also possible. In some embodiments, method 200 may be used to fabricate FinFET devices or other multi-gate devices.

[0060] With respect to the description provided herein, methods and structures for providing a multi-gate device (e.g., such as a GAA transistor) having multiple semiconductor channel layers selected based on the device type implemented by the multi-gate device are disclosed. In some embodiments, a core (logic) device can be implemented using a smaller number of semiconductor channel layers compared to an SRAM device and an analog device, while both the SRAM device and the analog device can be implemented using a larger number of semiconductor channel layers compared to the core (logic) device. In some instances, a core (logic) device can be implemented using a smaller number of semiconductor channel layers to reduce total device capacitance and provide increased device speed. Optionally, in various embodiments, a SRAM device can be implemented using a larger number of semiconductor channel layers to provide increased cell current. In some embodiments, an analog device can be implemented using a larger number of semiconductor channel layers to provide increased cell capacitance. In some instances, the number of semiconductor channel layers for the core (logic) device can be less than or equal to three (3), and the number of semiconductor channel layers for both the SRAM device and the analog device can be greater than or equal to four (4). In general, by providing a multi-gate device (e.g., a core device, an SRAM device, or an analog device) having multiple semiconductor channel layers selected based on the device type implemented, embodiments of the present disclosure provide methods and device structures that can simultaneously meet the different performance requirements of various different device types. Those skilled in the art will readily appreciate that the methods and structures described herein can be applied to a variety of other semiconductor devices to advantageously obtain similar benefits from these other devices without departing from the scope of the present disclosure.

[0061] Therefore, a method is described in one embodiment of the present disclosure, the method comprising providing a first fin in a first device type region and providing a second fin in a second device type region. In some embodiments, each of the first fin and the second fin includes a plurality of semiconductor channel layers. In some instances, the method further comprises performing a two-step recess of the STI region on opposite sides of each of the first fin and the second fin to expose a first number of semiconductor channel layers among the plurality of semiconductor channel layers of the first fin in the first device type region and a second number of semiconductor channel layers among the plurality of semiconductor channel layers of the second fin in the second device type region. In various embodiments, the method further comprises forming a first gate structure in the first device type region and forming a second gate structure in the second device type region, wherein the first gate structure is formed above the first fin having the first number of exposed semiconductor channel layers, and wherein the second gate structure is formed above the second fin having the second number of exposed semiconductor channel layers.

[0062] In another embodiment, a method is discussed that includes providing a plurality of fins extending from a substrate, wherein each of the plurality of fins includes a stack of epitaxial layers, wherein the stack of epitaxial layers has a plurality of first type layers and a plurality of second type layers. In some embodiments, the method also includes forming a plurality of STI components inserted into the plurality of fins. Thereafter, in some cases, a first STI recess process is performed to expose a first number of first type layers and a first number of second type layers within each of the plurality of fins. In some embodiments, after the first STI recess process, a second number of first type layers and a second number of second type layers remain embedded within the STI component. In some instances, the method also includes performing a second STI recess process to expose a second number of first type layers and a second number of second type layers in a first region of the semiconductor device, wherein after the second STI process, the second number of first type layers and the second number of second type layers remain embedded within the STI component in a second region of the semiconductor device.

[0063] In yet another embodiment, a semiconductor device is discussed that includes a first transistor located in a first device type region of a substrate and a second transistor located in a second device type region of the substrate. In some embodiments, the first transistor includes a first gate structure and a first source / drain component adjacent to the first gate structure, and the second transistor includes a second gate structure and a second source / drain component adjacent to the second gate structure. In various instances, the first transistor includes a first fin having a first number of semiconductor channel layers disposed above a first STI region and in lateral contact with the first source / drain component, and the second transistor includes a second fin having a second number of semiconductor channel layers disposed above a second STI region and in lateral contact with the second source / drain component, and the first number of semiconductor channel layers is different from the second number of semiconductor channel layers.

[0064] In yet another embodiment, a method for manufacturing a semiconductor device is provided, comprising: providing a first fin in a first device type region and providing a second fin in a second device type region, wherein each of the first fin and the second fin includes a plurality of semiconductor channel layers; performing a two-step recess of a shallow trench isolation (STI) region on opposite sides of each of the first fin and the second fin to expose a first number of semiconductor channel layers among the plurality of semiconductor channel layers of the first fin in the first device type region and a second number of semiconductor channel layers among the plurality of semiconductor channel layers of the second fin in the second device type region; and forming a first gate structure in the first device type region and forming a second gate structure in the second device type region, wherein the first gate structure is formed above the first fin having the first number of exposed semiconductor channel layers, and wherein the second gate structure is formed above the second fin having the second number of exposed semiconductor channel layers.

[0065] In the above method, the first step of the two-step recessing exposes a first number of semiconductor channel layers of the first fin in the first device type region and the second fin in the second device type region, and wherein the second step of the two-step recessing exposes at least one additional semiconductor channel layer of the second fin in the second device type region to provide a second number of exposed semiconductor channel layers.

[0066] In the above method, after the two-step recessing, at least one semiconductor channel layer of the first fin remains embedded in the shallow trench isolation region of the first device type region.

[0067] In the above method, the second number of semiconductor channel layers is greater than the first number of semiconductor channel layers.

[0068] In the above method, the first device type region includes a core device region, and wherein the second device type region includes an analog device region or a static random access memory (SRAM) device region.

[0069] In the above method, the first gate structure corresponds to a first transistor, wherein the second gate structure corresponds to a second transistor, and wherein both the first transistor and the second transistor comprise a gate-all-around (GAA) transistor.

[0070] In the above method, it also includes: after performing the two-step recessing of the shallow trench isolation region and before forming the first gate structure and the second gate structure, forming a double-layer dielectric over the shallow trench isolation region and on opposite sides of each of the first fin and the second fin.

[0071] In the above method, the double-layer dielectric includes a low-K dielectric layer disposed above the shallow trench isolation region and a high-K dielectric layer disposed above the low-K dielectric layer.

[0072] In the above method, it also includes: after performing two-step recessing of the shallow trench isolation area and before forming the first gate structure and the second gate structure, etching the source / drain region of the second device type area to remove the first portion of the second number of exposed semiconductor channel layers to form a first trench in the source / drain region of the second device type area; and after etching the source / drain region of the second device type area, etching the source / drain region of the first device type area to remove the first portion of the first number of exposed semiconductor channel layers to form a second trench in the source / drain region of the first device type area.

[0073] In the above method, it also includes: after forming the first trench and the second trench, epitaxially growing a source / drain component in each of the first trench and the second trench, wherein the source / drain component grown in the first trench contacts a second portion of a second number of exposed semiconductor channel layers disposed under the second gate structure, and wherein the source / drain component grown in the second trench contacts a second portion of a first number of exposed semiconductor channel layers disposed under the first gate structure.

[0074] In yet another embodiment, a method for manufacturing a semiconductor device is provided, comprising: providing a plurality of fins extending from a substrate, wherein each of the plurality of fins comprises a stack of epitaxial layers, the stack of epitaxial layers having a plurality of first type layers and a plurality of second type layers; forming a plurality of shallow trench isolation (STI) features inserted into the plurality of fins; performing a first shallow trench isolation recess process to expose a first number of each of the first type layers and the second type layers within each of the plurality of fins, and wherein, after the first shallow trench isolation recess process, each of the second number of the first type layers and the second type layers remains embedded in the shallow trench isolation feature; and performing a second shallow trench isolation recess process to expose a second number of each of the first type layers and the second type layers in a first region of the semiconductor device, wherein, after the second shallow trench isolation recess process, each of the second number of the first type layers and the second type layers remains embedded in the shallow trench isolation feature in a second region of the semiconductor device.

[0075] In the above method, the first area includes an analog device area or a static random access memory (SRAM) device area, and wherein the second area includes a core device area.

[0076] In the above method, it also includes: after performing the second shallow trench isolation recess process, selectively removing a portion of each of the multiple second type layers exposed by the first recess process and the second recess process within each of the first region and the second region of the semiconductor device to form a gap between adjacent layers of the multiple first type layers.

[0077] In the above method, the method further includes: after selectively removing a portion of each of the plurality of second type layers, forming a portion of a gate structure in each of the gaps between adjacent layers of the plurality of first type layers.

[0078] In the above method, the exposed first number of first type layers and the second number of first type layers include channel layers associated with transistors in each of the first region and the second region, and wherein the first number of channel layers in the first region is greater than the second number of channel layers in the second region.

[0079] In the above method, the transistor in each of the first region and the second region includes a gate-all-around (GAA) transistor.

[0080] In yet another embodiment, a semiconductor device is provided, comprising: a first transistor located in a first device type region of a substrate, wherein the first transistor comprises a first gate structure and a first source / drain component adjacent to the first gate structure; and a second transistor located in a second device type region of the substrate, wherein the second transistor comprises a second gate structure and a second source / drain component adjacent to the second gate structure; wherein the first transistor comprises a first fin having a first number of semiconductor channel layers disposed above a first shallow trench isolation (STI) region and in laterally contact with the first source / drain component, wherein the second transistor comprises a second fin having a second number of semiconductor channel layers disposed above a second shallow trench isolation region and in laterally contact with the second source / drain component, and wherein the first number of semiconductor channel layers is different from the second number of semiconductor channel layers.

[0081] In the above semiconductor device, at least one semiconductor channel layer of the first fin is embedded in the first shallow trench isolation region.

[0082] The semiconductor device further includes: a first double-layer dielectric disposed above the first shallow trench isolation region and on the opposite side of the first gate structure; and a second double-layer dielectric disposed above the second shallow trench isolation region and on the opposite side of the second gate structure.

[0083] In the above semiconductor device, a first top surface of the first shallow trench isolation region is offset from a second top surface of the second shallow trench isolation region by an amount equal to the thickness of at least one pair of Si / SiGe epitaxial layers of the first fin embedded in the first shallow trench isolation region.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a first fin in a first device type region and providing a second fin in a second device type region, wherein each of the first fin and the second fin includes a plurality of semiconductor channel layers; performing a two-step recess of a shallow trench isolation (STI) region on opposite sides of each of the first fin and the second fin to expose a first number of semiconductor channel layers of the first fin in the first device type region and a second number of semiconductor channel layers of the second fin in the second device type region; forming a double-layer dielectric over the shallow trench isolation region and on opposite sides of each of the first fin and the second fin, wherein a distance between two adjacent double-layer dielectrics is greater than a width of the first fin and the second fin located below the double-layer dielectric from top to bottom; and A first gate structure is formed in the first device type region, and a second gate structure is formed in the second device type region, wherein the first gate structure is formed above the first fin having the first number of exposed semiconductor channel layers, and wherein the second gate structure is formed above the second fin having the second number of exposed semiconductor channel layers.

2. The method according to claim 1, wherein: The first step of the two-step recessing exposes the first number of semiconductor channel layers of the first fin in the first device type region and the second fin in the second device type region, and wherein the second step of the two-step recessing exposes at least one additional semiconductor channel layer of the second fin in the second device type region to provide the second number of exposed semiconductor channel layers.

3. The method according to claim 1, wherein: After the two-step recessing, at least one semiconductor channel layer of the first fin remains embedded in the shallow trench isolation region of the first device type region.

4. The method according to claim 1, wherein: The second number of semiconductor channel layers is greater than the first number of semiconductor channel layers.

5. The method according to claim 1, wherein: The first device type region includes a core device region, and wherein the second device type region includes an analog device region or a static random access memory (SRAM) device region.

6. The method according to claim 1, wherein: The first gate structure corresponds to a first transistor, wherein the second gate structure corresponds to a second transistor, and wherein the first transistor and the second transistor each comprise a gate-all-around (GAA) transistor.

7. The method according to claim 1, further comprising: The double-layer dielectric is formed after performing the two-step recessing of the shallow trench isolation region and before forming the first gate structure and the second gate structure.

8. The method according to claim 7, wherein: The double-layer dielectric includes a low-K dielectric layer disposed above the shallow trench isolation region and a high-K dielectric layer disposed above the low-K dielectric layer.

9. The method according to claim 1, further comprising: After performing the two-step recessing of the shallow trench isolation region and before forming the first gate structure and the second gate structure, etching the source / drain region of the second device type region to remove a first portion of the second amount of exposed semiconductor channel layer to form a first trench in the source / drain region of the second device type region; as well as After etching the source / drain region of the second device type region, etching the source / drain region of the first device type region to remove the first number of exposed first portions of the semiconductor channel layer to form a second trench in the source / drain region of the first device type region.

10. The method according to claim 9, further comprising: After forming the first trench and the second trench, a source / drain feature is epitaxially grown in each of the first trench and the second trench, wherein the source / drain feature grown in the first trench contacts a second portion of the second number of exposed semiconductor channel layers disposed below the second gate structure, and wherein the source / drain feature grown in the second trench contacts a second portion of the first number of exposed semiconductor channel layers disposed below the first gate structure.

11. A method for manufacturing a semiconductor device, comprising: providing a plurality of fins extending from a substrate, wherein each of the plurality of fins comprises a stack of epitaxial layers having a plurality of first type layers and a plurality of second type layers; forming a plurality of shallow trench isolation (STI) features inserted into the plurality of fins; performing a first shallow trench isolation recess process to expose a first number of each of the first type layer and the second type layer within each of the plurality of fins, and wherein a second number of each of the first type layer and the second type layer remains embedded within the shallow trench isolation feature after the first shallow trench isolation recess process; and performing a second shallow trench isolation recess process to expose each of the second number of the first type layer and the second type layer in the first region of the semiconductor device, wherein after the second shallow trench isolation recess process, each of the second number of the first type layer and the second type layer remains embedded in the shallow trench isolation feature in the second region of the semiconductor device; A double-layer dielectric is formed above the shallow trench isolation component and on opposite sides of each of the plurality of fins, wherein a distance between two adjacent double-layer dielectrics is greater than a width of a fin located below the double-layer dielectric among the plurality of fins from top to bottom.

12. The method according to claim 11, wherein: The first region includes an analog device region or a static random access memory (SRAM) device region, and wherein the second region includes a core device region.

13. The method according to claim 11, further comprising: After performing the second shallow trench isolation recess process, portions of each of the multiple second type layers exposed by the first shallow trench isolation recess process and the second shallow trench isolation recess process within each of the first region and the second region of the semiconductor device are selectively removed to form gaps between adjacent layers of the multiple first type layers.

14. The method according to claim 13, further comprising: After selectively removing the portion of each of the plurality of second type layers, a portion of a gate structure is formed within each of the gaps between adjacent layers of the plurality of first type layers.

15. The method according to claim 11, wherein: The first number of exposed first type layers and the second number of exposed first type layers include channel layers associated with transistors in each of the first region and the second region, and wherein the first number of channel layers in the first region is greater than the second number of channel layers in the second region.

16. The method according to claim 15, wherein: The transistor in each of the first region and the second region includes a gate-all-around (GAA) transistor.

17. A semiconductor device comprising: a first transistor located in a first device type region of the substrate, wherein the first transistor comprises a first gate structure and a first source / drain feature adjacent to the first gate structure; and a second transistor located in a second device type region of the substrate, wherein the second transistor includes a second gate structure and a second source / drain feature adjacent to the second gate structure; wherein the first transistor includes a first fin having a first number of semiconductor channel layers disposed over a first shallow trench isolation (STI) region and in lateral contact with the first source / drain feature, wherein the second transistor includes a second fin having a second number of semiconductor channel layers disposed over a second shallow trench isolation region and in lateral contact with the second source / drain feature, and wherein the first number of semiconductor channel layers is different from the second number of semiconductor channel layers, The semiconductor device further includes: a first double-layer dielectric disposed above the first shallow trench isolation region and on an opposite side of the first gate structure; Wherein, a top surface of the first source / drain component exceeds a top surface of a top layer of the first double-layer dielectric.

18. The semiconductor device according to claim 17, wherein: At least one semiconductor channel layer of the first fin is embedded in the first shallow trench isolation region.

19. The semiconductor device according to claim 17, further comprising: A second double-layer dielectric is disposed above the second shallow trench isolation region and on an opposite side of the second gate structure.

20. The semiconductor device according to claim 17, wherein A first top surface of the first shallow trench isolation region is offset from a second top surface of the second shallow trench isolation region by an amount equal to a thickness of at least one pair of Si / SiGe epitaxial layers of the first fin embedded in the first shallow trench isolation region.

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