Semiconductor device and method for forming the same

Abstract

The semiconductor device includes a fin structure. A source / drain region is formed on the fin structure. A first gate structure is disposed above the fin structure. A source / drain contact is disposed above the source / drain region. The source / drain contact has a protruding section that at least partially protrudes above the first gate structure. The source / drain contact electrically couples the source / drain region and the first gate structure together. The present invention also provides a method for forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] In deep submicron integrated circuit technology, embedded static random access memory (SRAM) devices have become popular storage cells for high-speed communications, image processing, and system-on-chip (SOC) products. The amount of embedded SRAM in microprocessors and SOCs continues to increase to meet the performance requirements of each new technology generation. As silicon technology continues to scale from one generation to the next, parasitic effects may increasingly affect the performance of SRAM devices. For example, as semiconductor component sizes continue to shrink, parasitic resistance may become a larger factor, which may reduce the minimum operating voltage (Vmin) of the SRAM cell. This may result in subpar SRAM performance or even device failure.

[0003] Thus, while existing SRAM devices have generally been adequate for their intended purposes, they have not been completely satisfactory in every respect. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a fin structure; a source / drain region formed on the fin structure; a first gate structure disposed above the fin structure; and a source / drain contact disposed above the source / drain region, wherein the source / drain contact has a protruding segment that protrudes at least partially above the first gate structure, and wherein the source / drain contact electrically couples the source / drain region and the first gate structure together.

[0005] Other embodiments of the present application provide a semiconductor device, including: a fin structure comprising a semiconductor material; a source / drain formed on the fin structure; a gate formed above the fin structure; and a source / drain contact physically connected to the source / drain and the gate, wherein the source / drain contact has an asymmetric profile.

[0006] Still other embodiments of the present invention provide a method for forming a semiconductor device, comprising: providing a semiconductor device, comprising: a fin structure, a source / drain region formed on the fin structure, a gate structure at least partially wrapping the fin structure, and a dielectric material formed above the source / drain region and above the gate structure; performing an etching process on the semiconductor device, wherein the etching process forms an opening extending through the dielectric material and at least partially exposing the source / drain region and the gate structure; and filling the opening with a conductive material to electrically couple the gate structure and the source / drain region together. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present invention and therefore should not be viewed as limiting the scope of the present invention, as the present invention may be equally well applied to other embodiments.

[0008] Figure 1 A circuit schematic diagram for a 1-bit SRAM cell according to an embodiment of the present invention is shown.

[0009] Figure 2 A three-dimensional perspective view of a FinFET device according to an embodiment of the present invention is shown.

[0010] Figure 3 A top view layout of a portion of an SRAM cell array according to an embodiment of the present invention is shown.

[0011] Figure 3A A top view layout of a portion of an SRAM cell array according to another embodiment of the present invention is shown.

[0012] Figures 4 to 13 A series of cross-sectional side views of a portion of an SRAM cell array at various stages of fabrication are shown in accordance with an embodiment of the present invention.

[0013] Fig.14 An integrated circuit manufacturing system according to an embodiment of the present invention is shown.

[0014] Fig.15 The flowchart of manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] Furthermore, when "about", "approximately", etc. are used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range including the value, such as within + / -10% of the value or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0018] The present invention is directed to, but not limited to, static random access memory (SRAM) devices. SRAM devices are semiconductor memory devices that use bistable latch circuits (eg, flip-flops) to store binary bits of information. Figure 1 An exemplary circuit schematic diagram of a single-port SRAM cell (e.g., a 1-bit SRAM cell) 5 is shown. The single-port SRAM cell 5 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass-gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, such as the p-type FinFETs discussed above, while transistors PG1, PG2, PD1, and PD2 are n-type FinFETs discussed above. Since the SRAM cell 5 includes six transistors in the illustrated embodiment, it may also be referred to as a 6T SRAM cell.

[0019] The drains of the pull-up transistor PU1 and the pull-down transistor PD1 are coupled together, and the drains of the pull-up transistor PU2 and the pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to a power supply voltage Vcc (also referred to as Vdd), and the sources of the pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be electrically grounded.

[0020] The first storage node SN1 of the first data latch is coupled to the bit line BL through the pass gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through the pass gate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes, which are usually at opposite logic levels (logic high or logic low). The gates of the pass gate transistors PG1 and PG2 are coupled to the word line WL.

[0021] SRAM devices such as SRAM cell 5 can be implemented using "planar" transistor devices and / or FinFET devices. In this regard, FinFET devices are fin field effect transistor devices that have become increasingly popular in the semiconductor industry recently. FinFET devices have several advantages over conventional metal oxide semiconductor field effect transistor (MOSFET) devices (e.g., "planar" transistor devices). These advantages may include better chip area efficiency, higher carrier mobility, and a manufacturing process that is compatible with the manufacturing process of planar devices. Therefore, it may be desirable to design an integrated circuit (IC) chip that uses FinFET devices for part or all of the IC chip.

[0022] FinFET devices may be complementary metal oxide semiconductor (CMOS) devices, including P-type metal oxide semiconductor (PMOS) FinFET devices and N-type metal oxide semiconductor (NMOS) FinFET devices. It should be understood that FinFET devices may be used as examples to discuss some aspects of the following disclosure, but it should be understood that, except for those specifically claimed, the present application is not limited to FinFET devices.

[0023] refer to Figure 2 , a perspective view of an exemplary FinFET device 10 is shown. The FinFET device structure 10 includes an N-type FinFET device structure (NMOS) 15 and a P-type FinFET device structure (PMOS) 25. The FinFET device structure 10 includes a substrate 102. The substrate 102 may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 may include other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 may include an epitaxial layer located above the bulk semiconductor.

[0024] The FinFET device structure 10 also includes one or more fin structures 104 (e.g., Si fins) extending from the substrate 102 in the Z direction and surrounded by spacers 105 in the Y direction. The fin structure 104 extends in the X direction and may optionally include germanium (Ge). The fin structure 104 can be formed by using appropriate processes such as photolithography and etching processes. In some embodiments, the fin structure 104 is etched from the substrate 102 using a dry etch or plasma process. In some other embodiments, the fin structure 104 can be formed by multiple patterning lithography processes, such as a double patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing a pattern into two staggered patterns. DPL allows for increased density of components (e.g., fins). The fin structure 104 also includes an epitaxially grown material 12, which can be used (together with a portion of the fin structure 104) as a source / drain of the FinFET device structure 10.

[0025] An isolation structure 108, such as a shallow trench isolation (STI) structure, is formed to surround the fin structure 104. In some embodiments, a lower portion of the fin structure 104 is surrounded by the isolation structure 108, and an upper portion of the fin structure 104 protrudes from the isolation structure 108, such as Figure 2 In other words, part of the fin structure 104 is embedded in the isolation structure 108. The isolation structure 108 prevents electrical interference or crosstalk.

[0026] The FinFET device structure 10 also includes a gate stack structure, including a gate electrode 110 and a gate dielectric layer (not shown) located below the gate electrode 110. The gate electrode 110 may include polysilicon or metal. The metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt) or other applicable materials. The gate electrode 110 may be formed in a gate-last process (or a gate replacement process). Hard mask layers 112 and 114 may be used to define the gate electrode 110. A dielectric layer 115 may also be formed on the sidewalls of the gate electrode 110 and above the hard mask layers 112 and 114. In at least one embodiment, the dielectric layer 115 is directly in contact with the gate electrode 110.

[0027] The gate dielectric layer (not shown here) Figure 2 The dielectric material may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or the like, or a combination thereof.

[0028] In some embodiments, the gate stack structure includes additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer, or other applicable layers. In some embodiments, the gate stack structure is formed over a central portion of the fin structure 104. In some other embodiments, multiple gate stack structures are formed over the fin structure 104. In some other embodiments, the gate stack structure includes a dummy gate stack and is later replaced by a metal gate (MG) after a high thermal budget process is performed.

[0029] The gate stack structure is formed by a deposition process, a photolithography process and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods and / or combinations thereof. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Optionally, the photolithography process can be implemented or replaced by other suitable methods, such as maskless lithography, electron beam writing and ion beam writing.

[0030] Figure 3 A top view of a portion of an SRAM cell array 200 implemented using FinFETs according to an embodiment of the present invention is shown. Figure 3 The top view is defined by the X-axis (spanning only Figure 2 X-axis) and Y-axis (spanning only Figure 2 Y direction) limited. Notice, Figure 3 The X axis in is the vertical axis, and Figure 3 The Y axis in is the horizontal axis. Also note that Figure 3 The top view shown may correspond to an idealized top view of the SRAM cell array 200. For example, Figure 3 The various components shown may have straight sides or be shaped as rectangles or polygons. In actual manufactured devices, Figure 3 The components in may have more rounded, curved or other non-straight edges. In some embodiments, Figure 3 The top view of may correspond to the top view of the pattern on one or more photomasks used to form the SRAM cell array 200, because the pattern on the photolithography mask does have more straight edges than the pattern on the device actually manufactured, and is more similar to a rectangle or a polygon. In other embodiments, Figure 3 The top view of FIG. 2 may represent a top view of a portion of an actually fabricated SRAM cell array 200 , with the understanding that the edges and contours of an actually fabricated SRAM cell array 200 are not completely linear or straight.

[0031] The SRAM cell array 200 includes a plurality of SRAM cells, such as Figure 1 The SRAM cell array 200 may be implemented at least in part using a plurality of fin structures, such as fin structures 210 to 215, each of which may be Figure 2 1. The fin structures 210 to 215 each extend in the X direction in an extended manner. The fin structures 210 to 215 may also be referred to as active regions. The source / drain regions and / or channel regions of the transistors may be formed on the fin structures 210 to 215 or as part of the fin structures 210 to 215.

[0032] The SRAM cell array 200 also includes a plurality of gate structures, such as gate structures 220 to 223, each of which may be implemented as Figure 2 20 to 223 may each include a high-k gate dielectric and a metal gate electrode. In other words, each of the gate structures 220 may be an HKMG structure. Each of the gate structures 220 to 223 may wrap around one or more fin structures 210 to 215, but in Figure 3 In the top view of FIG. 8 , the gate structures 220 to 223 are shown extending in the Y direction perpendicular to the X direction, and the fin structures 210 to 215 each extend in the X direction.

[0033] Fin structures 210 to 215 and gate structures 220 to 223 may form transistors. For example, in an embodiment, the pull-up (PU) transistor of the SRAM cell 5 is formed by transistors in the N-doped region, while the pull-down (PD) transistor and the pass gate (PG) transistor are formed by transistors in the P-doped region.

[0034] It should be understood that some of the gate structures 220 to 223 may be separated from each other by isolation structures, also referred to as cut metal gate (CMG) structures. For example, gate structure 220 and gate structure 221 may have been initially formed as a single continuous gate structure and then "broken up" or "separated" by the CMG structure. The same may be true for gate structures 222 to 223. In other words, a CMG structure may be disposed between gate structures 220 to 221 in the Y direction, and another CMG structure may be disposed between gate structures 222 to 223 in the Y direction. However, for simplicity reasons, in Figure 3 The CMG structure is not specifically shown in FIG.

[0035] The SRAM cell array 200 includes a plurality of source / drain contacts, such as source / drain contacts 240 to 247. The source / drain contacts 240 to 247 are formed on the source / drain regions of the transistor and provide electrical connections to the source / drain regions of the transistor. The source / drain contacts 240 to 247 extend primarily in the Y direction. However, a subset of the source / drain contacts 240 to 247 may also have a protruding segment that protrudes in the X direction. For example, most of the source / drain contact 243 (e.g., greater than 50%) extends in the Y direction, but it also has a protruding segment 243A that protrudes in the X direction, so that the source / drain contact 243 has a top view profile similar to the character "L". Similarly, most of the source / drain contacts 244 extend in the Y direction, but it also has a protruding segment 244A that protrudes in the -X direction. The protruding segment 243A at least partially overlaps the gate structure 221 in the top view, and the protruding segment 244A at least partially overlaps the gate structure 222 in the top view. As will be more easily seen from the cross-sectional view of the SRAM cell array 200 discussed below, the protruding segment 243A is electrically connected to the gate structure 221, and the protruding segment 244A is electrically connected to the gate structure 222.

[0036] The implementation of source / drain contacts with protruding segments (such as protruding segments 243A and 244A) is a unique aspect of the present invention. In conventional SRAM cell arrays, source / drain contacts extend only in a single direction (e.g., only in the Y direction) without protruding segments. These source / drain contacts are not used to provide electrical connection to the gate structure. Moreover, the gate structure and source / drain contacts in conventional SRAM cell arrays can be electrically connected together using butt contacts formed on the source / drain contacts and the gate structure. In other words, a portion of such butt contacts can be electrically connected to the source / drain contacts, and another portion of such butt contacts can be electrically connected to the gate structure.

[0037] Unfortunately, the presence of these butt contacts can limit the lateral position or size of metal lines formed over them. Figure 4 To explain this more clearly, Figure 4 is a schematic partial cross-sectional side view of a portion of an SRAM cell array, wherein the cross-sectional view is taken along Figure 3 The top view is taken along the cutting line A-A'. Figure 4 The cross-sectional view corresponds to a plane defined by the Y direction (horizontal direction) and the Z direction (vertical direction).

[0038] like Figure 4As shown, source / drain contacts 243 and 244 are disposed in or surrounded by an interlayer dielectric (ILD) 260 (also referred to as an ILD0 layer). ILD 260 surrounds conductive components such as source / drain contacts 243 to 244 and provides electrical isolation for the conductive components. In some embodiments, the ILD may include a low-k dielectric material (e.g., a dielectric material having a dielectric constant less than that of silicon dioxide (about 4)). As non-limiting examples, the low-k dielectric material may include a porous organosilicate film such as SiOCH, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), spin-on organic polymer dielectrics, spin-on silicon-based polymer dielectrics, or combinations thereof.

[0039] An etch stop layer 270 is formed over the ILD 260. The etch stop layer 270 and the ILD 260 may have different material compositions. Another ILD 280 (also referred to as an ILD1 layer) is disposed over the etch stop layer 270. The ILD 280 may have a substantially similar material composition as the ILD 260. In a conventional SRAM cell array, a butting contact (electrically interconnecting a source / drain contact and a gate structure) may be embedded in the ILD 280. However, in Figure 4 As can be seen in FIG. 2 , the SRAM cell array 200 lacks such a butting contact in the ILD 280. Moreover, the protruding source / drain contacts 243 to 244 provide the function of the butting contact.

[0040] A multi-layer interconnect (MLI) structure is formed over the ILD 280. The MLI structure can be formed over the substrate and can include multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., leads) between various microelectronic components of a semiconductor device (e.g., the SRAM cell array 200). For example, the MLI structure can include multiple conductive components, such as contacts, vias, or metal lines. The metal lines can be arranged in multiple metal layers stacked vertically above each other, and the vias are used to electrically interconnect metal lines from different layers together. The metal lines and vias can provide electrical connections to transistor components such as gates, sources, and / or drains. The conductive components can include conductive materials such as aluminum, aluminum / silicon / copper alloys, titanium, titanium nitride, tungsten, polysilicon, metal silicides, or combinations thereof. Alternatively, the conductive components can include copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, or combinations thereof. For simplicity, over Figure 4The metal layer 300 (also referred to as the M0 layer) of the MLI structure is shown in FIG. Figure 4 Other metal layers above the metal layer 300 are omitted.

[0041] As an example, the metal layer 300 includes a plurality of metal lines 310 to 314. Each of the metal lines 310 to 314 is connected in an extended manner. Figures 2 to 3 In other words, each of the metal lines 310 to 314 extends in a direction perpendicular to the YZ plane. Some of the metal lines 310 to 314 may be used as signal lines of the SRAM cell array 200. For example, the metal lines 311 and 313 may be used as bit lines (BL) or bar bit lines (BLB) of the SRAM cell array 200 (see Figure 1 ). Each of the metal lines 311 and 313 can extend continuously through multiple SRAM cells. As electrical conductors, ideally, the metal lines 311 and 313 should have substantially zero resistance. However, in real-world devices, each of the metal lines 311 and 313 may generate a parasitic resistance that is a function of its size (e.g., length in the X direction and width in the Y direction). For example, as the width of the metal line 311 or 313 (e.g., the lateral dimension measured in the Y direction) decreases, the parasitic resistance may increase. In older technology generations greater than the 5 nanometer technology generation, this parasitic resistance can be ignored to some extent because the size of the metal lines may be large enough.

[0042] However, as the device scaling trend continues to reduce the size of microelectronic components (e.g., including the size of metal lines 311 and 313), the parasitic resistance of metal lines 311 or 313 may rise to a level that is no longer negligible, but will greatly reduce the performance of the semiconductor device. For example, according to Ohm's law, the voltage drop across a resistor is equal to the current flowing through the resistor multiplied by the resistance of the resistor. This relationship between voltage and resistance can be expressed by a mathematical formula V=I*R, where V represents voltage, I represents current, and R represents resistance.

[0043] In the present case, each of the metal lines 311 and 313 can be modeled as a resistor (due to its parasitic resistance). Therefore, during the operation of the SRAM cell array 200, each of the metal lines 311 and 313 may experience a voltage drop over its length (in the X direction). The voltage drop may reduce certain SRAM operating parameters or standards, such as the minimum operating voltage (hereinafter referred to as Vmin). In some cases, the drop in Vmin may be in the range of from about 5 millivolts (mV) to about 200mV. If Vmin is not met, the SRAM cell may encounter a read failure, a write failure, an access failure, and / or a retention failure. In order to exacerbate this problem, the device scaling down process may also need to scale down the SRAM power supply voltage (e.g., Vdd). Since Vmin may be related to the power supply voltage, the scaling down of the power supply voltage may also reduce the error margin (or degradation amount) that Vmin may experience.

[0044] In order to reduce parasitic resistance, it may be desirable to expand the lateral dimensions of metal lines 311 and 313 in the Y direction. However, in conventional SRAM cell arrays, the presence of butt contacts in ILD 280 may have prevented lateral expansion of metal lines 311 or 313. For example, if the butt contact is located in the portion of ILD 280 between metal lines 312 and 313, the lateral expansion of metal line 313 may cause an electrical short between metal line 313 and the butt contact, which may cause device failure or failure. Therefore, conventional SRAM cell arrays may have design rules that specify a minimum distance between the distance (in the Y direction) between butt contacts and metal lines 311 and / or 313. These design rules constrain or limit the lateral expansion of metal lines 311 and / or 313. This effectively limits how much metal lines 311 and / or 313 can be expanded laterally, which means that conventional SRAM manufacturing has a limit on how much the resistance of metal lines 311 and / or 313 can be reduced because the resistance is inversely proportional to the size of the metal line (e.g., the larger the width of metal line 311 or 313, the lower the resistance, and vice versa).

[0045] In contrast to conventional SRAM cell arrays, the SRAM cell array 200 of the present invention does not have butting contacts in the ILD 280, which frees up a lot of space for metal lines 311 and / or 313 to expand laterally in the Y direction. Figure 4In the illustrated embodiment, metal line 313 can expand in the Y direction toward metal line 312, and this lateral expansion is limited by the design rule that specifies the spacing between metal lines 313 and 312, rather than the spacing between metal line 313 and the butt contact (which is located closer to metal line 313 than metal line 312). Therefore, the present invention allows for a more flexible resistance reduction of metal lines (such as metal lines 311 or 313) compared to conventional SRAM devices. Furthermore, it is possible to replace the butt contact in the ILD 280 in a conventional SRAM cell array with the uniquely shaped source / drain contacts 243 / 244 (with protruding portions) of the present invention.

[0046] Return to reference Figure 3 , the protruding segments 243A and 244A each have a dimension 340 measured in the X direction. The dimension 340 refers to how far each protruding segment 243A and 244A protrudes. For example, the main portion of the source / drain contact 243 has a boundary 345 extending in the Y direction, while in the top view, the protruding segment 243A has a boundary 346 extending in the Y direction and overlapping the gate structure 221. The dimension 340 is measured from the boundary 345 to the boundary 346.

[0047] Each of the protruding segments 243A and 244A also has a dimension 350 measured in the Y direction. Dimension 350 refers to the width of each of the protruding segments 243A and 244A. For example, each of the protruding segments 244A has a boundary 355 and a boundary 356 extending in the X direction. Dimension 350 is measured from boundary 355 to boundary 356. The values ​​of dimensions 340 and 350 are specifically configured so that the protruding segments 243A and 244A (of the source / drain contacts 243 and 244) have a sufficient amount of contact area with the intended gate structure so that they can effectively replace the docking contacts, but at the same time, they are not too large to cause manufacturing difficulties, process defects, or the risk of electrical short circuits with other undesirable components of the SRAM cell array 200.

[0048] According to various aspects of the present invention, in order to optimize the performance of the SRAM cell array 200, the dimensions 340 and 350 are specifically configured to be within a specific range. The range of the dimensions 340 and 350 can be limited relative to the size or size of other components of the SRAM cell array 200. For example, each of the gate structures 220 to 223 has a dimension 360 measured in the X direction, and each of the gate structures 220 to 223 can be separated or spaced apart from the nearest source / drain contact 243 / 244 in the X direction by a distance 370. In some embodiments, the dimension 340 is greater than the sum of the distance 370 and 1 / 2 of the dimension 360. This can be expressed by a mathematical formula: dimension 340>=distance 370+1 / 2*(dimension 360). At the same time, the dimension 340 is less than the sum of the distance 370 and the dimension 360. This can be expressed by a mathematical formula: dimension 340<=distance 370+dimension 360. Among other things, this range of dimension 340 helps ensure that protruding segment 243A can make sufficient physical contact with gate structure 221 (because it protrudes at least halfway into gate structure 221), but it does not protrude too far to avoid electrically shorting (also known as bridging) with source / drain contact 241.

[0049] Still refer to Figure 3 , each of the fin structures 210 to 215 has a dimension 380 measured in the Y direction. The fin structure 213 is separated from the adjacent fin structure 212 by a distance 385 (also referred to as a fin-to-fin spacing). The fin structure 213 is also separated from the end of the gate structure 222 (or from the CMG structure that separates the gate structures 222 to 223) by a distance 390. Or stated another way, the gate structure 222 protrudes beyond the fin structure 213 in the Y direction by a distance 390. In some embodiments, the dimension 350 is greater than the sum of the distance 390 and the dimension 380. This can be mathematically represented by: dimension 350>=distance 390+dimension 380. At the same time, the dimension 350 is less than the sum of the distance 390, the dimension 380, and 1 / 2 of the distance 385. This can be mathematically represented by: dimension 350<=distance 390+dimension 380+1 / 2*(distance 385). Among other things, this range of dimensions 350 helps ensure that protruding segment 244A can make sufficient physical contact with desired portions of gate structure 222 and fin structure 213 , but does not protrude so far as to electrically short with source / drain contact 243 or fin structure 212 .

[0050] Figure 3A Another embodiment of an SRAM cell array 200 is shown. Figure 3A The embodiment shown is Figure 3 The embodiments shown are substantially similar. Therefore, for reasons of consistency and clarity, the same components are labeled the same in both embodiments. One difference between the embodiments is that Figure 3Compared with the embodiment shown in Figure 3A In the illustrated embodiment, the protruding segments 243A and 244A may further protrude outward in the Y direction. For example, the boundary 355 of the protruding segment 244A may be further pushed out in the -Y direction, however, the rest of the source / drain contact 244 may still retain the boundary 355A (i.e., the boundary 355A is not aligned with the source / drain contact 244). Figure 3 355 in the embodiment of FIG. 1 ). Note that although Figure 3A The dimension 350 of the embodiment is greater than that in Figure 3 In the embodiment of the size 350, the size 350 can still have the same Figure 3 The same range as the illustrated embodiment, for example, is greater than the sum of distance 390 and dimension 380, but less than the sum of distance 390, dimension 380, and 1 / 2 of distance 385.

[0051] Figures 5 and 6 2 is a schematic partial cross-sectional side view of a portion of the SRAM cell array 200 to further illustrate the structural details of the uniquely shaped source / drain contacts 243 to 244 of the present invention. Specifically, Figure 5 corresponds to a cross section taken at cutting line BB' (which includes the protruding section 243A), and Figure 6 corresponds to a cross section taken at the cutting line CC' (which is the portion of the source / drain contact 243 outside the protruding section 243A). In other words, Figures 5 and 6 The cross-sectional view in is obtained by taking a section along an XZ plane defined by an X direction (horizontal) and a Z direction (vertical).

[0052] like Figures 5 and 6 As shown, the source / drain region 400 is formed on the fin structure 211 to 212 or as part of the fin structure 211 to 212. For example, the source / drain region 400 can be epitaxially grown on the fin structure 211 to 212. The fin structure 211 to 212 can be adjacent to the isolation structure 230, such as shallow trench isolation (STI). In other words, each of the fin structures 211 to 212 can be laterally partially surrounded by the isolation structure 230. The gate structure 221 to 222 is formed above the fin structure 211 to 212 and partially wraps the fin structure 211 to 212 (for example, as shown above with reference to Figure 2 In the illustrated embodiment, a portion of the gate structure 221 is also partially located above the isolation structure 230. In other words, a portion of the gate structure 221 is located above the fin structure 212, while another portion of the gate structure 221 is located above the isolation structure 230. However, it should be understood that this is merely a non-limiting example, and in other embodiments, the gate structure 221 (or gate structure 222) need not be partially formed above the isolation structure 230.

[0053] The source / drain contact 243 (including the protruding segment 243A) is formed on the source / drain region 400 to provide an electrical connection to the source / drain region 400. The source / drain contact 243 (and the protruding segment 243A) is formed between two of the adjacent gate structures 221 to 222 (or between the gate structures 220 and 222). As described above, the gate structures 220 to 222 can be HKMG structures. For example, the gate structures 220 to 222 can include a gate dielectric layer 410 including a high-k dielectric material (e.g., a material with a dielectric constant greater than about 4). It should be understood that the gate dielectric layer 410 can also include an interfacial layer (IL) (or formed above the interfacial layer), which can include silicon oxide as a non-limiting example. For simplicity, the IL is not shown separately here.

[0054] Each of the gate structures 220 to 222 may also include a metal gate electrode. The metal gate electrode includes one or more work function metal layers 420 and a filling metal component 430. The work function metal layer 420 is configured to adjust the work function of the corresponding transistor device to achieve a desired threshold voltage Vt. In some embodiments, the work function metal layer 420 includes: TiAl, TiAlN, TaCN, TiN, WN or W or a combination thereof. The filling metal component 430 of the metal gate electrode serves as the main conductive portion of the metal gate electrode. The filling metal component 430 may include tungsten, aluminum, copper or a combination thereof. The filling metal component 430 may serve as the main conductive portion of the metal gate electrode.

[0055] In some embodiments, the gate structures 221 to 222 are formed by a gate replacement process in which the dummy gate is removed and replaced by the gate dielectric layer 410, the work function metal layer 420, and the filling metal component 430. Therefore, the gate dielectric layer 410 and the work function metal layer 420 may each have a U-shape in a cross-sectional view because they may be formed by partially filling the opening by removing the dummy gate structure.

[0056] The gate structures 221-222 are surrounded by one or more dielectric materials 450. Some dielectric materials 450 may include gate spacers formed on the sidewalls of the gate structures 221-222. Portions of the dielectric material 450 may also be disposed over the gate structures 221-222 to protect and / or electrically insulate the gate structures 221-222. In some embodiments, the dielectric material 450 includes silicon nitride (SiN). The dielectric material 450 may also be laterally surrounded by the ILD 260. The ILD 280 is disposed over the dielectric material 450.

[0057] As described above, a unique physical characteristic of the SRAM cell array 200 of the present invention is the shape or profile of the source / drain contacts 243 having the protruding segments 243A. Figure 5As shown, the protruding segment 243A protrudes in the X direction and has a portion that is in physical contact with the upper surface of the gate structure 221, for example, at least partially in physical contact with the upper surface of the work function metal layer 420 and / or the upper surface of the fill metal component 430. Therefore, the protruding segment 243A (and therefore the source / drain contact 243) is electrically connected to the gate structure 221. The protruding segment 243A has an asymmetric cross-sectional profile because its "right" portion protrudes outward in the X direction, but its "left" portion does not. At the same time, the remaining source / drain contacts 243 (such as Figure 6 221 or 222. As shown in FIG. 222, the source / drain contacts 243 are substantially symmetrical and have no substantially outwardly protruding portion in the X direction. Therefore, the remaining source / drain contacts 243 are not in physical contact with the gate structures 220, 221 or 222.

[0058] Since the protruding segment 243A of the source / drain contact 243 is now used to provide an electrical connection to the gate structure 221, this eliminates the need to form a butt contact separately in the ILD 280 to electrically couple the source / drain contact 243 and the gate structure 221 together. Advantageously, replacing the butt contact with a unique source / drain contact 243 in this article allows the metal line formed above it to be laterally expanded in the X direction, which reduces the resistance of the metal line. As described above, the reduction in resistance can, for example, improve the performance of the SRAM device relative to Vmin. In addition, since it is no longer necessary to form a butt contact, the manufacturing of the SRAM cell array 200 here is easier because it has one less process step. The simplification of the manufacturing process can also lead to fewer defects and reduced costs. In addition, the larger footprint of the source / drain contact 243 (due to the protruding segment 243A) improves its "landing window" in manufacturing.

[0059] Figures 7 to 14 2 is a series of cross-sectional views (in the XZ plane) showing the manufacturing steps for forming source / drain contacts 243 to 244 having protruding segments 243A to 244A according to an embodiment of the present invention. Figure 3 The cutting line BB' is taken.

[0060] Reference now Figure 7 , the SRAM cell array 200 has formed source / drain regions 400 and gate structures 221 to 222 . The dielectric material 450 and the ILD 260 surround the gate structures 221 to 222 , and the ILD 280 is formed over the dielectric material 450 .

[0061] Reference now Figure 8, an etching process 500 such as a dry etching process is performed on the SRAM cell array 200. For example, a patterned hard mask layer 510 may be formed over the ILD 280. The patterned hard mask layer 510 may be defined by a photolithography process including one or more photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, and drying (e.g., hard baking) processes (not necessarily performed in this order). It should be understood that the patterned hard mask layer 510 is used to define the position, size, and / or shape of the opening 520 (and therefore the position, size, and / or shape of the source / drain contacts to be formed in the opening 520).

[0062] The etching process 500 forms an opening 520 that extends vertically through the ILD 280, the dielectric material 450, the ILD 260, and partially into the source / drain region 400. The patterned hard mask layer 510 protects portions of the layers below it during the etching process 500. The opening 520 exposes a portion of the gate structure 221. The etching process 500 is configured to have an etching selectivity between the material of the gate structure and the ILDs 260 and 280 and the dielectric material 450, so that the ILDs 260 and 280 and the dielectric material 450 can be removed without substantially affecting the gate structure 221 (e.g., the etching rate of the ILDs 260 and 280 and the dielectric material 450 is much faster than that of the gate structure 221). In addition, during the etching process 500, the ILDs 260 and 280 can be etched substantially faster than the dielectric material 450. Due to these different etch rates, the portion of the upper surface 530 of the gate structure 221 is substantially flatter than the upper surface 531 of the dielectric material 450 exposed by the opening 520 . In other words, the upper surface 531 is more inclined than the upper surface 530 .

[0063] Reference now Fig. 9 , a deposition process 550 is performed to form a protective layer 570 in the opening 520. The deposition process 550 may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD or other suitable deposition techniques. In some embodiments, the protective layer 570 may include a polymer material. Note that the protective layer 570 does not have to completely fill the opening 520, but the upper surface 580 of the protective layer 570 is located above the upper surface 530 of the gate structure 221 (or higher than the upper surface 530 of the gate structure 221). This allows the protective layer 570 to protect the gate structure 221 in one or more processes to be performed subsequently. Conventional methods for manufacturing SRAM devices do not include the formation of the protective layer 570.

[0064] Reference now Fig.10, a wet cleaning process 600 is performed on the SRAM cell array 200 to remove the patterned hard mask layer 510. In some embodiments, the wet cleaning process 600 may include applying a halogen-containing fluid to remove the patterned hard mask layer 510. In some embodiments, the halogen-containing fluid may include HF, F2, HCl, Cl2, HBr, or a combination thereof.

[0065] The protection layer 570 can protect the gate structure 221 during the wet cleaning process 600. For example, if the protection layer 570 has not been formed, the wet cleaning process 600 can at least partially remove the gate dielectric layer 410 (and / or a possible metal gate electrode layer). By forming the protection layer 570 before the wet cleaning process 600, the present invention protects gate structures such as the gate structure 221 from being damaged.

[0066] Reference now Fig.11 , a protective layer removal process 620 is performed on the SRAM cell array 200 to remove the protective layer 570. In some embodiments, the protective layer removal process 620 uses a dry etching process to remove the protective layer 570. The dry etching process includes forming a plasma using an oxygen-containing gas, a hydrogen-containing gas, and / or a hydrogen-containing gas. The protective layer 570 is removed because it has achieved its purpose (e.g., protecting the gate structure 221 during the wet cleaning process 600) and is no longer used in subsequent processes. In addition, removing the protective layer 570 will release the space in the opening 520 so that it can be filled with a conductive material layer to form a source / drain contact.

[0067] Reference now Fig.12 , a liner forming process 640 is performed to form a liner 650 in the opening 520. The liner forming process 640 may include a deposition process to deposit a liner material on the surface of each layer exposed by the opening 520. Note that for simplicity, in the above discussion Figure 5 The liner 650 is not specifically shown in the figure. In some embodiments, the liner material may include a dielectric material, such as silicon nitride. The liner formation process 640 may also include an etching process to etch away a portion of the liner 650 disposed above the gate structure 221 and above the source / drain region 400. This allows the upper surface 530 of the gate electrode (e.g., the work function metal layer 420 and the fill metal component 430) and the upper surface 655 of the source / drain region 400 to remain exposed so that the source / drain contacts of the subsequently formed fill opening 520 can be in physical and electrical contact with the gate electrode and the source / drain region 400. Note that in some embodiments, the patterned hard mask layer 510 may also be removed before or after the liner formation process 640.

[0068] Reference now Fig.13 , a contact forming process 670 is performed to form source / drain contacts 243 in the opening 520. Fig.13 The protruding segment 243A of the source / drain contact 243 is shown in the cross-sectional view of FIG. The contact formation process 670 may include one or more deposition processes to deposit a conductive material, such as cobalt, copper, aluminum, tungsten, or a combination thereof, in the opening 520. The deposited conductive material completely fills the opening 520 and may even be deposited on the top surface of the ILD 280. The contact formation process 670 may also include a planarization process (e.g., a CMP process) to remove portions of the conductive material outside the opening 520 and planarize the deposited conductive material and the upper surface of the ILD 280. The remaining portion of the conductive material in the opening 520 forms the source / drain contact 243.

[0069] In addition to having a unique top view profile, the source / drain contact 243 also has a unique cross-sectional profile. Fig.13 is asymmetric in the cross-sectional view because the protruding segment 243A protrudes in the X direction. Due to the unique manufacturing process flow used to form the source / drain contact 243, the source / drain contact 243 has multiple inclined sidewalls 680, 681 and 682 (also referred to as side walls). At least some of the inclined sidewalls 680 to 682 are inclined at different angles relative to each other. For example, sidewall 680 and sidewall 681 can be inclined at different angles, and sidewall 681 and sidewall 682 can also be inclined at different angles. Sidewall 681 and sidewall 682 are joined together by a surface 685 of the source / drain contact 243, which surface 685 is substantially flatter than the sidewalls 680 to 682. Surface 685 is inclined due to etching (see Figure 8 The etching process 500 is used for the opening 520 of the source / drain contact 243 to improve the etching selectivity between the gate structure 221 and the ILD 260 and the dielectric material 450 and make it more planar.

[0070] Note also that the sloped sidewalls 680-682 are in physical contact with the liner 650, but the surface 685 is not. Without the liner 650, the sidewall 680 would have been in physical contact with the ILD 260, the sidewall 681 would have been in physical contact with the dielectric material 450 (e.g., the gate spacer), and the sidewall 682 would have been in physical contact with both the dielectric material 450 and the ILD 280.

[0071] Since the source / drain contact 243 has a lateral protruding profile and partially protrudes above the gate structure 221, the source / drain contact 243 electrically interconnects the source / drain region 400 and the gate structure 221. Therefore, the source / drain contact 243 effectively replaces the function of the butt contact that has been implemented in the conventional SRAM cell array. As described above, the removal of the butt contact allows the metal line formed above the ILD 280 to be expanded laterally. The lateral expansion of the metal line helps to reduce the parasitic resistance of the metal line because the resistance is inversely proportional to the width (or lateral dimension) of the metal line. Since SRAM devices are manufactured in smaller and smaller technology nodes (e.g., 5 nanometers or smaller nodes), the reduction in resistance is very helpful because the parasitic resistance is more obvious for these devices with smaller and smaller geometric dimensions. If not mitigated, the parasitic resistance of the metal line (e.g., used as a bit line of the SRAM) may reach a point where the voltage drop over the length of the metal line will cause a significant undesirable voltage degradation. This situation is further complicated by the fact that the metal line may extend continuously in the X direction across many cells of the SRAM cell array 200. Since the far cells at the far "ends" of the SRAM cell array are associated with the largest parasitic resistance, they will experience the largest unexpected (and undesirable) voltage drops because the longer the length of the metal line, the greater the parasitic resistance.

[0072] As a non-limiting example, the voltage drop over the length of the metal line may deteriorate the Vmin of the SRAM cell. Vmin may be the lowest voltage at which the SRAM cell can be read. However, the voltage drop due to the parasitic resistance over the length of the metal line may cause Vmin to be too high, which may cause the transistor of the SRAM cell to be unable to turn on (and therefore unable to read the SRAM). The present invention can achieve a reduction in the resistance of the metal line by giving the metal line a larger expansion space, because eliminating the butt contact means that the expansion of the metal line is not limited by the position of the butt contact. Therefore, the larger metal line produces a reduced parasitic resistance and improves the performance of the SRAM device.

[0073] Fig.14 An integrated circuit manufacturing system 700 is shown in accordance with an embodiment of the present invention. Manufacturing system 700 includes multiple entities 702, 704, 706, 708, 710, 712, 714, 716 ..., N connected by a communication network 718. Network 718 may be a single network, or may be a variety of different networks, such as an intranet and the Internet, and may include wired and wireless communication channels.

[0074] In an embodiment, entity 702 represents a service system for manufacturing collaboration; entity 704 represents a user, such as a product engineer who monitors a product of interest; entity 706 represents an engineer, such as a process engineer who controls a process and related recipes, or an equipment engineer to monitor or adjust conditions and settings of a process tool; entity 708 represents a metrology tool for IC testing and measurement; entity 710 represents a semiconductor process tool, such as an EUV tool for performing a lithography process to define irregularly shaped metal lines of an SRAM device; entity 712 represents a virtual metrology module associated with process tool 710; entity 714 represents an advanced process control module associated with process tool 710 and additional other process tools; and entity 716 represents a sampling module associated with process tool 710.

[0075] Each entity can interact with other entities and can provide and / or receive integrated circuit manufacturing, processing control and / or computing power to other entities. Each entity can also include one or more computer systems for implementing calculations and implementing automation. For example, the advanced processing control module of entity 714 can include a plurality of computer hardware with software instructions encoded therein. The computer hardware can include a hard drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0076] The integrated circuit manufacturing system 700 enables interaction between entities for integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In an embodiment, the advanced process control includes adjusting process conditions, settings and / or recipes of a processing tool applied to an associated wafer based on metrology results.

[0077] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of the subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0078] One capability provided by the IC manufacturing system 700 can enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced process control. Another capability provided by the IC manufacturing system 700 can integrate systems between facilities such as between metrology tools and process tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools and process tools can enable manufacturing information to be more effectively incorporated into manufacturing processes or APC modules, and can enable wafer data from in-line or field measurements using metrology tools integrated in related process tools.

[0079] Fig.15 8 is a flow chart showing a method 800 for manufacturing a semiconductor device. The method 800 includes a step 810 of providing a semiconductor device. The semiconductor device includes a fin structure, a source / drain region formed on the fin structure, a gate structure at least partially wrapping the fin structure, and a dielectric material formed over the source / drain region and over the gate structure.

[0080] The method 800 includes step 820 of performing an etching process on the semiconductor device. The etching process forms an opening extending through the dielectric material and at least partially exposing the source / drain region and the gate structure. In some embodiments, the etching process is configured to have an etching selectivity between the gate structure and the dielectric material, so that the dielectric material is etched at a much faster rate than the gate structure. In some embodiments, the opening is etched to have an "L" shape in a top view.

[0081] The method 800 includes step 830 to form a protective layer to partially fill the opening. In some embodiments, a polymer layer is formed as the protective layer. In some embodiments, the protective layer is formed such that an upper surface of the protective layer is disposed above an upper surface of the gate structure.

[0082] The method 800 includes step 840 of performing a wet cleaning process on the semiconductor device after the protection layer has been formed.

[0083] The method 800 includes step 850 to remove the protective layer after the wet cleaning process has been performed.

[0084] The method 800 includes a step 860 of filling the opening with a conductive material to electrically couple the gate structure and the source / drain regions together.

[0085] In some embodiments, the gate structure is a first gate structure, and the semiconductor device further includes a second gate structure. The first gate structure and the second gate structure are formed on opposite sides of the source / drain region. In some embodiments, the etching process is performed without exposing the second gate structure to the opening.

[0086] It should be understood that method 800 may include additional steps that may be performed before, during, or after step 810. For example, method 800 may include a step of forming a dielectric liner on the sides of the opening, which may be performed before filling the opening in step 860. A conductive material is formed on the dielectric liner. Other steps may include formation of interconnect layers, packaging, testing, etc. For simplicity, these additional steps are not discussed in detail herein.

[0087] In summary, the present invention replaces the butt-jointed contacts in conventional devices with source / drain contacts of unique shapes. For example, although conventional SRAM cell arrays may use butt-jointed contacts (which may be contacts formed in the ILD) to electrically interconnect the source / drain and the gate, the present invention omits the formation of such butt-jointed contacts. Instead, the present invention carefully configures the shape / profile of the source / drain contact so that it has a protruding segment that protrudes toward the gate and is in physical contact with the upper surface of the gate. Therefore, the source / drain contact of the present invention can be configured to have an "L"-shaped shape or profile in a top view and an asymmetric profile (due to the protruding segment) in a cross-sectional view.

[0088] Based on the above discussion, it can be seen that the present invention provides advantages over conventional methods. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages here, and no specific advantages are required for all embodiments. One advantage is improved device performance. For example, as device size continues to shrink, the parasitic resistance of the metal line may play an important role in causing undesirable voltage losses along the length of the metal line. This situation is exacerbated when the metal line is long, which may be the case when the metal line is used to carry SRAM signals such as bit lines or inverted bit lines. In order to minimize the parasitic resistance of the metal line by lateral expansion of the metal line (i.e., increasing its width). However, the presence of butt contacts in conventional devices effectively limits the expansion of the metal line because as the metal line expands, the risk of electrical bridging (e.g., short circuit) of the butt contacts may increase. The present invention eliminates this problem by not forming butt contacts, which provides more space for the metal line to expand laterally, and thus reduces the parasitic resistance of the metal line and optimizes device performance, such as relative to the minimum operating voltage. Another advantage is that due to its larger size, the landing window of the source / drain contact is better. Another advantage is its compatibility with existing manufacturing processes and lower implementation cost, since the formation of unique source / drain contacts can be achieved by configuring the source / drain contact mask pattern design.

[0089] The above advanced lithography processes, methods and materials can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between components, and the above disclosure is well suited for these spacings. In addition, spacers, also called mandrels, used to form fins of FinFETs can be processed according to the above disclosure.

[0090] One aspect of the present invention relates to a semiconductor device. The semiconductor device includes a fin structure. A source / drain region is formed on the fin structure. A first gate structure is disposed above the fin structure. A source / drain contact is disposed above the source / drain region. The source / drain contact has a protruding section that protrudes at least partially above the first gate structure. The source / drain contact electrically couples the source / drain region and the first gate structure together.

[0091] In some embodiments, the semiconductor device further comprises a second gate structure; wherein: the source / drain contact is disposed between the first gate structure and the second gate structure but is not in physical contact with the second gate structure; and the fin structure, the source / drain region, the first gate structure, the second gate structure, and the source / drain contact are components of a static random access memory (SRAM) cell. In some embodiments, the source / drain contact has an "L"-shaped top view profile. In some embodiments, in a cross-sectional view, the source / drain contact comprises a plurality of inclined sidewalls. In some embodiments, at least some of the inclined sidewalls are inclined at different angles. In some embodiments, the semiconductor device further comprises: a dielectric liner disposed on the inclined sidewalls of the source / drain contact. In some embodiments, in a top view, a majority of the source / drain contact extends in a first direction; and in a top view, the protruding segment protrudes from the majority of the source / drain contact in a second direction different from the first direction. In some embodiments, the protruding segment has a first dimension measured in the second direction; the first gate structure has a second dimension measured in the second direction; the first gate structure is spaced apart from the majority portion by a distance in the second direction; the first dimension is greater than the sum of the distance and 1 / 2 of the second dimension; and the first dimension is less than the sum of the distance and the second dimension. In some embodiments, the protruding segment has a first dimension measured in the first direction; the fin structure is spaced apart from an end of the first gate structure by a first distance in the first direction; the fin structure has a second dimension measured in the first direction; the fin structure is spaced apart from an adjacent fin structure by a second distance in the first direction; the first dimension is greater than the sum of the first distance and the second dimension; and the first dimension is less than the sum of the first distance, the second dimension, and 1 / 2 of the second distance.

[0092] Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes a fin structure including a semiconductor material. The semiconductor device includes a source / drain formed on the fin structure. The semiconductor device includes a gate formed above the fin structure. The semiconductor device includes a source / drain contact physically connected to the source / drain and the gate, wherein the source / drain contact has an asymmetric profile.

[0093] In some embodiments, the asymmetric profile is due to portions of the source / drain contacts protruding toward the gate and being physically and electrically connected to the gate. In some embodiments, in a top view, the asymmetric profile comprises an "L" shaped profile.

[0094] Another aspect of the present invention includes a method. A semiconductor device is provided, comprising: a fin structure, a source / drain region formed on the fin structure, a gate structure at least partially encapsulating the fin structure, and a dielectric material formed above the source / drain region and above the gate structure. An etching process is performed on the semiconductor device. The etching process forms an opening extending through the dielectric material and at least partially exposing the source / drain region and the gate structure. The opening is filled with a conductive material to electrically couple the gate structure and the source / drain region together. In some embodiments, the method further includes, before filling the opening: forming a protective layer to partially fill the opening. A wet cleaning process is performed on the semiconductor device after the protective layer has been formed; and after the wet cleaning process has been performed, removing the protective layer. In some embodiments, forming the protective layer includes forming a polymer layer as the protective layer. In some embodiments, the protective layer is formed so that the upper surface of the protective layer is disposed above the upper surface of the gate structure. In some embodiments, the method further includes: before filling the opening: forming a dielectric liner on the side of the opening, wherein the conductive material is formed on the dielectric liner. In some embodiments, the etching process is configured to have an etching selectivity between the gate structure and the dielectric material, so that the dielectric material is etched at a substantially faster rate than the gate structure. In some embodiments, the gate structure is a first gate structure; the semiconductor device further includes a second gate structure; the first gate structure and the second gate structure are formed on opposite sides of the source / drain region; and the etching process is performed without exposing the second gate structure to the opening. In some embodiments, in the top view, the opening is etched to have an "L" shape.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand the following detailed description. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention. For example, by implementing different thicknesses for the bit line conductors and the word line conductors, different resistances of the conductors can be achieved. However, other techniques for changing the resistance of the metal conductors may also be used.

Claims

1. A semiconductor device, comprising: Fin structure; a source / drain region formed on the fin structure; A first gate structure is disposed above the fin structure; as well as a source / drain contact disposed above the source / drain region, wherein the source / drain contact has a protruding section that protrudes at least partially above the first gate structure, wherein the source / drain contact electrically couples the source / drain region and the first gate structure together; wherein a majority of the source / drain contacts extend in a first direction in a top view; The protruding segment protrudes away from the majority portion in a second direction different from the first direction in top view; The protruding segment has a first dimension measured in the first direction; The fin structure is spaced apart from an end of the first gate structure by a first distance in the first direction; the fin structure having a second dimension measured in the first direction; The fin structure is spaced apart from the adjacent fin structure by a second distance in the first direction; The first dimension is greater than the sum of the first distance and the second dimension; and The first size is smaller than the sum of the first distance, the second size and 1 / 2 of the second distance.

2. The semiconductor device according to claim 1, further comprising a second gate structure; in: The source / drain contact is disposed between the first gate structure and the second gate structure but is not in physical contact with the second gate structure; as well as The fin structure, the source / drain regions, the first gate structure, the second gate structure, and the source / drain contacts are components of a static random access memory (SRAM) cell.

3. The semiconductor device according to claim 1, wherein The source / drain contacts have an "L" shaped top view profile.

4. The semiconductor device according to claim 1, wherein: In a cross-sectional view, the source / drain contacts include a plurality of inclined sidewalls.

5. The semiconductor device according to claim 4, wherein: At least some of the inclined side walls are inclined at different angles.

6. The semiconductor device according to claim 4, further comprising: A dielectric liner is disposed on the inclined sidewalls of the source / drain contact.

7. The semiconductor device according to claim 1, wherein: The protruding segment is in direct contact with the first gate structure.

8. The semiconductor device according to claim 1, wherein: the protruding segment having a third dimension measured in the second direction; the first gate structure having a fourth dimension measured in the second direction; the first gate structure is spaced apart from the majority portion by a third distance in the second direction; The third dimension is greater than the sum of the third distance and 1 / 2 of the fourth dimension; and The third size is smaller than the sum of the third distance and the fourth size.

9. The semiconductor device according to claim 6, wherein: The dielectric liner exposes a portion of an upper surface of the first gate structure, and the protruding segment directly contacts the portion of the upper surface.

10. A semiconductor device comprising: a fin structure including semiconductor material; A source / drain formed on the fin structure; a gate formed above the fin structure; as well as a source / drain contact physically connected to the source / drain and the gate, wherein the source / drain contact has an asymmetric profile including a portion extending in a first direction in top view and a protruding segment protruding away from the portion in a second direction different from the first direction in top view; wherein the protruding segment has a first dimension measured in the first direction; The fin structure is spaced apart from an end of the gate by a first distance in the first direction; the fin structure having a second dimension measured in the first direction; The fin structure is spaced apart from the adjacent fin structure by a second distance in the first direction; The first dimension is greater than the sum of the first distance and the second dimension; and The first size is smaller than the sum of the first distance, the second size and 1 / 2 of the second distance.

11. The semiconductor device according to claim 10, wherein: The asymmetric profile is due to the portion of the source / drain contact protruding toward the gate and being physically and electrically connected to the gate.

12. The semiconductor device according to claim 10, wherein: In top view, the asymmetric profile comprises an "L" shaped profile.

13. A method of forming a semiconductor device, comprising: A semiconductor device is provided, comprising: a fin structure, a source / drain region formed on the fin structure, a gate structure at least partially wrapping the fin structure, and a dielectric material formed above the source / drain region and above the gate structure; performing an etching process on the semiconductor device, wherein the etching process forms an opening extending through the dielectric material and at least partially exposing the source / drain region and the gate structure; forming a dielectric liner on a side of the opening, wherein the dielectric liner exposes a portion of an upper surface of the gate structure; and The opening is filled with a conductive material over the dielectric liner and directly over the portion of the upper surface of the gate structure to electrically couple the gate structure and the source / drain regions together.

14. The method of claim 13, further comprising, before filling the opening: forming a protective layer to partially fill the opening, performing a wet cleaning process on the semiconductor device after the protective layer has been formed; and After the wet cleaning process has been performed, the protective layer is removed.

15. The method according to claim 14, wherein: Forming the protective layer includes forming a polymer layer as the protective layer.

16. The method according to claim 14, wherein: The protection layer is formed so that an upper surface of the protection layer is disposed above an upper surface of the gate structure.

17. The method according to claim 13, wherein: The opening includes a plurality of inclined side walls.

18. The method according to claim 13, wherein: The etching process is configured to have an etch selectivity between the gate structure and the dielectric material such that the dielectric material is etched at a substantially faster rate than the gate structure.

19. The method of claim 13, wherein: The gate structure is a first gate structure; The semiconductor device further includes a second gate structure; The first gate structure and the second gate structure are formed on opposite sides of the source / drain region; as well as The etching process is performed without exposing the second gate structure to the opening.

20. The method according to claim 13, wherein: In the top view, the opening is etched to have an "L" shape.

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