A low-loss and low-leakage trench MOS power device and preparation method

Abstract

The present invention relates to a trench MOS power device with low loss and leakage and a preparation method, comprising a plurality of trench MOS device units arranged in parallel and repeated; each unit cell structure comprises: a substrate; an epitaxial layer arranged on the surface of the substrate; a trench arranged in the epitaxial layer; a portion at the bottom of the trench and located in the epitaxial layer is formed with a single injection doping of N-type impurities; a gate trench oxide layer arranged on the sidewall of the trench; a gate polysilicon layer is filled in the gate trench oxide layer; a P-type lightly doped well layer is formed around the gate trench oxide layer; an N-type heavily doped source region is arranged on the upper part of the well layer and located around the gate trench oxide layer; an interlayer dielectric layer is arranged on the surface of the epitaxial layer; and a source contact hole that penetrates the interlayer dielectric layer and connects to the source region. The present invention reduces the gate-source leakage current and reduces the conduction loss by 15% while maintaining the same breakdown voltage, greatly improving the competitiveness of the product.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a trench MOS power device with low loss and leakage and a preparation method thereof. Background Art

[0002] Due to the development of power semiconductor devices, the size of many electronic devices has become smaller and smaller while the efficiency has increased accordingly. As one of the main power semiconductor devices, the trench MOS device (trench metal oxide semiconductor field effect transistor) is a new type of vertical structure device developed on the basis of planar VDMOS. Although both are high cell density devices, the trench MOS device has more obvious advantages in comparison: such as lower on-resistance, switching loss and faster switching speed. In recent years, trench MOS devices have been widely used in lithium battery protection, motor drive and synchronous rectification of AC / DC power supply.

[0003] For trench MOS devices, there are several key parameters: breakdown voltage, gate-source leakage and on-resistance. The breakdown voltage reflects the blocking ability of the device, the gate-source leakage reflects the gate leakage current, and the conduction loss reflects the conduction ability of the device. Ideally, in general, it is always hoped that a trench MOS device with smaller gate-source leakage can be obtained under the same breakdown voltage, smaller conduction loss and the same gate-source voltage. At the same time, the optimization of conduction loss also means energy saving, so these are the focus of research in the field. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention discloses a trench MOS power device with low loss and leakage and a preparation method thereof.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A trench MOS power device with low loss and leakage, comprising a plurality of trench MOS device units repeatedly arranged in parallel; each unit cell structure comprises:

[0007] substrate;

[0008] An epitaxial layer disposed on the surface of the substrate;

[0009] A trench is provided in the epitaxial layer; a primary implantation doping of N-type impurities is formed at the bottom of the trench and in the portion located in the epitaxial layer;

[0010] A gate trench oxide layer is arranged on the sidewall of the trench; a gate polysilicon layer is filled inside the gate trench oxide layer; and a P-type lightly doped well layer is formed around the gate trench oxide layer;

[0011] An N-type heavily doped source region disposed on the upper portion of the well layer and located around the gate trench oxide layer;

[0012] An interlayer dielectric layer disposed on the surface of the epitaxial layer;

[0013] A source contact hole penetrates the interlayer dielectric layer and connects to the source region.

[0014] A further technical solution is that the bottom of the groove is a smooth semicircular structure.

[0015] A further technical solution is that the width of the groove is 0.18-0.28 um and the depth is 1.4-1.8 um.

[0016] A further technical solution is that the thickness of the gate trench oxide layer is 80-90 nm.

[0017] A further technical solution is that the concentration of impurities injected once is 1.5 to 2.5E12 / cm 2 .

[0018] A further technical solution is that the properties of the impurity ions doped by the primary implantation and the properties of the impurity ions in the epitaxial layer are of the same conductivity type.

[0019] A method for preparing a trench MOS power device with low loss and leakage as described in any one of the above items, characterized by comprising:

[0020] Step S1. forming a substrate and an epitaxial layer on the substrate;

[0021] Step S2. depositing a hard mask layer on the surface of the epitaxial layer; coating a photoresist on the surface of the hard mask layer and forming a groove pattern on the surface of the photoresist;

[0022] Step S3. Using photoresist as a barrier to etch the hard mask layer;

[0023] Step S4. removing the photoresist on the surface of the hard mask layer, using the etched hard mask layer as a mask, etching the epitaxial layer, and forming a groove in the epitaxial layer;

[0024] Step S5. Using the etched hard mask layer as a mask, doping is performed once at the bottom of the trench;

[0025] Step S6. After removing the hard mask layer, a sacrificial oxide layer is formed; then the sacrificial oxide layer is removed and a diffusion process is used to form a gate trench oxide layer on the trench sidewall;

[0026] Step S7. Filling the gate trench oxide layer with a gate polysilicon layer and etching back the gate polysilicon layer so that the gate polysilicon layer is lower than the top of the trench;

[0027] Step S8. P-type light doping is performed on the entire plane of the device and annealing is performed to form a well layer;

[0028] Step S9. exposing the source region and performing N-type heavy doping and annealing to form a source region;

[0029] Step S10. Depositing an interlayer dielectric layer on the entire device surface;

[0030] Step S11: forming a source contact hole penetrating the interlayer dielectric layer and connecting to the source region.

[0031] Its further technical solution includes:

[0032] After step S4, the method further includes:

[0033] The morphology of the bottom of the groove is optimized into a smooth semicircular structure by using an etching process.

[0034] The beneficial effects of the present invention are as follows:

[0035] The entire conduction loss of the trench MOS device is Rds(on)=RN(source region loss)+RCH(channel loss)+RA(accumulation region loss)+RD(epitaxial layer loss)+RS(SUB loss). The present invention directly performs the same type of ion implantation on the epitaxial layer at the bottom of the trench, reducing RD (epitaxial layer loss), thereby reducing the conduction loss of the product by 15% and improving the competitiveness of the product.

[0036] Furthermore, the present invention also performs morphology optimization processing (Rounding Etch) on the bottom of the groove, and directly uses the epitaxial layer part at the bottom of the groove for one-time implantation. This reduces the gate-source leakage current and reduces the conduction loss by 15% while maintaining the same breakdown voltage, greatly improving the competitiveness of the product. This is because the bottom of the groove of the longitudinal structure formed in the epitaxial layer by etching process is smoothed to form a rounded semicircular structure, thereby weakening the electric field distribution at the corners of the bottom of the groove and reducing the gate-source leakage current.

[0037] The structure of the invention is simple and ingenious, does not require any changes in other materials or structures, is concise and clear, and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the deposition of substrate and epitaxial layer and the growth and lithography of hard mask layer.

[0039] Figure 2 Schematic diagram of the hard mask layer after removing the photoresist.

[0040] Figure 3 Schematic diagram of the trench after etching using a hard mask layer for masking.

[0041] Figure 4 This is a schematic diagram after the morphology of the groove bottom is further optimized.

[0042] Figure 5 Schematic diagram of ion implantation at the bottom of the trench.

[0043] Figure 6 Schematic diagram of removing the hard mask and forming a sacrificial oxide layer.

[0044] Figure 7 Schematic diagram of forming a gate trench oxide layer after removing the sacrificial oxide layer.

[0045] Figure 8 Schematic diagram of gate polysilicon filling and back etching.

[0046] Fig. 9 A schematic diagram of forming a P-type well layer.

[0047] Fig.10 A schematic diagram of forming a source region.

[0048] Fig.11 It is a schematic diagram of the interlayer dielectric layer and the source contact hole.

[0049] In the figure: 101, substrate; 102, epitaxial layer; 103, trench; 104, semicircular structure; 105, primary implantation doping; 106, gate trench oxide layer; 107, gate polysilicon layer; 108, well layer; 109, source region; 110, interlayer dielectric layer; 111, source contact hole; 201, hard mask layer; 301, photoresist; 401, sacrificial oxide layer. DETAILED DESCRIPTION

[0050] The specific implementation of the present invention will be described below in conjunction with the accompanying drawings.

[0051] Fig.11 It is a schematic diagram of the interlayer dielectric layer and the source contact hole. Fig.11 A schematic diagram of a trench MOS device formed after the manufacturing process of the trench MOS device is completed is shown. Fig.11 , the device structure includes:

[0052] A substrate 101, and an epitaxial layer 102 is formed on the surface of the substrate 101. In this embodiment, the substrate is N+ type, and the epitaxial layer is N- type.

[0053] The epitaxial layer 102 has a trench 103. The bottom of the trench 103 and the portion located in the N-type epitaxial layer 102 are implanted with a doping agent 105. In this embodiment, the implanted doping agent 105 is an N-type doping agent.

[0054] A gate trench oxide layer 106 is disposed on the sidewall of the trench 104 . A gate polysilicon layer 107 is filled inside the gate trench oxide layer 106 , and the upper surface of the gate polysilicon layer 107 is lower than the upper end of the trench 103 .

[0055] A P-type lightly doped well layer 108 is formed around the gate trench oxide layer 106 .

[0056] An N-type heavily doped source region 109 is formed on the upper portion of the P-type lightly doped well layer 108 and at the periphery of the gate trench oxide layer 106. An interlayer dielectric layer 110 is disposed on the surface of the N-type epitaxial layer 102.

[0057] The source contact hole 111 penetrates the interlayer dielectric layer 110 and connects to the source region 109 .

[0058] Preferably, the bottom of the groove 103 is optimized to be a smooth semicircular structure 104. Fig.11 In the structure shown, the bottom of the groove 103 is optimized by etching process to form a smooth semicircular structure 104, thereby weakening the electric field distribution at the bottom corner of the groove 103 and reducing the gate-source leakage current. In a specific embodiment, the gate-source leakage current at a gate-source voltage of 20V can be reduced by 10% after the bottom of the groove 103 is smoothed.

[0059] Preferably, the width of the trench 103 is 0.18-0.28 um, and the depth is 1.4-1.8 um.

[0060] Preferably, the thickness of the gate trench oxide layer 106 is 80-90 nm.

[0061] Preferably, the impurity concentration of the first implantation doping 105 is 1.5 to 2.5E12 / cm 2 .

[0062] Preferably, as described in the above embodiment, the properties of the impurity ions injected into the doping 105 and the properties of the impurity ions in the epitaxial layer are of the same conductivity type. The entire conduction loss of the trench MOS device is Rds(on)=RN (source region loss)+RCH (channel loss)+RA (accumulation region loss)+RD (epitaxial layer loss)+RS (SUB loss). The present invention directly performs the same type of ion implantation on the epitaxial layer 102 at the bottom of the trench 103, thereby reducing RD (epitaxial layer loss), and can reduce the conduction loss of the product by 15% when the forward conduction voltage drop is substantially unchanged.

[0063] The present invention also discloses a trench MOS power device with low loss and leakage and a preparation method thereof, comprising:

[0064] Step S1. Form a substrate 101 and an epitaxial layer 102 on the substrate 101. In this embodiment, the substrate 101 is of N+ type, and the epitaxial layer 102 is of N- type.

[0065] Step S2 . Deposit a hard mask layer 201 , ie, silicon dioxide, on the surface of the N-type epitaxial layer 102 using a deposition process, coat the surface of the hard mask layer 201 with a photoresist 301 , and form a trench pattern on the surface of the photoresist 301 . Figure 1 Schematic diagram of the deposition of substrate and epitaxial layer and the growth and lithography of hard mask layer. Figure 1 The device structure after performing step S1 and step S2 is shown.

[0066] Step S3: using photolithography technology on the surface of the hard mask layer 201, using the photoresist 301 as a barrier, to etch the hard mask layer 201.

[0067] Step S4. Using a cleaning process, remove the photoresist 301 on the surface of the hard mask layer 201, and use the etched hard mask layer 201 as a mask to etch the epitaxial layer 102 to form a trench 103 in the epitaxial layer 102; Figure 2 Schematic diagram of the hard mask layer after removing the photoresist. Figure 2 The pattern on the hard mask layer 201 from which the photoresist 301 is removed is shown. Figure 3 Schematic diagram of the trench after etching using a hard mask layer for masking. Figure 3 The trench 103 etched in the epitaxial layer 102 is shown, with a feature size of 0.25um and a depth of 1.5um.

[0068] Preferably, a re-etching process is added after step S4 to optimize the morphology of the bottom of the groove 103 to make it a rounded semicircular structure 104 with smoother lines. Figure 4 This is a schematic diagram after the morphology of the bottom of the groove is further optimized. Figure 4 As shown, the bottom of the groove 103 is rounded.

[0069] Step S5. After using a cleaning process to remove the etching products and silicon slag in step S4, the hard mask layer 201 etched in step S3 is directly used as a mask to perform a primary doping 105 on the bottom of the trench 103. Preferably, the impurity concentration of the primary doping 105 is 1.5 to 2.5E12 / cm 2 Preferably, the properties of the impurity ions of the primary implantation doping 105 and the properties of the impurity ions of the epitaxial layer 2 are of the same conductivity type, that is, the primary implantation doping uses N-type impurities. Figure 5 Schematic diagram of ion implantation at the bottom of the trench.

[0070] Step S6: After removing the hard mask layer 201 , a sacrificial oxide layer 401 is formed. Then, the sacrificial oxide layer 401 is removed and a diffusion process is used to form a gate trench oxide layer 106 on the sidewall of the trench 103 . Figure 6 Schematic diagram of removing the hard mask and forming a sacrificial oxide layer. Figure 7 Schematic diagram of forming a gate trench oxide layer after removing the sacrificial oxide layer. Figure 6 , Figure 7 .

[0071] Step S7 . Using a deposition process, fill the gate polysilicon layer 107 inside the gate trench oxide layer 106 and perform back etching, so that the gate polysilicon layer 107 is lower than the top of the trench 103 . Figure 8 Schematic diagram of gate polysilicon filling and back etching.

[0072] Step S8: Using an implantation process, the entire plane of the device is lightly doped with P-type and annealed to form a well layer 108 . Fig. 9 A schematic diagram of forming a P-type well layer.

[0073] Step S9 . Using a photolithography process, the source region is exposed and N-type heavy doping and annealing are performed to form the source region 109 . Fig.10 A schematic diagram of forming a source region.

[0074] Step S10: Using a deposition process, deposit an interlayer dielectric layer 110 on the entire device surface.

[0075] Step S11 . Using photolithography and etching processes, a source contact hole 111 penetrating the interlayer dielectric layer 110 and connecting to the source region 109 is formed. Fig.11 It is a schematic diagram of the interlayer dielectric layer and the source contact hole.

[0076] After step S11, there are steps for manufacturing the metal layer and the passivation layer. These steps are conventional processes in the field of semiconductor device manufacturing and will not be described in detail here.

[0077] In the above process steps, the hard mask layer 201 etched in step S3 is directly used for masking, and the bottom of the trench 103 is implanted with doping 105 once, thereby eliminating the process of photoresist coating and etching, thereby reducing the manufacturing cost.

[0078] It can be seen from the product test data that by using the above process flow, the forward conduction voltage drop of the device remains basically unchanged while the conduction loss can be reduced by 15%. If the preferred solution is used, that is, an etching process is added after step S4, and the morphology of the bottom of the groove 103 is further optimized to make it a smooth semicircular structure 104 with smoother lines, the gate-source leakage current at 20V can be reduced by 10%.

[0079] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. The present invention may be modified in any form without violating the basic structure of the present invention.

Claims

1. A low loss and leakage trench MOS power device, characterized in that: It includes multiple trench MOS device units that are repeatedly arranged in parallel; each unit cell structure includes: A substrate (101); An epitaxial layer (102) disposed on the surface of the substrate (101); A groove (103) is provided in the epitaxial layer (102); a primary implantation doping (105) of N-type impurities is formed at the bottom of the groove (103) and in the portion located in the epitaxial layer (102); A gate trench oxide layer (106) is arranged on the side wall of the trench (103); a gate polysilicon layer (107) is filled inside the gate trench oxide layer (106); and a P-type lightly doped well layer (108) is formed around the gate trench oxide layer (106); An N-type heavily doped source region (109) disposed on the upper portion of the well layer (108) and located around the gate trench oxide layer (106); An interlayer dielectric layer (110) disposed on the surface of the epitaxial layer (102); A source contact hole (111) penetrating the interlayer dielectric layer (110) and connected to the source region (109); The properties of the impurity ions implanted once (105) and the impurity ions of the epitaxial layer (102) are of the same conductivity type.

2. The low loss and leakage trench MOS power device according to claim 1, characterized in that: The bottom of the groove (103) is a smooth semicircular structure (104).

3. The low loss and leakage trench MOS power device according to claim 1, characterized in that: The width of the groove (103) is 0.18-0.28 um, and the depth is 1.4-1.8 um.

4. The low loss and leakage trench MOS power device according to claim 1, characterized in that: The thickness of the gate trench oxide layer (106) is 80-90 nm.

5. The low loss and leakage trench MOS power device according to claim 1, characterized in that: The impurity concentration of the primary implanted doping (105) is 1.5 to 2.5E12 / cm 2 .

6. A method for preparing a trench MOS power device with low loss and leakage as claimed in any one of claims 1 to 5, characterized in that: include: Step S1. forming a substrate (101) and an epitaxial layer (102) on the substrate (101); Step S2. Depositing a hard mask layer (201) on the surface of the epitaxial layer (102); coating a photoresist (301) on the surface of the hard mask layer (201) and forming a groove pattern on the surface of the photoresist (301); Step S3. Using the photoresist (301) as a barrier, etching the hard mask layer (201); Step S4. removing the photoresist (301) on the surface of the hard mask layer (201), using the etched hard mask layer (201) as a mask, etching the epitaxial layer (102), and forming a groove (103) in the epitaxial layer (102); Step S5. Using the etched hard mask layer (201) as a mask, perform a doping implantation (105) on the bottom of the trench (103); Step S6. After removing the hard mask layer (201), a sacrificial oxide layer (401) is formed; Then, the sacrificial oxide layer (401) is removed and a diffusion process is used to form a gate trench oxide layer (106) on the side wall of the trench (103); Step S7: Filling the gate polysilicon layer (107) inside the gate trench oxide layer (106) and etching back so that the gate polysilicon layer (107) is lower than the top of the trench (103); Step S8. P-type light doping is performed on the entire plane of the device and annealing is performed to form a well layer (108); Step S9. exposing the source region and performing N-type heavy doping and annealing to form a source region (109); Step S10. Depositing an interlayer dielectric layer (110) on the entire device surface; Step S11: forming a source contact hole (111) penetrating the interlayer dielectric layer (110) and connecting to the source region (109).

7. A preparation method according to claim 6, characterized in that: include: After step S4, the method further includes: Using an etching process, the morphology of the bottom of the groove (103) is optimized to be a smooth semicircular structure (104); Then proceed to step S5.

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