Hybrid packaging method and hybrid packaging structure applied to electronic devices

Abstract

The present invention discloses a hybrid packaging method and a hybrid packaging structure applied to electronic devices. The hybrid packaging method applied to electronic devices comprises: combining at least one substrate or at least one substrate with at least one first chip and a lead frame; performing wire bonding processing on the lead frame combined with the substrate or the first chip and the substrate, and then performing packaging processing. A hybrid packaging method applied to electronic devices provided by an embodiment of the present invention can achieve chip integration by matching circuits, high requirements on chip heat dissipation capacity, reduce packaging thermal resistance, stabilize chip performance, reduce cost, reduce the appearance volume of electronic equipment, and improve the efficiency of PCB unit area use.

Description

Technical Field

[0001] The present invention particularly relates to a hybrid packaging method and a hybrid packaging structure applied to electronic devices, belonging to the technical field of semiconductor packaging. Background Art

[0002] Lead frame packaging products (such as QFN / DFN packaging) can only mount single chips or multiple chips to achieve circuit integration, but the internal structure of the chip cannot pass large currents and high voltages, and the power cannot be too high, which cannot meet all market demands; substrate packaging products (such as LGA / BGA package) can meet large currents and high voltages, and design circuit matching to achieve chip integration, but cannot meet power devices with high heat dissipation requirements, have unstable performance, low working efficiency, and high production costs. Summary of the invention

[0003] The main purpose of the present invention is to provide a hybrid packaging method and a hybrid packaging structure applied to electronic devices to overcome the deficiencies in the prior art.

[0004] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0005] An embodiment of the present invention provides a hybrid packaging method for electronic devices, which includes:

[0006] combining at least one substrate or at least one substrate and at least one first chip with a lead frame;

[0007] A wire bonding process is performed on the lead frame combined with the substrate or the first chip and the substrate, and then a packaging process is performed.

[0008] Furthermore, the hybrid packaging method applied to electronic devices specifically includes: mounting at least one first chip on the lead frame by at least one of the methods of glue dispensing, glue brushing, and flip-chip mounting.

[0009] Furthermore, the hybrid packaging method applied to electronic devices specifically includes: mounting at least one substrate on the lead frame by at least one of dispensing patches or welding patches.

[0010] Furthermore, the hybrid packaging method applied to electronic devices specifically includes: mounting at least one substrate and at least one first chip on a lead frame simultaneously, or mounting at least one substrate and at least one first chip on a lead frame in a set order.

[0011] Furthermore, the hybrid packaging method applied to electronic devices includes: combining at least one component and / or at least one second chip on the substrate, and then combining the substrate with a lead frame.

[0012] Furthermore, at least one second chip is mounted on the substrate by at least one of the following methods: adhesive patching, adhesive patching, and flip-chip patching.

[0013] Furthermore, at least one component is bonded to the substrate at least by welding.

[0014] Furthermore, the first chip or the second chip includes any one or a combination of two or more of a silicon chip, a gallium arsenide chip, a gallium nitride chip, and a silicon carbide chip, but is not limited thereto.

[0015] Furthermore, the components include any one of resistors, capacitors, and inductors, or a combination of two or more thereof, but are not limited thereto.

[0016] Furthermore, the substrate includes any one or a combination of two or more of a multi-ceramic substrate, a mixed sintered substrate, a copper-clad substrate, and a flexible substrate, but is not limited thereto.

[0017] Furthermore, the hybrid packaging method applied to electronic devices specifically includes: connecting the first chip, the substrate and the lead frame through metal wires.

[0018] Furthermore, the hybrid packaging method applied to electronic devices specifically includes at least using injection molding to implement the packaging process.

[0019] An embodiment of the present invention also provides a hybrid packaging structure for electronic devices, which includes at least one substrate or at least one substrate and at least one first chip, a lead frame and a plastic package body, at least the substrate or the substrate and the first chip, and the lead frame are all encapsulated in the plastic package body, the substrate and at least one first chip are both combined on the lead frame, and any one of the substrate, the first chip, and the lead frame is also bonded with a metal wire to at least electrically connect the substrate or the substrate and the first chip to the lead frame, and the substrate is also combined with at least one component and / or at least one second chip.

[0020] Furthermore, the first chip or the second chip includes any one or a combination of two or more of a silicon chip, a gallium arsenide chip, a gallium nitride chip, and a silicon carbide chip, but is not limited thereto.

[0021] Furthermore, the components include any one of resistors, capacitors, and inductors, or a combination of two or more thereof, but are not limited thereto.

[0022] Furthermore, the substrate includes any one or a combination of two or more of a multi-ceramic substrate, a mixed sintered substrate, a copper-clad substrate, and a flexible substrate, but is not limited thereto.

[0023] Compared with the prior art, the advantages of the present invention include: a hybrid packaging method for electronic devices provided in an embodiment of the present invention can match the circuit to achieve chip integration, high-requirement chip heat dissipation capability, reduce packaging thermal resistance, stabilize chip performance, reduce costs, reduce the appearance and volume of electronic equipment, and improve the utilization efficiency of PCB unit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of a substrate in a typical implementation case of the present invention;

[0025] Figure 2 It is a schematic diagram of a structure formed with components and a chip substrate in a typical implementation case of the present invention;

[0026] Figure 3 It is a schematic diagram of the structure of a chip mounted on a substrate in a typical implementation case of the present invention;

[0027] Figure 4 It is a schematic diagram of the structure of a substrate patch on a lead frame in a typical implementation case of the present invention;

[0028] Figure 5 It is a schematic diagram of the structure of a chip mounted on a lead frame in a typical implementation case of the present invention. DETAILED DESCRIPTION

[0029] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows. Unless otherwise specified, the processing technology used in the embodiments of the present invention can be used by those skilled in the art.

[0030] The hybrid package structure can realize chip integration, meet high heat dissipation requirements and reduce costs. The mixed production of substrate and lead frame is a new hybrid package form with circuit integration and high heat dissipation. The plastic package contains chip patches (die attached) and substrate (laminate) patches (the substrate contains components and chips). By utilizing the maximum space in the plastic package, it can match the circuit to realize chip integration, high-requirement chip heat dissipation capacity, reduce package thermal resistance, improve chip performance stability, reduce costs, reduce the appearance volume of electronic equipment, and improve the efficiency of PCB unit area use.

[0031] The embodiment of the present invention provides a method for hybrid production of a laminate and a lead frame, wherein a chip patch and a substrate patch are included in a plastic package (the substrate includes processes such as welding components and mounting chips), and the substrate-matching hybrid packaging form can achieve high chip integration, meet high chip heat dissipation requirements, ensure continuous and stable electrical performance, reduce costs, reduce the appearance and volume of electronic devices, and improve the unit area utilization efficiency of PCB boards.

[0032] At present, SMD (passive components) are mostly packaged in QFN / DFN packages, but existing components cannot meet the needs of complex circuit integration; QFN / DFN die (integrated circuit bare die) packaging technology is also relatively common, but multi-die products have high requirements on the packaging volume, different dies have different applications, different patch processes, and the cost of different wafers is also high. Compared with the existing technology, the packaging structure and method provided by the present invention have flexible circuit debugging (optimal performance is debugged through components, if it is a wafer, the performance is fixed after tape out) and stable performance (high Q value components can be selected).

[0033] The packaging structure and method provided by the present invention for electronic devices also need to consider the Warpage factor of the substrate. For example, the CTE of copper is 16, and the CTE of Epoxy (Ag) is 20. Then the CTE (coefficient of thermal expansion) of the substrate needs to be adapted between 10-20 to avoid severe warping and excessive stress during high-temperature welding / curing, which may lead to failure of packaging reliability.

[0034] The packaging structure and method for electronic devices provided by the present invention need to consider the substrate loading method in the selection method of the patch process, such as tapping (similar to components-SMD) or similar blue film UV removal (diepick up form), and parameters such as substrate thickness can be set by referring to the existing QFN / DFN Mold Cap thickness of OSAT (OSAT).

[0035] The packaging structure method for electronic devices provided by the present invention needs to pay attention to the following in the packaging patch:

[0036] 1) Selection of nozzle (to pick up substrate patches): The hollow height and edge width of the nozzle need to be designed according to the layout of the substrate and the position of the SMD (surface mount device) of the components to prevent the substrate wiring from being crushed and the components from being hit;

[0037] 2) DA machine (die attached) vacuum strength adjustment. When there are many components on the substrate and the chip is thick, the weight is much heavier than the die itself and is not of the same order of magnitude. Therefore, it is necessary to evaluate the appropriate absorption method to overcome the difficulty of DA (drive amplifier);

[0038] 3.) DA Epoxy selection: If there is a high heat dissipation requirement, then if sintered silver glue is used, because the workability of sintered silver is very poor, it is necessary to pay attention to the side glue creeping to be ≤95% of the die / substrate thickness. If the glue amount is too large, it will easily cause silver migration and leakage in the reliability experiment;

[0039] 4) Wire bonding arc collision, the design of the WB pressure plate needs to avoid the wire arc height to prevent sagging wire;

[0040] 5) Selection of compound for plastic encapsulation: There are too many processes / materials due to component welding, chip welding, substrate welding, die welding, etc. It is necessary to pay attention to the voids generated during the compound injection molding process and the influence of stress after plastic encapsulation. To avoid voids and incompleteness, the resin system can choose a compound with a smaller SPIRAL FLOW and a smaller filler size; to solve the packaging stress, a compound with a smaller Young's modulus can be used. During the thermal process, part of the stress can be absorbed and converted by the material itself (it is best to do stress simulation to determine the material structure after determining the material).

[0041] See also Figure 1-Figure 5 The embodiment of the present invention further provides a substrate and lead frame hybrid packaging structure, which includes at least one substrate 11 and at least one first chip 32, a lead frame 61 and a plastic package 51, at least the substrate 11, the first chip 32 and the lead frame 61 are all packaged in the plastic package 51, the substrate 11 and the at least one first chip 32 are all combined on the lead frame 61, and a metal wire 41 is bonded to any one of the substrate 11, the first chip 32 and the lead frame 61 to at least electrically connect the substrate 11 and the first chip 32 to the lead frame 61, and at least one component 21 and / or at least one second chip 22 are also combined on the substrate 11.

[0042] For details, please refer to Figure 1The substrate 11 can be made of a multilayer board or of different materials according to the needs of the designer to achieve circuit matching. The components 21 include but are not limited to capacitors, inductors, resistors, etc. The second chip 22 is mounted on the substrate 11 by dispensing, brushing, flip-chip, etc., wherein the components 21 and the second chip 22 can be mounted separately or not, or both can be mounted at the same time. The specific settings can be made according to the needs of technicians in this field. After the components and the second chip are mounted, they need to be cured or reflow soldered according to the parameters in the material manual.

[0043] For details, please refer to Figure 4 The substrate 11 can be formed by two methods: jig cutting (Jig saw) and tape cutting (Tape saw). The single substrate obtained after jig cutting needs to be placed in a tray. It can be decided whether to directly use the tray packaging and mount the chips on the equipment, or to use the tape packaging and weld it to the lead frame 61 (similar to the SMT method of components) according to the processing capacity of each foundry; the substrate formed by the tape cutting method can be mounted on the lead frame 61 by dispensing chips (similar to wafer saw, using UV film + Ring), and the first chip 32 is mounted on the lead frame 61 by chip bonding; wherein, the bonding method of the substrate 11 and the first chip 32 does not limit the type and method of the chip material, and curing or reflow soldering is required after the chip is mounted.

[0044] For details, please refer to Figure 4 The lead frame 61, the first chip 32, and the substrate 11 are all bonded with metal wires 41, and the metal wires 41 include but are not limited to copper wires, palladium-plated copper wires, gold wires, aluminum wires, silver alloy wires, etc. The material of the plastic package 51 can be resin. Of course, those skilled in the art can select different resin systems, different dielectric constants, different Young's moduli, different glass temperatures, and resin materials of different filler sizes according to electrical requirements and process requirements. A post-curing process is required after the encapsulation is completed, and the parameters of the post-curing are set according to the material datasheet.

[0045] Specifically, an embodiment of the present invention provides a hybrid packaging method for electronic devices, which includes the following steps: combining at least one substrate 11 or at least one substrate 11 and at least one first chip 32 with a lead frame 61;

[0046] The wire frame 61 combined with the substrate 11 or the first chip 32 and the substrate 11 is wire bonded, and then packaged.

[0047] 1) at least one component 21 is combined on the substrate 11 by at least welding, and at least one second chip 22 is mounted on the substrate 11 by at least one of the methods of glue patch, glue patch, and flip chip patch 2;

[0048] 2) at least one of the substrates 11 is mounted on the lead frame 61 by at least one of the methods of dispensing glue patches or welding patches, and at least one of the first chips 32 is mounted on the lead frame 61 by at least one of the methods of dispensing glue patches, brushing glue patches, and flip-chip patches;

[0049] 3) The lead frame 61 on which the first chip 32 and the substrate 11 are mounted in the above step 2) is subjected to wire bonding, and then a packaging process is performed.

[0050] Specifically, the substrate 11 in the embodiment of the present invention includes but is not limited to various types of substrates such as multi-ceramic substrates, mixed sintered substrates, copper-clad substrates, and flexible boards. The components 21 include but are not limited to components such as resistors, capacitors, and inductors. The methods for mounting the substrate 11 to the lead frame include but are not limited to methods such as dispensing patches and welding patches. Among them, the mounting process of the first chip 32 and the mounting process of the substrate 11 can be completed simultaneously or separately, and in no particular order.

[0051] Specifically, the first chip 32 in step 2) can also be mounted on the substrate 11 (chip bonding includes a flip chip process), but at least one chip is mounted on the lead frame. The first chip 32 and the second chip 22 include but are not limited to silicon chips, gallium arsenide chips, gallium nitride chips, silicon carbide chips, etc.

[0052] A hybrid packaging method for electronic devices provided in an embodiment of the present invention can achieve chip integration through matching circuits, high-requirement chip heat dissipation capability, reduce packaging thermal resistance, stabilize chip performance, reduce costs, reduce the appearance and volume of electronic devices, and improve the utilization efficiency of PCB unit area.

[0053] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A hybrid packaging method for electronic devices, characterized in that include: combining at least one first chip with the lead frame; Combining at least one component and / or at least one second chip on a substrate, and then combining the substrate with a lead frame; The wire frame combined with the first chip and the substrate is wire-bonded, and at least encapsulated by injection molding, so that at least the substrate, the first chip and the wire frame are all encapsulated in a plastic package.

2. The hybrid packaging method for electronic devices according to claim 1, characterized in that Specifically include: At least one first chip is mounted on the lead frame by at least one of the following methods: glue dispensing, glue brushing, and flip-chip mounting.

3. The hybrid packaging method for electronic devices according to claim 1, characterized in that Specifically include: At least one substrate is mounted on the lead frame by at least one of a dispensing method and a welding method.

4. The hybrid packaging method for electronic devices according to claim 1, characterized in that Specifically, it includes: mounting at least one substrate and at least one first chip on the lead frame at the same time, or mounting at least one substrate and at least one first chip on the lead frame in a set order.

5. The hybrid packaging method for electronic devices according to claim 1, characterized in that include: At least one second chip is mounted on the substrate by at least one of the following methods: dispensing, brushing, and flip-chip mounting.

6. The hybrid packaging method for electronic devices according to claim 1, characterized in that: At least one component is bonded to the substrate at least by welding.

7. The hybrid packaging method for electronic devices according to claim 1, characterized in that: The first chip or the second chip includes any one of a silicon chip, a gallium arsenide chip, a gallium nitride chip, and a silicon carbide chip, or a combination of two or more thereof.

8. The hybrid packaging method for electronic devices according to claim 1, characterized in that: The components include any one of resistors, capacitors, and inductors, or a combination of two or more thereof.

9. The hybrid packaging method for electronic devices according to claim 1, characterized in that: The substrate includes any one of a multi-ceramic substrate, a mixed sintered substrate, a copper-clad substrate, and a soft substrate, or a combination of two or more thereof.

10. The hybrid packaging method for electronic devices according to claim 1, characterized in that Specifically include: The first chip, the substrate and the lead frame are connected by metal wires.

11. A hybrid packaging structure for electronic devices, characterized in that include: At least one substrate and at least one first chip, a lead frame and a plastic package, wherein the substrate, the first chip and the lead frame are all encapsulated in the plastic package, and the substrate and at least one first chip are all combined on the lead frame. Metal wires are also bonded to any one of the substrate, the first chip and the lead frame to at least electrically connect the substrate or the substrate and the first chip to the lead frame, and at least one component and / or at least one second chip are also combined on the substrate.

12. The hybrid packaging structure according to claim 11, characterized in that: The first chip or the second chip includes any one of a silicon chip, a gallium arsenide chip, a gallium nitride chip, and a silicon carbide chip, or a combination of two or more thereof.

13. The hybrid packaging structure according to claim 11, characterized in that: The components include any one of resistors, capacitors, and inductors, or a combination of two or more thereof.

14. The hybrid packaging structure according to claim 11, characterized in that: The substrate includes any one of a multi-ceramic substrate, a mixed sintered substrate, a copper-clad substrate, and a soft substrate, or a combination of two or more thereof.

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