integrated circuit packaging

Abstract

Various embodiments of an integrated circuit package and a method of forming such a package are disclosed. The package includes: a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer; a die disposed in a cavity of the core layer; and an encapsulation disposed in the cavity between the die and a sidewall of the cavity. The package further includes: a first patterned conductive layer disposed within the first dielectric layer; a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is located between the device and the core layer; a second patterned conductive layer disposed within the second dielectric layer; and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is located between the conductive pad and the core layer.

Description

Background Art

[0001] A variety of electronic components, such as those used in implantable medical devices (IMDs), employ electronic circuits, for example, for providing electrical stimulation to human tissue and / or for monitoring physiological conditions. Such IMDs can deliver electrotherapy energy in the form of shock energy and stimulation pulses to selected body tissue. These IMDs typically include an output circuit for generating electrical energy under specified conditions, and at least one lead with a stimulation electrode for delivering the electrical energy to the selected tissue. For example, cardiac pacemakers and implantable cardioverter-defibrillators (ICDs) have been developed for maintaining a desired heart rate during an episode of bradycardia, or for performing cardioversion or defibrillation therapy on the heart when a severe arrhythmia is detected. Other medical devices that stimulate nerve, brain, muscle, and organ tissue are also known for treating a variety of conditions.

[0002] Currently available IMDs (including ICDs and implantable pulse generators (IPGs)) typically consist of a metal housing that is sealed and therefore impermeable to bodily fluids; and a plug or connector assembly mounted to the housing for electrical and mechanical connection to one or more leads. Such devices also include telemetry capabilities for communicating with external devices. Over the past few years, IMDs have evolved from relatively bulky devices to complex, compact devices with increasingly powerful functionality. For example, numerous improvements have been made to cardioversion / defibrillation leads and electrodes, which enable precise delivery of cardioversion / defibrillation energy to a selected portion or portions of the upper and lower cardiac chambers, significantly reducing the delivered shock energy required for cardioversion or defibrillation. High-voltage output circuitry has also been improved to provide monophasic, biphasic, or multiphasic cardioversion / defibrillation shocks or pulse waveforms, sometimes using specific combinations of cardioversion / defibrillation electrodes, which effectively reduce the shock energy required for cardioversion or defibrillation.

[0003] The miniaturization of IMDs (Integrated Devices) is driving the reduction in size and cost of all IMD components, including electronic circuitry. The desire is to increase the density and reduce the size of these components, thereby making the overall circuit more compact. As IMD size decreases, the electronic circuitry of the IMD is being formed as an integrated circuit to fit within the smallest possible space. Furthermore, as component size is also reduced, it is desirable to improve the use of space within the IMD package.

[0004] One response to this desire has been through technological improvements in the packaging of devices, where the output circuitry is included through packaging techniques such as reconstituted wafer packaging. In particular, development efforts in reconstituted wafer packaging (also known as fan-out wafer-level packaging) have focused on producing thinner and smaller electronic packages. Summary of the Invention

[0005] In general, the present disclosure provides various embodiments of an integrated circuit package and a method of forming such a package. The integrated circuit package may include: a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer; a die disposed in a cavity of the core layer; and an encapsulation disposed in the cavity, between the die and a sidewall of the cavity. The package may also include: a first patterned conductive layer disposed within the first dielectric layer; and a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is located between the device and the core layer, wherein the device is electrically connected to the die. The package may also include: a second patterned conductive layer disposed within the second dielectric layer; and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is located between the conductive pad and the core layer, wherein the conductive pad is electrically connected to the die.

[0006] In one aspect, the present disclosure provides an integrated circuit package, comprising: a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer; a die disposed in a cavity of the core layer; and an encapsulation disposed in the cavity between the die and a sidewall of the cavity. The integrated circuit package further comprises: a first patterned conductive layer disposed within the first dielectric layer; a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is located between the device and the core layer, wherein the device is electrically connected to the die; a second patterned conductive layer disposed within the second dielectric layer; and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is located between the conductive pad and the core layer. The conductive pad is electrically connected to the die.

[0007] In another aspect, the present disclosure provides a method for forming an integrated circuit package. The method includes: providing a cavity in a core layer; providing a carrier layer on the core layer and above the cavity; and providing a die within the cavity and on the carrier layer. The method further includes: providing a first dielectric layer on the core layer and above the cavity, such that the core layer is located between the first dielectric layer and the carrier layer, wherein the first dielectric layer includes a first patterned conductive layer provided between a first sublayer and a second sublayer of the first dielectric layer, and wherein the first patterned conductive layer includes a field plate spaced apart from the die; removing the carrier layer from the core layer; and providing a second dielectric layer on the core layer, such that the core layer is between the first dielectric layer and the second dielectric layer. The second dielectric layer includes a second patterned conductive layer provided between the first sublayer and the second sublayer of the second dielectric layer.

[0008] Unless otherwise indicated, all headings provided herein are for the convenience of the reader and should not be used to limit the meaning of any text that follows the heading.

[0009] The term "comprise" and variations thereof do not have a limiting meaning when these terms appear in this application. Such terms should be understood to imply the inclusion of stated steps or elements or groups of steps or elements, but not the exclusion of any other steps or elements or groups of steps or elements.

[0010] In this application, terms such as "a," "an," and "the" are not intended to refer to only a singular entity, but include general categories of which specific examples can be used for illustration. The terms "a," "an," and "the" are used interchangeably with the term "at least one." The phrases "at least one" and "including at least one" following a list refer to any one item in the list and any combination of two or more items in the list.

[0011] The phrases "at least one of" and "comprising at least one of" following a list refer to any one item in the list and any combination of two or more items in the list.

[0012] As used herein, the term “or” is generally employed in its sense including “and / or” unless the content clearly dictates otherwise.

[0013] The term "and / or" means one or all of the listed elements, or a combination of any two or more of the listed elements.

[0014] As used herein in connection with measured quantities, the term "about" refers to the variation in the measured quantity that would be expected by one skilled in the art making the measurements and exercising a level of care commensurate with the purpose of the measurements and the precision of the measuring devices used. As used herein, a number "up to" (e.g., up to 50) is inclusive of that number (e.g., 50).

[0015] Also herein, the recitations of numerical ranges by endpoints include all numbers subsumed within that range as well as the endpoints (eg, 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, 5, etc.).

[0016] These and other aspects of the present disclosure will be apparent from the detailed description below. However, the above summary should not be construed as limiting the claimed subject matter in any case. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Throughout the specification, reference is made to the accompanying drawings, wherein like reference numerals represent like elements, and wherein:

[0018] Figure 1 is a schematic cross-sectional view of one embodiment of an integrated circuit package.

[0019] Figure 2 yes Figure 1 Schematic top view of a major surface of a die of an integrated circuit package.

[0020] Figure 3A-Figure 3I are various cross-sectional views of one embodiment of an integrated circuit package, wherein Figure 3A is a schematic cross-sectional view of the core layer; Figure 3B is a schematic cross-sectional view of a cavity provided in a core layer; Figure 3C is a schematic cross-section of a carrier disposed on a core layer; Figure 3D is a schematic cross-sectional view of a tube die disposed in a cavity of a core layer; Figure 3E is a schematic cross-sectional view of a first dielectric layer disposed on the core layer and over the cavity; Figure 3F is a schematic cross-sectional view of a carrier removed from a core layer and a second dielectric layer disposed on the core layer; Figure 3G is a schematic cross-sectional view of a field plate disposed within a first dielectric layer and a patterned conductive layer on an outer surface of a second dielectric layer; Figure 3H is a schematic cross-sectional view of a patterned conductive layer disposed on an outer surface of a first dielectric layer; and Figure 3I is a schematic cross-sectional view of a conductive pad disposed on an outer surface of the second dielectric layer.

[0021] Figure 4 is a schematic plan view of one embodiment of an implantable medical device including an integrated circuit package.

[0022] Figure 5 is a schematic cross-sectional view of another embodiment of an integrated circuit package. DETAILED DESCRIPTION

[0023] In general, the present disclosure provides various embodiments of an integrated circuit package and a method of forming such a package. The integrated circuit package may include: a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer; a die disposed in a cavity of the core layer; and an encapsulation disposed in the cavity, between the die and a sidewall of the cavity. The package may also include: a first patterned conductive layer disposed within the first dielectric layer; and a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is located between the device and the core layer, wherein the device is electrically connected to the die. The package may also include: a second patterned conductive layer disposed within the second dielectric layer; and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is located between the conductive pad and the core layer, wherein the conductive pad is electrically connected to the die.

[0024] A microelectronic component, such as a semiconductor chip or die, is typically a flat body with electrical connection contacts disposed on an outer surface, where the electrical connection contacts are connected to the internal circuitry of the component itself. Microelectronic components are typically packaged to form an integrated circuit package or assembly having a surface that can be surface-mounted with terminals that are electrically connected to the internal contacts of the component. The package or assembly can then be connected to test equipment to determine whether the packaged device meets the desired performance standards. Once tested, the package can be connected to a larger circuit, for example, a circuit in an electronic product such as an implantable medical device. The package or assembly for such a microelectronic component may include the integrated circuit package described herein.

[0025] One or more embodiments of integrated circuit packages can provide one or more benefits over existing packages. For example, placing one or more dies within a cavity disposed within the core layer of the integrated circuit package can provide a smaller package size (i.e., height) than existing packages. Furthermore, because the die can be a flip-chip die (when disposed within the cavity of the core layer, the flip-chip die can be electrically connected via one or more die contacts disposed on the top or bottom surface of the die), wire bonding may not be required to connect the die to the patterned conductive layer of the package. Various embodiments of the methods described herein for forming such packages can also package multiple dies and other components in a single process flow, thereby reducing the cost of manufacturing these integrated circuit packages. In one or more embodiments, the parasitic inductance of the interconnects to the packaged die can be lower than the parasitic inductance generated by wire bonding. This can enable the die to operate at higher frequencies and can also reduce induced voltage spikes when switching high currents. Furthermore, the overall resistance of one or more embodiments of the packages described herein can exhibit reduced resistive losses and increased current capacity. Furthermore, one or more packages described herein can include multiple contacts for the die distributed over the source and drain pads of the package. Such a configuration can reduce the current density in the die, increase the maximum current capability, and reduce power loss. Such a configuration can also allow heat to be drawn from the die through two or more sides of the package. In addition, one or more embodiments of the packages described herein can allow components and integrated circuit packages to be stacked on top of each other to form a three-dimensional high-voltage stacked structure.

[0026] The core layer can include any suitable material or materials. In one or more embodiments, the core layer can be a glass core layer. Such a glass core layer can be manufactured using any suitable technology or technologies. Compared to other types of materials (e.g., silicon) that can be used for the core layer, the glass core layer can provide improved dielectric properties. Such improved dielectric properties can allow one or more conductive layers to be disposed directly on the core layer without first disposing a dielectric layer between the core layer and the patterned conductive layer. In addition, one or more embodiments of the glass core layer can exhibit improved warping resistance.

[0027] Figure 1-Figure 21 are various views of one embodiment of an integrated circuit package 10. The integrated circuit package 10 includes a substrate 12 having a core layer 14 disposed between a first dielectric layer 16 and a second dielectric layer 18. One or more die 20 are each disposed in a cavity 22 of the core layer 14. Furthermore, an encapsulation 24 is disposed in each cavity 22 between the corresponding die 20 and the sidewalls 26 of the cavity. The package 10 also includes a first patterned conductive layer 28 disposed within the first dielectric layer 16. One or more devices 30 are disposed on an outer surface 32 of the first dielectric layer 16 such that the first patterned conductive layer 28 is between the one or more devices and the core layer 14. The one or more devices 30 are electrically connected to the one or more die 20. The package 10 also includes a second patterned conductive layer 34 disposed within the second dielectric layer 18. In one or more embodiments, one or more conductive pads 36 may be disposed on or in an outer surface 38 of the second dielectric layer 18 such that the second patterned conductive layer 34 is between the conductive pads and the core layer 14. Furthermore, in one or more embodiments, one or more of the conductive pads 36 may be electrically connected to one or more dies 20 using any suitable technique or techniques as further described herein.

[0028] The substrate 12 may include any suitable substrate. In addition, the substrate 12 may include any suitable material or materials, such as metals, polymers, or inorganic materials, and combinations thereof. In one or more embodiments, the substrate 12 may be a non-conductive or dielectric substrate that provides electrical isolation between various conductors, vias, dies, and the like. For convenience and without intent to be limiting, Figure 1 Substrate 12 is depicted as a unitary (i.e., single) layer. In one or more embodiments, substrate 12 can include any suitable number of layers, wherein the layers can be formed of the same or different materials. Furthermore, substrate 12 can have any suitable dimensions. For example, substrate 12 can have any suitable thickness measured in a direction normal to outer surface 32 of first dielectric layer 16. Furthermore, substrate 12 can be formed using any suitable technique or techniques.

[0029] In one or more embodiments, the substrate 12 includes a core layer 14 disposed between a first dielectric layer 16 and a second dielectric layer 18. The core layer 14 can include any suitable material or materials, for example, the same materials described herein with respect to the substrate 12. In one or more embodiments, the core layer 14 can include one or more of glass, quartz, sapphire, FR4 (flame retardant 4), ceramic, and the like. In one or more embodiments, the core layer 14 provides the entire substrate 12. Furthermore, in one or more embodiments, one or more additional layers can be disposed on the core layer 14 to form the substrate 12. For example, in one or more embodiments, one or more patterned conductive layers (not shown) can be disposed on one or both surfaces of the core layer 14 to provide the substrate 12.

[0030] The core layer 14 can include one or more cavities 22. The cavities 22 can be formed in the core layer 14 using any suitable technique or techniques. In one or more embodiments, the one or more cavities 22 can extend completely through the core layer 14. Furthermore, in one or more embodiments, the depth or height of the one or more cavities 22, measured in a direction normal to the outer surface 32 of the first dielectric layer 16, can be less than the thickness of the core layer, such that such cavities do not extend through the core layer 14. Each cavity 22 can take any suitable shape in a plane parallel to the outer surface 32 of the first dielectric layer 16, such as an elliptical, rectangular, polygonal, etc.

[0031] Each cavity 22 includes one or more sidewalls 24. Each sidewall 24 may be in a plane normal to the outer surface 32 of the first dielectric layer 16 (i.e., in a plane perpendicular to the outer surface 32 of the first dielectric layer 16). Figure 1 The sidewalls 24 may take any suitable shape (in the plane of the first dielectric layer 16). In one or more embodiments, the sidewalls 24 may have a flat surface that is orthogonal to the outer surface 32 of the first dielectric layer 16. In one or more embodiments, one or more sidewalls 24 may be tapered such that the cross-sectional area of the cavity 22 varies in a direction orthogonal to the outer surface 32 of the first dielectric layer 16. Additionally, in one or more embodiments, one or more sidewalls 24 may include one or more curved portions.

[0032] The cavity 22 can have any suitable dimensions. In one or more embodiments, at least one cavity 22 can have a width in a direction parallel to the outer surface 32 of the first dielectric layer 16 that is greater than the width of the die 20 disposed in the cavity. In one or more embodiments, the width of the cavity 22 can be equal to the width of the die 20 disposed therein, such that the die contacts one or more portions of the sidewalls 24 of the cavity.

[0033] First dielectric layer 16 and second dielectric layer 18 may comprise any suitable material or materials, such as polyimide, bismaleimide triazine, polybenzoxazole, photoresist, glass, quartz, sapphire, and the like. In one or more embodiments, at least one of first dielectric layer 16 and second dielectric layer 18 comprises an electrically insulating material. Furthermore, first dielectric layer 16 and second dielectric layer 18 may have any suitable dimensions. In one or more embodiments, at least one of first dielectric layer 16 and second dielectric layer 18 may comprise two or more layers or sublayers, and each sublayer may comprise the same or different materials. For example, first dielectric layer 16 comprises first sublayer 48 and second sublayer 50. Furthermore, second dielectric layer 18 comprises first sublayer 52 and second sublayer 54. First sublayer 48 and second sublayer 50 of first dielectric layer 16 may be deposited together using any suitable technique or techniques. In one or more embodiments, first sublayer 48 and second sublayer 50 may be laminated together to form first dielectric layer 16. Similarly, the first sublayer 52 and the second sublayer 54 of the second dielectric layer 18 may be disposed together using any suitable technique or techniques. In one or more embodiments, the first sublayer 52 and the second sublayer 54 may be laminated together to form the second dielectric layer 18. Although depicted as each including two sublayers, the first dielectric layer 16 and the second dielectric layer 18 may each include any suitable number of sublayers.

[0034] Any suitable technique or techniques may be used to form first dielectric layer 16 and second dielectric layer 18. In one or more embodiments, at least one of first dielectric layer 16 and second dielectric layer 18 may be formed on substrate 12. In one or more embodiments, at least one of first dielectric layer 16 and second dielectric layer 18 may be formed separately and then connected to substrate 12, for example, by laminating one or both of the first dielectric layer and second dielectric layer to the substrate.

[0035] As described herein, the integrated circuit package 10 may include one or more dies 20. Furthermore, the package 10 may include any suitable number of dies 20 arranged in any suitable arrangement or array. In one or more embodiments, the one or more dies 20 may be disposed in a cavity 22 of the core layer 14. Although depicted as including one die 20 per cavity 22, in one or more embodiments, two or more dies may be disposed within a single cavity. In one or more embodiments, the one or more dies 20 may be disposed in the cavity 22 such that the die is completely within the cavity. For example, each die 20 may have a die height measured in a direction normal to the outer surface 32 of the first dielectric layer 16 that is no greater than a height of the cavity 22 in which the die is disposed. In one or more embodiments, the die height of one or more dies 20 may be greater than the height of the cavity 22 in which the corresponding die is disposed.

[0036] The package 10 may include one or more dies 20 of any suitable type. In one or more embodiments, the package 10 may include one or more dies 20 that may be used in, for example, an implantable medical device (e.g., see Figure 4 As used herein, the term "high voltage die" refers to an electronic component or device that can operate at a potential greater than about 50V between any two electrical terminals or contacts of the component. Such a high voltage component can further operate at a DC voltage greater than about 100V, and can even further operate at a DC voltage greater than about 500V, 1000V, 1600V, 3000V or even higher, perhaps tens of times thousands of volts or more. In one or more embodiments, the package 10 may include one or more low voltage dies. In one or more embodiments, the one or more dies 20 may include one or more field effect transistors (FETs), metal oxide semiconductors (MOS), MOSFETs, insulated gate bipolar junction transistors (IGBTs), thyristors, bipolar transistors, diodes, MOS controlled thyristors, resistors, capacitors, etc. Although Figure 1 The dies 20 are illustrated as being on the same plane, but in one or more embodiments, the dies may be arranged in a stacked relationship.

[0037] In one or more embodiments, one or more dies 20 may include a field termination structure 40 ( Figure 2 In one or more embodiments, the main surface 42 faces the field plate 44 ( Figure 1 ), the field plate may be electrically connected to at least one of the first patterned conductive layer 28, the second patterned conductive layer 34, and a conductive pad 36 disposed on or in an outer surface 38 of the second dielectric layer 18 as further described herein.

[0038] The field termination structure 40 may include any suitable conductor or conductors fabricated using any suitable material or materials. Furthermore, the field termination structure 40 may include any suitable structure adapted to at least partially control the propagation of the electric field within the die 20 to mitigate or prevent avalanche breakdown. For example, in one or more embodiments, the field termination structure 40 may include a mesa-type structure. Such breakdown may occur when the critical electric field of the die material (e.g., silicon) is exceeded. In one or more embodiments, the field termination structure 40 may include one or more floating P-type rings in an N-type substrate. The P-type rings may occupy a volume at the outer surface 42 of the die 20 and may cause the depletion region in the N-type material of the die to extend further on the die surface where the electric field may be greatest. The volume occupied by these P-type rings may force the depletion region in the N-type substrate of the die 20 to extend to a larger area and distance at the outer surface 42 and within the die (because charge balance needs to be maintained for the main reverse biased PN junction). These P-type rings may be spaced in a manner to provide a relatively consistent electric field across the surface 42 and within the die 20. As Figure 2 As shown, field termination structure 40 may include one or more rings that may be disposed on outer surface 42 of die 20 in any suitable shape or pattern.

[0039] The die 20 may be electrically connected to at least one of the first patterned conductive layer 28, the second patterned conductive layer 34, the third patterned conductive layer 46, and the one or more conductive pads 36 using any suitable technique or techniques. In one or more embodiments, one or more vias 60 may be provided through the first sub-layer 48 of the first dielectric layer 16 to electrically connect the one or more top contacts 21 of the die 20 to the first patterned conductive layer 28. Additionally, in one or more embodiments, one or more vias 66 may be provided through the first sub-layer 52 of the second dielectric layer 18 to electrically connect the one or more bottom contacts 23 of the die 20 to the second patterned conductive layer 34.

[0040] Also disposed within the one or more cavities 22 of the core layer 14 is an encapsulant 24. The encapsulant 24 can be disposed in any suitable portion or portions of the cavity 22. In one or more embodiments, the encapsulant 24 is disposed in the cavity 22, between the die 20 and one or more portions of the sidewalls 26 of the cavity. The encapsulant 24 can include any suitable material or materials, such as UV-curable or thermally curable encapsulant materials, such as BCB, polybenzobisoxazole, epoxy resin, photoresist, and epoxy resin, such as SINR3170 silicone resin manufactured by Shin-Etsu Chemical Co., Ltd., R4507 EMC (epoxy mold compound) manufactured by Nagase, and G730 EMC manufactured by Sumitomo, etc. The encapsulant 24 can be disposed within the cavity using any suitable technique or techniques. In one or more embodiments, a portion of the first dielectric layer 16 can form the encapsulant 24, as further described herein. Encapsulant 24 may be adapted to at least partially seal die 20 within cavity 22 such that the die remains in the cavity.

[0041] As mentioned herein, the encapsulant 24 can be disposed in the cavity 22 between the die 20 and the sidewalls 26 of the cavity using any suitable technique or techniques. In one or more embodiments, the encapsulant 24 can include a portion of the first dielectric layer 16. For example, the die 20 can be disposed within the cavity 22, and the first dielectric layer 16 can be disposed on the core layer 14 (or substrate 12) by, for example, laminating the first dielectric layer to the core layer. During the lamination process, a portion of the first dielectric layer 16 can flow into the cavity 22 between the die 20 and the sidewalls 26 of the cavity such that the portion at least partially encapsulates the die within the cavity. In one or more embodiments in which the first dielectric layer 16 includes sublayers, one or more portions of the first sublayer 48 disposed on the core layer (or substrate 12) can flow into the cavity 22 to form the encapsulant 24.

[0042] Disposed within the first dielectric layer 16 is a first patterned conductive layer 28. The first dielectric layer 16 may include any suitable number of patterned conductive layers disposed on or within the first dielectric layer. In one or more embodiments, the first dielectric layer 16 may include a third patterned conductive layer 46 disposed on the outer surface 32 of the first dielectric layer 16. Furthermore, the first patterned conductive layer 28 and the third patterned conductive layer 46 may include one or more conductive layers of any suitable type, such as one or more redistribution layers. The first patterned conductive layer 28 and the third patterned conductive layer 46 may be electrically connected to additional patterned conductive layers, devices, conductive pads, etc. using one or more conductive vias 47 disposed within the first dielectric layer 16. The first patterned conductive layer 28 and the third patterned conductive layer 46 may include any suitable conductive material or materials and may be formed using any suitable technique or techniques further described herein. Furthermore, the first patterned conductive layer 28 and the third patterned conductive layer 46 may be disposed within or on the first dielectric layer 16 using any suitable technique or techniques.

[0043] The first patterned conductive layer 28 may be disposed at any suitable location within the first dielectric layer 16. In one or more embodiments, the first patterned conductive layer 28 may be disposed between the first sub-layer 48 and the second sub-layer 50 of the first dielectric layer 16.

[0044] Additionally, a second patterned conductive layer 34 is disposed within the second dielectric layer 18. The second patterned conductive layer 34 can include any suitable patterned conductive layer, for example, the same patterned conductive layer described with respect to the first patterned conductive layer 28. The second dielectric layer 18 can include any suitable number of patterned conductive layers disposed within or on the second dielectric layer. In one or more embodiments, the second patterned conductive layer 34 can be disposed between the first sublayer 52 and the second sublayer 54 of the second dielectric layer 18. The second patterned conductive layer 34 can be electrically connected to at least one of the dies 20 via vias 66, to the first patterned conductive layer 28 via vias 47, to the third patterned conductive layer 46 via vias 47, and to one or more conductive pads 36.

[0045] One or more devices 30 are disposed on an outer surface 32 of the first dielectric layer 16. The integrated circuit package 10 may include any suitable number of devices 30. Furthermore, the integrated circuit package 10 may include any suitable device, such as at least one of a capacitor, a resistor, a passive integrated capacitor system, a logic circuit, an analog circuit, etc. The one or more devices 30 may be disposed on the outer surface 32 of the first dielectric layer 16 such that the first patterned conductive layer 28 is located between the device and the core layer 14.

[0046] Any suitable technique or techniques may be used to electrically connect one or more of devices 30 to one or more of dies 20. For example, in Figure 1 In the illustrated embodiment, the first device 30a and the second device 30b are electrically connected to the die 20 via the third patterned conductive layer 46 and a via 60 disposed through the first dielectric layer 16. The devices 30a, 30b can be electrically connected to the third patterned conductive layer 46 using any suitable technique or techniques. In one or more embodiments, one or more device contacts 62 of the device 30 can be electrically connected to the third patterned conductive layer 46. The device contacts 62 can be disposed in any suitable position relative to the third patterned conductive layer 46. For example, in one or more embodiments, the device contacts 62 can be disposed between the device 30 and the third patterned conductive layer 46. In one or more embodiments, the one or more device contacts 62 can be disposed on a top surface 64 of the device 30 and wire-bonded to the third patterned conductive layer 46 (not shown).

[0047] One or more conductive pads 36 are disposed on the outer surface 54 of the second dielectric layer 18. The conductive pads 36 can be disposed at any suitable location on or in the second dielectric layer 18. Furthermore, the integrated circuit package 10 can include any suitable number of conductive pads 36. The conductive pads 36 can include any suitable type of electrical connector, such as solder balls, solder, bumps, copper pillars, copper pillars with solder caps, conductive polymers, compliant interconnects, and the like. In one or more embodiments, the conductive pads 36 are disposed such that the second patterned conductive layer 34 is located between the conductive pads and the core layer 14. Furthermore, in one or more embodiments, the one or more conductive pads 36 are electrically connected to the one or more dies 30. For example, as Figure 1 As shown, the conductive pad 36 is electrically connected to the die 20 via a via 66 extending from the second patterned conductive layer 34 to the die. In one or more embodiments, the one or more conductive pads 36 may be electrically connected to at least one of the second patterned conductive layer 34, the one or more dies 20, the first patterned conductive layer 28, the third patterned conductive layer 46, and the one or more devices 30. Furthermore, in one or more embodiments, the one or more conductive pads 36 may be electrically connected to the one or more field plates 44 using any suitable technique or techniques.

[0048] The field plate 44 may be disposed at any suitable location on or within the integrated circuit package 10. Figure 1In the embodiment shown, field plates 44 are disposed within first dielectric layer 16 such that one or more of the field plates are spaced apart from one or more of dies 20. Field plates 44 may comprise a portion of first patterned conductive layer 28 or be separate from the first patterned conductive layer. In one or more embodiments, one or more of field plates 44 may be formed simultaneously with first patterned conductive layer 28. Field plates 44 may comprise any suitable field plates, such as those described in U.S. Patent No. 8,664,756 to Boone et al., entitled “RECONSTITUTED WAFERPACKAGE WITH HIGH VOLTAGE DISCRETE ACTIVE DICE AND INTEGRATED FIELD PLATE FOR HIGH TEMPERATURE LEAKAGE CURRENT STABILITY.”

[0049] In one or more embodiments, field plate 44 is spaced from die 20 by an optimal spacing gap that is large enough to prevent dielectric breakdown of the insulator, but close enough to establish a sufficiently strong field to control the system. The optimal spacing distance can be determined based on the characteristics of the dielectric material of first dielectric layer 16 and the testing and / or operating conditions of die 20. In one or more embodiments, the characteristics considered may include the operating conditions of package 10, including conditions such as operating voltage and temperature with respect to the breakdown characteristics of the dielectric material of first dielectric layer 16. In one or more embodiments, the distance of the spacing gap between field plate 44 and die 20 may alternatively or additionally be determined based on the dielectric strength of the material used to form first dielectric layer 16. In one or more embodiments, depending on the operating and / or testing parameters of a given component, the spacing gap may be at least approximately 25 μm to no greater than approximately 300 μm. The controlling factor in the design and selection of the spacing gap is that field plate 44 will be effective up to the maximum breakdown strength of die 20 to prevent field effect leakage at room temperature and above. For example, a 1000 V MOSFET designed to operate at 80% of its rated voltage at 125° C. may have a field plate 44 spaced apart from the field termination structure 40 by a distance in the range of 50 to 200 μm. As another example, a spacing of about 50 μm to about 75 μm may prevent dielectric breakdown and ensure current stability for a die operating at 80% of its rated 1600 V and temperatures up to 150° C. during high-temperature leakage current testing. As a result, for a given dielectric material, the higher the voltage rating of the component or die, the larger the spacing gap between the die 20 and the field plate 44 may be required to prevent dielectric breakdown and ensure stability of the leakage current and eliminate or substantially prevent field effect leakage at room temperature. Furthermore, positioning the field plate 44 within the first dielectric layer 16 may allow the dimensions of the individual conductive pads 36 to be determined independently of the spacing requirements of the field plate 44.

[0050] In one or more embodiments, at least a portion of the field plate 44 overlaps the field termination structure 40 of the die 20 in a direction normal to the outer surface 32 of the first dielectric layer 16. In one or more embodiments, the field plate 44 substantially overlaps the field termination structure 40, i.e., a majority of the field plate's surface area overlaps a majority of the field termination structure's surface area. As an illustration of an embodiment, the percentage comprising a majority can be 51%, 75%, 85%, 98%, or any variation within these percentages. In one or more embodiments, the surface area of the field plate 44 can extend beyond the surface area of the field termination structure 40. In one or more embodiments, the field plate 44 can be sized to be substantially coextensive with the surface area of the front side of the die 20. In one or more embodiments, the size of the field plate 44 can be determined based on the planar surface area of the field termination structure 40. Thus, the field plate 44 has a surface area that is at least the size of the surface area of the field termination structure 40. In one or more embodiments, if there are multiple concentric field termination structures 40, the field plates 44 can be formed in a corresponding plurality of separate field plates, each having the surface area of its respective field termination structure, or can be formed as a single field plate having a surface area that approximates the surface area of the entire annular ring including the concentric terminal rings. In embodiments where the surface area of the field plates 44 is sized based on the size of the field termination structures 40, the surface area of the field plates can be coextensive with the surface area of the field termination structures and / or can extend beyond the surface area of the field termination structures. Additionally, the field plates 44 are aligned with the field termination structures 40, positioned directly above the field termination structures, or generally in the same vertical plane as the field termination structures.

[0051] In one or more embodiments, field plate 44 can be adapted to receive a bias voltage to generate an electric field between die 20 and the field plate. The bias voltage can be at least as large as the bias voltage applied to die 20, with the voltages having the same polarity. For example, for a package 10 having an n-type substrate, a positive bias voltage is applied to field plate 44, and the positive bias voltage can be at least as large as the maximum positive bias voltage applied to die 20. Similarly, for a package 10 having a p-type substrate, a negative bias voltage is applied to field plate 44, and the negative bias voltage can be at least as large as the maximum negative bias voltage applied to die 20. If the component has unidirectional blocking properties, such as a MOSFET or diode, field plate 44 can be directly connected to a terminal of die 20. In one or more embodiments where die 20 has a bidirectional blocking property, such as a thyristor, the voltage on field plate 44 can be switched. In either case, the field plate 44 is biased with a polarity that promotes surface accumulation of majority carriers at the lightly doped surface region at the field stop structure 40 .

[0052] The field plate 44 can be electrically connected to one or more second conductive pads 36a disposed on the outer surface 38 of the second dielectric layer 18. The field plate 44 can be connected to the second conductive pads 36a using any suitable technique or techniques. In one or more embodiments, the field plate 44 can be electrically connected to the second conductive pads 36a via a via 47 extending between the first dielectric layer 16 and the second dielectric layer 18.

[0053] As described herein, one or more embodiments of an integrated circuit package may include a glass core layer. For example, Figure 5 is a schematic cross-sectional view of another embodiment of an integrated circuit package 300. Figure 1-Figure 2 All design considerations and possibilities of the integrated circuit package 10 also apply to Figure 5 Integrated circuit package 300.

[0054] Package 300 includes a substrate 302 including a glass core layer 304 including a first major surface 306, a second major surface 308, and a cavity 310 disposed between the first and second major surfaces of the glass core layer. Package 300 further includes a die 312 disposed in the cavity 310 of the glass core layer 304, and an encapsulant 314 disposed in the cavity between the die and a sidewall 316 of the cavity. A first patterned conductive layer 318 may be disposed adjacent to the first major surface 306 of the glass core layer 304. As used herein, the term "adjacent to the first major surface" refers to an element or component being disposed closer to the first major surface 306 of the glass core layer 304 than to the second major surface 308 of the glass core layer. Package 300 further includes a second patterned conductive layer 320 disposed adjacent to the second major surface 308 of the glass core layer 304. As used herein, the term "adjacent to the second major surface" refers to an element or component being disposed closer to the second major surface 308 of the glass core layer 304 than to the first major surface 306 of the glass core layer. Package 300 also includes one or more conductive vias 322 disposed in the glass core layer 304, extending between the first major surface 306 and the second major surface 308 of the glass core layer. In one or more embodiments, the conductive vias 322 can be electrically connected to at least one of the first patterned conductive layer 318 and the second patterned conductive layer 320. Furthermore, the die 312 is electrically connected to at least one of the first patterned conductive layer 318 and the second patterned conductive layer 320 using any suitable technique or techniques. In one or more embodiments, the die 312 is electrically connected to each of the first patterned conductive layer 318 and the second patterned conductive layer 320.

[0055] In one or more embodiments, the package 300 may include one or more devices (not shown) disposed on at least one of the first patterned conductive layer 318 and the second patterned conductive layer 320. Such one or more devices may include any suitable devices, such as Figure 1 Device 30 of package 10. One or more devices may be electrically connected to at least one of first patterned conductive layer 318 and second patterned conductive layer 320 using any suitable technique or techniques.

[0056] Disposed adjacent the first major surface 306 of the glass core layer 304 is a first patterned conductive layer 318. In one or more embodiments, the first patterned conductive layer 318 may be disposed directly on the first major surface 306 of the glass core layer 304. In one or more embodiments, a dielectric layer 324 may be disposed between the first patterned conductive layer 318 and the first major surface 306 of the glass core layer 304. The dielectric layer 324 may include any suitable dielectric layer or layers, e.g., Figure 1 The first dielectric layer 16 of the package 10. The dielectric layer 324 can be disposed on the first major surface 306 of the glass core layer 304 using any suitable technique or techniques, for example, the dielectric layer can be laminated to the glass core layer.

[0057] Additionally, the second patterned conductive layer 320 may be disposed directly on the second major surface 318 of the glass core layer 304. In one or more embodiments, a second dielectric layer (e.g., the second dielectric layer 18 of the package 10) may be disposed between the second patterned conductive layer 320 and the second major surface 308 of the glass core layer 304. The second dielectric layer 320 may be disposed on the second major surface 308 of the glass core layer 304 using any suitable technique or techniques, for example, the second dielectric layer may be laminated to the glass core layer.

[0058] Disposed between the die 312 and the sidewalls 316 of the cavity 310 is an encapsulant 314. The encapsulant 314 may comprise any suitable material or materials suitable for encapsulating a die, such as those described herein. Figure 1 The encapsulant 314 may be the same material as described for the encapsulant 24 of the package 10. In one or more embodiments, the encapsulant 314 may include one or more portions of the dielectric layer 324 as described herein with respect to the first dielectric layer 16 of the package 10.

[0059] The die 312 disposed within the cavity 310 of the glass core layer 304 can include any suitable device or circuit, such as the same device or circuit described herein with respect to the die 20 of the package 10. In one or more embodiments, the die 312 can include high voltage electrical components. In one or more embodiments, the die 312 can include low voltage components.

[0060] Any suitable technique or techniques may be used to form Figures 1 to 2 The integrated circuit package 10 and Figure 5 The integrated circuit package 300. For example, Figure 3A-Figure 3I are various schematic cross-sectional views of one embodiment of a method 100 of forming an integrated circuit package 10. Although reference is made to Figures 1 to 2 While the method 100 is described with respect to an integrated circuit package 10, the method 100 may be used to form any suitable integrated circuit package. Furthermore, the method 100 is illustrated as including one die 20; however, the method may be used to form an integrated circuit package including two or more dies. In one or more embodiments, the method 100 may be used to simultaneously form two or more integrated circuit packages 10 using one or more wafers.

[0061] exist Figure 3A In one or more embodiments, a core layer 14 is provided. In one or more embodiments, one or more additional layers may be disposed on one or both major surfaces of the core layer 14 to provide the substrate 12. Figure 3B As shown in , one or more cavities 22 can be formed in the core layer 14 using any suitable technique or techniques, such as drilling, laser drilling, chemical etching, plasma etching, stamping, etc. In addition, one or more vias 47 can be formed using any suitable technique or techniques. For example, in one or more embodiments, an opening can be formed using any suitable technique or techniques, and a conductive material can be disposed within the opening to form the conductive via 47. In one or more embodiments, the via 47 can be formed after the patterned conductive layers 28, 34, 46 (if included) have been formed.

[0062] exist Figure 3C middle, Carrier layer 102 The carrier layer 102 may be disposed on the bottom surface 104 of the core layer 14 and above the cavity 22. The carrier layer 102 may include any suitable carrier or carrier. In one or more embodiments, a suitable release layer (not shown) may be disposed between the carrier layer 102 and the bottom surface 104 of the core layer 14. In addition, an optional glass layer (not shown) may be disposed on the carrier layer 102 such that the carrier layer is between the optional glass layer and the core layer 14. This optional glass layer may provide additional support for the core layer 14 during processing of the integrated circuit package 10.

[0063] The die 20 may be provided in a manner suitable for the application of the present invention using any suitable technique or techniques. Figure 3D In embodiments where cavity 22 extends completely through core layer 14, die 20 may be placed directly on carrier layer 102 or a release layer disposed on the carrier layer.

[0064] exist Figure 3EIn the embodiment, the first dielectric layer 16 can be disposed on the core layer 14 and above the cavity 22, such that the core layer is between the first dielectric layer 16 and the carrier layer 102 using any suitable technique or techniques. In embodiments where the first dielectric layer 16 includes sub-layers, the first sub-layer 48 can be as follows: Figure 3E 20 is shown disposed on the core layer 16. In one or more embodiments, the first sublayer 48 of the first dielectric layer 16 can be disposed on the core layer 14 such that a portion or portions of the first sublayer flow into the cavity to provide the encapsulation 24 between the sidewalls 26 of the cavity and the die 20. In one or more embodiments, the first dielectric layer 16 (or the first sublayer 48 of the first dielectric layer) can be laminated to the core layer 14.

[0065] like Figure 3F As shown, the carrier layer 102 can be removed using any suitable technique or techniques. Furthermore, the second dielectric layer 18 can be disposed on the core layer 14 using any suitable technique or techniques. For example, the second dielectric layer or a sublayer of the second dielectric layer can be laminated to the core layer. In embodiments where the second dielectric layer 18 includes two or more sublayers, the first sublayer 52 can be disposed on the core layer 14.

[0066] exist Figure 3G In one embodiment, the first patterned conductive layer 28 can be disposed on or within the first sub-layer 48 of the first dielectric layer 16 using any suitable technique or techniques. For example, in one or more embodiments, a continuous conductive layer can be disposed on the first sub-layer 48, and the continuous conductive layer can then be patterned using any suitable technique or techniques (e.g., photoresist application, photolithography, electroless plating, electroplating, chemical etching, dry etching, physical vapor deposition, etc.). In one or more embodiments, the field plate 44 can be disposed within the first dielectric layer 16 using any suitable technique or techniques such that the field plate is spaced apart from the die 20. In one or more embodiments, the first patterned conductive layer 28 can include the field plate 44.

[0067] Additionally, second patterned conductive layer 34 can be disposed on first sublayer 52 of second dielectric layer 18 using any suitable technique or techniques, such as the same technique or techniques used to form first patterned conductive layer 28. Prior to forming first patterned conductive layer 28 and second patterned conductive layer 34, one or more vias 60 can be disposed through first sublayer 48 to electrically connect first patterned conductive layer 28 to die 20. Additionally, one or more vias 66 can be formed through first sublayer 52 of second dielectric layer 18 to electrically connect second patterned conductive layer 34 to die 20. Vias 60, 66 can be formed using any suitable technique or techniques. Additionally, via 47 can extend through first sublayer 48 of first dielectric layer 16 and be electrically connected to first patterned conductive layer 28 using any suitable technique or techniques. Via 47 can also extend through first sublayer 52 of second dielectric layer 18 using any suitable technique or techniques.

[0068] exist Figure 3H , the second sublayer 50 of the first dielectric layer 16 can be disposed over the first patterned conductive layer 28 and the first sublayer 48 using any suitable technique or techniques. In one or more embodiments, the second sublayer 50 can be disposed over the entire first patterned conductive layer 28. The third patterned conductive layer 46 can be disposed over the second sublayer 50 using any suitable technique or techniques, such as the same technique used to form the first patterned conductive layer 28. Additionally, a via 60 can be extended through the first dielectric layer 16 between the outer surface 32 of the first dielectric layer and the die 20 using any suitable technique or techniques, such that the die is electrically connected to the third patterned conductive layer 46. In one or more embodiments, a via 47 can be extended through the second sublayer 40 of the first dielectric layer 16 such that the third patterned conductive layer 46 is electrically connected to the first patterned conductive layer 28 and the second patterned conductive layer 34.

[0069] In addition, if Figure 3H As shown, the second sub-layer 54 of the second dielectric layer 18 can be disposed on the first sub-layer 52 of the second dielectric layer using any suitable technique or techniques. The second sub-layer 54 can be disposed over one or more portions of the second patterned conductive layer 34 and the first sub-layer 52 of the second dielectric layer 18. In one or more embodiments, the integrated circuit package 10 does not include the second sub-layer 54.

[0070] exist Figure 3I In the embodiment, one or more conductive pads 36 may be disposed on or in the second dielectric layer 18 using any suitable technique or techniques. In one or more embodiments, the one or more conductive pads 36 may be electrically connected to at least one of the first patterned conductive layer 28, the die 20, the second patterned conductive layer 34, the third patterned conductive layer 46, and the one or more devices 30 ( Figure 1 Although shown as being at least partially disposed within the second sub-layer 54, the conductive pads 36 may be disposed on the outer surface 38 of the second sub-layer.

[0071] The various embodiments of the integrated circuit packages described herein can be used in any suitable electronic system. For example, one or more embodiments of the integrated circuit packages described herein can be used in an IMD, an ICD, an IPG, an insertable cardiac monitor, an implantable diagnostic monitor, a deep brain stimulator, an implantable neurostimulator, an injectable neurostimulator, an implantable ventricular assist device, and the like. Figure 4 FIG2 is a schematic plan view of an embodiment of an implantable medical device (IMD) 200. IMD 200 includes a housing 202 and electronic components 204 disposed within the housing. Electronic components 204 may include any suitable electronic device, such as at least one of a capacitor, a resistor, a passive integrated capacitor system, a logic circuit, an analog circuit, a crystal, an accelerometer, an RF circuit, an antenna, a transformer, a connector, and the like. In one or more embodiments, electronic components 204 include an integrated circuit package 206. Package 206 may include any suitable integrated circuit package, such as Figures 1 to 2 The integrated circuit package 10 and Figure 5 2. The integrated circuit package 206 can be electrically connected to the other electronic components 204 using any suitable technique or techniques. A power source 208 is also disposed within the IMD housing 202 and is electrically connected to the electronic components using any suitable technique or techniques. The power source can include any suitable power source or combination of power sources, such as one or more batteries, capacitors, inductively coupled energy devices, photovoltaic devices, beta-voltaic devices, alpha-voltaic devices, and thermoelectric devices.

[0072] Example methods according to the techniques of this disclosure include the following.

[0073] Example 1: A method for forming an integrated circuit package, comprising: setting a cavity in a core layer; setting a carrier layer on the core layer and above the cavity; setting a tube die in the cavity and on the carrier layer; setting a first dielectric layer on the core layer and above the cavity so that the core layer is located between the first dielectric layer and the carrier layer, wherein the first dielectric layer includes a first patterned conductive layer set between a first sublayer and a second sublayer of the first dielectric layer, wherein the first patterned conductive layer includes a field plate spaced apart from the tube die; removing the carrier layer from the core layer; and setting a second dielectric layer on the core layer so that the core layer is located between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer includes a second patterned conductive layer set between the first sublayer and the second sublayer of the second dielectric layer.

[0074] Example 2: The method of Example 1, wherein setting the first dielectric layer on the core layer and above the cavity includes: setting the first sublayer on the core layer; setting the first patterned conductive layer on the first sublayer; and setting the second sublayer on the first patterned conductive layer and the first sublayer.

[0075] Example 3: The method of Example 2, wherein disposing the first dielectric layer on the core layer over the cavity further comprises disposing at least a portion of the first sublayer in the cavity between the die and a sidewall of the cavity.

[0076] Example 4: The method according to any one of Examples 1 to 3 further includes: setting a through hole passing through the first dielectric layer between the outer surface of the first dielectric layer and the tube core, wherein the tube core is electrically connected to the through hole; and setting a device on the outer surface of the first dielectric layer so that the device is electrically connected to the tube core through the through hole.

[0077] Example 5: The method of Example 4 further includes: disposing a third patterned conductive layer on an outer surface of the first dielectric layer, wherein the device and the through hole are electrically connected to the third patterned conductive layer.

[0078] Example 6: The method according to any one of Examples 1 to 5 further includes: providing a second through-hole passing through the second dielectric layer between the outer surface of the second dielectric layer and the tube core, wherein the tube core is electrically connected to the second through-hole; and providing a conductive pad on the outer surface of the second dielectric layer, so that the conductive pad is electrically connected to the tube core through the second through-hole.

[0079] Example 7: The method of any one of Examples 1 to 6, wherein disposing the second dielectric layer on the core layer and above the cavity comprises: disposing the first sublayer on the core layer; disposing the second patterned conductive layer on the first sublayer; and disposing the second sublayer on the second patterned conductive layer and the first sublayer.

[0080] All references and publications cited herein are expressly incorporated into the present disclosure in their entirety by reference, unless they may directly contradict the present disclosure. The exemplary embodiments of the present disclosure have been discussed, and reference has been made to possible variations within the scope of the present disclosure. These and other variations and modifications in the present disclosure will be apparent to those skilled in the art without departing from the scope of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments set forth herein. Therefore, the present disclosure is limited only by the claims provided below.

Claims

1. An integrated circuit package, comprising: a substrate comprising a core layer disposed between a first dielectric layer and a second dielectric layer; a tube core, the tube core being disposed in the cavity of the core layer; an encapsulation body disposed in the cavity between the die and a sidewall of the cavity; a first patterned conductive layer disposed within the first dielectric layer; a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, wherein the device is electrically connected to the die; a second patterned conductive layer disposed within the second dielectric layer; a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is located between the conductive pad and the core layer, wherein the conductive pad is electrically connected to the die; and A field plate is disposed within the first dielectric layer, wherein the field plate is spaced apart from the die and adapted to receive a bias voltage to generate an electric field between the die and the field plate. 2 . The package of claim 1 , wherein the second dielectric layer is disposed on and in contact with the core layer.

3. The package according to claim 1, wherein The field plate is electrically connected to a second conductive pad disposed on an outer surface of the second dielectric layer.

4. The package according to claim 1, wherein The die further includes a field termination structure disposed on an outer surface of the die facing the field plate, wherein at least a portion of the field plate overlaps the field termination structure in a direction normal to the outer surface of the first dielectric layer.

5. The package according to any one of claims 1 to 4, wherein The first dielectric layer and the second dielectric layer are laminated to the substrate.

6. The package according to any one of claims 1 to 4, wherein The encapsulant includes a portion of the first dielectric layer.

7. The package according to any one of claims 1 to 4, wherein The die includes high voltage electrical components.

8. The package according to claim 7, wherein: The high voltage electrical components are operable at a potential of at least 500 volts.

9. The package according to any one of claims 1 to 4, wherein The die includes at least one of a field effect transistor, a metal oxide semiconductor field effect transistor, an insulated gate bipolar junction transistor, a thyristor, a bipolar transistor, a diode, a MOS controlled thyristor, a resistor, and a capacitor.

10. The package according to any one of claims 1 to 4, wherein Each of the first dielectric layer and the second dielectric layer includes two or more sub-layers laminated together.

11. The package according to claim 10, wherein: The first patterned conductive layer is disposed between two sub-layers of the first dielectric layer.

12. The package according to claim 10, wherein The second patterned conductive layer is disposed between two sub-layers of the second dielectric layer.

13. The package according to any one of claims 1 to 4, wherein The integrated circuit is incorporated into an implantable medical device.

14. A method of forming an integrated circuit package, comprising: providing a cavity in the core layer; disposing a carrier layer on the core layer over the cavity; disposing a die within the cavity and on the carrier layer; disposing a first dielectric layer on the core layer over the cavity such that the core layer is between the first dielectric layer and the carrier layer, wherein the first dielectric layer comprises a first patterned conductive layer disposed between a first sublayer and a second sublayer of the first dielectric layer, wherein the first patterned conductive layer comprises a field plate spaced apart from the die, and wherein the field plate is adapted to receive a bias voltage to generate an electric field between the die and the field plate; removing the carrier layer from the core layer; and A second dielectric layer is disposed on the core layer such that the core layer is located between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer includes a second patterned conductive layer disposed between the first sublayer and the second sublayer of the second dielectric layer.

15. The method according to claim 14, characterized in that Disposing the first dielectric layer on the core layer, above the cavity, comprises: disposing the first sub-layer on the core layer; disposing the first patterned conductive layer on the first sub-layer; and The second sub-layer is disposed on the first patterned conductive layer and the first sub-layer.

16. The method according to claim 15, characterized in that Disposing the first dielectric layer on the core layer over the cavity further includes disposing at least a portion of the first sublayer in the cavity between the die and a sidewall of the cavity.

17. The method according to claim 14, characterized in that Further including: providing a through-hole through the first dielectric layer between an outer surface of the first dielectric layer and the die, wherein the die is electrically connected to the through-hole; as well as A device is disposed on an outer surface of the first dielectric layer such that the device is electrically connected to the die through the via.

18. The method according to claim 17, characterized in that Further including: A third patterned conductive layer is disposed on an outer surface of the first dielectric layer, wherein the device and the via are electrically connected to the third patterned conductive layer.

19. The method according to claim 14, wherein Further including: providing a second through-hole passing through the second dielectric layer between an outer surface of the second dielectric layer and the tube die, wherein the tube die is electrically connected to the second through-hole; as well as A conductive pad is disposed on an outer surface of the second dielectric layer so as to be electrically connected to the die through the second through-hole.

20. The method of claim 14, wherein: Disposing the second dielectric layer on the core layer over the cavity comprises: disposing the first sub-layer on the core layer; disposing the second patterned conductive layer on the first sub-layer; and The second sub-layer is disposed on the second patterned conductive layer and the first sub-layer.

21. The method of claim 14, wherein: Providing the cavity in the core layer comprises at least one of the following means: drilling, laser drilling, chemical etching, plasma etching, and punching.

22. The method of claim 14, wherein: Also includes: A release layer is disposed on the core layer before disposing a carrier layer on the core layer over the cavity, wherein the release layer is disposed between the core layer and the carrier layer.

23. The method of claim 14, wherein: Also includes: A glass layer is disposed on the carrier layer before the die is disposed within the cavity on the carrier layer such that the carrier layer is between the glass layer and the core layer.

24. The method of claim 15, wherein: The step of providing the first dielectric layer further comprises: providing a continuous conductive layer on the first sublayer of the first dielectric layer; and The continuous conductive layer is patterned to provide the first patterned conductive layer.

25. The method of claim 20, wherein: The step of providing a second dielectric layer further comprises: providing a continuous conductive layer on the first sublayer of the second dielectric layer; and The continuous conductive layer is patterned to provide the second patterned conductive layer.

26. The method of claim 14, wherein: The step of providing a first dielectric layer includes laminating the first dielectric layer onto the core layer and above the cavity.

27. The method of claim 14, wherein: The step of providing a second dielectric layer includes laminating the second dielectric layer onto the core layer.

28. The method of claim 14, wherein: The die includes a field termination structure disposed on an outer surface of the die facing the field plate, wherein at least a portion of the field plate overlaps the field termination structure in a direction normal to the outer surface of the first dielectric layer.

29. The method of claim 14, wherein: The die includes high voltage electrical components.

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