Semiconductor device using leads and stacked semiconductor package

Abstract

Semiconductor device and stacked semiconductor package using leads. A semiconductor device and a stacked semiconductor package are disclosed. The semiconductor device may include a semiconductor chip and a plurality of chip pads arranged on the semiconductor chip in a second horizontal direction perpendicular to the first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a lead extending in the first horizontal direction when viewed from the top; and a second chip pad connected to a diagonal lead extending in a direction at an angle to the first horizontal direction and the second horizontal direction when viewed from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.

Description

Technical Field

[0001] Example embodiments relate to semiconductor technology, and more particularly, to a semiconductor device and a stacked semiconductor package using wires. Background Art

[0002] With the development of manufacturing process technology of semiconductor devices, the size of semiconductor chips continues to shrink. However, when various functions are to be supported by one semiconductor chip, the number of required signal input / output increases, thereby increasing the number of chip pads on the semiconductor chip. However, due to problems related to the reuse of wire bonding equipment or due to the reduction of bonding force or bonding strength with bonding wires, it is not easy to reduce the size of chip pads. Therefore, the rate of reduction of the area occupied by chip pads cannot keep up with the rate of increase in the integration of semiconductor devices. Therefore, the size of semiconductor chips may be limited by the size of chip pads. Summary of the invention

[0003] Various embodiments relate to a semiconductor device and a stacked semiconductor package whose size can be reduced.

[0004] In an embodiment, a semiconductor device may include: a semiconductor chip; and a plurality of chip pads arranged on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a lead extending in the first horizontal direction when viewed from the top; and a second chip pad connected to a diagonal lead extending in a direction at an angle to the first horizontal direction and the second horizontal direction when viewed from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.

[0005] In an embodiment, a stacked semiconductor package may include: a substrate; and a plurality of semiconductor chips stacked above the substrate, each semiconductor chip having a pad unit provided with a first chip pad and a second chip pad, and offset relative to each other in a first horizontal direction so that the pad unit is exposed. The first chip pad of the semiconductor chip may be connected to a lead extending in the first horizontal direction when viewed from the top, and one or more of the plurality of second chip pads of the semiconductor chip may be connected to a diagonal lead extending in a direction angled to the first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction when viewed from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 It is shown Figure 1 An expanded plan view of first to third chip pads and leads connected thereto.

[0008] Figure 3 is a perspective view showing a stacked semiconductor package according to an embodiment of the present disclosure.

[0009] Figure 4 yes Figure 3 A plan view of a stacked semiconductor package is shown.

[0010] Figure 5 is a perspective view showing a stacked semiconductor package according to an embodiment of the present disclosure.

[0011] Figure 6 yes Figure 5 A plan view of a stacked semiconductor package is shown.

[0012] Figure 7 is a block diagram illustrating an electronic system including a semiconductor device or a stacked semiconductor package according to an embodiment of the present disclosure.

[0013] Figure 8 is a block diagram illustrating a memory card including a semiconductor device or a stacked semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The advantages and features of the present disclosure and methods for achieving them will become apparent from the following description of the exemplary embodiments described with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0015] The figures, sizes, ratios, angles, and quantities of the elements given in the drawings describing the embodiments of the present disclosure are merely illustrative and non-restrictive. Throughout the specification, similar reference numerals represent similar elements. When describing the present disclosure, when it is determined that the detailed description of the known prior art may obscure the subject matter or clarity of the present disclosure, its detailed description will be omitted. It will be understood that, unless otherwise specifically stated, the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the means listed thereafter. In the case of using an indefinite article or a definite article when involving a singular noun (e.g., "one", "a", "the"), unless otherwise specifically stated, the article may include the plural number of the noun.

[0016] Even if not explicitly stated, elements in the embodiments of the present disclosure should be construed as including error tolerances.

[0017] In addition, when describing the elements of the present disclosure, there may be terms similar to the first, second, A, B, (a) and (b) used. These are only to distinguish one element from another element, rather than to imply or suggest the essence, order, sequence or quantity of the element. In addition, the elements in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical spirit of the present disclosure, the first element may be the second element.

[0018] If an element is described as being "connected," "coupled," or "linked" to another element, the element may be directly "connected," "coupled," or "linked," but another element may be inserted between them or the respective elements may be indirectly "connected," "coupled," or "linked" via a third element. When describing a positional relationship, such as "element A on element B," "element A above element B," "element A below element B," and "element A next to element B," another element C may be disposed between elements A and B unless the terms "directly" or "immediately" are explicitly used. When describing a positional relationship, for example, when describing a positional relationship between two elements (e.g., "on," "above," "below," or "next to"), one or more other elements may be located between the two elements as long as terms such as "directly" or "immediately" are not used.

[0019] In addition, the features of the various exemplary embodiments of the present disclosure may be partially or completely connected, combined or separated. Various interactions and operations are technically possible. The various exemplary embodiments may be implemented individually or in combination.

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, two directions substantially parallel to the top surface of the substrate and intersecting each other are defined as a first horizontal direction HD1 and a second horizontal direction HD2, respectively, and a direction protruding vertically from the top surface of the substrate is defined as a vertical direction VD. The first horizontal direction HD1 and the second horizontal direction HD2 may substantially cross each other vertically to form a plane substantially parallel to the top surface of the substrate, and a diagonal direction DD may cross the first horizontal direction HD1 and the second horizontal direction HD2 at an angle on the same plane. The vertical direction VD may correspond to a direction perpendicular to the first horizontal direction HD1 and the second horizontal direction HD2. In the accompanying drawings, the direction indicated by the arrow and the direction opposite thereto represent the same direction.

[0021] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 An expanded plan view of first to third chip pads and leads connected thereto.

[0022] Reference Figure 1 , the semiconductor chip 20 includes a plurality of chip pads 21 to 23 disposed at one end thereof in a first horizontal direction HD1. The chip pads 21 to 23 may be arranged at one end of the semiconductor chip 20 in a second horizontal direction HD2, and serve as contacts of the semiconductor chip 20 for connection with an external device. The first horizontal direction HD1 and the second horizontal direction HD2 may correspond to directions intersecting each other at substantially right angles while forming a plane substantially parallel to the top surface of the semiconductor chip 20. Figure 1 The chip pads 21 to 23 are shown to be arranged in one column in the second horizontal direction HD2 , but conceivable embodiments of the present disclosure are not limited thereto, and the chip pads 21 to 23 may be arranged in two or more columns.

[0023] The chip pads 21 to 23 may be classified into a first chip pad 21, a second chip pad 22, and a third chip pad 23. The first chip pad 21 is connected to a straight lead 31, and the second chip pad 22 is connected to a diagonal lead 32. The third chip pad 23 not connected to a lead may correspond to a test pad that is used when testing the semiconductor chip 20 but is not used after the semiconductor chip 20 undergoes packaging.

[0024] In a plan view, the straight leads 31 may extend in the first horizontal direction HD1. In addition, in a plan view, the diagonal leads 32 may extend in a diagonal direction DD that is inclined at an angle with respect to the first horizontal direction HD1 and the second horizontal direction HD2.

[0025] Reference Figure 2 , the straight lead 31 in the first horizontal direction HD1 may be bonded to the first chip pad 21. Therefore, the contact portion 31A of the straight lead 31 bonded to the top surface of the first chip pad 21 may have an elliptical shape with a major axis substantially parallel to the first horizontal direction HD1. The diagonal lead 32 is bonded to the second chip pad 22 in the diagonal direction DD. Therefore, the contact portion 32A of the diagonal lead 32 bonded to the top surface of the second chip pad 22 may have an elliptical shape with a major axis substantially parallel to the diagonal direction DD.

[0026] In order to ensure the bonding with the leads 31 and 32, the first chip pad 21 and the second chip pad 22 need to have a sufficient size so that the contact portions 31A and 32A of the leads 31 and 32 can land. Since a large number of chip pads 21 to 23 are provided on the semiconductor chip 20 to support various functions, it is necessary to reduce the area of ​​the chip pads 21 to 23 in order to reduce the overall size of the semiconductor chip 20. Specifically, in the second horizontal direction HD2 corresponding to the arrangement direction of the chip pads 21 to 23, the width of the chip pads 21 to 23 must be reduced.

[0027] Since the contact portion 32A of the diagonal lead 32 has an elliptical shape with the major axis in the diagonal direction DD inclined relative to the first horizontal direction HD1 and the second horizontal direction HD2, the width w2 of the second chip pad 22 in the second horizontal direction HD2 may be set to a value substantially the same as the length d2 of the second chip pad 22 in the first horizontal direction HD1, so that the contact portion 32A of the diagonal lead 32 may land on the second chip pad 22. For example, the second chip pad 22 may have a square shape with a width w2 and a length d2 of 60 μm.

[0028] The width w1 of the first chip pad 21 may be set to a value smaller than the width w2 of the second chip pad 22. For example, the width w2 of the second chip pad 22 may be set to 60 μm, and the width w1 of the first chip pad 21 may be set to 55 μm. Since the contact portion 31A of the straight lead 31 has an elliptical shape with the major axis in the first horizontal direction HD1, the contact portion 31A of the straight lead 31 may land on the first chip pad 21 even if the width w1 of the first chip pad 21 is smaller than the width w2 of the second chip pad 22. The length d1 of the first chip pad 21 in the first horizontal direction HD1 may be substantially equal to the length d2 of the second chip pad 22. For example, the first chip pad 21 may have a rectangular shape with a width w1 and a length d1 of 55 μm and 60 μm, respectively.

[0029] During the chip test process, the probe of the test equipment is connected to the third chip pad 23 to input / output the necessary test signal, and the test equipment determines whether the semiconductor chip 20 is defective based on the reading result of the output signal. For normal testing, the size of the third chip pad 23 needs to be large enough to prevent poor contact with the probe. However, as the thickness of the probe decreases with the development of improved test equipment, the area of ​​the third chip pad 23 required for contact with the probe can be reduced. Therefore, when the third chip pad 23 has the same size as the second chip pad 22, the size of the third chip pad 23 can act as a restriction on the size of the semiconductor chip 20.

[0030] In some embodiments, the third chip pad 23 may have a smaller size than the second chip pad 22. The width w3 of the third chip pad 23 may be smaller than the width w2 of the second chip pad 22, and the length d3 of the third chip pad 23 may be smaller than the length d2 of the second chip pad 22. For example, the second chip pad 22 may have a square shape with a width w2 and a length d2 of 60 μm, and the third chip pad 23 may have a square shape with a width w3 and a length d3 of 55 μm.

[0031] Figure 3 is a perspective view showing a stacked semiconductor package according to an embodiment of the present disclosure. Figure 4 yes Figure 3 A plan view of a stacked semiconductor package is shown.

[0032] Reference Figure 3 and Figure 4 According to the stacked semiconductor package 100 of the embodiment, a plurality of semiconductor chips 20A to 20D may be stacked on a substrate 10 having a plurality of bonding fingers 11, 12A and 12B. The semiconductor chips 20A to 20D may be chips of the same type. In the present embodiment, the semiconductor chips 20A to 20D are flash memory chips. However, the present embodiment is not limited thereto. In other embodiments that can be imagined in the present disclosure, the semiconductor chips 20A to 20D may be different types of memory chips or non-memory chips.

[0033] The semiconductor chips 20A to 20D may be manufactured on a single wafer using the same process steps and may have the same structure. Each of the semiconductor chips 20A to 20D may include a pad unit P disposed at an edge thereof in a first horizontal direction HD1, in which a plurality of chip pads 21 to 23 are disposed. The pad unit P may be elongated in a second horizontal direction HD2 perpendicular to the first horizontal direction HD1.

[0034] The chip pads 21 to 23 may be arranged in the pad unit P in the second horizontal direction HD2. The chip pads 21 to 23 may be classified into a first chip pad 21, a second chip pad 22, and a third chip pad 23. For simplicity of illustration, Figure 3 and Figure 4 It is shown that one first chip pad 21, one second chip pad 22, and one third chip pad 23 are provided on each of the semiconductor chips 20A to 20D. However, in fact, a plurality of first chip pads 21, a plurality of second chip pads 22, and a plurality of third chip pads 23 may be located on each of the semiconductor chips 20A to 20D.

[0035] The semiconductor chips 20A to 20D may be stacked offset in the first horizontal direction HD1 so that the pad unit P of each of the semiconductor chips 20A to 20D is exposed. In a top view, the first chip pads 21 of the semiconductor chips 20A to 20D may be arranged in a row in the first horizontal direction HD1. Similarly, in a top view, the second chip pads 22 and the third chip pads 23 of the semiconductor chips 20A to 20D may also be arranged in a row in the first horizontal direction HD1.

[0036] The first chip pads 21 of the semiconductor chips 20A to 20D arranged in a row in the first horizontal direction HD1 may be connected to the first bonding fingers 11 formed in or arranged on the substrate 10 through the first leads 41. In a top view, the first leads 41 may extend in the first horizontal direction HD1 and be sequentially connected to the first bonding fingers 11 of the substrate 10 and the first chip pads 21 of the semiconductor chips 20A to 20D. In order to connect the first bonding fingers and the semiconductor chips 20D to 20A, the first leads 41 may also extend upward or downward in the vertical direction VD while extending along the first horizontal direction HD1.

[0037] The same signal may be input to each of the first chip pads 21 arranged in a row in the first horizontal direction HD1 through the first lead 41. The first chip pad 21 may include a data input / output pad for inputting or outputting data. Data input through the first bonding fingers 11 of the substrate 10 may be commonly input to the first chip pads 21 of the semiconductor chips 20A to 20D through the first lead 41, and data output from the first chip pads 21 of the semiconductor chips 20A to 20D may be output to the first bonding fingers 11 of the substrate 10 through the first lead 41.

[0038] The first chip pad 21 may be used as a command input pad for inputting a command to the semiconductor chips 20A to 20D, or as an address input pad for inputting an address to the semiconductor chips 20A to 20D. The first chip pad 21 may be used as a power supply voltage pad for inputting a power supply voltage Vcc to the semiconductor chips 20A to 20D, or as a ground voltage pad for inputting a ground voltage Vss to the semiconductor chips 20A to 20D.

[0039] The stacked semiconductor package 100 may have a multi-channel structure using multiple channels to send signals. The semiconductor chips 20A to 20D included in the stacked semiconductor package 100 may be divided into multiple channel groups. For example, two semiconductor chips 20C and 20D located at the top or near the top of the stack may be included in the first channel group, and two semiconductor chips 20A and 20B located at the bottom or near the bottom of the stack may be included in the second channel group. The second chip pads 22 of the semiconductor chips 20A to 20D may correspond to chip pads for signal transmission and may be connected to different bonding fingers of different channel groups.

[0040] Different signals may be input to the second chip pads 22 of the semiconductor chips 20A to 20D for each channel group. For example, a first signal may be input to the second chip pads 22 of the semiconductor chips 20C and 20D belonging to the first channel group, while a second signal may be input to the second chip pads 22 of the semiconductor chips 20A and 20B belonging to the second channel group.

[0041] The second chip pads 22 of the semiconductor chips 20C and 20D belonging to the first channel group may be connected to the second bonding finger 12A disposed in or on the substrate 10 through the second lead 42. The second chip pads 22 of the semiconductor chips 20A and 20B belonging to the second channel group may be connected to the third bonding finger 12B disposed in or on the substrate 10 through the third lead 43.

[0042] In the top view, the second bonding finger 12A of the substrate 10 may not be arranged in a row with the second chip pads 22 of the semiconductor chips 20A to 20D in the first horizontal direction HD1. For example, the second bonding finger 12A may be offset relative to the row of second chip pads 22 in the second horizontal direction HD2. In such a case, when viewed in the top view, at least a portion of the second lead 42 may extend in a diagonal direction DD that is inclined relative to the first horizontal direction HD1 and the second horizontal direction HD2. For example, the second lead 42 may include a first portion 42A connecting the second bonding finger 12A of the substrate 10 and the second chip pad 22 of the semiconductor chip 20C and a second portion 42B connecting the second chip pad 22 of the semiconductor chip 20C and the second chip pad 22 of the semiconductor chip 20D. In the top view, the first portion 42A of the second lead 42 may extend in the diagonal direction DD.

[0043] In the top view, the third bonding fingers 12B of the substrate 10 may be arranged in a row with the second die pads 22 of the semiconductor chips 20A to 20D in the first horizontal direction HD1. In the top view, the third leads 43 may extend in the first horizontal direction HD1. In an embodiment, the leads 42A connecting the second bonding fingers 12A of the substrate 10 and the second die pads 22 of the semiconductor chip 20C correspond to diagonal leads, and the other leads correspond to straight leads, that is, leads parallel to the first horizontal direction HD1 in the top view.

[0044] Reference Figure 4 , the lead 42A is bonded to the second chip pad 22 of the semiconductor chip 20C in the diagonal direction DD. Therefore, the contact portion 42C of the lead 42A bonded to the top surface of the second chip pad 22 of the semiconductor chip 20C may have an elliptical shape with a major axis substantially in the diagonal direction DD. The first lead 41 may be bonded to the first chip pad 21 of the semiconductor chips 20A to 20D in the first horizontal direction HD1. Therefore, the contact portion 41A of the first lead 41 bonded to the top surface of the first chip pad 21 may have an elliptical shape with a major axis parallel to the first horizontal direction HD1.

[0045] In order to ensure the bonding between the second die pad 22 of the semiconductor chip 20C and the second lead 42A, the width w2 of the second die pad 22 in the second horizontal direction HD2 may be set to a value substantially the same as the length d2 of the second die pad 22 in the first horizontal direction HD1. For example, the second die pad 22 may have a square shape with a width w2 and a length d2 of 60 μm.

[0046] The width w1 of the first chip pad 21 may be smaller than the width w2 of the second chip pad 22. For example, the width w2 of the second chip pad 22 may be set to 60 μm, and the width w1 of the first chip pad 21 may be set to 55 μm. Since the contact portion 41A of the first lead 41 has an elliptical shape with the major axis in the first horizontal direction HD1, the contact portion 41A of the first lead 41 may land on the first chip pad 21 even if the width w1 of the first chip pad 21 is set to a value smaller than the width w2 of the second chip pad 22. The length d1 of the first chip pad 21 in the first horizontal direction HD1 may be substantially equal to the length d2 of the second chip pad 22. For example, the first chip pad 21 may have a rectangular shape with a width w1 and a length d1 of 55 μm and 60 μm, respectively.

[0047] The third chip pad 23 that does not need to be connected to the lead may correspond to a test pad used during chip testing. The third chip pad 23 may have a smaller size than the second chip pad 22. The width w3 of the third chip pad 23 may be smaller than the width w2 of the second chip pad 22, and the length d3 of the third chip pad 23 may be smaller than the length d2 of the second chip pad 22. For example, the second chip pad 22 may have a square shape with a width w2 and a length d2 of 60 μm, and the third chip pad 23 may have a square shape with a width w3 and a length d3 of 55 μm.

[0048] Figure 5 is a perspective view showing a stacked semiconductor package according to an embodiment of the present disclosure. Figure 6 yes Figure 5 A plan view of a stacked semiconductor package is shown.

[0049] Reference Figure 5 and Figure 6 , a stacked semiconductor package 200 according to an embodiment may have a structure in which a plurality of semiconductor chips 20A to 20D are stacked in a vertical direction VD over a substrate 10 having a plurality of bonding fingers 11 and 12 .

[0050] The semiconductor chips 20A to 20D may be manufactured on a single wafer using the same process steps and have substantially the same structure. Each of the semiconductor chips 20A to 20D may include a pad unit P disposed at an edge thereof in a first horizontal direction HD1, the pad unit P having a plurality of chip pads 21 to 24. The pad unit P may be elongated in a second horizontal direction HD2 substantially perpendicular to the first horizontal direction HD1.

[0051] The chip pads 21 to 24 may be arranged in the pad unit P or on the pad unit P in the second horizontal direction HD2. The chip pads 21 to 24 may be classified into a first chip pad 21, a second chip pad 22, a third chip pad 23, and a fourth chip pad 24. For simplicity of illustration, Figure 5 and Figure 6 It is shown that one first chip pad 21, one second chip pad 22, one third chip pad 23, and one fourth chip pad 24 are provided in or on the pad unit P of each of the semiconductor chips 20A to 20D. However, in fact, there may be a plurality of first chip pads 21, a plurality of second chip pads 22, a plurality of third chip pads 23, and a plurality of fourth chip pads 24 in each of the semiconductor chips 20A to 20D.

[0052] The semiconductor chips 20A to 20D may be offset or staggered in the first horizontal direction HD1 so that the pad unit P is exposed. In a top view, the first chip pads 21 of the semiconductor chips 20A to 20D may be arranged in a row in the first horizontal direction HD1. The second chip pads 22 of the semiconductor chips 20A to 20D may also be arranged in a row in the first horizontal direction HD1. Similarly, in a top view, the other third chip pads 23 and the fourth chip pads 24 may also be arranged in a row in the first horizontal direction HD1.

[0053] The first chip pads 21 of the semiconductor chips 20A to 20D arranged in a row in the first horizontal direction HD1 can be connected to the first bonding fingers 11 formed in or on the substrate 10 through the first leads 51. In the top view, it is seen that the first leads 51 extend in the first horizontal direction HD1 and are sequentially connected to the first bonding fingers 11 of the substrate 10 and the first chip pads 21 of the semiconductor chips 20A to 20D while extending upward or downward in the vertical direction VD.

[0054] The same signal may be input to the first chip pads 21 arranged in a row in the first horizontal direction HD1 through the first lead 51. The first chip pads 21 may include an input / output pad. Data input through the first bonding fingers 11 of the substrate 10 may be commonly input to the first chip pads 21 of the semiconductor chips 20A to 20D through the first lead 51, and data output from the first chip pads 21 of the semiconductor chips 20A to 20D may be output to the first bonding fingers 11 of the substrate 10 through the first lead 51. Commands or addresses input through the first bonding fingers 11 of the substrate 10 may be commonly input to the first chip pads 21 of the semiconductor chips 20A to 20D through the first lead 51.

[0055] The second die pads 22 of the lowermost semiconductor chip 20A may be connected to the second bonding fingers 12 of the substrate 10 through straight wires 52A. Each second die pad 22 included in the semiconductor chips 20B to 20D may be connected to a corresponding fourth die pad 24 of another semiconductor chip through diagonal wires 52B.

[0056] Semiconductor chips 20A to 20D can be distinguished from each other by chip addresses. Semiconductor chips 20A to 20D may not include pads for storing chip addresses, but may store chip addresses in their internal memory areas. In order to store chip addresses that are different from each other, semiconductor chips 20A to 20D may include enable input pads and enable output pads. The second chip pad 22 may correspond to the enable input pad, and the fourth chip pad 24 may correspond to the enable output pad. According to the signal applied to the second chip pad 22 and the fourth chip pad 24, the chip address may be stored in semiconductor chips 20A to 20D in sequence. For example, a logic high signal may be applied to the second chip pad 22 of the bottom semiconductor chip 20A from the second bonding finger 12 of the substrate 10. In this state, when the chip address is input to the first chip pad 21 of the semiconductor chips 20A to 20D, the chip address may be stored in the bottom semiconductor chip 20A. When the chip address is completely stored in the lowermost semiconductor chip 20A, the output signal of the fourth chip pad 24 of the lowermost semiconductor chip 20A transitions from logic low to logic high, and no chip address is stored in the lowermost semiconductor chip 20A any more.

[0057] When the signal of the fourth chip pad 24 of the bottom semiconductor chip 20A is changed to logic high, the logic high signal is applied to the second chip pad 22 of the semiconductor chip 20B connected to the fourth chip pad 24 of the bottom semiconductor chip 20A through the diagonal lead 52, so that the semiconductor chip 20B is ready to store the address. Then, when the chip address is input to the first chip pad 21 of the semiconductor chips 20A to 20D, the chip address can be stored in the semiconductor chip 20B. When the chip address is completely stored in the semiconductor chip 20B, the output signal of the fourth chip pad 24 of the semiconductor chip 20B is changed from logic low to logic high, and no chip address is stored in the semiconductor chip 20B. In this way, the chip address can be stored in the semiconductor chips 20A to 20D in sequence.

[0058] To ensure bonding with the diagonal leads 52B, the width w2 of the second and fourth die pads 22 and 24 of the semiconductor chips 20A to 20D in the second horizontal direction HD2 may be substantially equal to the length d2 thereof in the first horizontal direction HD1 .

[0059] A width w1 of the first chip pad 21 may be smaller than a width w2 of the second chip pad 22 , and a length d1 of the first chip pad 21 may be substantially equal to a length d2 of the second chip pad 22 .

[0060] The third chip pad 23 that does not need to be connected to the lead may correspond to a test pad used during chip testing. The third chip pad 23 may have a smaller size than the second chip pad 22. The width w3 of the third chip pad 23 may be smaller than the width w2 of the second chip pad 22, and the length d3 of the third chip pad 23 may be smaller than the length d2 of the second chip pad 22.

[0061] According to the embodiments disclosed herein, the width of a chip pad connected to a straight lead can be set to a smaller value than the width of a chip pad connected to a diagonal lead, so that the area occupied by the chip pad can be reduced without reducing the bonding force or strength with the lead. Therefore, the size of the semiconductor chip can be reduced.

[0062] The above-described semiconductor device and stacked semiconductor package may be used in various semiconductor devices and package modules.

[0063] Figure 7 is a block diagram illustrating an electronic system including a semiconductor device or a stacked semiconductor package according to an embodiment of the present disclosure. Figure 8 is a block diagram illustrating a memory card including a semiconductor device or a stacked semiconductor package according to an embodiment of the present disclosure.

[0064] Reference Figure 7, the semiconductor device or stacked semiconductor package according to the embodiments described herein may be used in an electronic system 710. The electronic system 710 may include a controller 711, an input / output unit 712, and a memory 713. The controller 711, the input / output unit (IO unit) 712, and the memory 713 may be electrically coupled to each other through a bus 715 that provides a data movement path.

[0065] For example, the controller 711 may include at least one microprocessor, at least one digital signal processor, at least one microcontroller, and at least one logic circuit capable of performing the same functions as these components. The memory 713 may include at least one of a semiconductor device or a stacked semiconductor package according to the disclosed embodiments. The input / output unit 712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 713, which is a device for storing data, may store data or / and commands to be executed by the controller 711, etc.

[0066] The memory 713 may include a volatile memory device such as a DRAM or / and a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in a mobile terminal or an information processing system such as a desktop computer. The flash memory may be configured by an SSD (solid state drive). In this case, the electronic system 710 may stably store a large amount of data in the flash memory system.

[0067] The electronic system 710 may also include an interface 714 configured to be able to send data to and receive data from a communication network. The interface 714 may be a wired or wireless type. For example, the interface 714 may include an antenna, a wired transceiver, or a wireless transceiver.

[0068] The electronic system 710 may be understood as a mobile system, a personal computer, a computer for industrial use, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0069] In the case where the electronic system 710 is a device capable of performing wireless communications, the electronic system 710 can be used in a communication system such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0070] Reference Figure 8, the semiconductor device or stacked semiconductor package according to the embodiments disclosed herein may be provided in the form of a memory card 800. For example, the memory card 800 may include a memory 810 such as a nonvolatile memory device and a memory controller 820. The memory 810 and the memory controller 820 may store data or read the stored data.

[0071] The memory 810 may include at least any one of the nonvolatile memory devices to which the semiconductor device or stacked semiconductor package according to the embodiment is applied, and the memory controller 820 may control the memory 810 to read stored data or store data in response to a read / write request from the host 830 .

[0072] Although various embodiments are described above, those skilled in the art will appreciate that the described embodiments are only examples. Therefore, the semiconductor device and stacked semiconductor package with extended bandwidth described herein should not be limited based on the described embodiments.

[0073] CROSS-REFERENCE TO RELATED APPLICATIONS

[0074] This application claims the benefit of Korean Patent Application No. 10-2019-0122846, filed on October 4, 2019, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device include: Semiconductor chips; as well as a plurality of chip bonding pads, the plurality of chip bonding pads being arranged on the semiconductor chip in a second horizontal direction perpendicular to the first horizontal direction, Wherein, the plurality of chip pads include: a first chip pad connected to a lead extending in the first horizontal direction when viewed from the top; and a second die attach pad connected to a diagonal lead extending in a diagonal direction at an angle to the first horizontal direction and the second horizontal direction when viewed from the top, wherein the contact portion of the lead extending in the first horizontal direction bonded to the top surface of the first chip pad has an elliptical shape with a major axis parallel to the first horizontal direction, and the contact portion of the diagonal lead bonded to the top surface of the second chip pad has an elliptical shape with a major axis parallel to the diagonal direction, and Wherein, a width of the first chip pad in the second horizontal direction is smaller than a width of the second chip pad in the second horizontal direction.

2. The semiconductor device according to claim 1, in, A length of the second chip pad in the first horizontal direction is equal to a width of the second chip pad in the second horizontal direction.

3. The semiconductor device according to claim 1, in, A length of the first chip pad in the first horizontal direction is equal to a length of the second chip pad in the first horizontal direction.

4. The semiconductor device according to claim 1 , further comprising a third chip pad provided on the semiconductor chip and not connected to a lead, in, The width of the third chip pad in the second horizontal direction is smaller than the width of the second chip pad in the second horizontal direction, and the length of the third chip pad in the first horizontal direction is smaller than the length of the second chip pad in the first horizontal direction.

5. A stacked semiconductor package, the stacked semiconductor package include: substrate; as well as A plurality of semiconductor chips are stacked above the substrate, each of the semiconductor chips having a pad unit provided with a first chip pad and a second chip pad, and each of the semiconductor chips is offset relative to each other in a first horizontal direction so that the pad unit is exposed, wherein the first chip pads of the plurality of semiconductor chips are connected to leads extending in the first horizontal direction when viewed from the top, and one or more of the second chip pads of the plurality of semiconductor chips are connected to diagonal leads extending in a diagonal direction that is angled with the first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction when viewed from the top, wherein the contact portion of the lead extending in the first horizontal direction bonded to the top surface of the first chip pad has an elliptical shape with a major axis parallel to the first horizontal direction, and the contact portion of the diagonal lead bonded to the top surface of the second chip pad has an elliptical shape with a major axis parallel to the diagonal direction, and Wherein, a width of the first chip pad in the second horizontal direction is smaller than a width of the second chip pad in the second horizontal direction.

6. The stacked semiconductor package according to claim 5, in, The substrate comprises: a first bonding finger arranged in a row with the first chip pad of the semiconductor chip in the first horizontal direction and connected to a straight lead; and A second bonding finger is not arranged in a row with the second chip pad of the semiconductor chip in the first horizontal direction and is connected to the diagonal lead.

7. The stacked semiconductor package according to claim 5, in, A length of the second chip pad in the first horizontal direction is equal to a width of the second chip pad in the second horizontal direction.

8. The stacked semiconductor package according to claim 5, in, A length of the first chip pad in the first horizontal direction is equal to a length of the second chip pad in the first horizontal direction.

9. The stacked semiconductor package according to claim 5, in, Each of the plurality of semiconductor chips includes a third chip pad to which no lead is connected, The width of the third chip pad in the second horizontal direction is smaller than the width of the second chip pad in the second horizontal direction, and the length of the third chip pad in the first horizontal direction is smaller than the length of the second chip pad in the first horizontal direction.

10. The stacked semiconductor package according to claim 9, in, The third chip pad includes a test pad coupled to a test device during testing of the semiconductor chip.

11. The stacked semiconductor package according to claim 5, in, The plurality of semiconductor chips are divided into a plurality of channel groups, and the plurality of the second chip pads include chip pads for signal transmission and are allocated to the respective channel groups.

12. The stacked semiconductor package according to claim 5, in, The first chip pads include input / output pads for inputting / outputting data.

13. The stacked semiconductor package according to claim 5, in, The first chip pad includes a power supply voltage pad for inputting a power supply voltage or a ground voltage pad for inputting a ground voltage.

14. The stacked semiconductor package according to claim 5, in, The first chip pad includes a command input pad for inputting a command or an address input pad for inputting an address.

15. The stacked semiconductor package according to claim 5, in, Each of the plurality of semiconductor chips includes a fourth chip pad disposed in the pad unit, The fourth chip pad of each of the plurality of semiconductor chips is connected to the second chip pad of another one of the plurality of semiconductor chips through the diagonal wire.

16. The stacked semiconductor package according to claim 15, in, The length of the fourth chip pad in the first horizontal direction is equal to the length of the second chip pad in the first horizontal direction, and the width of the fourth chip pad in the second horizontal direction is equal to the width of the second chip pad in the second horizontal direction.

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