Voltage generating circuit and input buffer including the voltage generating circuit

Abstract

A voltage generating circuit and an input buffer including the voltage generating circuit. A voltage generating circuit may include: a first transistor coupled to an internal power supply voltage terminal and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal and configured to operate according to a first reference voltage generated based on an external power supply voltage. As a threshold voltage of the second transistor increases according to an increase in a level of the internal power supply voltage, the voltage generating circuit may limit a change in a level of a second reference voltage generated by a drain terminal of the second transistor.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor circuits, and more particularly, to a voltage generating circuit and an input buffer including the voltage generating circuit. Background Art

[0002] The semiconductor circuit includes an input buffer for receiving an input signal provided from the outside of the semiconductor circuit.

[0003] The input buffer may operate according to different types of power supply voltages, ie, a power supply voltage provided from the outside (hereinafter, referred to as an external power supply voltage) or / and a power supply voltage provided from the inside (hereinafter, referred to as an internal power supply voltage).

[0004] It is very important for the input buffer to have stable output characteristics regardless of different types of power supply voltages. Summary of the invention

[0005] In one embodiment, a voltage generating circuit may include: a first transistor coupled to an internal power supply voltage terminal and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal and configured to operate according to a first reference voltage generated based on an external power supply voltage. As a threshold voltage of the second transistor increases according to an increase in a level of the internal power supply voltage, the voltage generating circuit may limit a level change of a second reference voltage generated by a drain terminal of the second transistor.

[0006] In one embodiment, an input buffer may include: an amplifier circuit configured to receive an internal power supply voltage and generate an output signal by amplifying an input signal according to a compensation bias voltage and a first reference voltage generated based on an external power supply voltage; and a compensation circuit configured to generate a compensation bias voltage according to a pre-compensation signal generated by a replica circuit and a second reference voltage generated by the compensation circuit, the replica circuit being configured by a replica amplifier circuit, wherein the compensation circuit generates the second reference voltage, the level of which is restricted to vary according to a rise in the level of the internal power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating a configuration of an input buffer according to one embodiment.

[0008] Figure 2 It is an example Figure 1 Diagram of the configuration of the amplifier circuit.

[0009] Figure 3 It is an example Figure 1 Diagram of the configuration of the compensation circuit.

[0010] Figure 4 is a diagram illustrating a configuration of an input buffer according to another embodiment.

[0011] Figure 5 It is an example Figure 4 Diagram of the configuration of the compensation circuit. DETAILED DESCRIPTION

[0012] Hereinafter, a voltage generation circuit and an input buffer including the same according to the present disclosure will be described below through various examples of embodiments with reference to the accompanying drawings.

[0013] Various embodiments relate to a voltage generating circuit capable of having stable output characteristics regardless of changes in power supply voltage and an input buffer including the voltage generating circuit.

[0014] Figure 1 is a diagram illustrating a configuration of an input buffer according to an embodiment.

[0015] Reference Figure 1 , the input buffer 100 according to the embodiment may include an amplifier circuit 200 and a compensation circuit 300 .

[0016] The amplifier circuit 200 may generate a differential output signal OUT / OUTB by amplifying a differential input signal IN / INB according to an internal power supply voltage VCCI and a compensation bias voltage VBCMFB.

[0017] The data signal DQ may be input as a differential input signal IN among the differential input signals IN / INB, and the first reference voltage VREFQ may be input as a differential input signal INB among the differential input signals IN / INB.

[0018] The compensation circuit 300 may include a replica circuit configured by replicating the amplifier circuit 200 , and generates a compensation bias voltage VBCMFB according to an internal power supply voltage VCCI and any one of differential input signals IN / INB (eg, the differential input signal INB).

[0019] The internal power supply voltage VCCI and the first reference voltage VREFQ may be generated by a circuit (eg, the voltage generating circuit 10 ) included in a semiconductor device using the input buffer 100 according to the embodiment.

[0020] The voltage generation circuit 10 may generate the internal power supply voltage VCCI and the first reference voltage VREFQ using the external power supply voltage VCCQ. The external power supply voltage VCCQ may be provided from outside the semiconductor circuit including the input buffer 100.

[0021] Figure 2 It is an example Figure 1 Diagram of the configuration of the amplifier circuit.

[0022] Reference Figure 2 , the amplifier circuit 200 may include a plurality of transistors 201 , 204 , 205 , 206 , and 207 and a plurality of loads ( LD1 and LD2 ) 208 and 209 .

[0023] The first transistor 201 may operate as a current source configured to adjust an amount of current according to the internal power supply voltage VCCI in response to the compensation bias voltage VBCMFB.

[0024] The first transistor 201 may have a source terminal configured to receive the internal power supply voltage VCCI and a gate terminal configured to receive the compensation bias voltage VBCMFB.

[0025] The first transistor 201 may have a drain terminal coupled to a source terminal of the second transistor 204 and a source terminal of the third transistor 205 .

[0026] The second transistor 204 and the third transistor 205 may constitute a differential pair 203 .

[0027] The second transistor 204 may receive the differential input signal INB among the differential input signals IN / INB through its gate terminal and generate the differential output signal OUTB among the differential output signals OUT / OUTB through its drain terminal.

[0028] The third transistor 205 may receive the differential input signal IN among the differential input signals IN / INB through its gate terminal and generate the differential output signal OUT among the differential output signals OUT / OUTB through its drain terminal.

[0029] The fourth transistor 206 may have a drain terminal coupled to the drain terminal of the second transistor 204 and a gate terminal configured to receive the enable signal EN.

[0030] One terminal of the first load ( LD1 ) 208 is coupled to the ground terminal, and the other terminal thereof is coupled to the source terminal of the fourth transistor 206 .

[0031] The fifth transistor 207 may have a drain terminal coupled to the drain terminal of the third transistor 205 and a gate terminal configured to receive the enable signal EN.

[0032] One terminal of the second load ( LD2 ) 209 is coupled to the ground terminal, and the other terminal thereof is coupled to the source terminal of the fifth transistor 207 .

[0033] The above-mentioned amplifier circuit 200 can generate a differential output signal OUT / OUTB by amplifying the data signal DQ according to the first reference voltage VREFQ during the activation interval (e.g., high level interval) of the enable signal EN, and correct the level of the differential output signal OUT / OUTB according to the compensation bias voltage VBCMFB.

[0034] Since the compensation bias voltage VBCMFB has a value obtained by compensating for a variation in the internal power supply voltage VCCI, the amplifier circuit 200 according to the embodiment may control the differential output signal OUT / OUTB to have a stable level.

[0035] Although not shown, the amplifier circuit 200 may further include a slicer and a rail-to-rail amplifier circuit for converting the level of the differential output signal OUT / OUTB into a voltage level that a complementary metal oxide semiconductor (CMOS) circuit will operate or recognize.

[0036] Figure 3 It is an example Figure 1 Diagram of the configuration of the compensation circuit.

[0037] Reference Figure 3 The compensation circuit 300 may include a replica circuit 310 , a differential amplifier 320 , and a voltage generating circuit 330 .

[0038] The replica circuit 310 can be implemented by replicating Figure 2 The amplifier circuit 200 is configured according to the embodiment of the present invention, and therefore has the same electrical characteristics as the amplifier circuit 200.

[0039] The replica circuit 310 may include a plurality of transistors 311 to 313 and a load (LD) 314 .

[0040] The first transistor 311 may operate as a current source configured to adjust an amount of current according to the internal power supply voltage VCCI in response to the compensation bias voltage VBCMFB.

[0041] The first transistor 311 may have a source terminal configured to receive the internal power supply voltage VCCI and a gate terminal configured to receive the compensation bias voltage VBCMFB.

[0042] The first transistor 311 may have a drain terminal coupled to a source terminal of the second transistor 312 .

[0043] The second transistor 312 may receive the first reference voltage VREFQ or DQ through a gate terminal thereof and generate a pre-compensation signal OIN2_CMFB through a drain terminal thereof.

[0044] The third transistor 313 may have a drain terminal coupled to the drain terminal of the second transistor 312 and a gate terminal configured to receive the enable signal EN.

[0045] One terminal of the load (LD) 314 may be coupled to the ground terminal, and the other terminal thereof may be coupled to the source terminal of the third transistor 313 .

[0046] The differential amplifier 320 may generate the compensation bias voltage VBCMFB by comparing the pre-compensation signal OIN2_CMFB and the divided voltage VCCI / 2, for example, during a high level interval of the enable signal EN.

[0047] The voltage generating circuit 330 may generate a divided voltage VCCI / 2 by dividing the internal power voltage VCCI.

[0048] The voltage generating circuit 330 may include a plurality of transistors 331 and 332 and voltage dividing resistors 333 and 334 .

[0049] The first transistor 331 may have a source terminal configured to receive the internal power voltage VCCI and a gate terminal configured to receive the inverted enable signal ENB.

[0050] One terminal of the first resistor 333 may be coupled to the drain terminal of the first transistor 331 .

[0051] One terminal of the second resistor 334 may be coupled to the other terminal of the first resistor 333 .

[0052] In the embodiment, the case where the divided voltage VCCI / 2 has a value corresponding to half of the internal power supply voltage VCCI has been used as an example, and the first resistor 333 and the second resistor 334 may be designed to have the same resistance value. Since the first resistor 333 and the second resistor 334 have the same resistance value, the divided voltage VCCI / 2 corresponding to half of the internal power supply voltage VCCI can be generated from the node to which the first resistor 333 and the second resistor 334 are connected.

[0053] The second transistor 332 may have a drain terminal coupled to the other terminal of the second resistor 334 , a gate terminal configured to receive the enable signal EN, and a source terminal coupled to the ground terminal.

[0054] The operation of the input buffer 100 according to the embodiment having the above-described configuration will be described as follows.

[0055] The replica circuit 310 of the compensation circuit 300 may have Figure 2 Therefore, the pre-compensation signal OIN2_CMFB output from the replica circuit 310 may be controlled to have the same voltage level variation as any one of the differential output signals OUT / OUTB output from the amplifier circuit 200 .

[0056] Since the differential amplifier 320 generates the compensation bias voltage VBCMFB by comparing the pre-compensation signal OIN2_CMFB and the divided voltage VCCI / 2, the compensation bias voltage VBCMFB may have a value obtained by compensating for a variation in the internal power voltage VCCI.

[0057] The amplifier circuit 200 generates a differential output signal OUT / OUTB by amplifying the differential input signal IN / INB according to the compensation bias voltage VBCMFB.

[0058] Therefore, regardless of the variation of the internal power supply voltage VCCI, the differential output signal OUT / OUTB can have a stable level.

[0059] Figure 4 is a diagram illustrating a configuration of an input buffer according to an embodiment.

[0060] Reference Figure 4 , the input buffer 101 according to the embodiment may include an amplifier circuit 200 and a compensation circuit 301 .

[0061] The amplifier circuit 200 may generate a differential output signal OUT / OUTB by amplifying the differential input signal IN / INB according to the compensation bias voltage VBCMFB.

[0062] The data signal DQ may be input as a differential input signal IN among the differential input signals IN / INB, and the first reference voltage VREFQ may be input as a differential input signal INB among the differential input signals IN / INB.

[0063] The amplifier circuit 200 can be used with Figure 2 Configure in the same way.

[0064] The compensation circuit 301 may include a replica circuit configured by replicating the amplifier circuit 200 , and generates a compensation bias voltage VBCMFB according to any one of the differential input signals IN / INB (eg, the differential input signal INB).

[0065] The compensation circuit 301 may control the compensation bias voltage VBCMFB so that its variation is less sensitive to variations in the internal power supply voltage VCCI than to variations in the external power supply voltage VCCQ.

[0066] The compensation circuit 301 may control the compensation bias voltage VBCMFB to have a level that is insensitive to a variation of the internal power supply voltage VCCI and is obtained by compensating for a variation of the external power supply voltage VCCQ.

[0067] Figure 5 It is an example Figure 4 Diagram of the configuration of the compensation circuit.

[0068] Reference Figure 5 , the compensation circuit 301 may include a replica circuit 410 , a differential amplifier 420 , and a voltage generating circuit 430 .

[0069] The replica circuit 410 may be configured by replicating the amplifier circuit 200 , and thus has the same electrical characteristics as the amplifier circuit 200 .

[0070] The replica circuit 410 may include a plurality of transistors 411 to 413 and a load (LD) 414 .

[0071] The first transistor 411 may operate as a current source configured to adjust an amount of current according to the internal power supply voltage VCCI in response to the compensation bias voltage VBCMFB.

[0072] The first transistor 411 may have a source terminal configured to receive the internal power supply voltage VCCI and a gate terminal configured to receive the compensation bias voltage VBCMFB.

[0073] The first transistor 411 may have a drain terminal coupled to a source terminal of the second transistor 412 .

[0074] The second transistor 412 may receive the first reference voltage VREFQ through a gate terminal thereof and generate a pre-compensation signal OIN2_CMFB through a drain terminal thereof.

[0075] The third transistor 413 may have a drain terminal coupled to the drain terminal of the second transistor 412 and a gate terminal configured to receive the enable signal EN.

[0076] One terminal of the load 414 is coupled to the ground terminal, and the other terminal thereof is coupled to the source terminal of the third transistor 413 .

[0077] The differential amplifier 420 may generate the compensation bias voltage VBCMFB by comparing the pre-compensation signal OIN2_CMFB and the second reference voltage VCMFB_REF, for example, during a high level interval of the enable signal EN.

[0078] The differential amplifier 420 may increase the level of the compensation bias voltage VBCMFB as the level of the second reference voltage VCMFB_REF decreases, and may decrease the level of the compensation bias voltage VBCMFB as the level of the second reference voltage VCMFB_REF increases.

[0079] The voltage generating circuit 430 may generate a second reference voltage VCMFB_REF according to the internal power voltage VCCI and the first reference voltage VREFQ.

[0080] The voltage generation circuit 430 may generate a second reference voltage VCMFB_REF whose changes are less sensitive to changes in the internal power voltage VCCI than to changes in the external power voltage VCCQ based on the internal power voltage VCCI and the first reference voltage VREFQ.

[0081] The voltage generation circuit 430 may generate a second reference voltage VCMFB_REF that is insensitive to variations in the internal power voltage VCCI and has a level obtained by compensating for variations in the external power voltage VCCQ according to the internal power voltage VCCI and the first reference voltage VREFQ.

[0082] The voltage generating circuit 430 may include a plurality of transistors 431 to 435 coupled between the internal power supply voltage terminal VCCI and a ground voltage terminal.

[0083] The first transistor 431 may have a source terminal configured to receive the internal power supply voltage VCCI and a gate terminal coupled to a drain terminal thereof.

[0084] The second transistor 432 may have a source terminal coupled to the drain terminal of the first transistor 431 and a gate terminal coupled to the drain terminal thereof.

[0085] Each of the first transistor 431 and the second transistor 432 may have a diode connection configuration in which a gate terminal and a drain terminal thereof are coupled to each other. The first transistor 431 may be referred to as a first diode-connected transistor, and the second transistor 432 may be referred to as a second diode-connected transistor.

[0086] The internal power supply voltage VCCI may be applied to a bulk terminal of the first transistor 431 and a bulk terminal of the second transistor 432 .

[0087] The third transistor 433 may have a drain terminal coupled to the drain terminal of the second transistor 432 and a gate terminal configured to receive the first reference voltage VREFQ.

[0088] The second reference voltage VCMFB_REF may be generated from a node to which the drain terminal of the second transistor 432 and the drain terminal of the third transistor 433 are coupled.

[0089] The fourth transistor 434 may have a drain terminal coupled to the source terminal of the third transistor 433 and a gate terminal coupled to the drain terminal thereof.

[0090] The fifth transistor 435 may have a drain terminal coupled to the source terminal of the fourth transistor 434 , a gate terminal configured to receive the enable signal EN, and a source terminal configured to receive a ground voltage.

[0091] A ground voltage may be applied to the body terminal of the third transistor 433 , the body terminal of the fourth transistor 434 , and the body terminal of the fifth transistor 435 .

[0092] The operation of the input buffer 101 according to the embodiment having the above-described configuration will be described below.

[0093] The voltage generating circuit 430 has a single current path structure including a plurality of transistors 431 to 435 connected in series between the internal power supply voltage terminal VCCI and the ground voltage terminal, and the first reference voltage VREFQ is applied to the gate terminal of the third transistor 433. Therefore, since the drain-source voltage Vds of the third transistor 433 decreases when the level of the first reference voltage VREFQ rises, that is, when the level of the external power supply voltage VCCQ rises, the voltage generating circuit 430 can reduce the level of the second reference voltage VCMFB_REF.

[0094] The voltage generation circuit 430 may generate the second reference voltage VCMFB_REF at a level inversely proportional to a level of the external power voltage VCCQ.

[0095] Since the first transistor 431 and the second transistor 432 are diode-connected transistors and receive the internal power supply voltage VCCI through body terminals thereof, threshold voltages of the first transistor 431 and the second transistor 432 rise and fall according to rise and fall of the level of the internal power supply voltage VCCI.

[0096] As the threshold voltages of the first transistor 431 and the second transistor 432 rise and fall, a variation of the second reference voltage VCMFB_REF caused by the rise and fall of the internal power voltage VCCI may be limited.

[0097] The limitation of the variation of the second reference voltage VCMFB_REF may correspond to the case where the first transistor 431 and the second transistor 432 are configured as diode-connected transistors, but not to the case of general transistors to which a diode connection structure is not applied.

[0098] As described above, the voltage generation circuit 430 may generate the second reference voltage VCMFB_REF to have a level that is insensitive to the level variation of the internal power voltage VCCI and is inversely proportional to the level of the external power voltage VCCQ.

[0099] As the level of the second reference voltage VCMFB_REF rises and falls, the differential amplifier 420 may lower and raise the level of the compensation bias voltage VBCMFB.

[0100] Since the compensation bias voltage VBCMFB varies in inverse proportion to the second reference voltage VCMFB_REF, the compensation bias voltage VBCMFB has a level that is insensitive to the level variation of the internal power voltage VCCI and is obtained by compensating for the level variation of the external power voltage VCCQ.

[0101] The amplifier circuit 200 may generate a differential output signal OUT / OUTB by amplifying the differential input signal IN / INB according to the compensation bias voltage VBCMFB.

[0102] Therefore, regardless of how the internal power supply voltage VCCI and the external power supply voltage VCCQ vary, the differential output signal OUT / OUTB can have a stable level.

[0103] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples, and therefore, the operating method of the data storage device described herein should not be limited based on the described embodiments.

[0104] CROSS-REFERENCE TO RELATED APPLICATIONS

[0105] This application claims the benefit of Korean Application No. 10-2019-0122901 filed on October 4, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A voltage generating circuit, the voltage generating circuit comprising: a first transistor coupled to an internal power supply voltage terminal through a source terminal thereof and configured as a diode-connected transistor in which a gate terminal and a drain terminal thereof are coupled to each other; a second transistor coupled to the drain terminal of the first transistor through its source terminal and configured as a diode-connected transistor in which its gate terminal and drain terminal are coupled to each other; as well as a third transistor coupled between the second transistor and a ground voltage terminal and configured to operate according to a first reference voltage generated based on an external power supply voltage, Here, as the threshold voltage of the second transistor increases according to the increase in the level of the internal power supply voltage, the voltage generation circuit limits the level change of the second reference voltage generated through the drain terminal of the second transistor.

2. The voltage generating circuit according to claim 1, wherein: The voltage generation circuit generates the second reference voltage inversely proportional to a change in level of the first reference voltage.

3. The voltage generating circuit according to claim 1, wherein: The internal supply voltage is applied to a body terminal of at least one of the first transistor and the second transistor.

4. The voltage generating circuit according to claim 1, further comprising: A fourth transistor is coupled between the third transistor and the ground voltage terminal.

5. The voltage generating circuit according to claim 4, wherein: The fourth transistor is configured as a diode-connected transistor whose gate terminal and drain terminal are coupled to each other.

6. The voltage generating circuit according to claim 4, wherein: A ground voltage is applied to a body terminal of the fourth transistor.

7. An input buffer, the input buffer comprising: an amplifier circuit configured to receive the internal power supply voltage and generate an output signal by amplifying an input signal according to the compensation bias voltage and a first reference voltage generated based on the external power supply voltage; as well as a compensation circuit configured to generate the compensation bias voltage according to a pre-compensation signal generated by a replica circuit and a second reference voltage generated by the compensation circuit, the replica circuit being configured by replicating the amplifier circuit and including a voltage generating circuit, The compensation circuit limits a level variation of the generated second reference voltage as a threshold voltage of at least one transistor among a plurality of transistors in the voltage generating circuit increases according to an increase in a level of the internal power supply voltage.

8. The input buffer according to claim 7, wherein: The compensation circuit generates the second reference voltage in inverse proportion to a change in a level of the first reference voltage.

9. The input buffer according to claim 7, wherein: The amplifier circuit comprises: a current source configured to adjust an amount of current according to the compensation bias voltage; and A differential pair is coupled between the current source and a ground voltage terminal and is configured to generate the output signal by amplifying the input signal.

10. The input buffer according to claim 7, wherein: The compensation circuit further includes: a differential amplifier configured to generate the compensation bias voltage by comparing the pre-compensation signal and the second reference voltage, The voltage generating circuit is configured to generate the second reference voltage based on the internal power supply voltage and the first reference voltage, and the second reference voltage is less sensitive to changes in the internal power supply voltage than to changes in the external power supply voltage.

11. The input buffer according to claim 10, wherein: The plurality of transistors are included in the voltage generating circuit and include: a first transistor configured to receive the internal power supply voltage through a source terminal thereof and configured as a diode-connected transistor whose gate terminal and drain terminal are coupled to each other; a second transistor which is coupled to the drain terminal of the first transistor through its source terminal and is configured as a diode-connected transistor whose gate terminal and drain terminal are coupled to each other; and a third transistor coupled between the second transistor and a ground voltage terminal and configured to operate according to the first reference voltage, Here, the voltage generating circuit limits a change in a level of the second reference voltage generated through the drain terminal of the second transistor as a threshold voltage of the second transistor increases according to an increase in a level of the internal power supply voltage.

12. The input buffer according to claim 11, wherein The internal supply voltage is applied to a body terminal of at least one of the first transistor and the second transistor.

13. The input buffer according to claim 11, further comprising: A fourth transistor is coupled between the third transistor and the ground voltage terminal.

14. The input buffer according to claim 13, wherein: The fourth transistor is configured as a diode-connected transistor whose gate terminal and drain terminal are coupled to each other.

15. The input buffer according to claim 13, wherein: A ground voltage is applied to a body terminal of the fourth transistor.

Images