Packaging structure and manufacturing method thereof

Abstract

A packaging structure includes at least one semiconductor die, an insulating sealant, and a rewiring structure. The at least one semiconductor die has a plurality of conductive pillars, wherein the top surfaces of the plurality of conductive pillars have a first roughness. The insulating sealant encapsulates the at least one semiconductor die. The rewiring structure is disposed on the insulating sealant in a stacking direction and is electrically connected to the at least one semiconductor die. The rewiring structure includes: a plurality of via portions and a plurality of conductor portions, embedded in a dielectric layer, wherein the top surfaces of the plurality of conductor portions have a second roughness, and the second roughness is greater than the first roughness.

Description

Technical Field

[0001] The disclosed embodiments relate to a packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices and integrated circuits are typically manufactured on a single semiconductor wafer. The die of the wafer can be processed at the wafer level and packaged with other semiconductor devices or dies, and various technologies have been developed for wafer level packaging (WLP). In addition, such a package can also be integrated into a semiconductor substrate or carrier after dicing. Therefore, the reliability of the electrical connection between the conductive terminals within each package and the internal components (e.g., redistribution wiring structures) is critical. Summary of the invention

[0003] The embodiment of the present disclosure provides a packaging structure, which includes at least one semiconductor die, an insulating sealant, and a rewiring structure. The at least one semiconductor die has a plurality of conductive pillars, wherein the top surfaces of the plurality of conductive pillars have a first roughness. The insulating sealant encapsulates the at least one semiconductor die. The rewiring structure is arranged on the insulating sealant in the stacking direction and is electrically connected to the at least one semiconductor die. The rewiring structure includes: a plurality of via portions and a plurality of conductor portions, which are embedded in a dielectric layer, wherein the top surfaces of the plurality of conductor portions have a second roughness, and the second roughness is greater than the first roughness.

[0004] The embodiment of the present disclosure provides a method for manufacturing a packaging structure. The method includes the following steps. A plurality of semiconductor dies are provided on a carrier, wherein the plurality of semiconductor dies include a plurality of conductive pillars. An insulating sealant is formed to encapsulate the plurality of semiconductor dies, wherein the top surface of the insulating sealant is substantially flush with the top surface of the plurality of conductive pillars. A cleaning process is performed on the plurality of conductive pillars, wherein the cleaning process includes a first cleaning step of using a first solution to clean the top surface of the plurality of conductive pillars for 20 seconds to 80 seconds, and wherein after the cleaning process, the top surface of the plurality of conductive pillars has a first roughness. A rewiring structure is formed on the insulating sealant in the stacking direction, wherein the step of forming the rewiring structure includes forming a plurality of via portions and a plurality of conductor portions embedded in a dielectric layer, and wherein the top surface of the plurality of conductor portions has a second roughness, and the second roughness is greater than the first roughness. The carrier is then peeled off.

[0005] The embodiment of the present disclosure provides a method for manufacturing a packaging structure. The method includes the following steps. At least one semiconductor die is provided on a carrier, wherein the at least one semiconductor die includes a plurality of conductive pillars. An insulating sealant is formed to encapsulate the at least one semiconductor die. A planarization process is performed by removing a portion of the insulating sealant to expose the top surfaces of the plurality of conductive pillars. After the planarization process, a single wafer spin cleaning process is performed on the plurality of conductive pillars, wherein the single wafer spin cleaning process includes dripping a first solution onto the top surfaces of the plurality of conductive pillars for 20 seconds to 80 seconds while rotating the carrier to clean the top surfaces of the plurality of conductive pillars. A rewiring structure is formed on the insulating sealant, wherein the rewiring structure is formed by the following steps. A plurality of conductor portions, a plurality of first through-hole portions, and a plurality of dielectric layers are formed which are alternately stacked, wherein the plurality of first through-hole portions are formed with a lateral dimension that is kept constant from a first end of the first through-hole portion to a second end of the first through-hole portion, and after forming each of the plurality of first through-hole portions, a through-hole cleaning process is performed on a surface of the second end, the through-hole cleaning process comprising dropping the first solution onto the surface of the second end of the first through-hole portion for 20 seconds to 80 seconds while rotating the carrier to clean the surface of the second end. The carrier is then peeled off. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A to Figure 1K are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure.

[0008] Figure 2A to Figure 2C are enlarged cross-sectional views of a semiconductor die at various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure.

[0009] Figure 3 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0010] Figure 4 is a schematic cross-sectional view of a package-on-package (PoP) structure according to some exemplary embodiments of the present disclosure.

[0011] Figure 5is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0012] Figure 6 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0013] Figure 7 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0014] Figure 8 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0015] Fig. 9 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure.

[0016] [Explanation of Symbols]

[0017] 102: Carrier

[0018] 104: Buffer layer

[0019] 104A: Peeling layer

[0020] 104B: Dielectric layer

[0021] 105: Die bonding film

[0022] 106A: first semiconductor die / semiconductor die

[0023] 106a-AS, 106b-AS: effective surface

[0024] 106a-BS, 106b-BS: Back surface

[0025] 106a-1, 106b-1: semiconductor substrate

[0026] 106a-2, 106b-2: Conductive pads

[0027] 106a-3, 106b-3: Passivation layer

[0028] 106a-4, 106b-4: Conductive pillars

[0029] 106a-4-TS, 106a-AM-TS, 106b-4-TS, 106b-AM-TS, 108-TS, 110-TS, 112-B-TS, 112-C-TS, 112-V-TS: Top surface

[0030] 106a-5, 106b-5: Protective layer

[0031] 106a-AM, 106b-AM: Alignment mark

[0032] 106B, 106B': second semiconductor die / semiconductor die

[0033] 108: Hole through insulation layer

[0034] 110: Insulation material

[0035] 110': Insulation seal

[0036] 112-Bx, 112-Cx: Conductor

[0037] 112-D: Second dielectric layer / dielectric layer

[0038] 112-Vx: First through hole portion

[0039] 112-V1, 112-W1: First end

[0040] 112-V2, 112-W2: Second end

[0041] 112-Wx: Second through hole portion

[0042] 114, 250: Conductive pads

[0043] 116, 118, 270: Conductive ball

[0044] 210: Substrate

[0045] 220: Semiconductor chips

[0046] 230: Binding line

[0047] 240: Pad

[0048] 260: Insulation seal

[0049] 280: Bottom filling glue

[0050] 301: belt

[0051] 302: Framework

[0052] DR1: Deposition direction

[0053] LD1, LD2: lateral dimensions

[0054] M1: First metal layer / metal layer

[0055] M2: Second metal layer / metal layer

[0056] M3: The third metal layer / metal layer

[0057] Mx: Solder layer

[0058] Pk2: Second package

[0059] PoP: Package on Package

[0060] PS1, PS2, PS3, PS4, PS5, PS6, PS7: packaging structure

[0061] RDL1: First redistribution layer

[0062] RDL2: Second redistribution layer

[0063] RDS: Rewired Structure

[0064] Rh: Groove height

[0065] Rx: Groove

[0066] SD1: Planar seed layer

[0067] SD2: Non-planar seed layer

[0068] SN1: First Solution

[0069] SN2: Second Solution DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a second feature is formed on or on a first feature may include an embodiment in which the second feature is formed to be in direct contact with the first feature, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature may not be in direct contact with the first feature. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0071] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "on," "over," "overlying," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0072] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce costs.

[0073] Figure 1A to Figure 1K Schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure. Figure 1A , providing a carrier 102 coated with a buffer layer 104. In some embodiments, the carrier 102 may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstructed wafer for the method of manufacturing a package structure.

[0074] In some embodiments, the buffer layer 104 includes a release layer 104A and a dielectric layer 104B, wherein the release layer 104A is located between the carrier 102 and the dielectric layer 104B. In some embodiments, the release layer 104A is disposed on the carrier 102, and the material of the release layer 104A may be any material suitable for bonding the carrier 102 to an upper layer (e.g., the dielectric layer 104B) or any wafer disposed on the carrier 102 and for releasing the carrier 102 from an upper layer (e.g., the dielectric layer 104B) or any wafer disposed on the carrier 102. In some embodiments, the release layer 104A may include a release layer (e.g., a light-to-heat conversion (LTHC) layer) or an adhesive layer (e.g., an ultraviolet curable adhesive layer or a heat curable adhesive layer). In some embodiments, the dielectric layer 104B may be formed over the release layer 104A. The dielectric layer 104B may be made of a dielectric material such as benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material.

[0075] It should be noted that the materials of the carrier 102, the peeling layer 104A, and the dielectric layer 104B are not limited to the description of the embodiment. In some alternative embodiments, the dielectric layer 104B may be optionally omitted; in other words, only the peeling layer 104A is formed on the carrier 102. In some embodiments, a die attach film (not shown) for attaching to the above components may be directly formed on the peeling layer 104A.

[0076] Reference Figure 1B , after providing the buffer layer 104, a plurality of through-insulating layer holes 108 and a plurality of semiconductor dies (a first semiconductor die 106A and a second semiconductor die 106B) are provided on the buffer layer 104 above the carrier 102. In some embodiments, the through-insulating layer holes 108 are integrated fan-out ("integrated fan-out, InFO") through-holes. In one embodiment, forming the through-insulating layer holes 108 includes: forming a mask pattern (not shown) having an opening; then forming a metal material (not shown) filling the opening by electroplating or deposition; and removing the mask pattern to form the through-insulating layer holes 108 on the buffer layer 104. The material of the mask pattern may include a positive photoresist or a negative photoresist. In one embodiment, the material of the through-insulating layer holes 108 may include a metal material, such as copper or a copper alloy. However, the present disclosure is not limited thereto.

[0077] In an alternative embodiment, the through-insulating layer hole 108 may be formed by: forming a seed layer (not shown) on the buffer layer 104; forming a mask pattern having an opening that exposes a portion of the seed layer; forming a metal material on the exposed portion of the seed layer by plating to form the through-insulating layer hole 108; removing the mask pattern; and then removing the portion of the seed layer exposed by the through-insulating layer hole 108. For example, the seed layer may be a titanium / copper composite layer. For simplicity, in Figure 1B Only four through-insulation layer holes 108 are shown in FIG. However, it should be noted that the number of through-insulation layer holes 108 is not limited thereto and can be selected according to requirements.

[0078] like Figure 1B As shown in , the first semiconductor die 106A and the second semiconductor die 106B can be picked up and placed on the buffer layer 104. In some embodiments, the first semiconductor die 106A has an active surface 106a-AS and a backside surface 106a-BS opposite to the active surface 106a-AS. For example, the backside surface 106a-BS of the first semiconductor die 106A can be attached to the buffer layer 104 through the die attach film 105. Similarly, the second semiconductor die 106B has an active surface 106b-AS and a backside surface 106b-BS opposite to the active surface 106b-AS. For example, the backside surface 106b-BS of the second semiconductor die 106B can be attached to the buffer layer 104 through the die attach film 105. By using the die attach film 105, better attachment between the first semiconductor die 106A, the second semiconductor die 106B and the buffer layer 104 is ensured. In the exemplary embodiment, only two semiconductor dies (106A / 106B) are shown. However, the present disclosure is not limited thereto. It should be noted that the number of semiconductor dies (106A / 106B) disposed on the buffer layer 104 may be adjusted based on product requirements.

[0079] In an exemplary embodiment, the first semiconductor die 106A and the second semiconductor die 106B respectively include a semiconductor substrate (106a-1 / 106b-1), a plurality of conductive pads (106a-2 / 106b-2), a passivation layer (106a-3 / 106b-3), a plurality of conductive pillars (106a-4 / 106b-4), a protection layer (106a-5 / 106b-5), and an alignment mark (106a-AM / 106b-AM). Figure 1BAs shown in , the plurality of conductive pads (106a-2 / 106b-2) are disposed on a semiconductor substrate (106a-1 / 106b-1). A passivation layer (106a-3 / 106b-3) is formed on the semiconductor substrate (106a-1 / 106b-1) and has an opening that partially exposes the conductive pads (106a-2 / 106b-2) on the semiconductor substrate (106a-1 / 106b-1). The semiconductor substrate (106a-1 / 106b-1) may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and also includes active components (e.g., transistors, etc.) and optional passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. The conductive pads (106a-2 / 106b-2) may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer (106a-3 / 106b-3) may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed by any suitable dielectric material. In addition, in some embodiments, a post-passivation layer (not shown) is optionally formed on the passivation layer (106a-3 / 106b-3). The post-passivation layer covers the passivation layer (106a-3 / 106b-3) and has a plurality of contact openings. The conductive pad (106a-2 / 106b-2) is partially exposed by the contact opening of the post-passivation layer. The post-passivation layer may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers. In some embodiments, the conductive column (106a-4 / 106b-4) is formed on the conductive pad (106a-2 / 106b-2) by plating. In some embodiments, along with the formation of the conductive pillars (106a-4 / 106b-4), alignment marks (106a-AM / 106b-AM) may be formed on the passivation layer (106a-3 / 106b-3). For example, the alignment marks (106a-AM / 106b-AM) and the conductive pillars (106a-4 / 106b-4) are formed of the same material. In some embodiments, a protective layer (106a-5 / 106b-5) is formed on the passivation layer (106a-3 / 106b-3) or on the post-passivation layer and covers the conductive pillars (106a-4 / 106b-4) and the alignment marks (106a-AM / 106b-AM) to protect these components.

[0080] In some embodiments, when a plurality of semiconductor dies (106A / 106B) are placed on the buffer layer 104, the semiconductor dies (106A / 106B) may then be arranged in an array, and when the semiconductor dies (106A / 106B) are arranged in an array, the through-insulating layer holes 108 may be classified into groups. The number of semiconductor dies (106A / 106B) may correspond to the number of groups of through-insulating layer holes 108. In the illustrated embodiment, the semiconductor dies (106A / 106B) may be picked up and placed on the buffer layer 104 after the through-insulating layer holes 108 are formed. However, the present disclosure is not limited thereto. In some alternative embodiments, the semiconductor dies (106A / 106B) may be picked up and placed on the buffer layer 104 before the through-insulating layer holes 108 are formed.

[0081] In addition, in some embodiments, the first semiconductor die 106A and the second semiconductor die 106B may be selected from an application-specific integrated circuit (ASIC) chip, an analog chip (e.g., a wireless and radio frequency chip), a digital chip (e.g., a baseband chip), an integrated passive device (IPD), a voltage regulator chip, a sensor chip, a memory chip, etc. For example, in one embodiment, the first semiconductor die 106A and the second semiconductor die 106B may be the same type of semiconductor die. In an alternative embodiment, the first semiconductor die 106A and the second semiconductor die 106B may be different types of semiconductor die. The present disclosure is not limited thereto.

[0082] Reference Figure 1C In the next step, an insulating material 110 is formed on the buffer layer 104 and on the semiconductor die (106A / 106B). In some embodiments, the insulating material 110 is formed to cover the through-insulating layer hole 108. In some embodiments, the insulating material 110 is formed by, for example, a compression molding process, filling the gap between the semiconductor die (106A / 106B) and the through-insulating layer hole 108 to encapsulate the semiconductor die (106A / 106B). The insulating material 110 also fills the gap between adjacent through-insulating layer holes 108 to encapsulate the through-insulating layer hole 108. At this stage, the conductive pillars (106a-4 / 106b-4), the protective layer (106a-5 / 106b-5), the alignment marks (106a-AM / 106b-AM) and the through-insulating layer hole 108 are encapsulated by the insulating material 110 and well protected. In other words, the conductive pillars ( 106 a - 4 / 106 b - 4 ), the alignment marks ( 106 a -AM / 106 b -AM) and the through-insulation-layer vias 108 are not exposed.

[0083] In some embodiments, the insulating material 110 includes a polymer (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material having low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In alternative embodiments, the insulating material 110 may include an acceptable insulating sealant material. In some embodiments, the insulating material 110 may also include an inorganic filler or inorganic compound (e.g., silica, clay, etc.) that can be added to the insulating material 110 to optimize the coefficient of thermal expansion (CTE) of the insulating material 110. The present disclosure is not limited thereto.

[0084] Reference Figure 1D In some embodiments, the insulating material 110 is partially removed to expose the conductive pillar (106a-4 / 106b-4), the alignment mark (106a-AM / 106b-AM) and the through-insulating layer hole 108. In some embodiments, the insulating material 110 and the protective layer (106a-5 / 106b-5) are ground or polished by a planarization step. For example, the planarization step is performed by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process until the top surface (106a-4-TS / 106b-TS) of the conductive pillar (106a-4 / 106b-4) and the top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM) are exposed. In some embodiments, the through-insulation hole 108 may be partially polished so that the top surface 108-TS of the through-insulation hole 108 is substantially flush with the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4) and the top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM), or substantially flush with the active surface (106a-AS / 106b-AS) of the first semiconductor die 106A and the second semiconductor die 106B. In other words, the conductive pillar (106a-4 / 106b-4), the alignment mark (106a-AM / 106b-AM) and the through-insulation hole 108 may also be lightly ground / polished. In the illustrated embodiment, the insulating material 110 is polished to form an insulating seal 110'.

[0085] Reference Figure 1EIn some embodiments, after the mechanical grinding or chemical mechanical polishing (CMP) step, a cleaning process may be performed. For example, a cleaning process is performed to clean and remove residues generated by the planarization step, and to form a substantially flat and smooth surface. In some embodiments, the cleaning process includes a first cleaning step of using a first solution SN1 to clean the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4), clean the top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM), and clean the top surface 108-TS of the through-insulation layer hole 108 for 20 seconds to 80 seconds. For example, in some embodiments, a single wafer spin cleaning process is performed as a first cleaning step to clean the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4) by dropping the first solution SN1 onto the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4) for 20 seconds to 80 seconds while rotating the carrier 102. The top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM) and the top surface 108-TS of the through-insulation layer hole 108 may be cleaned in a similar manner to the single wafer spin cleaning process. In some embodiments, the first cleaning step is performed using the first solution SN1 for at least 20 seconds to ensure that the roughness of the applied surface is reduced to a certain extent, and the first cleaning step is performed using the first solution SN1 for less than 80 seconds to prevent excessive etching or damage to the applied surface.

[0086] In some embodiments, the pH of the first solution SN1 is in the range of pH 0.5 to pH 5. In some embodiments, the first solution SN1 includes at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid. In some embodiments, the concentration of the acid is in the range of 0.05 weight percent to 10 weight percent. In some alternative embodiments, the first solution SN1 includes at least one amine solution selected from the group consisting of ethanolamine, hydroxyethylethylenediamine, ammonium hydroxide and ammonium chloride. In some embodiments, the concentration of the amine solution is in the range of 10 weight percent to 35 weight percent. In certain embodiments, the above-mentioned acid and amine solution can be used alone or in combination in the first solution SN1. In an exemplary embodiment, the first solution SN1 is a citric acid solution.

[0087] In addition, in some embodiments, the cleaning process may optionally include a second cleaning step of using a second solution SN2 to clean the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4), clean the top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM), and clean the top surface 108-TS of the through-insulating layer hole 108 for 20 to 80 seconds. For example, in some embodiments, another single wafer spin cleaning process may be performed to clean the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4) by dripping the second solution SN2 onto the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4) for 20 seconds to 80 seconds while rotating the carrier 102. The top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM) and the top surface 108-TS of the through-insulation layer hole 108 may be cleaned in a similar manner to the single wafer spin cleaning process. In some embodiments, the second cleaning step is performed using the second solution SN2 for at least 20 seconds to ensure that the roughness of the applied surface is reduced to a certain extent, and the second cleaning step is performed using the second solution SN2 for less than 80 seconds to prevent excessive etching or damage to the applied surface.

[0088] In some embodiments, the pH of the second solution SN2 is in the range of pH 1.5 to pH 6. In some embodiments, the second solution SN2 includes at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid. In some embodiments, the concentration of the acid is in the range of 0.01 weight percent to 3 weight percent. In some alternative embodiments, the second solution SN2 includes at least one amine solution selected from the group consisting of ethanolamine, hydroxyethylethylenediamine, ammonium hydroxide and ammonium chloride. In some embodiments, the concentration of the amine solution is in the range of 10 weight percent to 35 weight percent. In certain embodiments, the above-mentioned acid and amine solution can be used alone or in combination in the second solution SN2. In some embodiments, the second solution SN2 can be the same as the first solution SN1. In alternative embodiments, the second solution SN2 can be different from the first solution SN1.

[0089] After performing a cleaning process (single wafer spin cleaning process), the top surfaces (106a-4-TS / 106b-4-TS) of the plurality of conductive pillars (106a-4 / 106b-4) may have a roughness Rg1. In some embodiments, before the cleaning process, the roughness of the top surfaces (106a-4-TS / 106b-4-TS) of the plurality of conductive pillars (106a-4 / 106b-4) is in the range of 1.5 μm to 5 μm. In certain embodiments, after the cleaning process, the roughness Rg1 is in the range of 0.1 μm to 1 μm. In some embodiments, the top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM) may have a roughness Rg2, and the top surface 108-TS of the through-insulation layer hole 108 may have a roughness Rg3. For example, the roughness Rg2 and the roughness Rg3 may be substantially equal to the roughness Rg1. In some embodiments, after the cleaning process, the top surface 110-TS of the insulating seal 110', the top surface 108-TS of the through-insulating layer hole 108, the top surface (106a-4-TS / 106b-4-TS) of the conductive pillar (106a-4 / 106b-4), the top surface (106a-AM-TS / 106b-AM-TS) of the alignment mark (106a-AM / 106b-AM), and the top surface of the polished protection layer (106a-5 / 106b-5) are substantially coplanar and flush with each other.

[0090] Figure 1F FIG. 1 is an enlarged cross-sectional view of semiconductor die 106A after a cleaning process according to some other embodiments of the present disclosure. Figure 1G As shown in , in some embodiments, after the cleaning process, there may be a groove Rx in the protection layer 106a-5. In other words, there may be a step height difference between the protection layer 106a-5 and the conductive pillar 106a-4. In some embodiments, the groove Rx may have a groove height Rh in the range of 0.1 μm to 5.0 μm. However, the present disclosure is not limited to this. In some alternative embodiments, there is no groove in the protection layer 106a-5, and the protection layer 106a-5 and the conductive pillar 106a-4 are substantially coplanar.

[0091] Reference Figure 1G and Figure 1H , describing the steps of forming a redistribution structure on the insulating sealing body 110'. Figure 1GAs shown in , in the first step, a plurality of via portions (first via portions 112-Vx) are formed on the conductive pillars (106a-4 / 106b-4) and on the through-insulating layer holes 108 in the build-up direction DR1. In some embodiments, the via portions (first via portions 112-Vx) are formed by forming a planar seed layer SD1 on the insulating seal 110'; forming a mask pattern having an opening that exposes a portion of the planar seed layer SD1; forming a conductive material on the exposed portion of the planar seed layer SD1 to form the via portions (first via portions 112-Vx) by plating; removing the mask pattern; and then removing the portion of the planar seed layer SD1 exposed by the via portion (first via portion 112-Vx). Thereafter, a dielectric material (not shown) may be formed to cover the via portion (first via portion 112-Vx), wherein the dielectric material is further ground or polished by a planarization step to form a dielectric layer 112-D. In some embodiments, the planarization step is performed by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process until a top surface 112-V-TS of the via portion (first via portion 112-Vx) is exposed.

[0092] In the illustrated embodiment, the via portion (first via portion 112-Vx) is formed with a lateral dimension LD1 that is constant from the first end 112-V1 of the via portion (first via portion 112-Vx) to the second end 112-V2 of the via portion (first via portion 112-Vx) in the build-up direction DR1. In some embodiments, after the planarization step, a via cleaning process (e.g., a single wafer spin cleaning process) may be performed to clean the top surface 112-V-TS of the second end 112-V2 of the via portion (first via portion 112-Vx) using the first solution SN1 for 20 seconds to 80 seconds to form a substantially flat and smooth surface. In certain embodiments, another via cleaning process (e.g., a single wafer spin cleaning process) may be optionally performed to clean the top surface 112-V-TS of the second end 112-V2 of the via portion using the second solution SN2 for 20 seconds to 80 seconds to form a substantially flat and smooth surface. The first solution SN1 and the second solution SN2 mentioned here are Figure 1E The first solution SN1 and the second solution SN2 mentioned in the above are the same, so their detailed description will be omitted here. After the through-hole cleaning process, the top surface 112-V-TS of the second end 112-V2 of the through-hole portion (the first through-hole portion 112-Vx) may have a roughness Rg4. For example, the roughness Rg4 after the through-hole cleaning process is in the range of 0.1 μm to 1 μm. In some embodiments, the roughness Rg4 may be substantially equal to the roughness Rg1.

[0093] Reference Figure 1HIn the next step, a plating and planarization process can be performed similar to the above Figure 1G In the manner described in , a planar seed layer SD1, a plurality of conductive body portions 112-Bx, a plurality of via portions (first via portions 112-Vx) and a second dielectric layer 112-D are formed and stacked in the stacking direction DR1. In an exemplary embodiment, after the planarization process, a top surface 112-V-TS of the via portion (first via portion 112-Vx) embedded in the second dielectric layer 112-D is exposed. Thereafter, the same via cleaning process may be performed to clean the surface of the uppermost via portion (first via portion 112-Vx) by using a first solution SN1 for cleaning and an optional second solution SN1. In this way, after the via cleaning process, the top surface 112-V-TS of the second end 112-V2 of the via portion (first via portion 112-Vx) may have a roughness Rg4. On the other hand, since the top surface 112-B-TS of the conductive body portion 112-Bx is covered by the dielectric layer 112-D and is not cleaned by the through-hole cleaning process, it may have a roughness Rg5, wherein the roughness Rg5 is greater than the roughness Rg4. In some embodiments, the roughness Rg1, the roughness Rg2, the roughness Rg3, and the roughness Rg4 are all less than the roughness Rg5.

[0094] Reference Fig. 1I , in some embodiments, then the formation may be repeated Figure 1G and Figure 1H The planar seed layer SD1, the via portion (the first via portion 112-Vx), the conductive body portion 112-Bx and the dielectric layer 112-D described in the embodiment are stacked alternately in the stacking direction DR1 to form the redistribution structure RDS. In some embodiments, the planar seed layer SD1, the via portion (the first via portion 112-Vx), the conductive body portion 112-Bx and the dielectric layer 112-D are stacked alternately in the stacking direction DR1 to form the redistribution structure RDS. In addition, in an exemplary embodiment, all the via portions (the first via portion 112-Vx) may have a top surface 112-V-TS having a roughness Rg4, and the conductive body portion 112-Bx may have a top surface 112-B-TS having a roughness Rg5, and the roughness Rg4 is less than the roughness Rg5. In some embodiments, a portion of the planar seed layer SD1 may be disposed on the via portion (the first via portion 112 -Vx) and physically contact the via portion (the first via portion 112 -Vx).

[0095] like Fig. 1IAs shown in , although three layers of via portions (first via portions 112-Vx) / conductor portions 112-Bx and four layers of dielectric layers 112-D are shown herein, the scope of the present disclosure is not limited thereto. In other embodiments, the number of layers of via portions (first via portions 112-Vx) / conductor portions 112-Bx and dielectric layers 112-D may be adjusted based on product requirements. In some embodiments, the redistribution structure RDS is electrically connected to the through-insulation layer hole 108 and the semiconductor die (106A / 106B) through the via portions (first via portions 112-Vx) and the conductor portions 112-Bx.

[0096] In an exemplary embodiment, the material of the dielectric layer 112-D may be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, etc., which can be patterned using photolithography and / or etching processes. In some embodiments, the material of the dielectric layer 112-D may be formed by a suitable fabrication technique (e.g., spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.). The present disclosure is not limited thereto.

[0097] Furthermore, in some embodiments, the material of the via portion (first via portion 112-Vx) and the conductor portion 112-Bx may be made of a conductive material formed by electroplating or deposition (e.g., aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof that can be patterned using photolithography and etching processes). Throughout the specification, the term "copper" is intended to include substantially pure elemental copper, copper containing inevitable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0098] Still refer to Fig. 1I After forming the redistribution structure RDS, a plurality of conductive pads 114 for electrical connection with conductive balls (or conductive bumps) may be provided on the exposed top surface of the topmost layer of the conductive body portion 112-Bx. In some embodiments, the conductive pads 114 are, for example, under-ball metallurgy (UBM) patterns for ball mounting. Fig. 1IAs shown in , the conductive pad 114 is formed on the rewiring structure RDS and is electrically connected to the rewiring structure RDS. In some embodiments, the material of the conductive pad 114 may include copper, nickel, titanium, tungsten, or alloys thereof, and the conductive pad 114 may be formed by, for example, an electroplating process. The number of the conductive pads 114 is not limited in the present disclosure and may be selected based on the design layout. In some alternative embodiments, the conductive pad 114 may be omitted. In other words, the conductive ball 116 (or conductive bump) formed in a subsequent step may be directly disposed on the rewiring structure RDS.

[0099] After forming the conductive pads 114, a plurality of conductive balls 116 are disposed on the conductive pads 114 and on the redistribution structure RDS. In some embodiments, the conductive balls 116 may be disposed on the conductive pads 114 by a ball implantation process or a reflow process. In some embodiments, the conductive balls 116 are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the conductive balls 116 are connected to the redistribution structure RDS through the conductive pads 114. In certain embodiments, some of the conductive balls 116 may be electrically connected to the semiconductor die (106A / 106B) through the redistribution structure RDS. In addition, some of the conductive balls 116 may be electrically connected to the through-insulation layer vias 108 through the redistribution structure RDS. The number of the conductive balls 116 is not limited to the present disclosure, and may be specified and selected based on the number of the conductive pads 114.

[0100] Reference Figure 1J In some embodiments, after forming the redistribution structure RDS and the conductive ball 116, Fig. 1I The structure shown in FIG. 3 is flipped over and attached to a belt 301 (eg, a cutting belt) supported by a frame 302. Figure 1J As shown in FIG. 1 , the carrier 102 is peeled off and separated from the dielectric layer 104B. In some embodiments, the peeling process includes projecting light such as laser or ultraviolet light onto the peeling layer 104A (e.g., LTHC release layer) so that the carrier 102 can be easily removed together with the peeling layer 104A. During the peeling step, before peeling the carrier 102 and the peeling layer 104A, a tape 301 is used to fix the package structure. After the peeling process, the backside surface of the dielectric layer 104B is revealed or exposed.

[0101] Reference Figure 1KIn some embodiments, after the stripping process, the dielectric layer 104B may be patterned to form a plurality of openings (not shown) exposing the bottom surface of the through-insulating layer holes 108. The number of openings formed corresponds to the number of through-insulating layer holes 108. Thereafter, a plurality of conductive balls 118 may be placed on the bottom surface of the through-insulating layer holes 108 exposed by the openings. The conductive balls 118 are, for example, reflowed to be bonded to the bottom surface of the through-insulating layer holes 108. Subsequently, a cutting process may be performed to section the entire wafer structure (cut through the redistribution structure RDS, the insulating seal 110' and the dielectric layer 104B) into a plurality of package structures PS1. At this point, the package structure PS1 with double-sided terminals according to some embodiments of the present disclosure is completed.

[0102] Figure 2A to Figure 2C is an enlarged cross-sectional view of a semiconductor die at various stages in a method of making a package structure according to some exemplary embodiments of the present disclosure. The method described here is similar to Figure 1C to Figure 1F Therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. The difference between the embodiments lies in the design of the conductive pillars (106a-4 / 106b-4). Figure 1C to Figure 1F In the embodiment shown in , the conductive pillars (106a-4 / 106b-4) are made of a single material (eg, copper pillars). However, the present disclosure is not limited thereto, and the conductive pillars (106a-4 / 106b-4) may be made of a variety of materials.

[0103] For example, refer to Figure 2A In some embodiments, before performing a planarization process (with Figure 1C ), the conductive pillar 106a-4 of the first semiconductor die 106A may include a first metal layer M1, a second metal layer M2, a third metal layer M3 and a solder layer Mx. In an exemplary embodiment, the first metal layer M1 is a copper layer, the second metal layer is a nickel layer, and the third metal layer M3 is a copper layer. In addition, at this stage, the protective layer 106a-5 completely covers the conductive pillar 106a-4.

[0104] Reference Figure 2B , a planarization step is performed to remove portions of the solder layer Mx and the third metal layer M3 so that the top surface (106a-4-TS) of the second metal layer M2 is revealed or exposed. In some embodiments, a remaining amount of the third metal layer M3 may remain on the second metal layer M2. In some embodiments, the remaining third metal layer M3 may be considered as a flank portion of the second metal layer M2. In an alternative embodiment, the third metal layer M3 may be completely removed by the planarization step. After performing the planarization step, a similar Figure 1EThe top surface 106a-4-TS of the conductive pillar 106a-4 (which is the surface of the second metal layer M2) is cleaned by the cleaning process (single wafer spin cleaning process) using the first solution SN1 (and the optional second solution SN2) described in .

[0105] Reference Figure 2C After performing a cleaning process, a conductive pillar 106a-4 having a copper layer (metal layer M1), a nickel layer (metal layer M2) and a side portion (metal layer M3) is formed. In some embodiments, the top surface (106a-4-TS) of the nickel layer (metal layer M2) has a first roughness Rg1. In some embodiments, the roughness Rg1 after the cleaning process is in the range of 0.1 μm to 1 μm. In some embodiments, the top surface (106a-4-TS) of the nickel layer (metal layer M2) is substantially coplanar with the top surface of the side portion (metal layer M3) and the top surface of the protective layer 106a-5. Thereafter, a cleaning process may be performed. Figure 1G to Figure 1K The same steps as described in the above are performed to form a redistribution structure RDS thereon and complete the formation of the packaging structure.

[0106] Figure 3 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 3 The package structure PS2 shown in Figure 1K Therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. Figure 3 The through-insulating layer hole 108 is omitted. Since the through-insulating layer hole 108 is omitted in the package structure PS2, the conductive ball 118 placed on the through-insulating layer hole 108 can also be omitted. Similar to the above-mentioned embodiment, a cleaning process (single wafer spin cleaning process) is performed to process the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM) and the surface of the first through-hole portion 112-Vx. Therefore, the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), and the surface of the first through-hole portion 112-Vx can have a smaller roughness, and the collapse problem of the through-hole or connection structure formed on the conductive pillar (106a-4 / 106b-4), the alignment mark (106a-AM / 106b-AM) and the first through-hole portion 112-Vx can be prevented.

[0107] Figure 4 is a schematic cross-sectional view of a package-on-package (PoP) structure according to some exemplary embodiments of the present disclosure. Figure 4 , when making the first package (for example Figure 1KAfter the package structure PS1 shown in FIG. 1 is formed, the second package Pk2 may be stacked on the package structure PS1 (first package) to form a package-on-package (PoP) structure. In some embodiments, the conductive balls 118 are omitted from the package structure PS1, so that the second package Pk2 may be stacked on the package structure PS1 and electrically connected to the package structure PS1 through the conductive balls 270. Figure 4 As shown in FIG. 1 , the second package Pk2 is electrically connected to the through-insulation-layer via 108 of the package structure PS1 through the conductive ball 270 .

[0108] In some embodiments, the second package Pk2 has a substrate 210, a plurality of semiconductor chips 220 mounted on one surface (e.g., top surface) of the substrate 210 and stacked on top of each other. In some embodiments, a bonding wire 230 is used to provide an electrical connection between the semiconductor chip 220 and the pad 240 (e.g., bonding pad). In some embodiments, an insulating seal 260 is formed to encapsulate the semiconductor chip 220 and the bonding wire 230 to protect these components. In some embodiments, a through-insulating layer hole (not shown) can be used to provide an electrical connection between the pad 240 and the conductive pad 250 (e.g., bonding pad), which is located on another surface (e.g., bottom surface) of the substrate 210. In some embodiments, the conductive pad 250 is electrically connected to the semiconductor chip 220 through these through-insulating layer holes (not shown). In some embodiments, the conductive pad 250 of the package structure Pk2 is electrically connected to the conductive ball 270. In some embodiments, a bottom filler 280 is further provided to fill the space between the conductive balls 270 to protect the conductive balls 270. After stacking the second package Pk2 on the package structure PS1 (first package) and providing electrical connection between the second package Pk2 and the package structure PS1 (first package), a package-on-package structure PoP may be fabricated.

[0109] Figure 5 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 5 The package structure shown in PS3 is similar to Figure 1K The package structure PS1 shown in FIG. 1 is a package structure PS1 shown in FIG. 1 , therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. The difference between the embodiments lies in the design of the second semiconductor die 106B′ and the redistribution structure RDS. Figure 5 As shown in FIG. 1 , the second semiconductor die 106B′ includes a conductive pillar 106 b - 4 having a first metal layer M1 (eg, a copper layer) and a second metal layer M2 (eg, a nickel layer). Figure 2A to Figure 2CThe semiconductor die 106B' is manufactured by the method described in For example, the top surface of the second metal layer M2 (nickel layer) can be processed using a cleaning process (single wafer spin cleaning process), and the top surface of the second metal layer M2 (nickel layer) has a first roughness Rg1.

[0110] In addition, in an exemplary embodiment, a redistribution structure RDS is formed by forming alternately stacked dielectric layers 112-D, non-planar seed layers SD2, via portions (second via portions 112-Wx), and conductive body portions 112-Cx. In some embodiments, the non-planar seed layer SD2 is conformally formed on the dielectric layer 112-D to have top surfaces located on different horizontal planes. In some embodiments, the via portion (second via portion 112-Wx) is disposed on the non-planar seed layer SD2 and contacts the non-planar seed layer SD2. In some embodiments, the lateral dimension LD2 of the via portion (second via portion 112-Wx) increases from the first end 112-W1 of the via portion (second via portion 112-Wx) to the second end 112-W2 of the via portion (second via portion 112-Wx) in the stacking direction DR1. In some embodiments, the conductive portion 112 -Cx may be directly disposed on the via portion (the second via portion 112 -Wx), and may be formed in the same step as the via portion (the second via portion 112 -Wx).

[0111] In some embodiments, the via portion (second via portion 112-Wx) and the conductor portion 112-Cx are connected to the Figure 1G to Figure 1I The via portion (first via portion 112-Vx) and the conductor portion 112-Bx are made of the same material as described above. However, in some embodiments, Figure 5 The via portion (second via portion 112-Wx) and the conductor portion 112-Cx shown in FIG. Figure 1G to Figure 1I The line width / spacing of the via portion (first via portion 112-Vx) and the conductor portion 112-Bx shown in FIG. 1 is larger than the line width / spacing of the via portion (first via portion 112-Vx) and the conductor portion 112-Bx. In addition, since the conductor portion 112-Cx and the via portion (second via portion 112-Wx) are manufactured in the same step, the through-hole cleaning process is not performed on the surface of the via portion (second through-hole portion 112-Wx). In some embodiments, the top surface 112-C-TS of the conductor portion 112-Cx is also not cleaned by the through-hole cleaning process, and therefore may have a roughness Rg5 (the same as the conductor portion 112-Bx).

[0112] Figure 6 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 6 The package structure shown in PS4 is similar to Figure 5Therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. Figure 6 The through-insulating layer hole 108 is omitted. Since the through-insulating layer hole 108 is omitted in the package structure PS4, the conductive ball 118 placed on the through-insulating layer hole 108 can also be omitted. Similar to the above-mentioned embodiment, a cleaning process (single wafer spin cleaning process) is performed to process the surface of the conductive pillar (106a-4 / 106b-4) and the surface of the alignment mark (106a-AM / 106b-AM). Therefore, the surface of the conductive pillar (106a-4 / 106b-4) and the surface of the alignment mark (106a-AM / 106b-AM) can have a smaller roughness, and the collapse problem of the through hole or connection structure formed on the conductive pillar (106a-4 / 106b-4) and the alignment mark (106a-AM / 106b-AM) can be prevented.

[0113] Figure 7 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 7 The package structure shown in PS5 is similar to Figure 1K The package structure PS1 shown in FIG. Figure 5 The package structure PS3 shown in FIG. 1 is a package structure PS3, therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. The difference between the embodiments lies in the design of the redistribution structure RDS. Figure 7 As shown in FIG. 1 , the redistribution structure RDS may include a first redistribution layer RDL1 and a second redistribution layer RDL2 stacked on the first redistribution layer RDL1 .

[0114] In some embodiments, the first redistribution layer RDL1 is composed of a dielectric layer 112-D, a non-planar seed layer SD2, a second through hole portion 112-Wx and a conductive portion 112-Cx. Figure 5 In some embodiments, the second redistribution layer RDL2 is composed of a dielectric layer 112-D, a planar seed layer SD1, a first through hole portion 112-Vx and a conductive portion 112-Bx, as shown in FIG. Figure 1A to Figure 1KIn other words, in an exemplary embodiment, the redistribution structure RDS may include via portions (first via portion 112-Vx / second via portion 112-Wx) having different designs. In some embodiments, the planar seed layer SD1 of the first redistribution layer RDL1 and the non-planar seed layer SD2 of the second redistribution layer RDL2 are separated and do not contact each other. In some embodiments, the planar seed layer SD1 is disposed on the first via portion 112-Vx and contacts the first via portion 112-Vx, while the second via portion 112-Wx is disposed on the non-planar seed layer SD2 and contacts the non-planar seed layer SD2.

[0115] Similar to the above-mentioned embodiment, a cleaning process (single wafer spin cleaning process) is performed to process the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), the surface of the through-insulating layer hole 108, and the surface of the first through-hole portion 112-Vx. Therefore, the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), the surface of the through-insulating layer hole 108, and the surface of the first through-hole portion 112-Vx can have a smaller roughness, and the collapse problem of the through hole or connection structure formed on the conductive pillar (106a-4 / 106b-4), the alignment mark (106a-AM / 106b-AM), the through-insulating layer hole 108, and the first through-hole portion 112-Vx can be prevented. In some embodiments, the plurality of conductive pillars (106a-4 / 106b-4) may have a roughness Rg1, the alignment mark (106a-AM / 106b-AM) may have a roughness Rg2, the through-insulation layer hole 108 may have a roughness Rg3, the first through-hole portion 112-Vx may have a roughness Rg4, and the conductive body portion (112-Bx / 112-Cx) may have a roughness Rg5. In an exemplary embodiment, the roughness Rg5 is greater than the roughnesses Rg1 to Rg4, and the roughnesses Rg1, Rg2, Rg3, and Rg4 may be substantially equal.

[0116] Figure 8 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 8 The package structure shown in PS6 is similar to Figure 7 Therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. Figure 8The through-insulating layer hole 108 is omitted. Since the through-insulating layer hole 108 is omitted in the package structure PS6, the conductive ball 118 placed on the through-insulating layer hole 108 can also be omitted. Similar to the above-mentioned embodiment, a cleaning process (single wafer spin cleaning process) is performed to process the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), and the surface of the first through-hole portion 112-Vx. Therefore, the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), and the surface of the first through-hole portion 112-Vx can have a smaller roughness, and the collapse problem of the through-hole or connection structure formed on the conductive pillar (106a-4 / 106b-4), the alignment mark (106a-AM / 106b-AM), and the first through-hole portion 112-Vx can be prevented.

[0117] Fig. 9 is a schematic cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Fig. 9 The package structure shown in PS7 is similar to Figure 8 The package structure PS6 shown in FIG. 1 is a package structure PS6 shown in FIG. 1 , therefore, the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted here. The difference between the embodiments lies in the design of the redistribution structure RDS. Figure 8 In the embodiment shown in , the redistribution structure RDS is formed by forming a first redistribution layer RDL1 having a second via portion 112 -Wx and then forming a second redistribution layer RDL2 having a first via portion 112 -Vx. However, the present disclosure is not limited thereto.

[0118] For example, if Fig. 9 As shown in , in some embodiments, the first redistribution layer RDL1 is composed of a dielectric layer 112-D, a planar seed layer SD1, a first through hole portion 112-Vx and a conductive body portion 112-Bx, as shown in FIG. Figure 1A to Figure 1K In some embodiments, the second redistribution layer RDL2 is composed of a dielectric layer 112-D, a non-planar seed layer SD2, a second through hole portion 112-Wx and a conductive body portion 112-Cx, as shown in FIG. Figure 5 In other words, the first redistribution layer RDL1 having the first through hole portion 112-Vx is formed and then the second redistribution layer RDL2 having the second through hole portion 112-Wx is formed. Fig. 9The rewiring structure RDS. Similar to the above-mentioned embodiment, a cleaning process (single wafer spin cleaning process) is performed to process the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), and the surface of the first through-hole portion 112-Vx. Therefore, the surface of the conductive pillar (106a-4 / 106b-4), the surface of the alignment mark (106a-AM / 106b-AM), and the surface of the first through-hole portion 112-Vx can have a smaller roughness, and the collapse problem of the through-hole or connection structure formed on the conductive pillar (106a-4 / 106b-4), the alignment mark (106a-AM / 106b-AM), and the first through-hole portion 112-Vx can be prevented.

[0119] In the above embodiment, at least one cleaning process (single wafer spin cleaning process) is performed using a specified cleaning solution (first solution / second solution) to clean the surface of the conductive column, the surface of the alignment mark, the surface of the through-insulating layer hole, and the surface of the via portion (first through-hole portion). In this way, the surface of the conductive column, the surface of the alignment mark, the surface of the through-insulating layer hole, and the surface of the via portion (first through-hole portion) can have a smaller roughness. Since the surface is smoother, the collapse problem of the through hole or connection structure formed on the conductive column, the through-insulating layer hole, and the via portion (first through-hole portion) can be prevented. Similarly, since the surface is smoother, the alignment mark will have a better alignment profile. In general, the reliability of the packaging structure can be improved.

[0120] According to some embodiments of the present disclosure, a packaging structure is provided, which includes at least one semiconductor die, an insulating sealant, and a rewiring structure. The at least one semiconductor die has a plurality of conductive pillars, wherein the top surfaces of the plurality of conductive pillars have a first roughness. The insulating sealant encapsulates the at least one semiconductor die. The rewiring structure is disposed on the insulating sealant in a stacking direction and is electrically connected to the at least one semiconductor die. The rewiring structure includes: a plurality of via portions and a plurality of conductor portions, which are embedded in a dielectric layer, wherein the top surfaces of the plurality of conductor portions have a second roughness, and the second roughness is greater than the first roughness.

[0121] In some embodiments, the package structure further comprises a through-insulation layer hole, the through-insulation layer hole is embedded in the insulating seal and electrically connected to the redistribution structure, wherein a surface of the through-insulation layer hole has a roughness substantially equal to the first roughness. In some embodiments, at least one of the plurality of conductive pillars comprises a copper layer and a nickel layer, and the nickel layer has the top surface of the first roughness.

[0122] According to some other embodiments of the present disclosure, a method for making a packaging structure is described. The method includes the following steps. A plurality of semiconductor dies are provided on a carrier, wherein the plurality of semiconductor dies include a plurality of conductive pillars. An insulating sealant is formed to encapsulate the plurality of semiconductor dies, wherein the top surface of the insulating sealant is substantially flush with the top surface of the plurality of conductive pillars. A cleaning process is performed on the plurality of conductive pillars, wherein the cleaning process includes a first cleaning step of using a first solution to clean the top surfaces of the plurality of conductive pillars for 20 seconds to 80 seconds, and wherein after the cleaning process, the top surfaces of the plurality of conductive pillars have a first roughness. A rewiring structure is formed on the insulating sealant in the stacking direction, wherein the step of forming the rewiring structure includes forming a plurality of via portions and a plurality of conductor portions embedded in a dielectric layer, and wherein the top surfaces of the plurality of conductor portions have a second roughness, and the second roughness is greater than the first roughness. The carrier is then peeled off.

[0123] In some embodiments, the pH of the first solution is in the range of pH 0.5 to pH 5. In some embodiments, the first solution is a citric acid solution. In some embodiments, the cleaning process further comprises performing a second cleaning step, wherein the second cleaning step uses a second solution to clean the top surface of the conductive pillar. In some embodiments, the second solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid, and nitric acid.

[0124] In another embodiment of the present disclosure, a method for making a packaging structure is described. The method includes the following steps. At least one semiconductor die is provided on a carrier, wherein the at least one semiconductor die includes a plurality of conductive pillars. An insulating sealant is formed to encapsulate the at least one semiconductor die. A planarization process is performed by removing a portion of the insulating sealant to expose the top surfaces of the plurality of conductive pillars. After the planarization process, a single wafer spin cleaning process is performed on the plurality of conductive pillars, wherein the single wafer spin cleaning process includes dripping a first solution onto the top surfaces of the plurality of conductive pillars for 20 seconds to 80 seconds while rotating the carrier to clean the top surfaces of the plurality of conductive pillars. A rewiring structure is formed on the insulating sealant, wherein the rewiring structure is formed by the following steps. A plurality of conductor portions, a plurality of first through-hole portions, and a plurality of dielectric layers are formed which are alternately stacked, wherein the plurality of first through-hole portions are formed with a lateral dimension that is kept constant from a first end of the first through-hole portion to a second end of the first through-hole portion, and after forming each of the plurality of first through-hole portions, a through-hole cleaning process is performed on a surface of the second end, the through-hole cleaning process comprising dropping the first solution onto the surface of the second end of the first through-hole portion for 20 seconds to 80 seconds while rotating the carrier to clean the surface of the second end. The carrier is then peeled off.

[0125] In some embodiments, the first solution includes at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid. In some embodiments, the first solution includes at least one amine solution selected from the group consisting of ethanolamine, hydroxyethylethylenediamine, ammonium hydroxide and ammonium chloride. In some embodiments, the single wafer spin cleaning process further includes: dripping a second solution onto the top surface of the plurality of conductive pillars for 20 seconds to 80 seconds while rotating the carrier to clean the top surface of the plurality of conductive pillars. In some embodiments, the second solution includes at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid.

[0126] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: at least one semiconductor die having a plurality of conductive pillars, wherein a top surface of at least one of the plurality of conductive pillars has a first roughness; an insulating sealant encapsulating the at least one semiconductor die; a redistribution structure disposed on the insulating sealant in a build-up direction, wherein the redistribution structure is electrically connected to the at least one semiconductor die and comprises: A plurality of conductive via portions and a plurality of conductive body portions are embedded in a dielectric layer, wherein the top surfaces of the plurality of conductive body portions have a second roughness, and the second roughness is greater than the first roughness, wherein the plurality of conductive via portions include a first through-hole portion, and the lateral dimension of the first through-hole portion is kept constant from the first end of the first through-hole portion to the second end of the first through-hole portion in the stacking direction, and the surface of the second end of the first through-hole portion has a third roughness, and the third roughness is less than the second roughness. 2 . The package structure according to claim 1 , wherein the plurality of via portions further comprises a second via portion, and a lateral dimension of the second via portion increases from a first end of the second via portion to a second end of the second via portion in the build-up direction.

3. The packaging structure according to claim 2, wherein the rewiring structure further comprises a plurality of planar seed layers and a plurality of non-planar seed layers separated from each other, the plurality of planar seed layers being arranged on and contacting the first through-hole portion, and the second through-hole portion being arranged on and contacting the plurality of non-planar seed layers. 4 . The packaging structure according to claim 1 , further comprising a through-insulation layer hole embedded in the insulating seal and electrically connected to the redistribution structure, wherein a surface of the through-insulation layer hole has a roughness equal to the first roughness. 5 . The package structure according to claim 1 , wherein the at least one of the plurality of conductive pillars comprises a copper layer and a nickel layer, and the nickel layer has the top surface of the first roughness.

6. A method for manufacturing a packaging structure, comprising: providing at least one semiconductor die on a carrier, wherein the at least one semiconductor die includes a conductive pillar; forming an insulating sealant encapsulating the at least one semiconductor die, and planarizing the insulating sealant to expose a top surface of the conductive pillar; performing a cleaning process on the conductive pillar, wherein the cleaning process includes a first cleaning step of cleaning the top surface of the conductive pillar using a first solution, and wherein the top surface of the conductive pillar has a first roughness after the cleaning process; A redistribution structure is formed on the insulating seal in the stacking direction, wherein the step of forming the redistribution structure includes forming a plurality of via portions and a plurality of conductive portions embedded in the dielectric layer, wherein the top surfaces of the plurality of conductive portions have a second roughness, and the second roughness is greater than the first roughness, wherein the step of forming the via portion comprises: forming a first via portion, the first via portion having a lateral dimension that is constant from a first end of the first via portion to a second end of the first via portion in the build-up direction, and performing a via cleaning process, the via cleaning process using the first solution to clean a surface of the second end of the first via portion, and wherein after the via cleaning process, the surface of the second end of the first via portion has a third roughness, and the third roughness is less than the second roughness; and The carrier is peeled off. 7 . The method for manufacturing a package structure according to claim 6 , wherein the first solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid. 8 . The method for manufacturing a package structure according to claim 6 , wherein the first solution comprises at least one amine solution selected from the group consisting of ethanolamine, hydroxyethylethylenediamine, ammonium hydroxide and ammonium chloride. 9 . The method for manufacturing a package structure according to claim 6 , wherein the pH of the first solution is in the range of pH 0.5 to pH 5. 10 . The method for manufacturing a package structure according to claim 6 , wherein the cleaning process further comprises performing a second cleaning step, wherein the second cleaning step uses a second solution to clean the top surface of the conductive pillar. 11 . The method for manufacturing a package structure according to claim 10 , wherein the second solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid.

12. A method for manufacturing a packaging structure, comprising: providing at least one semiconductor die on a carrier, wherein the at least one semiconductor die comprises a plurality of conductive pillars; forming an insulating seal encapsulating the at least one semiconductor die; performing a planarization process to remove a portion of the insulating seal and expose top surfaces of the plurality of conductive pillars; performing a single wafer spin cleaning process on the plurality of conductive pillars after the planarization process, wherein the single wafer spin cleaning process includes dropping a first solution onto the top surfaces of the plurality of conductive pillars for 20 seconds to 80 seconds while rotating the carrier to perform a cleaning process on the top surfaces of the plurality of conductive pillars, wherein the top surfaces of the plurality of conductive pillars have a first roughness after the cleaning process; as well as A redistribution structure is formed on the insulating seal, wherein the step of forming the redistribution structure comprises: forming a plurality of conductive body portions, a plurality of first through-hole portions, and a plurality of dielectric layers that are alternately stacked, wherein top surfaces of the plurality of conductive body portions have a second roughness that is greater than the first roughness, the plurality of first through-hole portions are formed with a lateral dimension that is constant from a first end of the plurality of first through-hole portions to a second end of the plurality of first through-hole portions, and after forming each of the plurality of first through-hole portions, a through-hole cleaning process is performed on a surface of the second end, the through-hole cleaning process comprising dropping the first solution onto the surface of the second end of the first through-hole portion for 20 seconds to 80 seconds while rotating the carrier to clean the surface of the second end, wherein after the through-hole cleaning process, the surface of the second end of the plurality of first through-hole portions has a third roughness that is less than the second roughness; and The carrier is peeled off. 13 . The method for manufacturing a package structure according to claim 12 , wherein the first solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid, and nitric acid. 14 . The method for manufacturing a package structure according to claim 12 , wherein the first solution comprises at least one amine solution selected from the group consisting of ethanolamine, hydroxyethylethylenediamine, ammonium hydroxide and ammonium chloride.

15. The method for manufacturing a packaging structure according to claim 12, further comprising: A plurality of second via portions are formed alternately stacked with the plurality of conductor portions and the plurality of dielectric layers, wherein the plurality of second via portions are formed with lateral dimensions increasing from first ends of the plurality of second via portions to second ends of the plurality of second via portions.

16. The method for manufacturing a packaging structure according to claim 12, wherein the single wafer spin cleaning process further comprises: A second solution is dropped onto the top surfaces of the plurality of conductive pillars for 20 seconds to 80 seconds while rotating the carrier to clean the top surfaces of the plurality of conductive pillars. 17 . The method for manufacturing a package structure according to claim 16 , wherein the second solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid.

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