Semiconductor Devices

Abstract

The present invention provides a semiconductor device, comprising: a first active pattern and a second active pattern, which extend in a first direction on a substrate; a first gate electrode and a second gate electrode, which extend in a second direction to intersect with the first active pattern and the second active pattern; a first source / drain contact, which extends in the second direction and is respectively connected to a first source / drain region of the first active pattern and a second source / drain region of the second active pattern; a first source / drain path, which is connected to the first source / drain contact; a first unit separation film, which extends in the second direction and intersects with the first active pattern and the second active pattern, between the first source / drain contact and the second gate electrode; a first gate path, which is connected to the second gate electrode and is arranged along the first direction together with the first source / drain path; and a first connecting wiring, which extends in the first direction and connects the first source / drain path and the first gate path.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device, a layout design method for the semiconductor device, and a method for manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices have attracted attention as important elements in the electronics industry due to characteristics such as miniaturization, multi-functions, and / or low manufacturing costs. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that perform arithmetic processing on logic data, and hybrid semiconductor devices including storage elements and logic elements, etc.

[0003] As the electronics industry is highly developed, the requirements for the characteristics of semiconductor devices are increasing. For example, the requirements for high reliability, high speed and / or multifunctionality of semiconductor devices are increasing. In order to meet these desired characteristics, the structures in semiconductor devices are becoming more and more complex and highly integrated. Summary of the invention

[0004] Aspects of the inventive concept provide a semiconductor device in which use of top wiring is reduced, and power loss and PnR (Place and Routing) resource loss are reduced.

[0005] Aspects of the inventive concept also provide a layout design method for a semiconductor device, in which use of top wiring is reduced, and power loss and PnR resource loss are reduced.

[0006] Aspects of the inventive concept also provide a method for manufacturing a semiconductor device, in which use of top wiring is reduced, and power loss and PnR resource loss are reduced.

[0007] However, aspects of the inventive concept are not limited to the aspects set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept pertains by referring to the detailed description of the inventive concept given below.

[0008] According to one aspect of the inventive concept, a semiconductor device includes: a substrate; a first active pattern extending in a first direction on the substrate; a second active pattern extending in the first direction on the substrate; a first gate electrode extending in a second direction, the second direction intersecting with the first direction, the first gate electrode intersecting with the first active pattern and the second active pattern; a first source / drain contact extending in the second direction on one side of the first gate electrode, the first source / drain contact connected to a first source / drain region of the first active pattern and a second source / drain region of the second active pattern; a first source / drain path connected to the first source / drain contact; a second gate electrode extending in the second direction, the second gate electrode intersecting with the first active pattern and the second active pattern; a first cell separation film extending in the second direction between the first source / drain contact and the second gate electrode, the first cell separation film intersecting with the first active pattern and the second active pattern; a first gate path connected to the second gate electrode and arranged along the first direction together with the first source / drain path; and a first connecting wiring extending in the first direction and connecting the first source / drain path and the first gate path.

[0009] According to an aspect of the inventive concept, a semiconductor device includes a first cell region and second and third cell regions, the second and third cell regions being respectively disposed at both sides of the first cell region in a first direction. The semiconductor device further includes: a first active region and a second active region, which extend in a first direction on the first unit region, the second unit region and the third unit region, and the second active region is spaced apart from the first active region in a second direction intersecting the first direction; a first gate electrode, which extends in the second direction in the first unit region; a first source / drain contact, which extends in the second direction on one side of the first gate electrode in the first unit region, and the first source / drain contact is connected to the first active region and the second active region; a second gate electrode, which extends in the second direction in the second unit region; a second source / drain contact, which is on one side of the second gate electrode in the second unit region; a first connecting wiring, which extends in the first direction and is connected to the second source / drain contact and the first gate electrode; a third gate electrode, which extends in the second direction in the third unit region; and a second connecting wiring, which extends in the first direction and is connected to the first source / drain contact and the third gate electrode, and the second connecting wiring and the first connecting wiring are spaced apart from each other in the second direction in the first unit region.

[0010] According to one aspect of the inventive concept, a semiconductor device includes: a first active pattern and a second active pattern, each of which extends in a first direction on a substrate, each of the first active pattern and the second active pattern including a plurality of line patterns sequentially stacked on the substrate and spaced apart from each other; a first gate electrode extending in a second direction, the second direction intersecting the first direction, the first gate electrode intersecting the first active pattern and the second active pattern; an input wiring connected to the first gate electrode and extending in the first direction; a source / drain contact extending in the second direction and connected to a first source / drain region of the first active pattern and a second source / drain region of the second active pattern at one side of the first gate electrode; a second gate electrode extending in the second direction and intersecting the first active pattern and the second active pattern; a cell separation film extending in the second direction between the first gate electrode and the second gate electrode, the cell separation film intersecting the first active pattern and the second active pattern; and a connection wiring extending in a straight line in the first direction and connected to the source / drain contact and the first gate electrode. The connection wiring and the input wiring may be spaced apart from each other in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the inventive concept will become more apparent by describing in detail example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0012] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments.

[0013] Figure 2 is a plan view for explaining a semiconductor device according to some embodiments. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA. Figure 4 It is along Figure 2 A cross-sectional view taken along line BB. Figure 5 It is along Figure 2 A cross-sectional view taken along line CC. Figure 6 It is along Figure 2 A cross-sectional view taken along line DD. Figure 7 It is along Figure 2 A cross-sectional view taken along line EE.

[0014] Figure 8 and Fig. 9 is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0015] Figures 10 to 14 is a layout diagram for explaining a semiconductor device according to some embodiments.

[0016] Fig.15is a plan view for explaining a semiconductor device according to some embodiments. Fig.16 It is along Fig.15 A cross-sectional view taken along line FF. Fig.17 It is along Fig.15 A cross-sectional view taken along line GG.

[0017] Fig.18 is a layout diagram for explaining a semiconductor device according to some embodiments.

[0018] Fig.19 is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments.

[0019] Fig. 20 is a flowchart for explaining a layout design method for a semiconductor device and a method of manufacturing the semiconductor device according to some embodiments.

[0020] Figure 21 to Figure 23 is a layout diagram for explaining a layout design method of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0021] In the following, reference will be made to Figures 1 to 18 Semiconductor devices according to some embodiments are described.

[0022] In the drawings of semiconductor devices according to some embodiments, although a fin field effect transistor (FinFET) including a channel region having a fin pattern shape is shown as an example, the present disclosure is not limited thereto. Of course, semiconductor devices according to some embodiments may include a tunneling field effect transistor (TFET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. In addition, semiconductor devices according to some embodiments of the inventive concept may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), and the like.

[0023] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of the present invention.

[0024] Figure 1 is a layout diagram for illustrating a semiconductor device according to some embodiments. For reference, Figure 1 It may be a layout of a standard cell provided in a cell library according to some embodiments.

[0025] Reference Figure 1, a semiconductor device according to some embodiments includes a plurality of cell regions CR1 to CR3 .

[0026] For example, a semiconductor device according to some embodiments may include a first cell region CR1 , and second and third cell regions CR2 and CR3 each disposed at both sides of the first cell region CR1 in the first direction X.

[0027] In some embodiments, the first to third cell regions CR1 to CR3 may be separated by first and second cell separation films I1a and I1b. The first and second cell separation films I1a and I1b may extend in a second direction Y intersecting the first direction X to separate the first to third cell regions CR1 to CR3.

[0028] For example, the first cell separation film I1a may extend between the first cell region CR1 and the second cell region CR2 in the second direction Y. Therefore, the first cell region CR1 and the second cell region CR2 may be separated by the first cell separation film I1a. For example, the second cell separation film I1b may extend between the first cell region CR1 and the third cell region CR3 in the second direction Y. Therefore, the first cell region CR1 and the third cell region CR3 may be separated by the second cell separation film I1b.

[0029] In addition, the semiconductor device according to some embodiments includes a first active region AR1, a second active region AR2, a plurality of gate electrodes G1 to G3, a plurality of source / drain contacts CA11 to CA33, a plurality of source / drain paths VA11 to VA33, a plurality of gate paths VB1 to VB3, a first power wiring VDD, a second power wiring VSS, and a plurality of wiring patterns M1.

[0030] The first active region AR1 and the second active region AR2 may extend side by side and may be spaced apart from each other. For example, the first active region AR1 and the second active region AR2 may extend in the first direction X, respectively. The second active region AR2 may be spaced apart from the first active region AR1 in the second direction Y. In some embodiments, the first active region AR1 and the second active region AR2 may be formed across the first to third unit regions CR1 to CR3, respectively.

[0031] In some embodiments, semiconductor elements (e.g., transistors) of different conductivity types may be formed on the first active region AR1 and the second active region AR2. Hereinafter, it will be described assuming that the first active region AR1 is a PFET region and the second active region AR2 is an NFET region. However, this is only an example, and of course, the first active region AR1 may be an NFET region and the second active region AR2 may be a PFET region.

[0032] The plurality of gate electrodes G1 to G3 may intersect the first active region AR1 and the second active region AR2, respectively. In addition, the plurality of gate electrodes G1 to G3 may extend side by side and may be spaced apart from each other. For example, the first gate electrode G1 to the third gate electrode G3 each extending in the second direction Y may be formed. The first gate electrode G1 to the third gate electrode G3 may be spaced apart from each other in the first direction X.

[0033] In some embodiments, the first gate electrode G1 may be formed in the first cell region CR1 , the second gate electrode G2 may be formed in the second cell region CR2 , and the third gate electrode G3 may be formed in the third cell region CR3 .

[0034] The plurality of source / drain contacts CA11 to CA33 may be disposed on both sides of the gate electrodes G1 to G3. For example, first to third source / drain contacts CA11 to CA13 disposed on both sides of the first gate electrode G1, fourth to sixth source / drain contacts CA21 to CA23 disposed on both sides of the second gate electrode G2, and seventh to ninth source / drain contacts CA31 to CA33 disposed on both sides of the third gate electrode G3 may be formed.

[0035] The first source / drain contact CA11 may be disposed in the first cell region CR1 on one side of the first gate electrode G1. In some embodiments, the first source / drain contact CA11 may connect the first active region AR1 and the second active region AR2. For example, the first source / drain contact CA11 may extend in the second direction Y and may be formed across the first active region AR1 and the second active region AR2.

[0036] The second source / drain contact CA12 and the third source / drain contact CA13 may be disposed in the first cell region CR1 on the other side of the first gate electrode G1. In some embodiments, the second source / drain contact CA12 and the third source / drain contact CA13 may be spaced apart from each other. For example, the second source / drain contact CA12 may be formed in the first active region AR1, and the third source / drain contact CA13 may be formed in the second active region AR2.

[0037] The fourth source / drain contact CA21 may be disposed in the second cell region CR2 at one side of the second gate electrode G2. In some embodiments, the fourth source / drain contact CA21 may connect the first active region AR1 and the second active region AR2.

[0038] The fifth source / drain contact CA22 and the sixth source / drain contact CA23 may be disposed at the other side of the second gate electrode G2 in the second cell region CR2. In some embodiments, the fifth source / drain contact CA22 and the sixth source / drain contact CA23 may be spaced apart from each other.

[0039] The seventh source / drain contact CA31 may be disposed in the third cell region CR3 at one side of the third gate electrode G3. In some embodiments, the seventh source / drain contact CA31 may connect the first active region AR1 and the second active region AR2.

[0040] The eighth source / drain contact CA32 and the ninth source / drain contact CA33 may be disposed in the third cell region CR3 on the other side of the third gate electrode G3. In some embodiments, the eighth source / drain contact CA32 and the ninth source / drain contact CA33 may be spaced apart from each other. For example, the eighth source / drain contact CA32 may be formed in the first active region AR1, and the ninth source / drain contact CA33 may be formed in the second active region AR2.

[0041] The plurality of source / drain vias VA11 to VA33 may be disposed to overlap with the source / drain contacts CA11 to CA33 and may be connected to the source / drain contacts CA11 to CA33. Here, the term 'overlap' means overlap in a third direction Z intersecting the first direction X and the second direction Y.

[0042] For example, the first source / drain path VA11 to the third source / drain path VA13 respectively connected to the first source / drain contact CA11 to the third source / drain contact CA13 may be formed. Furthermore, for example, the fourth source / drain path VA21 to the sixth source / drain path VA23 respectively connected to the fourth source / drain contact CA21 to the sixth source / drain contact CA23 may be formed. Furthermore, for example, the seventh source / drain path VA31 to the ninth source / drain path VA33 respectively connected to the seventh source / drain contact CA31 to the ninth source / drain contact CA33 may be formed.

[0043] The plurality of gate vias VB1 to VB3 may be disposed to overlap the gate electrodes G1 to G3 in the third direction Z, and may be connected to the gate electrodes G1 to G3.

[0044] For example, a first gate via VB1 connected to the first gate electrode G1 , a second gate via VB2 connected to the second gate electrode G2 , and a third gate via VB3 connected to the third gate electrode G3 may be formed.

[0045] The first power wiring VDD and the second power wiring VSS may extend side by side and may be spaced apart from each other. For example, each of the first power wiring VDD and the second power wiring VSS may extend in the first direction X. The second power wiring VSS may be spaced apart from the first power wiring VDD in the second direction Y. In some embodiments, the first power wiring VDD and the second power wiring VSS may be formed across the first cell region CR1 to the third cell region CR3, respectively.

[0046] In some embodiments, the first power wiring VDD may be connected to some portions of the plurality of source / drain contacts CA11 to CA33. For example, the first power wiring VDD may be arranged to overlap the second source / drain path VA12, the fifth source / drain path VA22, and the eighth source / drain path VA32 in the third direction Z. The first power wiring VDD may be connected to the second source / drain contact CA12, the fifth source / drain contact CA22, and the eighth source / drain contact CA32 through the second source / drain path VA12, the fifth source / drain path VA22, and the eighth source / drain path VA32.

[0047] In some embodiments, the second power wiring VSS may be connected to other portions of the plurality of source / drain contacts CA11 to CA33. For example, the second power wiring VSS may be arranged to overlap the third source / drain path VA13, the sixth source / drain path VA23, and the ninth source / drain path VA33 in the third direction Z. The second power wiring VSS may be connected to the third source / drain contact CA13, the sixth source / drain contact CA23, and the ninth source / drain contact CA33 through the third source / drain path VA13, the sixth source / drain path VA23, and the ninth source / drain path VA33.

[0048] The first power wiring VDD and the second power wiring VSS may provide power supply voltages. In some embodiments, a drain voltage may be applied to the first power wiring VDD, and a source voltage may be applied to the second power wiring VSS. For example, although a positive voltage (+) may be applied to the first power wiring VDD and a ground voltage GND or a negative voltage (-) may be applied to the second power wiring VSS, the present disclosure is not limited thereto.

[0049] The plurality of wiring patterns M1 may be formed between the first power wiring VDD and the second power wiring VSS. The plurality of wiring patterns M1 may be connected to other portions of the plurality of source / drain contacts CA11 to CA33 or the gate electrodes G1 to G3. For example, the plurality of wiring patterns M1 may include a first wiring IW, a first connection wiring CW1, a second connection wiring CW2, and a second wiring OW.

[0050] The first wiring IW may be connected to the second gate electrode G2. For example, the first wiring IW may be arranged to overlap with the second gate path VB2 in the third direction Z. The first wiring IW may be connected to the second gate electrode G2 through the second gate path VB2. In some embodiments, the first wiring IW may extend in a straight line in the first direction X and overlap with the second gate path VB2 in the third direction Z.

[0051] In some embodiments, the first wiring IW may be used as an input wiring that provides an input signal to the second cell region CR2 .

[0052] The first connection wiring CW1 may connect the fourth source / drain contact CA21 and the first gate electrode G1. For example, the first connection wiring CW1 may be disposed to overlap the fourth source / drain via VA21 and the first gate via VB1 in the third direction Z. The first connection wiring CW1 may be connected to the fourth source / drain contact CA21 and the first gate electrode G1 through the fourth source / drain via VA21 and the first gate via VB1.

[0053] The first connection wiring CW1 extends in the first direction X and may be formed across the second cell region CR2 and the first cell region CR1. In some embodiments, the first connection wiring CW1 may extend in a straight line in the first direction X. For example, the fourth source / drain path VA21 and the first gate path VB1 may be arranged along the first direction X. Therefore, the first connection wiring CW1 extends in a straight line in the first direction X and may overlap with the fourth source / drain path VA21 and the first gate path VB1 in the third direction Z.

[0054] In some embodiments, the first connection wiring CW1 receives an output signal from the second cell region CR2 and may provide it as an input signal to the first cell region CR1. That is, the first connection wiring CW1 may serve as an output wiring of the second cell region CR2 and as an input wiring of the first cell region CR1.

[0055] The second connection wiring CW2 may connect the first source / drain contact CA11 and the third gate electrode G3. For example, the second connection wiring CW2 may be disposed to overlap the first source / drain via VA11 and the third gate via VB3 in the third direction Z. The second connection wiring CW2 may be connected to the first source / drain contact CA11 and the third gate electrode G3 through the first source / drain via VA11 and the third gate via VB3.

[0056] The second connection wiring CW2 extends in the first direction X and may be formed across the first cell region CR1 and the third cell region CR3. In some embodiments, the second connection wiring CW2 may extend in a straight line in the first direction X. For example, the first source / drain path VA11 and the third gate path VB3 may be arranged along the first direction X. As a result, the second connection wiring CW2 extends in a straight line in the first direction X and may overlap with the first source / drain path VA11 and the third gate path VB3 in the third direction Z.

[0057] In some embodiments, the second connection wiring CW2 may receive an output signal from the first cell region CR1 and provide it as an input signal to the third cell region CR3. That is, the second connection wiring CW2 may serve as an output wiring of the first cell region CR1 and as an input wiring of the third cell region CR3.

[0058] The second wiring OW may be connected to the seventh source / drain contact CA31. For example, the second wiring OW may be arranged to overlap with the seventh source / drain path VA31 in the third direction Z. The second wiring OW may be connected to the seventh source / drain contact CA31 through the seventh source / drain path VA31. In some embodiments, the second wiring OW may extend in a straight line in the first direction X and overlap with the seventh source / drain path VA31 in the third direction Z.

[0059] In some embodiments, the second wiring OW may be used as an output wiring that receives an output signal from the third cell region CR3 .

[0060] In some embodiments, a plurality of wiring areas RA for arranging a plurality of wiring patterns M1 may be defined between the first power wiring VDD and the second power wiring VSS. At this time, the first connection wiring CW1 may be arranged in one of the plurality of wiring areas RA, and the second connection wiring CW2 may be arranged in another of the plurality of wiring areas RA.

[0061] For example, the first wiring region I to the fifth wiring region V sequentially arranged along the second direction Y may be formed between the first power wiring VDD and the second power wiring VSS. At this time, as shown, the first connection wiring CW1 may be disposed in the first wiring region I, and the second connection wiring CW2 may be disposed in the third wiring region III.

[0062] Therefore, the first connection wiring CW1 and the second connection wiring CW2 may be spaced apart from each other in the second direction Y. In the first cell region CR1, the first connection wiring CW1 and the second connection wiring CW2 may overlap in the second direction Y. In this case, since each of the first connection wiring CW1 and the second connection wiring CW2 may extend in the first direction X, the first connection wiring CW1 and the second connection wiring CW2 may not overlap with each other in the first direction X.

[0063] Although the plurality of wiring areas RA have been described as including only five wiring areas, this is merely an example, and the number of wiring areas RA may of course be various.

[0064] In some embodiments, the first connection wiring CW1 and the first wiring IW may be spaced apart from each other in the second direction Y. For example, the first connection wiring CW1 may be disposed in the first wiring region I, and the first wiring IW may be disposed in the third wiring region III. In some embodiments, the first wiring IW and the second connection wiring CW2 may overlap each other in the first direction X.

[0065] In some embodiments, the second connection wiring CW2 and the second wiring OW may be spaced apart from each other in the second direction Y. For example, the second connection wiring CW2 may be disposed in the third wiring region III, and the second wiring OW may be disposed in the first wiring region I. In some embodiments, the second wiring OW and the first connection wiring CW1 may overlap each other in the first direction X.

[0066] As the structure in semiconductor devices becomes more complex and highly integrated, the use of top wiring for wiring of semiconductor devices increases. However, excessive use of top wiring causes power loss and PnR resource loss, which leads to a decrease in performance and productivity of semiconductor devices.

[0067] However, the semiconductor device according to some embodiments may use the first connection wires CW1 and / or the second connection wires CW2 to reduce the use of top wires.

[0068] For example, as described above, the first gate via VB1 of the first cell region CR1 and the fourth source / drain via VA21 of the second cell region CR2 may be arranged along the first direction X. As a result, since the first connection wiring CW1 may extend in a straight line in the first direction X, the first connection wiring CW1 may connect the first gate electrode G1 of the first cell region CR1 and the fourth source / drain contact CA21 of the second cell region CR2 to each other without using an additional top wiring.

[0069] Furthermore, as described above, the first source / drain via VA11 of the first cell region CR1 and the third gate via VB3 of the third cell region CR3 may be arranged along the first direction X. As a result, since the second connection wiring CW2 may extend in a straight line in the first direction X, the second connection wiring CW2 may connect the first source / drain contact CA11 of the first cell region CR1 and the third gate electrode G3 of the third cell region CR3 to each other without using an additional top wiring.

[0070] Figure 2 is a plan view for explaining a semiconductor device according to some embodiments. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA. Figure 4 It is along Figure 2 A cross-sectional view taken along line BB. Figure 5 It is along Figure 2 A cross-sectional view taken along line CC. Figure 6 It is along Figure 2 A cross-sectional view taken along line DD. Figure 7 It is along Figure 2 A cross-sectional view taken along line EE.

[0071] Figures 2 to 7 The semiconductor device shown can be Figure 1 For the sake of convenience, the above description will be briefly described or omitted. Figure 1 The repeated portion of the content described.

[0072] Reference Figures 2 to 7 , a semiconductor device according to some embodiments may be formed on a substrate 100 .

[0073] The substrate 100 may be bulk silicon or SOI (silicon on insulator). Different from this, the substrate 100 may be a silicon substrate, or may include but is not limited to other materials such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide.

[0074] The substrate 100 may include a first active region AR1 and a second active region AR2. For convenience of explanation, hereinafter, it will be explained assuming that the first active region AR1 is a PFET region and the second active region AR2 is an NFET region.

[0075] In some embodiments, the first active region AR1 and the second active region AR2 may be separated by an element separation film I2. Figures 5 to 7 As shown, the element separation film I2 may extend in the first direction X and separate the first active region AR1 from the second active region AR2.

[0076] A plurality of active patterns F1 to F4 may be formed on the substrate 100. For example, the first active pattern F1 and the second active pattern F2 may be formed on the first active region AR1, and the third active pattern F3 and the fourth active pattern F4 may be formed on the second active region AR2. In some embodiments, each of the active patterns F1 to F4 may include a fin pattern protruding from the upper surface of the substrate 100.

[0077] The first to fourth active patterns F1 to F4 may extend side by side and may be spaced apart from each other. For example, each of the first to fourth active patterns F1 to F4 may extend in the first direction X. In addition, the first to fourth active patterns F1 to F4 may be sequentially arranged along the second direction Y. In some embodiments, each of the first to fourth active patterns F1 to F4 may be formed across the first to third cell regions CR1 to CR3.

[0078] In some embodiments, the first cell separation film I1a and the second cell separation film I1b may cross the first to fourth active patterns F1 to F4. The first cell separation film I1a and the second cell separation film I1b may define the first to third cell regions CR1 to CR3 across the first to fourth active patterns F1 to F4. For example, Figure 2 , Figure 3 and Figure 4 As shown, the first cell separation film I1a may define the first cell region CR1 and the second cell region CR2 across the first to fourth active patterns F1 to F4. In addition, the second cell separation film I1b may define the first cell region CR1 and the third cell region CR3 across the first to fourth active patterns F1 to F4.

[0079] The field insulating film 105 may be formed on the substrate 100. In some embodiments, the field insulating film 105 may surround some of the side surfaces of the first to fourth active patterns F1 to F4. Figure 5As shown, portions of the first to fourth active patterns F1 to F4 may protrude upward from the field insulating film 105 .

[0080] The field insulating film 105 may include, but is not limited to, silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), and combinations thereof.

[0081] The gate electrodes G1 to G3 may intersect the first to fourth active patterns F1 to F4, respectively. Each of the gate electrodes G1 to G3 may include a gate conductive film 130. For example, the gate conductive film 130 may include, but is not limited to, at least one of Ti, Ta, W, Al, Co, and a combination thereof. The gate conductive film 130 may include, for example, silicon, silicon germanium, etc., instead of metal.

[0082] Although the gate conductive film 130 is shown as a single film, the present disclosure is not limited thereto. Unlike the example shown, the gate conductive film 130 may be formed by stacking a plurality of conductive materials. For example, the gate conductive film 130 may include a work function regulating film for regulating the work function and a filling conductive film for filling the space formed by the work function regulating film. The work function regulating film may include at least one of TiN, TaN, TiC, TaC, TiAlC, and a combination thereof. The filling conductive film may contain, for example, W or Al.

[0083] The gate conductive film 130 may be formed by, for example, but not limited to, a replacement process.

[0084] In some embodiments, a first dummy gate electrode DG1 and a second dummy gate electrode DG2 may be formed to intersect each of the first to fourth active patterns F1 to F4. The first dummy gate electrode DG1 may extend in the second direction Y between the first and second cell regions CR1 and CR2, and the second dummy gate electrode DG2 may extend in the second direction Y between the first and third cell regions CR1 and CR3.

[0085] In some embodiments, the first dummy gate electrode DG1 may be formed on the first cell separation film I1a, and the second dummy gate electrode DG2 may be formed on the second cell separation film I1b. In some embodiments, the first dummy gate electrode DG1 and the second dummy gate electrode DG2 may be omitted, for example, their corresponding regions may be filled with the first cell separation film I1a and the second cell separation film I1b.

[0086] The gate dielectric film 120 may be interposed between the first to fourth active patterns F1 to F4 and the gate conductive film 130. For example, the gate dielectric film 120 may extend along the sidewall and bottom surface of the gate conductive film 130. However, the present disclosure is not limited thereto, and the gate dielectric film 120 may extend only along the bottom surface of the gate conductive film 130.

[0087] In some embodiments, a portion of the gate dielectric film 120 may be interposed between the field insulating film 105 and the gate conductive film 130. For example, Figure 5 As shown, the gate dielectric film 120 may extend along the upper surface of the field insulating film 105 .

[0088] The gate dielectric film 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, but is not limited to, for example, hafnium oxide.

[0089] The gate spacer 140 may be formed on the substrate 100 and the field insulating film 105. In addition, the gate spacer 140 may extend along both sides of the gate conductive film 130. Therefore, the gate spacer 140 may intersect the first to fourth active patterns F1 to F4. For example, the gate spacer 140 may extend in the second direction Y.

[0090] The gate spacer 140 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0091] The gate capping pattern 150 may cover the upper surface of the gate conductive film 130. For example, the gate capping pattern 150 may extend along the upper surface of the gate conductive film 130. In addition, the gate capping pattern 150 may extend in the second direction Y.

[0092] The first source / drain region 160 may be formed on the first active region AR1. For example, the first source / drain region 160 may be formed in the first active pattern F1 and the second active pattern F2 on both sides of the gate conductive film 130. However, the first source / drain region 160 may be insulated from the gate conductive film 130. For example, the first source / drain region 160 may be spaced apart from the gate conductive film 130 by the gate spacer 140.

[0093] The second source / drain region 260 may be formed on the second active region AR2. For example, the second source / drain region 260 may be formed in the third active pattern F3 and the fourth active pattern F4 on both sides of the gate conductive film 130. However, the second source / drain region 260 may be insulated from the gate conductive film 130. For example, the second source / drain region 260 may be spaced apart from the gate conductive film 130 by the gate spacer 140.

[0094] Each of the first source / drain region 160 and the second source / drain region 260 may include an epitaxial layer formed in the first to fourth active patterns F1 to F4 .

[0095] When the semiconductor device formed in the first active region AR1 is a PFET, the first source / drain region 160 may include p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the first source / drain region 160 may include at least one of B, C, In, Ga, and Al, and combinations thereof.

[0096] When the semiconductor device formed in the second active region AR2 is an NFET, the second source / drain region 260 may include n-type impurities or impurities for preventing diffusion of n-type impurities. For example, the second source / drain region 260 may include at least one of P, Sb, As, and combinations thereof.

[0097] Although each of the first source / drain region 160 and the second source / drain region 260 is illustrated as a single film, the present disclosure is not limited thereto. For example, the first source / drain region 160 and the second source / drain region 260 may be formed of a plurality of films including impurities of different concentrations.

[0098] A plurality of interlayer insulating films 110, 210, 310, and 410 may be formed on the substrate 100. For example, first to fourth interlayer insulating films 110, 210, 310, and 410 sequentially stacked on the substrate 100 may be formed.

[0099] In some embodiments, the first interlayer insulating film 110 and the second interlayer insulating film 210 may be formed to cover the field insulating film 105, the first source / drain region 160, the second source / drain region 260, the gate spacer 140, and the gate capping pattern 150. For example, the first interlayer insulating film 110 may cover the upper surface of the field insulating film 105, the upper surface of the first source / drain region 160, the upper surface of the second source / drain region 260, and the side surface of the gate spacer 140. For example, the second interlayer insulating film 210 may cover the upper surface of the gate capping pattern 150 and the upper surface of the first interlayer insulating film 110.

[0100] The first to fourth interlayer insulating films 110 , 210 , 310 , and 410 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0101] In some embodiments, the plurality of source / drain contacts CA11 to CA33 may penetrate the first interlayer insulating film 110 and the second interlayer insulating film 210, and may be connected to the first source / drain region 160 and / or the second source / drain region 260. For example, the second source / drain contact CA12, the fifth source / drain contact CA22, and the eighth source / drain contact CA32 may be connected to the first source / drain region 160. In addition, for example, the third source / drain contact CA13, the sixth source / drain contact CA23, and the ninth source / drain contact CA33 may be connected to the second source / drain region 260. In some embodiments, the first source / drain contact CA11, the fourth source / drain contact CA21, and the seventh source / drain contact CA31 may be connected to both the first source / drain region 160 and the second source / drain region 260.

[0102] In some embodiments, the plurality of source / drain vias VA11 to VA33 may penetrate the third interlayer insulating film 310 and may be connected to the source / drain contacts CA11 to CA33 .

[0103] In some embodiments, the plurality of gate vias VB1 to VB3 may penetrate the gate capping pattern 150 , the second interlayer insulating film 210 , and the third interlayer insulating film 310 , and may be connected to the gate electrodes G1 to G3 .

[0104] In some embodiments, the plurality of wiring patterns M1 may be disposed at the same level. In this specification, the expression “disposed at the same level” means that the wiring patterns are formed at the same height based on the upper surface of the substrate 100. In addition, in this specification, the term “same” means not only exactly the same thing, but also means slight differences that may occur due to process margins, etc.

[0105] For example, Figure 2 and Figure 3 As shown, the first connection wiring CW1 is formed in the fourth interlayer insulating film 410 and can be connected to the fourth source / drain via VA21 and the first gate via VB1. In addition, the second wiring OW is formed in the fourth interlayer insulating film 410 and can be connected to the seventh source / drain via VA31.

[0106] For example, Figure 2 and Figure 4 As shown, the first wiring IW is formed in the fourth interlayer insulating film 410 and may be connected to the second gate via VB2. In addition, the second connection wiring CW2 is formed in the fourth interlayer insulating film 410 and may be connected to the first source / drain via VA11 and the third gate via VB3.

[0107] Furthermore, in some embodiments, the plurality of wiring patterns M1 may be formed at the same level. In this specification, the expression "formed at the same level" means that the wiring patterns are formed by the same manufacturing process.

[0108] In some embodiments, the plurality of wiring patterns M1 may be disposed at the same level as the first power wiring VDD and / or the second power wiring VSS.

[0109] For example, Figure 2 and Figure 7 As shown, the first power wiring VDD is formed in the fourth interlayer insulating film 410 and can be connected to the second source / drain path VA12, the fifth source / drain path VA22, and the eighth source / drain path VA32. In addition, the second power wiring VSS is formed in the fourth interlayer insulating film 410 and can be connected to the third source / drain path VA13, the sixth source / drain path VA23, and the ninth source / drain path VA33.

[0110] In some embodiments, the plurality of wiring patterns M1 may be formed at the same level as the first power wiring VDD and / or the second power wiring VSS.

[0111] Therefore, it is possible to provide a semiconductor device in which use of additional top wiring is reduced and power loss and PnR resource loss are reduced.

[0112] In some embodiments, each of the source / drain contacts CA11 to CA33 may include a first barrier film 190 and a first filling film 192. The first barrier film 190 may extend along an upper surface of the first source / drain region 160, an upper surface of the second source / drain region 260, a side surface of the first interlayer insulating film 110, and a side surface of the second interlayer insulating film 210. The first filling film 192 may fill a space formed by the first barrier film 190.

[0113] In some embodiments, each of the source / drain vias VA11 to VA33 may include a second barrier film 290 and a second filling film 292. The second barrier film 290 may extend along upper surfaces of the source / drain contacts CA11 to CA33 and side surfaces of the third interlayer insulating film 310. The second filling film 292 may fill a space formed by the second barrier film 290.

[0114] In some embodiments, each of the gate vias VB1 to VB3 may include a third barrier film 390 and a third filling film 392. The third barrier film 390 may extend along upper surfaces of the gate electrodes G1 to G3, side surfaces of the gate capping pattern 150, side surfaces of the second interlayer insulating film 210, and side surfaces of the third interlayer insulating film 310. The third filling film 392 may fill a space formed by the third barrier film 390.

[0115] In some embodiments, the first power wiring VDD, the second power wiring VSS, and the plurality of wiring patterns M1 may respectively include a fourth barrier film 490 and a fourth filling film 492. The fourth barrier film 490 may extend along the upper surfaces of the source / drain vias VA11 to VA33, the upper surfaces of the gate vias VB1 to VB3, the upper surface of the third interlayer insulating film 310, and the side surfaces of the fourth interlayer insulating film 410. The fourth filling film 492 may fill the space formed by the fourth barrier film 490.

[0116] The first to fourth barrier films 190 to 490 may include a metal or a metal nitride for preventing diffusion of the first to fourth filling films 192 to 492. The first to fourth barrier films 190 to 490 may include, but are not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof.

[0117] The first to fourth filling films 192 to 492 may include, but are not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and alloys thereof.

[0118] The source / drain paths VA11 to VA33, the gate paths VB1 to VB3, the first power wiring VDD, the second power wiring VSS, and the wiring pattern M1 may be formed by, but not limited to, a single damascene process, for example. For example, the source / drain paths VA11 to VA33, the gate paths VB1 to VB3, the first power wiring VDD, the second power wiring VSS, and the wiring pattern M1 may of course be formed, for example, by a dual damascene process or other wiring processes.

[0119] Figure 8 and Fig. 9 is a cross-sectional view for illustrating a semiconductor device according to some embodiments. For ease of description, the above description will be briefly described or omitted. Figures 1 to 7 The repeated portion of the content described.

[0120] For reference, Figure 8 It is along Figure 2 A cross-sectional view taken along line AA, Fig. 9 It is along Figure 2A cross-sectional view taken along line CC.

[0121] Reference Figure 8 and Fig. 9 , in the semiconductor device according to some embodiments, each of the first to fourth active patterns F1 to F4 includes a plurality of line patterns 114 , 116 , and 118 .

[0122] For example, the first to fourth active patterns F1 to F4 may include first to third line patterns 114, 116, and 118 sequentially stacked on the substrate 100 and spaced apart from each other. For example, the first line pattern 114 may be spaced apart from the substrate 100 in the third direction Z, the second line pattern 116 may be spaced apart from the first line pattern 114 in the third direction Z, and the third line pattern 118 may be spaced apart from the second line pattern 116 in the third direction Z.

[0123] The first to third line patterns 114, 116, and 118 may extend in the first direction X, respectively. In addition, the first to third line patterns 114, 116, and 118 may penetrate the first to third gate electrodes G1 to G3, respectively. Fig. 9 As shown, the first to third gate electrodes G1 to G3 may surround outer surfaces of the first to third line patterns 114 , 116 , and 118 , respectively.

[0124] exist Fig. 9 , although the cross-sections of the first to third line patterns 114, 116, and 118 are each shown as a rectangle, this is only an example. For example, the cross-sections of the first to third line patterns 114, 116, and 118 may be other polygons or circles, respectively.

[0125] In some embodiments, each of the first to fourth active patterns F1 to F4 may further include a fin pattern 112 protruding from the upper surface of the substrate 100 and extending in the first direction X. The fin pattern 112 may be disposed, for example, under the first line pattern 114 .

[0126] Figures 10 to 14 is a layout diagram for illustrating a semiconductor device according to some embodiments. For ease of description, the above-mentioned Figures 1 to 7 The repeated portion of the content described.

[0127] Reference Fig.10 ,and Figure 1 In contrast, the second connection wiring CW2 is arranged in the fifth wiring area V.

[0128] For example, the first source / drain via VA11 and the third gate via VB3 may both be disposed in the fifth wiring region V. In some embodiments, the second connection wiring CW2 extends in the first direction X within the fifth wiring region V and may connect the first source / drain via VA11 and the third gate via VB3.

[0129] Reference Fig.11 ,and Figure 1 In contrast, the first connection wiring CW1 is arranged in the third wiring region III, and the second connection wiring CW2 is arranged in the first wiring region I.

[0130] For example, the fourth source / drain via VA21 and the first gate via VB1 may both be disposed in the third wiring region III. In some embodiments, the first connection wiring CW1 extends in the first direction X within the third wiring region III and may connect the fourth source / drain via VA21 and the first gate via VB1.

[0131] In addition, for example, the first source / drain path VA11 and the third gate path VB3 may both be disposed in the first wiring region I. In some embodiments, the second connection wiring CW2 extends in the first direction X within the first wiring region I and may connect the first source / drain path VA11 and the third gate path VB3.

[0132] In some embodiments, the first wires IW may be disposed in the first wiring region I, and the second wires OW may be disposed in the third wiring region III.

[0133] Reference Fig.12 ,and Fig.11 In contrast, the second connection wiring CW2 is arranged in the fifth wiring area V.

[0134] For example, the first source / drain via VA11 and the third gate via VB3 may both be disposed in the fifth wiring region V. In some embodiments, the second connection wiring CW2 extends in the first direction X within the fifth wiring region V and may connect the first source / drain via VA11 and the third gate via VB3.

[0135] Reference Fig.13 ,and Fig.11 In contrast, the first connection wiring CW1 is arranged in the fifth wiring area V.

[0136] For example, the fourth source / drain via VA21 and the first gate via VB1 may both be disposed in the fifth wiring region V. In some embodiments, the first connection wiring CW1 extends in the first direction X within the fifth wiring region V and may connect the fourth source / drain via VA21 and the first gate via VB1.

[0137] In some embodiments, the first wires IW may be disposed in the third wiring region III.

[0138] Reference Fig.14 ,and Fig.13 In contrast, the second connection wiring CW2 is arranged in the third wiring region III.

[0139] For example, the first source / drain via VA11 and the third gate via VB3 may both be disposed in the third wiring region III. In some embodiments, the second connection wiring CW2 extends in the first direction X within the third wiring region III and may connect the first source / drain via VA11 and the third gate via VB3.

[0140] In some embodiments, the second wiring OW may be disposed in the first wiring region I.

[0141] exist Figures 10 to 14 Although the plurality of wiring patterns M1 are shown as being arranged only in the first wiring region, the third wiring region, and the fifth wiring region V, this is only to simplify the description. For example, the plurality of wiring patterns M1 may of course be arranged in the second wiring region II and the fourth wiring region IV.

[0142] Fig.15 is a plan view for explaining a semiconductor device according to some embodiments. Fig.16 It is along Fig.15 A cross-sectional view taken along line FF. Fig.17 It is along Fig.15 For the sake of convenience, the above description will be briefly described or omitted. Figures 1 to 7 The repeated portion of the content described.

[0143] Reference Figures 15 to 17 , the semiconductor device according to some embodiments further includes a first connecting via SA and a second connecting via SB.

[0144] The first connection path SA may connect the source / drain contacts CA11 to CA33 and the source / drain paths VA11 to VA33. Fig.16 and Fig.17 As shown, the first connection vias SA may be interposed between the source / drain contacts CA11 to CA33 and the source / drain vias VA11 to VA33 to connect them.

[0145] The second connection path SB may connect the gate electrodes G1 to G3 and the gate paths VB1 to VB3. Fig.16 and Fig.17As shown, the second connection path SB is interposed between the gate electrodes G1 to G3 and the gate paths VB1 to VB3 to connect them.

[0146] Fig.18 is a layout diagram for illustrating a semiconductor device according to some embodiments. For ease of description, the above-mentioned Figure 1 The repeated portion of the content described.

[0147] Reference Fig.18 , the semiconductor device according to some embodiments further includes a fourth gate electrode G4, tenth source / drain contacts CA14 and eleventh source / drain contacts CA15, tenth source / drain paths VA14 to twelfth source / drain paths VA16, a fourth gate path VB4, a third wiring IW2, and a third connection wiring CW3.

[0148] The fourth gate electrode G4 may extend in the second direction Y within the first cell region CR1. For example, the second source / drain contact CA12 and the third source / drain contact CA13 may be disposed on one side of the fourth gate electrode G4. In some embodiments, the second source / drain contact CA12 and the third source / drain contact CA13 may be interposed between the first gate electrode G1 and the fourth gate electrode G4.

[0149] The tenth source / drain contact CA14 and the eleventh source / drain contact CA15 may be disposed on the other side of the fourth gate electrode G4 in the first cell region CR1. In some embodiments, the tenth source / drain contact CA14 and the eleventh source / drain contact CA15 may be spaced apart from each other. For example, the tenth source / drain contact CA14 may be formed in the first active region AR1, and the eleventh source / drain contact CA15 may be formed in the second active region AR2.

[0150] The tenth source / drain via VA14 is arranged to overlap with the tenth source / drain contact CA14 in the third direction Z and may be connected to the tenth source / drain contact CA14. The eleventh source / drain via VA15 is arranged to overlap with the eleventh source / drain contact CA15 in the third direction Z and may be connected to the eleventh source / drain contact CA15.

[0151] The twelfth source / drain via VA16 is disposed to overlap the first source / drain contact CA11 in the third direction Z and may be connected to the first source / drain contact CA11. In some embodiments, the twelfth source / drain via VA16 may be spaced apart from the first source / drain via VA11 in the second direction Y.

[0152] The fourth gate via VB4 is disposed to overlap the fourth gate electrode G4 in the third direction Z and may be connected to the fourth gate electrode G4.

[0153] The third wiring IW2 may be connected to the fourth gate electrode G4. For example, the third wiring IW2 may be disposed to overlap with the fourth gate via VB4 in the third direction Z. The third wiring IW2 may be connected to the fourth gate electrode G4 through the fourth gate via VB4.

[0154] In some embodiments, the first wiring IW may function as a first input wiring providing a first input signal to the first cell region CR1 , and the third wiring IW2 may function as a second input wiring providing a second input signal different from the first input signal to the first cell region CR1 .

[0155] The third connection wiring CW3 may connect the tenth source / drain contact CA14 and the first source / drain contact CA11. For example, the third connection wiring CW3 may be disposed to overlap the tenth source / drain via VA14 and the twelfth source / drain via VA16 in the third direction Z. The third connection wiring CW3 may be connected to the tenth source / drain contact CA14 and the first source / drain contact CA11 through the tenth source / drain via VA14 and the twelfth source / drain via VA16.

[0156] In some embodiments, the first connecting wiring CW1 may be placed in one of the plurality of wiring areas RA, the first wiring IW may be placed in another of the plurality of wiring areas RA, the second wiring OW may be placed in another of the plurality of wiring areas RA, and the third connecting wiring CW3 may be placed in another of the plurality of wiring areas RA.

[0157] For example, as shown, the first connection wiring CW1 may be disposed in the first wiring area I, the first wiring IW may be disposed in the fifth wiring area V, the second wiring OW may be disposed in the third wiring area III, and the third connection wiring CW3 may be disposed in the second wiring area II.

[0158] As a result, even when there are a plurality of input wirings, it is possible to provide a semiconductor device in which use of additional top wirings is reduced and power loss and PnR resource loss are reduced.

[0159] In the following, reference will be made to Figures 19 to 23 A layout design method for the semiconductor device and a method of manufacturing the semiconductor device according to some embodiments are described.

[0160] Fig.19is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments. Figures 1 to 18 The repeated portion of the content described.

[0161] Reference Fig.19 , the computer system may include a CPU 10, a working memory 30, an input / output device 50, and an auxiliary storage 70. Here, the computer system may be provided as a dedicated device for layout design of semiconductor devices according to some embodiments. In some embodiments, the computer system may also include various design and verification simulation programs.

[0162] The CPU 10 may execute software (applications, operating systems, device drivers, etc.) to be executed on the computer system. The CPU 10 may execute an operating system to be loaded into the working memory 30. The CPU 10 may execute various application programs to be driven based on the operating system. For example, the CPU 10 may execute a layout design tool 32, a placement and routing tool 34, and / or an OPC tool 36 loaded into the working memory 30.

[0163] An operating system or application program may be loaded into the working memory 30. When the computer system is booted, an operating system image (not shown) stored in the auxiliary storage 70 may be loaded into the working memory 30 according to the boot sequence. The operating system may support various input / output operations of the computer system.

[0164] A layout design tool 32 for layout design of a semiconductor device according to some embodiments may be loaded from the auxiliary storage 70 into the working memory 30. Subsequently, a place and route tool 34 may be loaded from the auxiliary storage 70 into the working memory 30, which will place the designed standard cells, rearrange the internal wiring patterns in the placed standard cells, and route the placed standard cells. Subsequently, an optical proximity correction (OPC) tool 36 for performing an OPC on the designed layout data may be loaded from the auxiliary storage 70 into the working memory 30.

[0165] The input / output (I / O) device 50 can control the input and output of the user from the user interface device. For example, the input / output device 50 can be equipped with a keyboard or a monitor to receive information input from the user. The user can use the input / output device 50 to receive input of information about the semiconductor area or data path that needs to adjust the operating characteristics. In addition, the processing progress, processing results, etc. of the OPC tool 36 can be displayed through the input / output device 50.

[0166] The auxiliary storage 70 may be provided as a storage medium of the computer system. The auxiliary storage 70 may store application programs, operating system images, and various data.

[0167] The system interconnector 90 may be a system bus for providing a network inside the computer system. The CPU 10, the working memory 30, the input / output device 50, and the auxiliary storage 70 may be electrically connected through the system interconnector 90 to exchange data with each other.

[0168] Fig. 20 is a flowchart for explaining a layout design method of a semiconductor device and a method of manufacturing the semiconductor device according to some embodiments.

[0169] Reference Fig. 20 , you can use the above reference Fig.19 The computer system described in the present invention performs the high-level design (S10) of the semiconductor integrated circuit. The high-level design may mean describing the integrated circuit to be designed in the native language of the host language. For example, a host language such as C language may be used for the high-level design. The circuit designed by the high-level design may be more specifically expressed by encoding or simulation of the register transfer level (RTL). Subsequently, the code generated by the register transfer level encoding is converted into a netlist and may be synthesized into the entire semiconductor element. The synthesized principle circuit is verified by a simulation tool, and the adjustment process may be completed according to the verification result.

[0170] Subsequently, a layout design (S20) for realizing a semiconductor integrated circuit for logic completion on a silicon substrate may be performed. For example, the layout design may be performed with reference to a principle circuit synthesized in a high-level design or a netlist corresponding thereto. The layout design may include a wiring process for placing and connecting various standard cells provided in a cell library according to defined design rules.

[0171] Layout can be a process for defining the form or size of patterns constituting transistors and metal wirings to be actually formed on a silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, PFETs, NFETs, P-WELLs, N-WELLs, gate electrodes, and layout patterns such as wiring patterns to be laid out thereon can be appropriately laid out.

[0172] Subsequently, wiring of the selected and laid out standard cells may be performed. Specifically, top wiring (wiring pattern) may be laid out on the laid out standard cells. By performing wiring, the laid out standard cells may be connected to each other according to the design.

[0173] After routing, the layout can be verified to see if there are any parts that violate the design rules. The items to be verified may include DRC (Design Rule Check), ERC (Electrical Rule Check), LVS (Layout Versus Schematic), etc.

[0174] Subsequently, an optical proximity correction (OPC) process (S30) may be performed. A layout pattern provided by the layout design may be implemented on a silicon substrate using a photolithography process. At this time, the optical proximity correction may be a technique for correcting deformation that may occur in the photolithography process.

[0175] Subsequently, a photomask may be manufactured based on the layout changed by the optical proximity correction (S40). The photomask may be manufactured, for example, in such a manner that a layout pattern is drawn using a chrome film coated on a glass substrate.

[0176] Subsequently, the generated photomask can be used to manufacture a semiconductor element (S50). In the semiconductor element manufacturing process using the photomask, various types of exposure and etching processes can be repeated. The form of the pattern formed on the silicon substrate during layout design can be sequentially formed through such a process.

[0177] Figure 21 to Figure 23 It is a layout diagram for illustrating a layout design method of a semiconductor device according to some embodiments. For the sake of convenience, the above description will be briefly described or omitted. Figures 1 to 20 The repeated portion of the content described.

[0178] Reference Fig.21 In the layout design method for a semiconductor device according to some embodiments, various cell layouts may be provided according to the layouts of the first connection wirings CW1 and the second connection wirings CW2.

[0179] For example, the layout of the first connection wiring CW1 and the second connection wiring CW2 may be used to provide Fig.21 The cell layout of (a) to (f) is shown in Figure 1. Fig.21 The first connection wiring CW1 and the second connection wiring CW2 are shown as being arranged only in the first wiring area I, the third wiring area III, and the fifth wiring area V, but this is only to simplify the description. For example, the first connection wiring CW1 or the second connection wiring CW2 can of course be arranged in the second wiring area II and the fourth wiring area IV.

[0180] Reference Fig. 22 , in the layout design method for a semiconductor device according to some embodiments, an input wiring IS for the first cell region CR1 may be provided.

[0181] In some embodiments, the input wiring IS may be laid out in one of the plurality of wiring areas RA. For example, the input wiring IS may be laid out in the first wiring area I as shown.

[0182] In this case, among various cell layouts, a cell layout in which the first connection wiring CW1 is arranged in the first wiring region I may be provided in the first cell region CR1. Fig.21 The cell layout of (a) or (b) may be provided in the first cell region CR1. Therefore, an input signal may be provided in the first cell region CR1 without using an additional top wiring.

[0183] Reference Fig.23 , in the layout design method for a semiconductor device according to some embodiments, an output wiring OS for the first cell region CR1 may be provided.

[0184] In some embodiments, the output wiring OS may be disposed in one of the plurality of wiring areas RA. For example, as shown, the output wiring OS may be disposed in the third wiring area III.

[0185] In this case, among various cell layouts, a cell layout in which the second connection wiring CW2 is arranged in the third wiring region III may be provided in the first cell region CR1. Fig.21 The cell layout of (a) or (f) may be provided in the first cell region CR1. Therefore, an output signal may be provided from the first cell region CR1 without using an additional top wiring.

[0186] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments presented without departing substantially from the principles of the inventive concept. Therefore, the embodiments presented are described in a general and descriptive sense only, and not for the purpose of limitation.

[0187] This application claims priority to Korean Patent Application No. 10-2019-0124324, filed on October 8, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: substrate; a first active pattern extending in a first direction on the substrate; a second active pattern extending in the first direction on the substrate; a first gate electrode extending in a second direction, the second direction intersecting the first direction, the first gate electrode intersecting the first active pattern and the second active pattern; a first source / drain contact extending in the second direction at one side of the first gate electrode, the first source / drain contact being connected to a first source / drain region of the first active pattern and a second source / drain region of the second active pattern; a first source / drain path connected to the first source / drain contact; a second gate electrode extending in the second direction, the second gate electrode intersecting the first active pattern and the second active pattern; a first cell separation film extending in the second direction between the first source / drain contact and the second gate electrode, the first cell separation film crossing the first active pattern and the second active pattern; a first gate path connected to the second gate electrode and arranged along the first direction together with the first source / drain path; as well as A first connection wiring extending in the first direction and connecting the first source / drain path and the first gate path. 2 . The semiconductor device according to claim 1 , wherein the first connection wiring extends in a straight line in the first direction.

3. The semiconductor device according to claim 1, further comprising: a second source / drain contact, on the other side of the first gate electrode, connected to the first source / drain region; a third source / drain contact at the other side of the first gate electrode, spaced apart from the second source / drain contact and connected to the second source / drain region; a first power supply wiring extending in the first direction and connected to the second source / drain contact; as well as A second power supply wiring extending in the first direction and connected to the third source / drain contact. 4 . The semiconductor device according to claim 3 , wherein the first connection wiring is arranged at the same height as the first power wiring and the second power wiring.

5. The semiconductor device according to claim 3, wherein the first power supply wiring is configured to have a drain voltage applied thereto, and The second power supply wiring is configured to have a source voltage applied thereto.

6. The semiconductor device according to claim 1, further comprising: a second source / drain contact on one side of the second gate electrode, spaced apart from the first source / drain contact by the first cell separation film and connected to the first source / drain region; a second source / drain path connected to the second source / drain contact; as well as An output wiring extending in the first direction and connected to the second source / drain path. 7 . The semiconductor device according to claim 6 , wherein the first connection wiring is at the same height as the output wiring.

8. The semiconductor device according to claim 1, further comprising: a second source / drain contact connected to the first source / drain region; a second source / drain path connected to the second source / drain contact; a second cell separation film extending in the second direction between the second source / drain contact and the first gate electrode, the second cell separation film intersecting the first active pattern and the second active pattern; a second gate path connected to the first gate electrode and arranged along the first direction together with the second source / drain path; as well as A second connection wiring extending in the first direction and connecting the second source / drain path and the second gate path. 9 . The semiconductor device according to claim 8 , wherein the first connection wiring and the second connection wiring are arranged at the same height. 10 . The semiconductor device according to claim 8 , wherein the second connection wiring is spaced apart from the first connection wiring in the second direction.

11. The semiconductor device according to claim 8, further comprising: a third gate electrode extending in the second direction and intersecting the first active pattern and the second active pattern at a side of the second source / drain contact; a third gate path connected to the third gate electrode; and An input wiring extending in the first direction and connected to the third gate path.

12. A semiconductor device comprising a first unit region, a second unit region and a third unit region, wherein the second unit region and the third unit region are respectively arranged on both sides of the first unit region in a first direction, the semiconductor device comprising: a first active region and a second active region extending in the first direction on the first cell region, the second cell region and the third cell region, the second active region being spaced apart from the first active region in a second direction intersecting the first direction; a first gate electrode extending in the second direction in the first cell region; a first source / drain contact extending in the second direction on one side of the first gate electrode in the first cell region, the first source / drain contact being connected to the first active region and the second active region, a second gate electrode extending in the second direction in the second cell region; a second source / drain contact on one side of the second gate electrode in the second cell region; a first connection wiring extending in the first direction and connected to the second source / drain contact and the first gate electrode; a third gate electrode extending in the second direction in the third cell region; as well as a second connecting wiring extending in the first direction and connected to the first source / drain contact and the third gate electrode, The second connection wiring and the first connection wiring are spaced apart from each other in the second direction in the first cell region. 13 . The semiconductor device according to claim 12 , wherein the first connection wiring and the second connection wiring are arranged at the same height. 14 . The semiconductor device according to claim 13 , wherein the second source / drain contact connects the first active region in the second cell region and the second active region in the second cell region.

15. The semiconductor device according to claim 13, further comprising: an input wiring connected to the second gate electrode and extending in the first direction in the second cell region, wherein The first connection wiring and the input wiring are spaced apart from each other in the second direction in the second cell region. 16 . The semiconductor device according to claim 15 , wherein the input wiring is at the same height as the first connection wiring and the second connection wiring. 17 . The semiconductor device according to claim 15 , wherein the input wiring overlaps the second connection wiring in the first direction.

18. The semiconductor device according to claim 12, further comprising: a third source / drain contact at one side of the third gate electrode in the third cell region; as well as an output wiring connected to the third source / drain contact in the third cell region and extending in the first direction, wherein the second connection wiring and the output wiring are spaced apart from each other in the second direction in the third cell region. 19 . The semiconductor device according to claim 18 , wherein the output wiring is at the same height as the first connection wiring and the second connection wiring. 20 . The semiconductor device according to claim 18 , wherein the output wiring overlaps with the first connection wiring in the first direction.

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