A semiconductor power device and a method for manufacturing the same

Abstract

The present invention relates to a semiconductor power device and a preparation method thereof, which comprises a substrate, wherein an epitaxial layer is provided on the front side of the substrate, and a drain metal electrode is provided on the back side; a plurality of grooves are provided on the epitaxial layer, a source N+ type junction is provided above the epitaxial layer, and an interlayer insulating film is provided above the epitaxial layer and the source N+ type junction; a source metal electrode and a gate metal electrode are provided on the interlayer insulating film; the source metal electrode contacts the ethyl silicate in the first groove and the third groove after passing through the interlayer insulating film and the source N+ type junction; the gate electrode contacts the polycrystalline gate in the fourth groove through the interlayer insulating film. When the TDMOS device is prepared by the present invention, the device size is small, the size of the n-type column region is reduced, and the on-state resistance of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a preparation method thereof. Background Art

[0002] Semiconductor power devices are generally used in the fields of automobiles, electromechanics, electric power industry, information and communication equipment, etc. Currently, commonly used power devices include VDMOSFET power devices and TDMOSFET power devices.

[0003] Figure 1 and Figure 2 The figure shows the currently improved VDMOSFET power device, namely the basic super junction VDMOSFET power device. The VDMOSFET power device can improve the performance of the power device, but its horizontal structure increases the device unit area, reduces the number of components in the same unit area, and has poor current driving capability.

[0004] TDMOSFET power devices are manufactured by etching grooves on a substrate to improve the quality of the gate oxide film and reduce on-state resistance during device manufacturing. Although the process has the disadvantage of being complex, a higher number of components per unit area can be achieved through integration than with VDMOSFET power devices. Figure 3 The figure shows a basic super junction TDMOSFET power device structure diagram. The width of the n-layer column region is a big disadvantage. This is a structure that is not conducive to the on-resistance of the power device, resulting in an increase in the on-resistance value of the TDMOSFET power device.

[0005] In view of this, the inventors have conducted in-depth thinking on the problems of the manufacturing process load and high on-resistance of the existing TDMOSFET power devices, and thus came up with the present invention. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor power device and a method for preparing the same, so as to reduce the on-state resistance of the semiconductor power device.

[0007] To achieve the above object, the technical solution adopted by the present invention is:

[0008] A semiconductor power device comprises a substrate, wherein an epitaxial layer is provided on the front side of the substrate and a drain metal electrode is provided on the back side;

[0009] The epitaxial layer is provided with a first trench, a second trench, a third trench, a fourth trench and a fifth trench, the second trench is located between the first trench and the third trench, the third trench is located between the second trench and the fourth trench, and the fourth trench is located between the third trench and the fifth trench;

[0010] The second trench and the fourth trench are provided with a P-type well at the periphery, a gate oxide film is provided on the inner sidewall, and a polycrystalline gate is filled inside; the polycrystalline gate in the fourth trench extends from the fourth trench to the outside of the fourth trench and is located above the epitaxial layer;

[0011] The peripheries of the first trench, the third trench and the fifth trench are provided with a P+ type region and a P type column region, the P+ type region is located at the upper part of the trench, and the P type column region is located at the lower part of the trench; the inner sidewalls of the first trench, the third trench and the fifth trench are provided with a doped epitaxial film, which is filled with ethyl silicate to form a TEOS film; an N type column region is formed between the first trench and the second trench;

[0012] A source N+ type junction is provided above the epitaxial layer, and an interlayer insulating film is provided above the epitaxial layer and the source N+ type junction; a source metal electrode and a gate metal electrode are provided on the interlayer insulating film; the source metal electrode contacts the TEOS film in the first trench and the third trench after passing through the spacer insulating film and the source N+ type junction; the gate electrode contacts the polycrystalline gate in the fourth trench through the interlayer insulating film.

[0013] A method for preparing a semiconductor power device comprises the following steps:

[0014] Step 1, forming the first level groove stage;

[0015] Growing an n-type epitaxial layer with a low doping concentration on an n+ type substrate, and growing a masking layer on the n-type epitaxial layer, and then defining the groove area by graphic processing, and etching the first-level groove;

[0016] Depositing a borosilicate glass film in the first-level trench and performing directional etching to leave the borosilicate glass film on the inner side of the first-level trench;

[0017] Step 2, forming a P-type well stage;

[0018] On the basis of step 1, the borosilicate glass film on the side wall of the trench is thermally treated to diffuse the boron dopant to form a P-type well; after the P-type well is formed, the borosilicate glass film remaining on the side wall of the trench is etched again to remove the borosilicate glass film, and the first-level trench is etched downward to a certain depth to form a second-level trench;

[0019] Step 3: Gate oxide film and polycrystalline gate formation stage;

[0020] Growing a gate oxide film in the second-level trench, and then etching it to leave the gate oxide film on the inner side of the second-level trench;

[0021] Continue to grow polysilicon doped with phosphorus or arsenic in the second-level trench, define it graphically, and form a polycrystalline gate;

[0022] Step 4, P+ type region formation stage;

[0023] A nitride layer is grown on the existing oxide layer of the polycrystalline gate; a P+ type region is then defined by patterning, a third level trench is defined by dry etching, and boron dopants are ion-implanted, and heat treatment is performed to diffuse the boron dopants to form a P+ type region;

[0024] Step 5, P-type column area formation stage;

[0025] removing the oxide film formed by the high temperature process, and further etching the third-level trench to form a fourth-level trench;

[0026] growing a doped epitaxial film on the sidewall of the fourth-level trench, and then growing a layer of borosilicate glass;

[0027] Finally, the dopant is diffused to the outside of the sidewall of the fourth-level trench through a heat treatment process to form a P-type column region; an n-type column region is formed between the two P-type column regions;

[0028] Step 6, TEOS film formation stage;

[0029] Based on the above steps, the borosilicate glass film is first wet-etched, and then low-pressure chemical deposition is used to fill ethyl silicate into the fourth-level groove area to form a TEOS film;

[0030] Next, the masking nitride film is removed with phosphoric acid, and the oxide film is dry-grown again;

[0031] Step 7, source N+ junction formation stage;

[0032] Based on the above steps, the source N+ junction region is firstly patterned and photolithographically defined, and then ion implantation of high concentration doped arsenic is performed, and then the photoresist is removed and heat treatment is performed to form a source N+ junction;

[0033] Step 8, interlayer insulating film formation stage;

[0034] Grow TEOS oxide film and borosilicate glass thin film oxide film, then grow HTO oxide film on the upper layer to form an interlayer insulating film, and then perform heat treatment; graphically define the contact part of the metal electrode, remove the oxide film by wet and dry etching, and then remove the photoresist;

[0035] Step 9, metal electrode formation stage;

[0036] After the above-mentioned graphic definition and etching operations, aluminum metal wires are deposited on the upper surface through metal wiring to form source metal electrodes and gate metal electrodes;

[0037] Metal wiring is performed on the back side of the N+ type substrate to form a drain metal electrode.

[0038] After adopting the above scheme, when the present invention prepares TDMOS devices, the device size is small, the size of the n-type column area is reduced, and it is beneficial to reduce the on-state resistance of the device. Moreover, the present invention manufactures the TDMOS device by growing epitaxial on the inner side wall of the groove, and heat-treating the epitaxial layer containing dopants during growth, and forming a uniform epitaxial film on the side wall of the groove, which can improve the turn-off leakage current of the channel and reduce the channel resistance. In addition, the super junction drain structure can allow the TDMOSFET source p+ type etching area to be enlarged, and the doped outer film is selectively grown on the side wall of the groove, and then heat-treated to form a p-type (or n-type) column area. This manufacturing method is simple and can effectively improve the breakdown voltage and low on-state resistance of the device without affecting the threshold voltage of the device material. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the basic superjunction VDMOS device structure (multi-layer epitaxial growth and buried layer diffusion form a superjunction);

[0040] Figure 2 Schematic diagram of the basic super junction VDMOS device structure (super junction composed of etched grooves, oxide layer and P+ type);

[0041] Figure 3 It is a schematic diagram of the basic super junction TDMOS device structure;

[0042] Figure 4 It is a schematic diagram of the structure of the super junction TDMOS device of the present invention;

[0043] 5 (a) to (i) are schematic diagrams of a super junction TDMOS device fabricated using the selective epitaxial technology of the present invention.

[0044] Description of labels:

[0045] N+ type substrate 1; N- type epitaxial layer 2; P- type well 3; gate oxide film 4; polycrystalline gate 5; P+ type region 6; TEOS film 7; p-type column region 8; doped epitaxial film 9; n-type column region 10; source N+ type junction 11; interlayer insulating film 12; gate metal electrode 13; source metal electrode 14; drain metal electrode 15. DETAILED DESCRIPTION

[0046] like Figure 4 As shown, the present invention discloses a semiconductor power device, which includes an N+ type substrate 1, wherein an N- type epitaxial layer 2 is provided on the front side of the N+ type substrate 1, and a drain metal electrode 15 is provided on the back side.

[0047] The N-type epitaxial layer 2 is provided with a first trench, a second trench, a third trench, a fourth trench and a fifth trench, wherein the second trench is located between the first trench and the third trench, the third trench is located before the second trench and the fourth trench, and the fourth trench is located between the third trench and the fifth trench.

[0048] The second trench and the fourth trench are provided with a P-type well 3 on their peripheries, a gate oxide film 4 on their inner sidewalls, and a polycrystalline gate 5 is filled inside; the polycrystalline gate 5 in the fourth trench extends from the fourth trench to the outside of the fourth trench and is located above the epitaxial layer.

[0049] A P+ type region 6 and a p-type column region 8 are provided on the periphery of the first trench, the third trench and the fifth trench, wherein the P+ type region 6 is located at the upper part of the trench and the p-type column region 8 is located at the lower part of the trench; an impurity-doped epitaxial film 9 is provided on the inner sidewalls of the first trench, the third trench and the fifth trench, and the interior is filled with ethyl silicate to form a TEOS film 7; an n-type column region 10 is formed between the first trench and the second trench.

[0050] A source N+ type junction 11 is provided above the epitaxial layer, and an interlayer insulating film 12 is provided above the epitaxial layer and the source N+ type junction 11; a source metal electrode 14 and a gate metal electrode 13 are provided on the interlayer insulating film 12; the source metal electrode 14 passes through the spacer insulating film and the source N+ type junction 11 and contacts with the TEOS film 7 in the first trench and the third trench; the gate electrode passes through the interlayer insulating film 12 and contacts with the polycrystalline gate 5 in the fourth trench.

[0051] Based on the same inventive concept, the present invention also discloses a method for preparing a semiconductor power device, which comprises the following steps:

[0052] Step 1, forming the first level groove stage;

[0053] As shown in FIG5(a), a low-doping concentration N-type epitaxial layer 2 is grown on an N+ type substrate 1, and an oxide film and a nitride film masking layer are sequentially grown on the N-type epitaxial layer 2. Then, the groove area is defined by graphics, and according to the depth requirement of the channel length, the etching depth is down to the micron level, and the first-level grooves (second groove, fourth groove) are photolithographically formed.

[0054] Next, a TEOS (Tetra Ethly Ortho Silicate)-based borosilicate glass (BSG) film is applied using a plasma chemical vapor deposition (PECVD) method and directional etching is performed to leave the borosilicate glass film on the inner side of the first-level groove.

[0055] Before depositing the borosilicate glass film, in this embodiment, a sacrificial oxide film needs to be grown in the first-level trench, and then the oxide film is wet-etched to reduce the roughness of the inner wall of the first-level trench.

[0056] In this embodiment, the mask layer may use only one oxide film or one nitride film, or may use both an oxide film and a nitride film as required. In addition, a structure in which an oxide film is formed on a nitride film may also be used.

[0057] The above-mentioned N+ type substrate 1 can be silicon and silicon carbide single crystal chips of various crystal types, and the low-doping concentration N-type epitaxial layer 2 grown on the N+ type substrate 1 is an epitaxial wafer of the same quality as the N+ type substrate 1.

[0058] Step 2, forming a P-type well 3 stage;

[0059] As shown in FIG5(b), on the basis of step 1, the borosilicate glass (BGS) film on the sidewall of the trench is heat treated to diffuse the boron dopant to form a P-type well 3. The surface concentration and diffusion depth of the P-type well 3 can determine and adjust the trench gate threshold. After the P-type well 3 is formed, the borosilicate glass (BGS) film remaining on the sidewall of the trench is etched again to remove the borosilicate glass (BGS) film, and the first-level trench is further etched down to a certain depth to form a second-level trench (second trench, fourth trench) to improve the leakage current and voltage characteristics of the channel.

[0060] Step 3, the gate oxide film 4 and the polycrystalline gate 5 are formed;

[0061] As shown in FIG5(c), during the growth of the gate oxide film 4 and the electrode formation stage, a sacrificial oxide film is first grown in the second-level trench and then etched to smooth the rough trench surface, and then a gate oxide film 4 of a complex structure is grown in the second-level trench, the gate oxide film 4 being formed of a thermal oxide film and CVD or ethyl silicate. Etching is performed to leave the gate oxide film 4 on the inner side of the second-level trench.

[0062] After the polysilicon doped with phosphorus or arsenic is grown in the second-level trench, further graphic definition and formation of a polycrystalline gate 5 are performed. When the polysilicon is dry-etched, an oxide film is formed on the polysilicon at an ultra-high temperature.

[0063] Step 4, P+ type region 6 formation stage;

[0064] As shown in FIG5(d), a nitride layer is grown on the existing oxide layer of the polycrystalline gate 5; then, the P+ type region 6 is graphically defined, and the third level trenches (first trench, third trench, fifth trench) are defined by dry etching, and then boron dopants are ion implanted and heat treated to diffuse the boron dopants to form the P+ type region 6.

[0065] Step 5, the p-type column region 8 is formed;

[0066] As shown in FIG. 5( e ), based on step 4, the oxide film formed by the high temperature process is first removed, and the third-level trench is further etched to form a fourth-level trench. Then, a doped epitaxial film 9 is grown on the sidewall of the fourth-level trench, and then a layer of borosilicate glass is grown. Finally, the dopant is diffused to the periphery of the trench sidewall through a heat treatment process to form a p-type column region 8. At this time, the concentration and diffusion depth of the dopant can be adjusted by adjusting the time and temperature.

[0067] Step 6, TEOS film 7 formation stage;

[0068] As shown in FIG. 5( f ), based on the above steps, the BSG film is first wet-etched, and then low-pressure chemical deposition (LPCVD) is used to fill ethyl silicate into the fourth-level trench area to form a TEOS film. Next, the masking nitride film is removed with phosphoric acid, and the oxide film is re-grown dry. An n-type column region 10 is formed between the two p-type column regions 8.

[0069] Step 7, source N+ type junction 11 formation stage;

[0070] As shown in FIG. 5( g ), based on the above steps, the source N+ junction 11 region is firstly patterned and photolithographically defined, and then ion-implanted with high-concentration doped arsenic, the photoresist is removed and heat-treated to form the source N+ junction 11. At this time, the source N+ junction 11 and the upper end surface of the polycrystalline gate 5 are aligned side by side.

[0071] Step 8, interlayer insulating film 12 formation stage;

[0072] As shown in FIG5(h), based on the above, a TEOS oxide film and a BPSG oxide film are first grown, and then an HTO oxide film is grown on the upper layer to form an interlayer insulating film 12, and then heat treated. The contact part of the metal electrode is graphically defined, and the oxide film is removed by wet and dry etching, and then the photoresist is removed.

[0073] Step 9, metal electrode formation stage;

[0074] As shown in FIG. 5( i ), after the above-mentioned graphic definition and etching operations, aluminum metal wires are deposited on the upper surface through metal wiring to form a source metal electrode 14 and a gate metal electrode 13 .

[0075] Metal wiring is performed on the back side of the N+ type substrate 1 to form a drain metal electrode 15. Specifically, the upper surface is first protected with tape, and the substrate is thinned from the back side according to the need for substrate thinning. Then phosphorus (or boron) ions are implanted in sequence to deposit Ti / Ni / Ag metals, and then the front tape is removed, followed by the final heat treatment operation and cleaning.

[0076] The present invention uses one or more etching grooves as a super junction source structure to reduce the on-resistance of a high-voltage and high-current TDMOSFET power device, grows an epitaxial film on the inner sidewall of the groove, and injects necessary dopants into the epitaxial film to create N-type and P-type regions. Therefore, the present invention can effectively reduce the on-resistance of the device and increase the breakdown voltage of the device without affecting the characteristics such as the threshold voltage of TDMOS. Since power semiconductor devices have high power consumption, the heat generated by the device is reduced or the power consumption of the device in the on state is reduced by reducing the resistance of the device, thereby improving the efficiency and reliability of the component.

[0077] In the TDMOS device, the technology of the present invention first forms the first-level TDMOS trench, and then forms the secondary trenches in sequence. After the first-level and secondary trenches are formed, an epitaxial layer is grown on the sidewalls of the trench; at the same time, n-type or p-type doping is injected into the epitaxial layer by applying an appropriate process, and then the doping material is diffused to the sidewalls of the trench by heat treatment to form a gate insulating film, and the interior of the trench is filled with a common oxide film or polysilicon to form an electrode to complete the manufacture of the device. The present invention also combines a super junction drain and shortens the channel length of the trench component.

[0078] The above description is merely an embodiment of the present invention and does not limit the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A semiconductor power device, characterized in that: It comprises a substrate, wherein an epitaxial layer is provided on the front side of the substrate, and a drain metal electrode is provided on the back side; The epitaxial layer is provided with a first trench, a second trench, a third trench, a fourth trench and a fifth trench, the second trench is located between the first trench and the third trench, the third trench is located between the second trench and the fourth trench, and the fourth trench is located between the third trench and the fifth trench; The second trench and the fourth trench are provided with a P-type well at the periphery, a gate oxide film is provided on the inner sidewall, and a polycrystalline gate is filled inside; the polycrystalline gate in the fourth trench extends from the fourth trench to the outside of the fourth trench and is located above the epitaxial layer; The peripheries of the first trench, the third trench and the fifth trench are provided with a P+ type region and a P type column region, the P+ type region is located at the upper part of the trench, and the P type column region is located at the lower part of the trench; the inner sidewalls of the first trench, the third trench and the fifth trench are provided with a doped epitaxial film, which is filled with ethyl silicate to form a TEOS film; an N type column region is formed between the first trench and the second trench; A source N+ type junction is provided above the epitaxial layer, and an interlayer insulating film is provided above the epitaxial layer and the source N+ type junction; a source metal electrode and a gate metal electrode are provided on the interlayer insulating film; the source metal electrode passes through the spacer insulating film and the source N+ type junction and contacts with the TEOS film in the first trench and the third trench; the gate metal electrode passes through the interlayer insulating film and contacts with the polycrystalline gate in the fourth trench.

2. A method for preparing a semiconductor power device, characterized in that: The following steps are involved: Step 1, forming the first level groove stage; Growing an n-type epitaxial layer with a low doping concentration on an n+ type substrate, and growing a masking layer on the n-type epitaxial layer, and then defining the groove area by graphic processing, and etching the first-level groove; Depositing a borosilicate glass film in the first-level trench and performing directional etching to leave the borosilicate glass film on the inner side of the first-level trench; Step 2, forming a P-type well stage; On the basis of step 1, the borosilicate glass film on the side wall of the trench is thermally treated to diffuse the boron dopant to form a P-type well; after the P-type well is formed, the borosilicate glass film remaining on the side wall of the trench is etched again to remove the borosilicate glass film, and the first-level trench is etched downward to a certain depth to form a second-level trench; Step 3: Gate oxide film and polycrystalline gate formation stage; Growing a gate oxide film in the second-level trench, and then etching it to leave the gate oxide film on the inner side of the second-level trench; Continue to grow polysilicon doped with phosphorus or arsenic in the second-level trench, and define it graphically to form a polycrystalline gate; Step 4, P+ type region formation stage; A nitride layer is grown on the existing oxide layer of the polycrystalline gate; a P+ type region is then defined by patterning, a third level trench is defined by dry etching, and boron dopants are ion-implanted, and heat treatment is performed to diffuse the boron dopants to form a P+ type region; Step 5, P-type column area formation stage; removing the oxide film formed by the high temperature process, and further etching the third-level trench to form a fourth-level trench; growing a doped epitaxial film on the sidewall of the fourth-level trench, and then growing a layer of borosilicate glass; Finally, the dopant is diffused to the outside of the sidewall of the fourth-level trench through a heat treatment process to form a P-type column region; an n-type column region is formed between the two P-type column regions; Step 6, TEOS film formation stage; Based on the above steps, the borosilicate glass film is first wet-etched, and then low-pressure chemical deposition is used to fill ethyl silicate into the fourth-level groove area to form a TEOS film; Next, the masking nitride film is removed with phosphoric acid, and the oxide film is dry-grown again; Step 7, source N+ junction formation stage; Based on the above steps, the source N+ junction region is firstly patterned and photolithographically defined, and then ion implantation of high concentration doped arsenic is performed, and then the photoresist is removed and heat treatment is performed to form a source N+ junction; Step 8, interlayer insulating film formation stage; Grow TEOS oxide film and borosilicate glass thin film oxide film, then grow HTO oxide film on the upper layer to form an interlayer insulating film, and then perform heat treatment; graphically define the contact part of the metal electrode, remove the oxide film by wet and dry etching, and then remove the photoresist; Step 9, metal electrode formation stage; After the above-mentioned graphic definition and etching operations, aluminum metal wires are deposited on the upper surface through metal wiring to form source metal electrodes and gate metal electrodes; Metal wiring is performed on the back side of the N+ type substrate to form a drain metal electrode.

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