Impedance calibration circuit and method

Abstract

Embodiments of the present application provide an impedance calibration circuit and method, comprising: a pull-up resistor device to be calibrated, wherein the first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, and the second connection end of the pull-up resistor device to be calibrated is connected to a power supply; a pull-down resistor device to be calibrated, wherein the first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-down resistor device to be calibrated is connected to the third connection end of the pull-up resistor device to be calibrated, and the third connection end of the pull-down resistor device to be calibrated is grounded; and a calibration unit, wherein the calibration unit includes a voltage receiving end and a calibration code output end, and the calibration unit receives a first voltage and a second voltage via the voltage receiving end. By utilizing the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated, and the calibration unit, the present application can more simply and efficiently implement resistance calibration.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit design, and specifically, but not limited to, an impedance calibration circuit and method. Background Art

[0002] With the development of electronic information technology, the requirements for the resistance of transistors inside chips are getting higher and higher. For example, in the manufacturing process of various transistors, since the resistance of the transistor inside the transistor varies greatly with the process, it is usually difficult to directly produce on-chip resistors with precise resistance values. Therefore, the resistance value of the on-chip resistor needs to be calibrated separately. Therefore, how to better calibrate the impedance within the chip is an urgent problem to be solved. Summary of the Invention

[0003] The embodiments of the present application provide an impedance calibration circuit and method, which mainly solve the technical problem of how to simplify the impedance calibration process.

[0004] In a first aspect, an embodiment of the present application provides an impedance calibration circuit, comprising: a pull-up resistor device to be calibrated, wherein the first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, and the second connection end of the pull-up resistor device to be calibrated is connected to a power supply end; a pull-down resistor device to be calibrated, wherein the first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-down resistor device to be calibrated is connected to the third connection end of the pull-up resistor device to be calibrated, and the third connection end of the pull-down resistor device to be calibrated is grounded; and a calibration unit, wherein the calibration unit comprises a voltage receiving end and a calibration code output end, the calibration unit receiving a first voltage and a second voltage through the voltage receiving end, the first voltage being the output voltage of the pull-up resistor device to be calibrated, and the second voltage being the output voltage of the pull-down resistor device to be calibrated, the calibration unit being configured to obtain a first calibration code and a second calibration code based on the first voltage and the second voltage, the calibration unit being configured to calibrate the resistance value of the pull-up resistor device to be calibrated using the first calibration code, and to calibrate the resistance value of the pull-down resistor device to be calibrated using the second calibration code.

[0005] Optionally, the impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is respectively connected to the pull-up resistor device to be calibrated and the calibration unit, and a second connection end of the calibration resistor is grounded.

[0006] Optionally, the pull-up resistor device to be calibrated includes multiple pull-up sub-resistance devices, each of the pull-up sub-resistance devices includes a first switching element and a first resistor, the first connection end of the first switching element is connected to the power supply end, the control end of the first switching element is connected to the calibration unit, the second connection end of the first switching element is connected to the first connection end of the first resistor, and the second connection end of the first resistor is respectively connected to the calibration resistor and the pull-down resistor device to be calibrated.

[0007] Optionally, the first switching element is a PMOS transistor, a source of the PMOS transistor is connected to the power supply end, a gate of the PMOS transistor is connected to the calibration unit, and a drain of the PMOS transistor is connected to the first connection end of the first resistor.

[0008] Optionally, the pull-down resistor device to be calibrated includes multiple pull-down sub-resistance devices, each of the pull-down sub-resistance devices includes a second resistor and a second switching element, the first connection end of the second resistor is connected to the first resistor, the second connection end of the second resistor is connected to the first connection end of the second switching element, the control end of the second switching element is connected to the calibration unit, and the second connection end of the second switching element is grounded.

[0009] Optionally, the second switch element is an NMOS transistor, a source of the NMOS transistor is connected to the second connection end of the second resistor, a gate of the NMOS transistor is connected to the calibration unit, and a drain of the NMOS transistor is grounded.

[0010] Optionally, the impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is respectively connected to the pull-down resistor device to be calibrated and the calibration unit, and a second connection end of the calibration resistor is grounded.

[0011] Optionally, the calibration unit includes a comparator, a logic processing unit, a converter and a latch; the comparator includes a first voltage receiving end and a second voltage receiving end, the first voltage receiving end is used to receive the first voltage or the second voltage, the second voltage receiving end is used to receive the reference voltage, the comparator is used to compare the first voltage with the reference voltage to obtain the first calibration code, and compare the second voltage with the reference voltage to obtain the second calibration code; the first connection end of the logic processing unit is connected to the comparator, the second connection end of the logic processing unit is connected to the first connection end of the converter, the second connection end of the converter is connected to the first connection end or the second connection end of the latch, the second connection end of the latch is connected to the pull-up resistor device to be calibrated, and the latch is used to store the first calibration code or the second calibration code transmitted by the converter.

[0012] In a second aspect, an embodiment of the present application further provides an impedance calibration method, which is applied to the impedance calibration circuit of the first aspect, and the method includes: receiving a first voltage and a second voltage, the first voltage being the output voltage of the pull-up resistor device to be calibrated, and the second voltage being the output voltage of the pull-down resistor device to be calibrated; obtaining a first calibration code and a second calibration code based on the first voltage and the second voltage; using the first calibration code to calibrate the resistance value of the pull-up resistor device to be calibrated, and using the second calibration code to calibrate the resistance value of the pull-down resistor device to be calibrated.

[0013] Optionally, calibrating the resistance of the pull-up resistor device to be calibrated using the first calibration code, and calibrating the resistance of the pull-down resistor device to be calibrated using the second calibration code, includes: determining the number of effective resistors according to the first calibration code and the second calibration code, and calibrating the resistance values ​​of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated according to the number of effective resistors.

[0014] An embodiment of the present application provides an impedance calibration circuit and method. The impedance calibration circuit includes a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated, and a calibration unit. The first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-up resistor device to be calibrated is connected to a power supply end, the first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-down resistor device to be calibrated is connected to a third connection end of the pull-up resistor device to be calibrated, and the third connection end of the pull-down resistor device to be calibrated is grounded. The calibration unit includes a voltage receiving end and a calibration code output end. The calibration unit receives a first voltage and a second voltage through the voltage receiving end, wherein the first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated. The calibration unit is configured to obtain a first calibration code and a second calibration code based on the first voltage and the second voltage. The calibration unit is configured to calibrate the resistance value of the pull-up resistor device to be calibrated using the first calibration code and to calibrate the resistance value of the pull-down resistor device to be calibrated using the second calibration code. The present application can achieve resistance calibration more simply and effectively by combining the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated, and the calibration unit, and can simplify the conditions for impedance calibration to a certain extent.

[0015] Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least some of the beneficial effects become obvious from the description in the specification of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural diagram of a basic impedance calibration circuit;

[0017] Figure 2 This is a schematic diagram of the pull-up resistor calibration structure in the basic impedance calibration circuit;

[0018] Figure 3 This is a schematic diagram of the structure corresponding to the pull-up resistor calibration in the basic impedance calibration circuit;

[0019] Figure 4 This is a schematic diagram of the structure corresponding to the pull-down resistor calibration in the basic impedance calibration circuit;

[0020] Figure 5 A schematic structural diagram of an impedance calibration circuit provided in one embodiment of the present application;

[0021] Figure 6 A schematic diagram of the physical structure of an impedance calibration circuit provided in one embodiment of the present application;

[0022] Figure 7 A schematic diagram of a pull-up resistor device to be calibrated in an impedance calibration circuit provided in one embodiment of the present application;

[0023] Figure 8 A schematic diagram of a pull-down resistor device to be calibrated in an impedance calibration circuit provided in one embodiment of the present application;

[0024] Figure 9 A flowchart of an impedance calibration method provided in one embodiment of the present application;

[0025] Figure 10 A circuit block diagram corresponding to a pull-up resistor device to be calibrated in an impedance calibration method provided in one embodiment of the present application;

[0026] Figure 11 This is a circuit block diagram corresponding to a pull-down resistor device to be calibrated in an impedance calibration method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] To ensure signal integrity, high-speed chip I / O (Input / Output) devices typically require the impedance of the transmitter and receiver to match the characteristic impedance of the channel, typically 50Ω. However, due to process variations, internal chip transistors and resistors can vary by approximately 20%. Therefore, to mitigate the impact of this variation on signal integrity, impedance calibration is necessary. FPGA I / O devices typically need to support a wide range of protocols. The voltage levels of different protocols cause transistors to operate in different voltage ranges, resulting in varying output impedances. Therefore, a single impedance calibration method cannot guarantee universal applicability or meet accuracy requirements. Furthermore, selecting different calibration settings for different protocols incurs significant costs. Furthermore, given limited I / O resources, reducing the number of I / O devices available for calibration means more resources are available to the application. Therefore, reducing the I / O resources used for calibration is a pressing issue.

[0029] The basic structure of the existing impedance calibration circuit is as follows Figure 1 As shown, Figure 1 R in u and R d They are pull-up and pull-down output impedance, MP <m:0>To adjust the pull-up impedance control code, MP <m:0>Used to control the number of branches that are turned on, such as MP <m:0>=11000, means opening 2 channels and closing the other 3 channels; MN <m:0>To adjust the pull-down impedance control code, MN <m:0>Used to control the number of branches that are turned on. Due to the impedance matching requirement, it is necessary to ensure that R u and R d To achieve a reliable accuracy range, the pull-up resistor and the pull-down resistor need to be calibrated separately.

[0030] To calibrate the pull-up output impedance R u For example (the pull-down path is closed at this time), the existing calibration method is as follows Figure 2 As shown, Figure 2 V in ref is the reference voltage, V out For output voltage, the calibration circuit module is used to compare V out With V ref The voltage of the two is used to determine the size of the two values, and then the control code MP is obtained by comparison. <m:0>Adjust the number of conduction paths to adjust the drive strength so that V out The output voltage is equal to the set reference voltage V ref .

[0031] When calibrating the impedance of different protocols, the existing technology requires external connection of different resistors and voltages, which increases the cost of chip configuration to a certain extent and has low applicability. For example, protocol 1 requires a common mode level of 0.5*V CCIO (V CCIO =1.2V), then the external VC needs to be grounded, and when Vout is calibrated to 0.5*V CCIO , at this time R u =R ref , and the common mode level is 0.5*V CCIO For example, protocol 2 requires the common mode level to be 0.75*V CCIO (V CCIO =1.2V), the external VC needs to be connected to 0.5*V CCIO , when Vout is calibrated to 0.75*V CCIO , then R u =R ref , and the common mode level is 0.75*V CCIO The calibration circuits for Protocol 1 and Protocol 2 are as follows: Figure 3 and Figure 4 As shown, through Figure 3 and Figure 4 It can be seen that the common mode level requirement is 0.5*V CCIO When you need to connect the external VC to V CCIO , and the common mode level requirement is 0.5*V CCIO When the external VC needs to be connected to 0.75V CCIO .

[0032] In summary, when calibrating impedance in the existing technology, different protocols require the system to provide different potentials, and the pull-up IO and pull-down IO need to be connected to external resistors at the same time to achieve calibration of the pull-up resistor and the pull-down resistor respectively. This increases the chip environment configuration cost to a certain extent, the user experience is not good, and the applicability is also relatively low.

[0033] In response to the above problems, the inventors proposed the impedance calibration circuit and method provided in the embodiments of the present application. The embodiments of the present application can simplify the implementation conditions of impedance calibration by combining the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated and the calibration unit, and can reduce the plate making requirements to a certain extent.

[0034] See also Figure 5 , is an impedance calibration circuit provided by an embodiment of the present application. The impedance calibration circuit 100 may include a pull-up resistor device 110 to be calibrated, a pull-down resistor device 120 to be calibrated, and a calibration unit 130.

[0035] In some embodiments, the first connection terminal 111 of the pull-up resistor device 110 to be calibrated is connected to the calibration unit 130, and the second connection terminal 112 of the pull-up resistor device 110 to be calibrated is connected to the power supply terminal 114. In addition, the first connection terminal 121 of the pull-down resistor device 120 to be calibrated is connected to the calibration unit 130, the second connection terminal 122 of the pull-down resistor device 120 to be calibrated is connected to the third connection terminal 113 of the pull-up resistor device 110 to be calibrated, and the third connection terminal 123 of the pull-down resistor device 120 to be calibrated is grounded.

[0036] In an embodiment of the present application, the calibration unit 130 may include a voltage receiving terminal 131 and a calibration code output terminal 132. The calibration unit 130 receives a first voltage and a second voltage through the voltage receiving terminal 131, where the first voltage is the output voltage of the pull-up resistor device 110 to be calibrated, and the second voltage is the output voltage of the pull-down resistor device 120 to be calibrated. The calibration unit 130 obtains a first calibration code and a second calibration code based on the first voltage and the second voltage. The calibration unit 130 is used to calibrate the resistance value of the pull-up resistor device 110 to be calibrated using the first calibration code, and to calibrate the resistance value of the pull-down resistor device 120 to be calibrated using the second calibration code.

[0037] For a clearer understanding, the relationship between the pull-up resistor device 110 to be calibrated, the pull-down resistor device 120 to be calibrated, and the calibration unit 130 is given in the embodiment of the present application. Figure 6 The physical structure diagram of the calibration circuit is shown in FIG. Figure 6 It can be seen that in other embodiments, the impedance calibration circuit 100, in addition to including the pull-up resistor device 110 to be calibrated, the pull-down resistor device 120 to be calibrated, and the calibration unit 130, may also include a calibration resistor 140, wherein the first connection end of the calibration resistor 140 is respectively connected to the pull-up resistor device 110 to be calibrated and the calibration unit 130, and the second connection end of the calibration resistor 140 is grounded (GND).

[0038] As a method, the pull-up resistor device 110 to be calibrated includes a plurality of pull-up sub-resistance devices 115, each of the pull-up sub-resistance devices 115 (R u ) includes a first switch element 1151 and a first resistor 1152, wherein a first connection end of the first switch element 1151 is connected to the power supply end 114 (V CCIO ), the control end of the first switch element 1151 is connected to the calibration unit 130, the second connection end of the first switch element 1151 is connected to the first connection end of the first resistor 1152, and the second connection end of the first resistor 1152 is connected to the calibration resistor 140 (R ref ) is connected to the pull-down resistor device 120 to be calibrated.

[0039] In a specific embodiment, the first switching element 1151 is a PMOS transistor, the source of the PMOS transistor is connected to the power supply terminal, the gate of the PMOS transistor is connected to the calibration unit 130, and the drain of the PMOS transistor is connected to the first connection terminal of the first resistor 1152. In addition, the first switching element 1151 may also be an NMOS transistor. The specific type of switch of the first switching element 1151 is not specifically limited here and can be selected according to actual circumstances.

[0040] In some other embodiments, the pull-down resistor device 120 to be calibrated includes a plurality of pull-down sub-resistance devices 124 (R d ), each of the pull-down sub-resistance devices 124 includes a second resistor 1241 and a second switch element 1242, the first connection end of the second resistor 1241 is connected to the first resistor 1152, the second connection end of the second resistor 1241 is connected to the first connection end of the second switch element 1242, the control end of the second switch element 1242 is connected to the calibration unit 130, and the second connection end of the second switch element 1242 is grounded (GND).

[0041] Alternatively, the second switch element 1242 is an NMOS transistor. The source of the NMOS transistor may be connected to the second connection terminal of the second resistor 1241, the gate of the NMOS transistor may be connected to the calibration unit 130, and the drain of the NMOS transistor is grounded. Alternatively, the second switch element 1242 may be a PMOS transistor. The specific type of the second switch element 1242 is not specifically limited here and may be selected based on actual circumstances.

[0042] In order to more clearly understand the calibration process of the corresponding resistance values ​​of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated, the following is given: Figure 7 and Figure 8 The structural diagram shown. Figure 7 The schematic diagram of the pull-up resistor to be calibrated is shown in Figure 1. Figure 7 It can be seen that the calibration unit 130 may include a comparator 133 , a logic processing unit 134 , a converter 135 and a latch 136 .

[0043] In some embodiments, the comparator 133 may include a first voltage receiving terminal and a second voltage receiving terminal, wherein the first voltage receiving terminal is configured to receive the first voltage or the second voltage (V out ), the second voltage receiving end is used to receive the reference voltage (V ref The first voltage receiving terminal may include a first sub-voltage receiving terminal and a second sub-voltage receiving terminal. The calibration unit 130 is connected to the pull-up resistor device 110 to be calibrated via the first sub-voltage receiving terminal and receives the output voltage of the pull-up resistor device to be calibrated, which can be used as the first voltage. The calibration unit 130 is connected to the pull-down resistor device 120 to be calibrated via the second sub-voltage receiving terminal and receives the output voltage of the pull-down resistor device to be calibrated, which can be used as the second voltage. The comparator 133 is used to compare the first voltage with the reference voltage to obtain the first calibration code (Mp <m:0>), and comparing the second voltage with the reference voltage to obtain the second calibration code (Mn <m:0>).

[0044] In addition, a first connection terminal of the logic processing unit 134 is connected to the comparator 133, and a second connection terminal of the logic processing unit 134 is connected to the first connection terminal of the converter 135. The logic processing unit 134 can also be referred to as a successive approximation logic. The logic processing unit 134 is configured to receive the comparison result sent by the comparator 133 and a clock signal (CLK), and to successively adjust the first voltage or the second voltage when the comparison result sent by the comparator 133 does not meet a preset condition. Therefore, the impedance calibration circuit in this embodiment of the present invention may further include a clock generation subcircuit, which is connected to the logic processing unit 134 and is configured to provide a clock signal to the logic processing unit 134.

[0045] As a mode, the second connection terminal of the converter 135 is connected to the first connection terminal or the second connection terminal of the latch. The function of the converter 135 is to control whether to calibrate the resistance value of the pull-up resistor device 110 to be calibrated or to calibrate the resistance value of the pull-down resistor device 120 to be calibrated. That is, when the converter 135 is connected to IO1 (the output of the pull-up resistor device 110 to be calibrated), the impedance calibration circuit 100 adjusts the resistance value of the pull-up resistor device 110 to be calibrated in the pull-up branch. At this time, the pull-down branch is in a closed state, that is, the second calibration code (Mn) of the pull-down branch is calibrated. <m:0>) is set to 0, and the pull-down branch where the pull-down resistor device 120 to be calibrated is located is in a closed state. Optionally, the second connection end of the latch 136 is connected to the pull-up resistor device 110 to be calibrated, and the latch 136 is used to store the first calibration code or the second calibration code transmitted by the converter 135.

[0046] In summary, when calibrating the resistance of the pull-up resistor device 110 to be calibrated, the inputs of the comparator 133 are the reference voltage (Vref) and the first voltage (Vout1), wherein the first voltage is the output voltage of the pull-up resistor device 110 to be calibrated, and the converter 135 is connected to the first calibration code value (Mp) of IO1 corresponding to the pull-up resistor device 110 to be calibrated. <m:0>The internal pull-down branch (the branch where the pull-down resistor device 120 to be calibrated is located) is calibrated by the second calibration code value (Mn <m:0>) is set to 0 to turn it off.

[0047] In the embodiment of the present invention, the first calibration code (Mp) can be obtained by the comparator 133 and the logic processing unit 134. <m:0>), and then the resistance of the pull-up resistor device 110 to be calibrated can be adjusted from high to low based on the first calibration code, so that the first voltage Vout gradually approaches the reference voltage Vref until the last bit is quantized. <m:0>The value is saved. In this way, the resistance of the pull-up resistor device to be calibrated can be calibrated. When the resistance calibration of the pull-up resistor device to be calibrated 110 is completed, the converter 135 switches to the Mn of IO2. <m:0>(the branch where the pull-down resistor device 120 to be calibrated is located), at this time, one end of the comparator 133 is connected to the reference voltage Vref, and the other end is connected to the voltage output end of the pull-down resistor device 120 to be calibrated, for receiving the second voltage.

[0048] As a method, the structure of the pull-down resistor device 120 to be calibrated is as follows: Figure 8 As shown, from Figure 8 It can be seen that when the resistance value of the pull-down resistor device 120 to be calibrated is calibrated, it is mainly based on the first calibration code obtained from the pull-up resistor device 110 to be calibrated. <m:0>Mp mapped to IO2 <m:0>The second calibration code Mn is obtained by the comparator 133 and the logic processing unit 134. <m:0>Then, the resistance of the pull-down resistor 120 to be calibrated can be adjusted from high to low based on the second calibration code, so that the second voltage Vout gradually approaches the reference voltage Vref until the last bit is quantized. <m:0>to save.

[0049] In some embodiments, the first calibration code value Mp output by the calibration unit 130 is <m:0>and the second calibration code value Mn <m:0>, corresponding to each section of the driver, the output impedance is the calibrated pull-up resistor R u With the pull-down resistor R d resistance value.

[0050] In other embodiments, the calibration resistor 140 included in the impedance calibration circuit 100 may also be connected to the pull-down resistor device 120 to be calibrated (not shown). Specifically, the first connection end of the calibration resistor 140 is respectively connected to the pull-down resistor device 120 to be calibrated and the calibration unit 130, and the second connection end of the calibration resistor 140 is grounded. In addition, the pull-down resistor device 120 to be calibrated includes a plurality of pull-down sub-resistors 124, each of which may include a second switch element 1242 and a second resistor 1241. The first connection end of the second switch element 1242 is connected to the power supply terminal 114, the control end of the second switch element 1242 is connected to the calibration unit 130, the second connection end of the second switch element 1242 is connected to the first connection end of the second resistor 1241, and the second connection end of the second resistor 1241 is respectively connected to the calibration resistor 140 and the pull-up resistor device 110 to be calibrated. The second switch element 1242 may be a PMOS transistor or an NMOS transistor.

[0051] As another example, the pull-up resistor device 110 to be calibrated includes a plurality of pull-up sub-resistance devices 115, each of which (R u ) includes a first switching element 1151 and a first resistor 1152. A first connection end of the first resistor 1152 is connected to the second resistor 1241, a second connection end of the first resistor 1152 is connected to the first connection end of the first switching element 1151, a control end of the first switching element 1151 is connected to the calibration unit 130, and a connection end of the first switching element 1151 is grounded. The first switching element 1151 can be a PMOS transistor or an NMOS transistor.

[0052] In summary, in an embodiment of the present invention, a calibration resistor 140 can be connected to the pull-up resistor device 110 to be calibrated, and the resistance of the pull-up resistor device 110 to be calibrated can be calibrated by the calibration resistor 140, and then the resistance of the pull-down resistor device 120 to be calibrated can be calibrated based on the calibration result of the pull-up resistor device 110 to be calibrated. Alternatively, in an embodiment of the present invention, a calibration resistor 140 can be connected to the pull-down resistor device 120 to be calibrated, and the resistance of the pull-down resistor device 120 to be calibrated can be calibrated by the calibration resistor 140, and then the resistance of the pull-up resistor device 110 to be calibrated can be calibrated based on the calibration result of the pull-down resistor device 120 to be calibrated. It can be seen that the calibration resistor 140 can be connected to the pull-up resistor device 110 to be calibrated, or it can be connected to the pull-down resistor device 120 to be calibrated. Specifically, whether to connect to the pull-up resistor device 110 to be calibrated or to the pull-down resistor device 120 to be calibrated is not explicitly limited here and can be selected according to actual circumstances.

[0053] An embodiment of the present application provides an impedance calibration circuit, which includes a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated, and a calibration unit, wherein a first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, a second connection end of the pull-up resistor device to be calibrated is connected to a power supply end, a first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-down resistor device to be calibrated is connected to a third connection end of the pull-up resistor device to be calibrated, and the third connection end of the pull-down resistor device to be calibrated is grounded. The calibration unit includes a voltage receiving end and a calibration code output end, the calibration unit receives a first voltage and a second voltage through the voltage receiving end, the first voltage being the output voltage of the pull-up resistor device to be calibrated, and the second voltage being the output voltage of the pull-down resistor device to be calibrated. The calibration unit is configured to obtain a first calibration code and a second calibration code based on the first voltage and the second voltage, and to calibrate the resistance value of the pull-up resistor device to be calibrated using the first calibration code and to calibrate the resistance value of the pull-down resistor device to be calibrated using the second calibration code. The present application can achieve resistance calibration more simply and effectively by combining the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated, and the calibration unit, thereby simplifying the conditions for impedance calibration to a certain extent.

[0054] See also Figure 9 , is a flow chart of an impedance calibration method provided in an embodiment of the present application, which is applied to the above-mentioned impedance calibration circuit, through Figure 9 It can be seen that the method may include steps S210 to S230.

[0055] Step S210: receiving a first voltage and a second voltage, wherein the first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated.

[0056] Step S220: obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage.

[0057] As a method, when the first voltage is obtained, the embodiment of the present invention can compare the first voltage with the reference voltage and determine whether the first voltage is greater than the reference voltage. If it is greater, the number of bits corresponding to the first calibration code value is 1; if the first voltage is less than the reference voltage, the number of bits corresponding to the first calibration code value is 0.

[0058] In addition, when the first voltage is greater than the reference voltage, the embodiment of the present invention can adjust the first voltage, that is, increase the first voltage, and then compare the increased first voltage with the reference voltage again to obtain another bit value corresponding to the first calibration code. The number of comparisons determines the number of bits of the corresponding code value. The specific number of comparisons can be selected according to actual conditions and is not explicitly limited here. For example, when calibrating the pull-up resistor, the reference voltage and the first voltage are compared and adjusted five times. The first voltage is equal to the reference voltage, and the first two times the first voltage is greater than the reference voltage, while the last three times the first voltage is less than the reference voltage. At this time, the first calibration code obtained is 11000, that is, MP <m:0>=11000, from the above introduction we know that MP <m:0>The control is to open the number of branches corresponding to the pull-up resistor to be calibrated. In addition, the embodiment of the present invention can also determine whether the first voltage is greater than the reference voltage. If it is less than, the first voltage is increased accordingly to achieve calibration of the pull-up resistor or the pull-down resistor.

[0059] Similar to the first calibration code acquisition process, the embodiment of the present invention can also compare the second voltage with the reference voltage when the second voltage is acquired, and determine whether the second voltage is greater than the reference voltage. If it is, the number of bits corresponding to the second calibration code value is 1. If the second voltage is less than the reference voltage, the number of bits corresponding to the second calibration code value is 0. In addition, when the second voltage is greater than the reference voltage, the embodiment of the present invention can adjust the second voltage, that is, increase the second voltage, and then compare the increased second voltage with the reference voltage again to obtain another bit value corresponding to the second calibration code. The number of comparisons determines the number of bits of the corresponding code value. For example, when calibrating the pull-down resistor, the reference voltage and the second voltage are compared and adjusted five times, and the second voltage is greater than the reference voltage for the first three times, and less than the reference voltage for the last two times. At this time, the second calibration code obtained is 11100, that is, MN <m:0>=11100, from the above introduction we know that MN <m:0>The control is to open the number of branches corresponding to the pull-down resistors to be calibrated. The adjustment of the pull-down resistor is similar to that of the pull-up resistor, so I will not go into details here.

[0060] Step S230: calibrating the resistance of the pull-up resistor to be calibrated using the first calibration code, and calibrating the resistance of the pull-down resistor to be calibrated using the second calibration code.

[0061] In some embodiments, after obtaining the first calibration code and the second calibration code, the present invention can use the first calibration code to calibrate the resistance of the pull-up resistor device to be calibrated, and can use the second calibration code to calibrate the resistance of the pull-down resistor device to be calibrated.

[0062] In other embodiments, after obtaining the reference voltage and the output voltage, the embodiment of the present invention can also obtain the number N of first resistors connected in the pull-up resistor to be calibrated according to a preset formula. p and the number N of second resistors connected in the pull-down resistor to be calibrated n , and obtain the resistance value of the calibration resistor R ref Specifically, when calibrating the pull-up resistor, the embodiment of the present invention can make R ref =a*R u , V ref =b*V CCIO , where R ref is the calibration resistor, R u is a pull-up resistor, V CCIO is the first voltage, a is the resistance coefficient, and b is the voltage coefficient, where b∈(0,1). In addition, the reference voltage Vref satisfies the following formula:

[0063]

[0064] The above formula represents the relationship between voltage and resistance value, where N p Refers to the number of effective resistors in the pull-up resistor device to be calibrated, that is, the number of segments in the pull-up resistor device to be calibrated. The actual number of segments is N p +1. R u Refers to the pull-up resistor value, R ref Refers to the calibration resistor value, V CCIO Refers to the output voltage value of the pull-up resistor device to be calibrated, that is, the first voltage value, V ref It refers to the reference voltage value.

[0065] In some implementations, after obtaining the above formula, embodiments of the present invention may convert it into a solution for a and b, that is, obtain the following formula:

[0066]

[0067] The embodiment of the present invention can Convert the numerator and denominator to the smallest irreducible integer and we get From the above introduction, we can know that the reference voltage V ref is known, so the value of b is also known. For example, the first voltage V CCIO =1V, reference voltage V ref =0.7V, we can get b=0.7 by calculation, and put the obtained b value into the above formula. Converting to the smallest irreducible integer, we can get Let N p +1=b2, From the above formula, we can calculate N p and R ref , and N can be obtained at the same time n =b1.

[0068] As a method, the embodiment of the present invention can determine the number of effective resistors according to the first calibration code and the second calibration code, and calibrate the resistance values ​​of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated according to the number of effective resistors.

[0069] In order to better understand the embodiment of the present invention, a specific implementation is now given. ref 0.75*V CCIO , where the first voltage V CCIO =1.2V, the pull-up resistor R needs to be calibrated u Equal to the pull-down resistor R d , and the resistance is 50Ω. Using the method described above, we can calculate b=V ref / V CCIO =0.75, Right now So we can get b2=3, b1=1, and then we can know N p +1=3, that is, N p =2, and N n = 1. Therefore, we can get Figure 10 and Figure 11 Schematic diagram of the calibration results.

[0070] For programmable devices like FPGAs, this embodiment of the present invention, combined with the configurable I / O drive capabilities, can fully utilize configurable resources, achieving an optimal solution for both convenience and resource utilization. Furthermore, this embodiment of the present invention integrates calibration functionality for different common-mode levels (reference voltages) within the chip, enabling easy configuration without requiring an external voltage source. This simplifies the implementation of impedance calibration and, to a certain extent, reduces platemaking requirements.

[0071] In summary, the embodiment of the present application provides an impedance calibration circuit and method, which can achieve impedance calibration more simply and efficiently by utilizing the impedance calibration circuit, wherein the impedance calibration circuit includes a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated, and a calibration unit, wherein the first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-up resistor device to be calibrated is connected to the power supply end, the first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, the second connection end of the pull-down resistor device to be calibrated is connected to the third connection end of the pull-up resistor device to be calibrated, and the pull-up resistor device to be calibrated is connected to the calibration unit. The third connection terminal of the pull-down resistor device is grounded. The calibration unit includes a voltage receiving terminal and a calibration code output terminal. The calibration unit receives a first voltage and a second voltage through the voltage receiving terminal. The first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated. The calibration unit is used to obtain a first calibration code and a second calibration code based on the first voltage and the second voltage. The calibration unit is used to calibrate the resistance value of the pull-up resistor device to be calibrated using the first calibration code, and to calibrate the resistance value of the pull-down resistor device to be calibrated using the second calibration code. The present application can more simply and effectively implement resistance calibration by combining the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated, and the calibration unit, thereby simplifying the conditions for impedance calibration to a certain extent. In addition, the embodiment of the present invention only requires one calibration resistor during calibration. After the calibration is completed, some IO can be released, saving IO and enhancing the universal applicability of customers.

[0072] It can be seen that those skilled in the art should understand that all or some of the steps, systems, and functional modules / units in the methods disclosed above can be implemented as software (which can be implemented using computer program code executable by a computing system), firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit.

[0073] In addition, it is well known to those skilled in the art that communication media generally contain computer-readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media. Therefore, the present invention is not limited to any specific hardware and software combination.

[0074] The above content is a further detailed description of the embodiments of the present invention in conjunction with specific implementation methods, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An impedance calibration circuit, characterized in that: The impedance calibration circuit comprises: A pull-up resistor device to be calibrated, wherein a first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, and a second connection end of the pull-up resistor device to be calibrated is connected to the power supply end; a pull-down resistor device to be calibrated, wherein a first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, a second connection end of the pull-down resistor device to be calibrated is connected to a third connection end of the pull-up resistor device to be calibrated, and the third connection end of the pull-down resistor device to be calibrated is grounded; a calibration unit, the calibration unit comprising a voltage receiving end and a calibration code output end, the calibration unit receiving a first voltage and a second voltage via the voltage receiving end, the first voltage being the output voltage of the pull-up resistor device to be calibrated, and the second voltage being the output voltage of the pull-down resistor device to be calibrated, the calibration unit being configured to obtain a first calibration code and a second calibration code based on the first voltage and the second voltage, the calibration unit being configured to calibrate the resistance value of the pull-up resistor device to be calibrated using the first calibration code, and to calibrate the resistance value of the pull-down resistor device to be calibrated using the second calibration code; Wherein, the calibration unit includes a comparator, a logic processing unit, a converter and a latch; The comparator includes a first voltage receiving terminal and a second voltage receiving terminal, the first voltage receiving terminal includes a first sub-voltage receiving terminal and a second sub-voltage receiving terminal, the first sub-voltage receiving terminal is connected to the pull-up resistor device to be calibrated, the second sub-voltage receiving terminal is connected to the pull-down resistor device to be calibrated, and the second voltage receiving terminal is used to receive a reference voltage. The first connection terminal of the logic processing unit is connected to the output terminal of the comparator. When the first sub-voltage receiving terminal receives the first voltage, the logic processing unit obtains a first calibration code through successive approximation logic. When the second sub-voltage receiving terminal receives the second voltage, the logic processing unit obtains a second calibration code through successive approximation logic. The second connection end of the logic processing unit is connected to the first connection end of the converter, the second connection end of the converter is connected to the first connection end or the second connection end of the latch, the output end of the latch is connected to the pull-up resistor device to be calibrated or the pull-down resistor device to be calibrated, and the latch is used to store the first calibration code or the second calibration code transmitted by the converter.

2. The impedance calibration circuit according to claim 1, wherein: The impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is respectively connected to the pull-up resistor device to be calibrated and the calibration unit, and a second connection end of the calibration resistor is grounded.

3. The impedance calibration circuit according to claim 2, wherein: The pull-up resistor device to be calibrated includes multiple pull-up sub-resistance devices, each of the pull-up sub-resistance devices includes a first switching element and a first resistor, the first connection end of the first switching element is connected to the power supply end, the control end of the first switching element is connected to the calibration unit, the second connection end of the first switching element is connected to the first connection end of the first resistor, and the second connection end of the first resistor is respectively connected to the calibration resistor and the pull-down resistor device to be calibrated.

4. The impedance calibration circuit according to claim 3, wherein: The first switch element is a PMOS transistor, a source of the PMOS transistor is connected to the power supply end, a gate of the PMOS transistor is connected to the calibration unit, and a drain of the PMOS transistor is connected to the first connection end of the first resistor.

5. The impedance calibration circuit according to claim 3, wherein: The pull-down resistor device to be calibrated includes multiple pull-down sub-resistance devices, each of the pull-down sub-resistance devices includes a second resistor and a second switching element, the first connection end of the second resistor is connected to the first resistor, the second connection end of the second resistor is connected to the first connection end of the second switching element, the control end of the second switching element is connected to the calibration unit, and the second connection end of the second switching element is grounded.

6. The impedance calibration circuit according to claim 5, characterized in that: The second switch element is an NMOS transistor, a source of the NMOS transistor is connected to the second connection end of the second resistor, a gate of the NMOS transistor is connected to the calibration unit, and a drain of the NMOS transistor is grounded.

7. The impedance calibration circuit according to claim 1, wherein: The impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is respectively connected to the pull-down resistor device to be calibrated and the calibration unit, and a second connection end of the calibration resistor is grounded.

8. An impedance calibration method, characterized in that: Applied to the impedance calibration circuit according to any one of claims 1 to 7, the method comprising: receiving a first voltage and a second voltage, wherein the first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated; Obtaining a first calibration code and a second calibration code by successive approximation logic according to the first voltage and the second voltage; The resistance value of the pull-up resistor device to be calibrated is calibrated using the first calibration code, and the resistance value of the pull-down resistor device to be calibrated is calibrated using the second calibration code.

9. The method according to claim 8, characterized in that The step of calibrating the resistance of the pull-up resistor device to be calibrated by using the first calibration code, and calibrating the resistance of the pull-down resistor device to be calibrated by using the second calibration code, comprises: The number of effective resistors is determined according to the first calibration code and the second calibration code, and the resistance values ​​of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated are calibrated according to the number of effective resistors.

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