Asynchronous processor architecture

Abstract

A data processing method, comprising: a control unit, at least one ALU (9), a set of registers (11), a memory (13) and a memory interface (15). The method comprises: a) obtaining (101, 102) the memory address of an operand; b) reading (103, 104) the operand from the memory (13); c) transmitting (105) an instruction to perform a calculation operation to the ALU (9) without any addressing instruction; d) performing all basic operations (106) by means of the ALU (9) receiving each operand at input from the register (11); e) storing (107) data forming the result of the processing operation on the register (11); f) obtaining (108) the memory address of each data forming the result of the processing operation; g) writing (109) the result to the memory (13) for storage by means of the obtained memory address via the memory interface (15).

Description

Technical Field

[0001] The present invention relates to the field of processors and to the functional architecture of processors. Background Art

[0002] Conventionally, a computing device comprises a collection of one or more processors. Each processor comprises one or more processing units or PUs. Each PU comprises one or more computing units called arithmetic logic units or ALUs. In order to have a high performance computing device, that is, a computing device that is fast in order to perform computing operations, it is conventional practice to provide a high number of ALUs. Therefore, the ALUs are able to process operations in parallel (i.e., simultaneously). Thus, the unit of time is a computing cycle. Therefore, the computing power of a computing device is usually quantified in terms of the number of operations that can be performed per computing cycle.

[0003] However, a significant portion of the computing power of a computing device is consumed in order to manage memory access operations. This device comprises a memory assembly, which itself comprises one or more memory cells, each memory cell having a fixed number of memory locations capable of permanently storing computing data. During computing processing operations, the ALU receives data at input from the memory cells and provides data at output, which is then stored on the memory cells. It should therefore be understood that, in addition to the number of ALUs, the number of memory cells is another criterion for determining the computing power of the device.

[0004] Data is routed between the ALU and the memory unit through the bus of the device in both directions. The term "bus" used herein generally refers to a system (or interface) for transferring data, including hardware (interface circuits) and protocols for managing exchanges. The bus itself transmits data, addresses, and control signals. Each bus itself also has hardware and software limitations that restrict the routing of data. Specifically, the bus has a limited number of ports on the memory unit side and a limited number of ports on the ALU side. Therefore, during a calculation cycle, a memory location can be accessed in a single direction (in "read" mode or in "write" mode) via the bus. In addition, during a calculation cycle, a memory location can only be accessed by a single ALU.

[0005] Between the bus and the ALU, the computing device usually includes a set of registers and a local memory unit, which can be regarded as a memory separate from the above-mentioned memory unit. For ease of understanding, the distinction between a "register" storing such data and a "local memory unit" storing a memory address is illustrated here. Each register is assigned to the ALU of a PU. A PU is assigned multiple registers. The storage capacity of a register is very limited compared to a memory unit, but its content can be directly accessed by the ALU.

[0006] In order to perform a calculation operation, each ALU must usually first obtain the input data of the calculation operation, usually the two operands of the basic calculation operation. Therefore, a "read" operation on the corresponding memory location via the bus is implemented to import each of the two operands into the register. The ALU then performs the calculation operation based on the data from the register and by exporting the result to the register in the form of a data item. Finally. A "write" operation is implemented to record the result of the calculation operation in the memory location. During this write operation, the result stored in the register is recorded in the memory location via the bus. It is inferred that each operation consumes one or more calculation cycles.

[0007] In known computing devices, attempts are usually made to execute multiple operations (or multiple instructions) during the same computing cycle in order to reduce the total number of computing cycles and thus increase efficiency. Reference is then made to parallel "processing chains" or "pipelines". However, there are often many interdependencies between operations. For example, as long as operands have not yet been read and they are not accessible on registers for the ALU, it is not possible to perform basic computing operations. Therefore, implementing a processing chain involves checking the interdependencies between operations (instructions), which is complex and therefore costly.

[0008] Multiple independent operations are usually performed during the same calculation cycle. Generally, for a given ALU and during the same calculation cycle, it is possible to perform a calculation operation and a read or write operation. In contrast, for a given ALU and during the same calculation cycle, it is not possible to perform a read operation and a write operation simultaneously (in the case of a single-port memory unit). On the other hand, memory access operations (buses) do not make it possible to perform a read or write operation for two ALUs separated from each other during the same calculation cycle and for a given memory location.

[0009] It is therefore known to perform the basic computing operations and write the obtained results to the memory during the same computing cycle. The economy in terms of computing cycles (or computing resources) is still poor.

[0010] The present invention aims to improve this situation. Summary of the invention

[0011] A data processing method is proposed, which can be decomposed into a set of basic operations to be performed by a computing device, the device comprising:

[0012] - control unit;

[0013] - at least one arithmetic logic unit;

[0014] a set of registers capable of supplying data forming operands to inputs of the first arithmetic logic unit and capable of receiving data from outputs of the arithmetic logic unit;

[0015] - memory;

[0016] -Memory interfaces, with the help of which data is transferred and routed between registers and memory.

[0017] The method comprises:

[0018] a) obtaining the memory address of each datum missing from the register and forming an operand for at least one basic operation to be performed, and;

[0019] b) reading each data from the memory via the memory interface with the aid of the obtained memory address so as to load the data into the register;

[0020] c) transmitting an instruction for executing a calculation operation from the control unit to the first arithmetic logic unit, the instruction not including any addressing instruction;

[0021] d) upon receiving an instruction to perform a calculation operation, and once the corresponding operands are available on the registers, performing all elementary operations by means of a first arithmetic logic unit receiving at input each operand from the registers;

[0022] e) storing data forming the result of the processing operation on a register at an output of the first arithmetic logic unit;

[0023] f) obtaining the memory address of each data used to form the result of the processing operation;

[0024] g) Writing each data forming a result of the processing operation from the register to the memory for storage by means of the obtained memory address via the memory interface.

[0025] This method makes it possible to avoid that the ALU performing the computational operations has to perform additional addressing operations that would otherwise require the computational operations to be stopped, by decoupling the tasks regarding the processing of memory addresses from the computational tasks over time. In doing so, the processing operation as a whole becomes asynchronous and self-adaptive: the underlying computational operation is started (by the instruction transmitted to the ALU) only when the memory address has been updated in the local memory unit. By decoupling the two types of operations (updating the memory address in the local memory unit on the one hand, and the computational operation on the other hand), it is possible to reduce the processing time. In other words, for a fixed number of resources, the sum of the time necessary to update the memory address in the local memory unit during a first process and then to perform the computational operation during a second process is less than the time necessary for the same number of resources to perform the entire processing operation during a single process (with on-the-fly memory address update access in the local memory unit). The time saving is particularly significant in the case of iterative processing operations that can usually be performed with the aid of computational loops.

[0026] According to another aspect, a computing device for processing data is provided, wherein the processing operation can be decomposed into a set of basic operations to be performed. The device comprises:

[0027] - control unit;

[0028] - at least one first arithmetic logic unit among a plurality of arithmetic logic units;

[0029] - a set of registers capable of supplying data forming operands to the inputs of the arithmetic logic unit and capable of receiving data from the outputs of the arithmetic logic unit;

[0030] - memory;

[0031] - a memory interface, by means of which data is transferred and routed between registers and memory. The computing device is configured to:

[0032] a) obtaining the memory address of each datum missing from the register and forming an operand for at least one basic operation to be performed, and;

[0033] b) reading each data from the memory via the memory interface with the aid of the obtained memory address so as to load the data into the register;

[0034] c) transmitting an instruction for executing a calculation operation from the control unit to the first arithmetic logic unit, the instruction not including any addressing instruction;

[0035] d) upon receiving an instruction to perform a computational operation, and once the operands are available in registers, performing all elementary operations by means of an arithmetic logic unit receiving each operand from the registers at input;

[0036] e) storing data forming the result of the processing operation on a register at an output of the first arithmetic logic unit;

[0037] f) obtaining the memory address of each data used to form the result of the processing operation;

[0038] g) via the memory interface, with the aid of the obtained memory address, write each data forming the result of the processing operation from the register to the memory for storage.

[0039] According to another aspect, a set of machine instructions is proposed for implementing the method as defined herein when the program is executed by a processor. According to another aspect, a computer program is proposed, in particular a compiled computer program, comprising instructions for implementing all or part of the method as defined herein when the program is executed by a processor. According to another aspect, a non-transitory computer readable recording medium is proposed, on which the program is recorded.

[0040] The following features can be implemented optionally. The features can be implemented independently of each other or in combination with each other:

[0041] - the first arithmetic logic unit performs all the basic calculation operations of the processing operation during the continuous calculation cycle, the first arithmetic logic unit does not perform any memory access operation during the calculation cycle. This makes it possible to avoid the first arithmetic logic unit from performing any memory access operation during the basic calculation operation and thus speed up the implementation of the calculation operation.

[0042] - At least one of the following steps includes an iterative loop:

[0043] a) obtaining the memory address of each datum missing from the register and forming an operand for at least one basic operation to be performed, and;

[0044] d) upon receiving an instruction to perform a calculation operation, performing all elementary operations by means of a first arithmetic logic unit receiving at input each operand from a register;

[0045] f) Obtaining the memory address of each data used to form the result of the processing operation.

[0046] This makes it possible to carry out particularly fast calculation processes, since they can be carried out repeatedly.

[0047] - The device further comprises at least one additional arithmetic logic unit separate from the first arithmetic logic unit that performs all basic operations. The additional arithmetic logic unit implements the following operations:

[0048] a) obtaining the memory address of each datum missing from the register and forming an operand for at least one basic operation to be performed; and

[0049] b) Reading each data from the memory via the memory interface with the aid of the obtained memory address so as to load the data into the register.

[0050] This makes it possible to allocate the functionality in a fixed manner for each ALU and thus improve its respective efficiency.

[0051] At the same time, the applicant also describes a method in which, after each read operation, the number of data read is greater than the number of precise data necessary to implement the next computing operation. Relatively speaking, this method can be called "temporary memory access". Thus, it is possible that one data item from the read data is used for a future computing operation, except for the computing operation implemented immediately after the read operation. In these cases, the necessary data is already obtained during a single memory access operation (wherein the bandwidth of the memory is increased), while the common method would have always required at least two separate memory access operations. Therefore, at least in some cases, the effect of this method is to reduce the consumption of computing cycles for memory access operations, and thus make it possible to improve the efficiency of the device. Over a long period of time (multiple consecutive computing cycles), the number of memory access operations (in read mode and / or in write mode) is reduced.

[0052] This method does not exclude losses: some data read and stored on a register may be lost (erased by other data subsequently stored on the same register) even before being used in a computing operation. However, over a large number of computing operations and computing cycles, the Applicant has observed an improvement in performance, including in the case where the data sets read are not selected. In other words, this method makes it possible to statistically improve the efficiency of the computing device compared to conventional methods, even in the case where the data read are not selected (or are selected randomly). BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Other features, details and advantages of the present invention will become apparent upon reading the following detailed description and analyzing the accompanying drawings, in which:

[0054] - Figure 1 The architecture of a computing device according to the present invention is presented;

[0055] - Figure 2 is a partial depiction of the architecture of a computing device according to the present invention;

[0056] - Figure 3 An example of a memory access operation is shown;

[0057] - Figure 4 Is from Figure 3 A variation of an instance of ;

[0058] - Figure 5 schematically illustrates an operational architecture according to the present invention; and

[0059] - Figure 6 A time-decomposed process diagram of an operation example according to the present invention is shown. DETAILED DESCRIPTION

[0060] Figure 1 An example of a computing device 1 is shown. The device 1 includes a set of one or more processors 3, sometimes referred to as central processing units or CPUs. The set of processors 3 includes at least one control unit 5 and at least one processing unit 7 or PU 7. Each PU 7 includes one or more computational units, referred to as arithmetic logic units 9 or ALU 9. In the example described herein, each PU 7 further includes a set of registers 11. The device 1 includes at least one memory 13 capable of interacting with the set of processors 3. To this end, the device 1 further includes a memory interface 15 or "bus".

[0061] In this context, the memory cells are considered to be single-port, that is, the read and write operations are performed during different cycles compared to memories known as "dual-port" memories (which are more expensive in terms of surface and require a larger dual control bus for reading and writing). As a variant, the proposed technical solution can be implemented using memories known as "dual-port" memories. In these embodiments, the read and write operations can be performed during the same computing cycle.

[0062] Figure 1 Three PUs 7 are shown: PU 1, PU X, and PU N. Only the structure of PU X is shown in detail for simplicity Figure 1 However, the structures of the PUs are similar to each other. In some variants, the number of PUs is different. The device 1 may include a single PU, two PUs or more than three PUs.

[0063] In the examples described herein, PU X includes four ALUs: ALU X.0, ALU X.1, ALU X.2, and ALU X.3. In some variants, a PU may include several ALUs different from each other and / or other than four, including a single ALU.

[0064] A set of registers 11 is included, here at least one register 11 allocated to each ALU. In the example described herein, PU X includes a single register 11 per ALU, that is, four registers, referenced as REG X.0, REG X.1, REG X.2 and REG X.3, and allocated to ALU X.0, ALU X.1, ALU X.2 and ALU X.3, respectively. In some variants, each ALU is allocated a plurality of registers 11.

[0065] Each register 11 is capable of providing operand data to the input of the ALU 9 and is capable of receiving data from the output of the ALU 9. In addition, each register 11 is capable of storing data obtained from the memory 13 via an operation called a "read" operation via the bus 15. In addition, each register 11 is capable of transferring stored data to the memory 13 via an operation called a "write" via the bus 15. The read and write operations are managed by controlling the memory access operations from the control unit 5.

[0066] The control unit 5 imposes the way in which each ALU 9 performs the basic computing operations, and more precisely their order, and assigns to each ALU 9 the operations to be performed. In the example described herein, the control unit 5 is configured to control the ALUs 9 according to the processing chain microarchitecture so that the ALUs 9 perform computing operations in parallel with each other. By way of example, the device 1 has a single instruction stream and multiple data stream architecture, called SIMD, standing for “Single Instruction Multiple Data”; and / or a multiple instruction stream and multiple data stream architecture, called MIMD, standing for “Multiple Instruction Multiple Data”. On the other hand, the control unit 5 is further designed to control memory access operations, and more precisely in this case read and write operations, by means of the memory interface 15. The two types of control (computation and memory access) are determined by Figure 1 The dashed arrow in the figure shows.

[0067] Reference now Figure 2 , where a single ALU Y is shown. Data transfer is shown by solid arrows. Because data is transferred step by step, it should be understood that Figure 2 The time t with simultaneous data transfer is not necessarily shown. In contrast, in order to transfer a data item from register 11 to ALU 9, for example, the data item must previously be transferred from memory 13 to register 11 via memory interface 15 (or bus) in this case.

[0068] exist Figure 2In the example of , three registers 11 respectively referenced as REG Y.0, REG Y.1 and REG Y.2 are assigned to the ALU referenced as ALU Y. Each ALU 9 has at least three ports, specifically two inputs and one output. For each operation, at least two operands are received by the first and second inputs, respectively. The result of the computation operation is transmitted via the output. Figure 2 In the example shown, the operands received at the input originate from register REG Y.0 and from register REG Y.2, respectively. The result of the computation operation is written to register REG Y.1. Once it has been written to register REG Y.1, the result (in the form of a data item) is written to memory 13 via memory interface 15. In some variants, at least one ALU may have more than two inputs and receive more than two operands for computation operations.

[0069] Each ALU 9 can execute:

[0070] - Integer arithmetic operations on data (addition, subtraction, multiplication, division, etc.);

[0071] - floating point arithmetic operations on data (addition, subtraction, multiplication, division, inversion, square root, logarithm, trigonometric functions, etc.);

[0072] -Logical operations (two's complement, AND, OR, XOR, etc.).

[0073] The ALUs 9 do not directly exchange data with each other. For example, if the result of a first computational operation performed by a first ALU constitutes an operand for a second computational operation to be performed by a second ALU, the result of the first computational operation should be written to at least register 11 before it can be used by the ALUs 9.

[0074] In some embodiments, data written to register 11 is further automatically written to memory 13 (via memory interface 15), even if the data item as a whole is obtained only to serve as an operand and not as a result of a processing procedure.

[0075] In some embodiments, data obtained to serve as operands and having a transient relevance (intermediate results that are meaningless as a whole at the end of a processing operation) are not automatically written to the memory 13 and may only be temporarily stored on the register 11. For example, if the result of a first computing operation performed by a first ALU constitutes an operand for a second computing operation to be performed by a second ALU, the result of the first computing operation should be written to the register 11. Next, the data item is transferred directly from the register 11 to the second ALU as an operand. It should thus be understood that the allocation of the register 11 to the ALU 9 may evolve over time, and more precisely, from one computing cycle to another. This allocation may more precisely be in the form of addressing data, which makes it possible to always locate the location of the data item, either on the register 11 or at a location in the memory 15.

[0076] In the following, the operation of the device 1 is described with respect to processing operations applied to computational data, the processing operations being decomposed into a set of operations, comprising computational operations performed in parallel by a plurality of ALUs 9 during a time period consisting of a sequence of computational cycles. It is thus considered that the ALUs 9 operate according to a processing chain microarchitecture. However, the processing operations performed by the device 1 and referred to herein may themselves constitute parts (or subsets) of a more global computational process. This more global process may include (among other parts or subsets) computational operations performed non-parallel by a plurality of ALUs, for example in a serial operating mode or in a cascaded manner.

[0077] The operating architecture (parallel or serial) may be constant or dynamic, for example imposed (controlled) by the control unit 5. For example, the architecture changes may depend on the data to be processed, and on the current instructions received at the input of the device 1. This dynamic adaptation of the architecture may be implemented early at the compilation stage by adapting the machine instructions generated by the compiler based on the type of data to be processed and the instructions when they can be inferred from the source code. This adaptation may also be implemented only at the device 1 or a processor executing conventional machine code, and which is programmed to implement a configuration instruction set depending on the data to be processed and the instructions currently received.

[0078] The memory interface 15 or "bus" transmits and routes data in both directions between the ALU 9 and the memory 15. The memory interface 15 is controlled by the control unit 5. The control unit 5 thus controls access to the memory 13 of the device 1 by means of the memory interface 15.

[0079] The control unit 5 controls the (computation) operations and memory access operations performed by the ALU 9 in a coordinated manner. The control performed by the control unit 5 includes performing a sequence of operations decomposed into computation cycles. The control includes generating a first cycle i and a second cycle ii. The first cycle i precedes the second cycle ii in time. As will be described in more detail in the following examples, the second cycle ii may be immediately after the first cycle i, or the first cycle i and the second cycle ii may be spaced apart from each other in time, for example with an intermediate cycle.

[0080] The first cycle i includes:

[0081] - performing a first computing operation by means of at least one ALU 9; and

[0082] - Downloading the first data set from the memory 13 to the at least one register 11 .

[0083] The second cycle ii comprises performing a second computational operation by means of at least one ALU 9. The second computational operation may be performed by the same ALU 9 as the first computational operation or by a separate ALU 9. At least a portion of the first data set downloaded during the first cycle i forms an operand for the second computational operation.

[0084] Reference now Figure 3 Some data or data blocks are referenced as A0 to A15 and stored in the memory 13. In the example, it is considered that the data A0 to A15 are grouped together in four forms, as follows:

[0085] - The reference data set is AA0_3, which consists of data A0, A1, A2 and A3;

[0086] - The data set referenced as AA4_7 consists of data A4, A5, A6 and A7;

[0087] - The data set referenced as AA8_11, consisting of data A8, A9, A10 and A11; and

[0088] -The data set with reference AA12_15 consists of data A12, A13, A14 and A15.

[0089] As a variant, the data may be grouped together in a different way, specifically in groups (or "blocks" or "slots") of two, three or more than four. A data set may be considered as a set of data accessible on the memory 13 during a single read operation by means of a single port of the memory interface 15. Likewise, the data of a data set may be written to the memory 13 during a single write operation by means of a single port of the memory interface 15.

[0090] Thus, during a first cycle i, at least one data set AA0_3, AA4_7, AA8_11 and / or AA12_15 is downloaded to at least one register 11. In the example in the figure, each of the data sets AA0_3, AA4_7, AA8_11 and / or AA12_15 is downloaded to a respective register 11, that is, four registers 11 separated from one another. Each of the registers 11 is at least temporarily assigned to a respective ALU 9, here respectively referenced as ALU 0, ALU 1, ALU 2 and ALU 3. During this same cycle i, the ALU 9 may have performed a computation operation.

[0091] During the second cycle ii, each ALU 9 performs a calculation operation for which at least one of the data items stored on the corresponding register 11 forms an operand. For example, ALU 0 performs a calculation operation for which one of its operands is A0. A1, A2 and A3 may not be used during the second cycle ii.

[0092] Generally speaking, downloading data from the memory 13 to the register 11 consumes less computing time than performing a computing operation with the aid of the ALU 9. Therefore, it can generally be considered that a memory access operation (here a read operation) consumes a single computing cycle, whereas performing a computing operation with the aid of the ALU 9 consumes one computing cycle or a series of multiple computing cycles, for example four.

[0093] exist Figure 3 In the example of FIG. 1 , there are a plurality of registers 11 assigned to each ALU 9, illustrated by the groups of registers 11 referenced as REG A, REG B and REG C. The data downloaded from the memory 13 to the registers 11 corresponds to the groups REG A and REG B. The group REG C is here intended to store data obtained via calculation operations performed by the ALU 9 (during write operations).

[0094] Registers 11 of groups REG B and REG C may thus contain a data set similar to that referenced by the registers of REG A:

[0095] - Group REG B includes four registers 11, on which a data set BB0_3 consisting of data B0 to B3, a data set BB4_7 consisting of data B4 to B7, a data set BB8_11 consisting of data B8 to B11, and a data set BB12_15 consisting of data B12 to B15 are respectively stored;

[0096] - Group REG C includes four registers 11, on which a data set CC0_3 consisting of data C0 to C3, a data set CC4_7 consisting of data C4 to C7, a data set CC8_11 consisting of data C8 to C11, and a data set CC12_15 consisting of data C12 to C15 are respectively stored.

[0097] exist Figure 3 In the example of , the data AN and BN constitute the operands for the calculation operation implemented by the ALU 9, and the data item CN constitutes the result, where "N" is an integer between 0 and 15. For example, in the case of addition, CN=AN+BN. In this example, the data processing operations implemented by the device 1 correspond to 16 operations. The 16 operations are independent of each other in the sense that the results of any of the 16 operations are not required to implement one of the other 15 operations.

[0098] Therefore, the implementation of the processing operations (16 operations) can be decomposed into 18 cycles, for example, as follows.

[0099] Example 1:

[0100] - Loop #0: Read AA0_3;

[0101] - Loop #1: Read BB0_3;

[0102] - Loop #2: compute C0 (from set CC0_3) and read AA4_7 (forming e.g. loop i);

[0103] - Loop #3: compute C1 (from set CC0_3) and read BB4_7 (forming e.g. loop i);

[0104] - Loop #4: Calculate C2 (from set CC0_3);

[0105] - Loop #5: Calculate C3 (from set CC0_3) and write CC0_3;

[0106] - Loop #6: compute C4 (from set CC4_7) and read AA8_11 (forming e.g. loop ii);

[0107] - Loop #7: compute C5 (from set CC4_7) and read BB8_11 (forming e.g. loop ii);

[0108] - Loop #8: Compute C6 (from set CC4_7) (forming e.g. loop ii);

[0109] - Loop #9: compute C7 (from set CC4_7) and write CC4_7 (forming e.g. loop ii);

[0110] - Loop #10: Calculate C8 (from set CC8_11) and read AA12_15;

[0111] - Loop #11: Calculate C9 (from set CC8_11) and read BB12_15;

[0112] - Loop #12: Calculate C10 (from set CC8_11);

[0113] - Loop #13: Calculate C11 (from set CC8_11) and write CC8_11;

[0114] - Loop #14: Calculate C12 (from set CC12_15);

[0115] - Loop #15: Calculate C13 (from set CC12_15);

[0116] - Loop #16: Calculate C14 (from set CC12_15);

[0117] - Loop #17: Calculate C15 (from set CC12_15) and write CC12_15.

[0118] It should thus be understood that, except for the initial cycles #0 and #1, memory access operations (read and write operations) are performed in parallel with computational operations without consuming additional computational cycles. Reading a data set containing (multiple) data or blocks of data rather than reading a single data item makes it possible to complete importing data from the memory 13 into registers even before the data becomes an operand necessary for a computational operation.

[0119] In the example of loop #2 above, if only the immediately required data item (A0) would have been read instead of reading the set AA0_3 = {A0; A1; A2; A3}, three additional read operations would have had to be performed subsequently to obtain A1, A2 and A3.

[0120] For better understanding, and for comparison, an implementation of a processing operation in which a single data item is read each time, rather than a data set containing (a plurality of) data, is reproduced below. Observe that 48 cycles are necessary.

[0121] Example 0:

[0122] - Loop #0: Read A0;

[0123] -Loop #1: Read B0;

[0124] - Loop #2: Calculate C0 and write C0;

[0125] -Loop #3: Read A1;

[0126] -Loop #4: Read B1;

[0127] - Loop #5: Calculate C1 and write it to C1;

[0128] -…

[0129] -Loop #45: Read A15;

[0130] - Loop #46: Read B15;

[0131] - Loop #47: Calculate C15 and write C15.

[0132] In Example 1 (18 cycles), it should be noted that the first two cycles #0 and #1 constitute initialization cycles. The number of initialization cycles I corresponds to the number of operands per computation operation. Next, the pattern of four consecutive cycles is repeated four times. For example, cycles #2 to #5 together form a certain pattern. The number of cycles per pattern corresponds to the number of data per data set D, and the number of patterns corresponds to the number of data sets to be processed E. Therefore, the total number of cycles can be expressed as follows: I+D*E.

[0133] Achieving good performance is equivalent to reducing the total number of loops to a minimum. Under the conditions under consideration (that is, 16 basic independent operations that can each be implemented via one loop), the optimal number of loops therefore seems to be equal to the number of basic operations (16) plus the initialization phase (2 loops), that is, a total of 18 loops.

[0134] In one variant, the number of data that can be accessed (in read mode or in write mode) in a single cycle (the number of data per data set D) is considered to be equal to three (instead of four), for example due to hardware limitations. The sequence of cycles can then be decomposed, for example, as follows:

[0135] - 2 cycles of initialization phase; and then

[0136] - 5 patterns for 3 cycles of a total of 15 basic computing operations out of 16 to be performed; and then

[0137] - Final loop for computing and recording the result of the last basic computation operation.

[0138] Example 2:

[0139] - Loop #0: Read AA0_2 = {A0; A1; A2};

[0140] - Loop #1: Read BB0_2 = {B0; B1; B2};

[0141] - Loop #2: Compute C0 (from set CC0_2 = {C0; C1; C2}) and read AA3_5 (forming e.g. loop i)

[0142] - Loop #3: compute C1 (from set CC0_2) and read BB3_5 (forming e.g. loop i);

[0143] - Loop #4: Calculate C2 (from set CC0_2) and write to CC0_2;

[0144] - Loop #5: compute C3 (from set CC3_5) and read AA6_8 (forming e.g. loop ii);

[0145] - Loop #6: compute C4 (from set CC3_5) and read BB6_8 (forming e.g. loop ii);

[0146] - Loop #7: compute C5 (from set CC3_5) and write CC3_5 (forming e.g. loop ii);

[0147] - Loop #8: compute C6 (from set CC6_8) and read AA9_11;

[0148] - Loop #9: compute C7 (from set CC6_8) and read BB9_11;

[0149] - Loop #10: Calculate C8 (from set CC6_8) and write CC6_8;

[0150] - Loop #11: compute C9 (from set CC9_11) and read AA12_14;

[0151] - Loop #12: Calculate C10 (from set CC9_11) and read BB12_14;

[0152] - Loop #13: Calculate C11 (from set CC9_11) and write CC9_11;

[0153] - Loop #14: compute C12 (from set CC12_14) and read A15 (forming e.g. loop i);

[0154] - Loop #15: compute C13 (from set CC12_14) and read B15 (forming e.g. loop i);

[0155] - Loop #16: Calculate C14 (from set CC12_14) and write CC12_14;

[0156] - Loop #17: Compute C15 (isolated data item) and write C15 (forming e.g. loop ii).

[0157] In Example 2, it is observed that each cycle includes a memory access operation (either in read mode or in write mode). Therefore, it should be understood that if the number D of data accessible in a single cycle is strictly less than three, additional cycles will be necessary to perform the memory access operation. Therefore, the optimal 18 cycles for 16 basic operations will no longer be achieved. However, even if the optimal is not achieved, the number of cycles remains significantly lower than the number of cycles required in Example 0. The embodiment in which the data set includes two data items shows an improvement over the currently existing embodiments.

[0158] In Example 1, if loop #2 and / or #3 corresponds to, for example, loop i as defined above, then each of loops #6, #7, #8, and #9 corresponds to loop ii. Of course, this can be transposed between versions. In Example 2, if loop #2 and / or #3 corresponds to, for example, loop i as defined above, then each of loops #5, #6, and #7 corresponds to loop ii. Of course, this can be transposed between versions.

[0159] In the examples described so far (in particular, examples 1 and 2), a low total number of cycles is achieved in particular, because the maximum number of memory access operations is performed per data set containing (a plurality of) data, rather than at the unit and in parallel with the calculation operations. Thus, for some parts of the process (for all parts in the optimized examples), the read operations of all necessary operands can be achieved even before the previous basic calculation operation has ended. Computational power is preferably saved in order to perform calculation operations and record (write operation) the results of the calculation operations in a common calculation cycle (e.g., in example 1, cycle #5).

[0160] In the example, an advanced read of operand data is implemented throughout the process (repeated from one pattern to another). The operands necessary for the computational operations performed during a certain pattern are automatically obtained (read) during the temporally previous pattern. It should be noted that in the degraded embodiment, the advanced read is implemented only partially (only for two consecutive patterns). This mode of degrading compared to the above example shows better results than the existing methods.

[0161] In the examples described so far, it has been recognized that data is read before serving as an operand. In some embodiments, the data read in advance are read randomly, or at least read independently of future computing operations to be performed. Therefore, at least some of the data read in advance among the data set effectively correspond to operands for subsequent computing operations, while other read data are not operands for subsequent computing operations. For example, at least some of the read data can be subsequently erased from register 11 when not used by ALU 9, usually erased by other data subsequently recorded on register 11. Therefore, some data are read unnecessarily (and they are unnecessarily recorded on register 11). However, at least some of the data from the read data set are effectively operands in order to realize the saving of computing cycles, and therefore the situation is improved compared to the current existing situation. Therefore, depending on the number of data to be processed and the number of cycles, it is likely that (in the mathematical sense of the term) at least some of the pre-fetched data will be effectively able to be used as operands in the computing operations performed by ALU 9 in subsequent cycles.

[0162] In some embodiments, the data read in advance is preselected depending on the computational operation to be performed. This makes it possible to improve the relevance of the pre-fetched data. Specifically, in the above example with 16 basic computational operations, each of the 16 basic computational operations requires a pair of operands at the input, namely A0 and B0; A1 and B1; ...; A15 and B15. If the data is read randomly, the two first cycles may correspond to read operations on AA0_3 and BB4_7. In this case, there is no valid complete operand pair on register 11 at the end of the first two cycles. Therefore, ALU 9 cannot implement any basic computational operation in subsequent cycles. Therefore, before the basic computational operation can begin, one or more additional cycles will be consumed for memory access operations, thereby increasing the total number of cycles and adversely affecting efficiency.

[0163] Counting the chances and probabilities that the data obtained in the reading pattern are as relevant as possible is sufficient to improve the currently existing situation, but it is not completely satisfactory. The situation can be further improved.

[0164] Implementing a prefetch algorithm makes it possible to obtain as early as possible all the operands of the next calculation operation to be performed. In the above example, reading AA0_3 and BB0_3 during the first two cycles makes it possible to make available on register 11, for example, all the operands necessary to implement the 4 first basic calculation operations.

[0165] This algorithm receives as input parameters information data about the calculation operation to be subsequently performed by the ALU 9 and more precisely about the necessary operands. This algorithm makes it possible to anticipate the future calculation operation to be performed and to select the data read (per set) at the output. This algorithm is implemented, for example, by the control unit 5 when controlling memory access operations.

[0166] According to the first method, once the data is recorded in the memory 13, an algorithm imposes the organization of the data. For example, the data needed to form a data set is concatenated and / or ordered so that the entire data set can be called by a single request. For example, if the addresses of data A0, A1, A2, and A3 are referenced as @A0, @A1, @A2, and @A3, respectively, the memory interface 15 can be configured in response to a read request on @A0 so as to also automatically read the data at the following three addresses @A1, @A2, and @A3.

[0167] According to a second method, the prefetch algorithm provides at output a memory access request adapted on the basis of the calculation operation to be subsequently performed by the ALU 9 and specifically related to the necessary operands. In the above example, the algorithm recognizes, for example, that the data to be read first are those of AA0_3 and BB0_3, so as to enable earlier in the subsequent cycle the basic calculation operation, giving the result CC0_3, that is, to calculate C0 with operands A0 and B0, to calculate C1 with operands A1 and B1, to calculate C2 with operands A2 and B2, and to calculate C3 with operands A3 and B3. Therefore, the algorithm provides at output a memory access request constructed so as to generate a read operation on AA0_3 and BB0_3.

[0168] Both approaches can optionally be combined with each other: the algorithm identifies the data to be read and the control unit 5 infers therefrom a memory access request at the memory interface 15 in order to obtain the data, the request being adapted based on the characteristics (structure and protocol) of the memory interface 15 .

[0169] In the above examples (specifically, Examples 1 and 2 above), the number of ALUs assigned to the basic computing operations is not limited. A single ALU 9 can perform all basic computing operations cycle by cycle. The basic computing operations to be performed can also be distributed over multiple ALUs 9 of the PU, for example four. In these cases, coordinating the distribution of computing operations over the ALUs using a technique that groups together the data to be read in each read operation can make it possible to further improve efficiency. A distinction is made between the two approaches.

[0170] In a first method, the data read in the operation form operands in a calculation operation performed by only the same ALU 9. For example, the groups AA0_3 and BB0_3 of data A0, A1, A2, A3, B0, B1, B2 and B3 are first read, and the first ALU is made responsible for calculating CC0_3 (C0, C1, C2 and C3). Then the groups AA4_7 (A4, A5, A6, A7) and BB4_7 (B4, B5, B6 and B7) are read, and the second ALU is made responsible for calculating CC4_7 (C4, C5, C6 and C7). It should thus be understood that the first ALU will be able to start performing a calculation operation before the second ALU is able to perform a calculation operation, because the operands necessary for the calculation operation of the first ALU will be valid on the register 11 before the operands necessary for the calculation operation of the second ALU. The ALUs 9 of the PUs then operate in parallel and asynchronously.

[0171] In the second method, the data read in the operation forms the operands in the calculation operation each implemented by a different ALU 9 (for example, four). For example, first read two groups of data including A0, A4, A8 and A12; B0, B4, B8 and B12 respectively. Make the first ALU responsible for calculating C0, the second ALU responsible for calculating C4, the third ALU responsible for calculating C8, and the fourth ALU responsible for calculating C12. It should be understood that the four ALUs will be able to start implementing their respective calculation operations at substantially the same time, because the necessary operands will be available on registers 11 at the same time as they are downloaded in the common operation. The ALUs 9 of the PU operate in parallel and synchronously. Depending on the type of calculation operation to be performed, the accessibility of data in memory and the available resources, one or the other of the two methods may be preferred. The two methods can also be combined: the ALUs can be organized into subgroups, the ALUs of the subgroups operate synchronously, and the subgroups operate asynchronously relative to each other.

[0172] In order to impose synchronous, asynchronous or mixed operation of the ALUs, the grouping of the data to be read together per read operation should be chosen to correspond to the distribution of the computation operations to the various ALUs.

[0173] In the above example, the basic computing operations are independent of each other. Therefore, it is inferred that the order in which they are executed does not have any importance. In some applications where at least some of the computing operations are dependent on each other, the order of computing operations may be specific. This situation usually occurs in the context of recursive computing operations. In these cases, the algorithm can be configured to identify the data to be acquired (read) as a priority. For example, if:

[0174] - a result C1 is obtained via a calculation operation whose one operand is C0, which itself is obtained from operands A0 and B0,

[0175] - obtains the result C5 via a calculation operation whose one operand is C4, which itself is obtained from operands A4 and B4,

[0176] - a result C9 is obtained via a calculation operation whose one operand is C8, which itself is obtained from operands A8 and B8, and

[0177] - a result C13 is obtained via a calculation operation whose one operand is C12, which itself is obtained from operands A12 and B12,

[0178] The algorithm can then be configured to read the following defined data sets during the first two initialization cycles #0 and #1:

[0179] -{A0;A4;A8;A12}, and

[0180] -{B0;B4;B8;B12}.

[0181] The data set thus restricted is Figure 4 In the figure, it can be shown that the data is Figure 3 In the embodiment shown in Figure 4 Implementation of the algorithm in this way makes it possible to read operands valid for priority-based computation operations and make them available on register 11. In other words, implementation of the algorithm makes it possible to increase the short-term relevance of the data read compared to random read operations.

[0182] The examples of processing units and methods described above should not be considered limiting, and other variations may be contemplated by a person skilled in the art within the scope of the protection sought, by way of example only. The examples may also take the following forms:

[0183] - a set of machine instructions executable by a processor of the computing device,

[0184] - a processor or a collection of processors,

[0185] - the implementation of this set of machine instructions on a processor,

[0186] - a processor architecture management method implemented by a processor,

[0187] - a computer program comprising a corresponding set of machine instructions, and

[0188] - A recording medium on which the set of machine instructions is recorded in a computational manner.

[0189] Reference now Figure 5. This figure shows an example of an operational architecture of the device 1, in which memory access and addressing processing operations are handled separately from the basic computing operations. This architecture may take the form of a computing method. It may optionally be combined with the above-described embodiments. Numerical references common to those in the previous figures indicate similar elements, specifically the control unit 5, ALU 9, registers 11, memory 13 and memory interface 15 or "bus".

[0190] For ease of understanding, the same naming convention is used: Consider a basic operation, such as addition, where AX and BX are data forming operands in order to obtain data items to form a result CX, where X is an integer between 0 and N, and N+1 is the number of basic operations to be performed during the processing operation. The set of N+1 operations forms the data processing operation as a whole. In addition, the memory address of each data is referenced by prefixing its name with the character "@" ("at" symbol). For example, the address of data item A0 is represented as "@A0".

[0191] For each addition (each value of X), an instruction set may be implemented by the computing device 1. An example of this instruction set is provided at the end of the description in the form of computer pseudo code. Typically, these instructions are applied consecutively during a common process implemented by the ALU 9. In the embodiments below, instructions for memory access operations and instructions for basic computational operations are handled by separate processes from each other.

[0192] In accordance with Figure 5 In one embodiment of a calculation method, the method can be decomposed into steps referenced as 101 to 109 respectively.

[0193] In steps 101 and 102, the memory address @A0 to @AN and @B0 to @BN of each data forming an operand for at least one basic operation to be performed is obtained, respectively. "Obtain" is understood to mean that, at the end of operations 101 and 102, one or more local memory units store the addresses of all the data forming the operands. These memory access operations are triggered, for example, by receiving instructions from the control unit 5. In some cases, at least some of the addresses are already stored in the local memory units. Therefore, no memory access operation is required at this stage to obtain the addresses previously installed on the local memory units.

[0194] In the example described herein, a distinction is made between step 101 concerning a first operand "A" of the addition and step 102 concerning a second operand "B" of the addition. The distinction between the two operands thus makes it possible to implement iterative loops specific to each of the two operands and possibly different from each other (in the sense of calculation).

[0195] As a variant, steps 101 and 102 can be carried out independently of one another and at least partially in parallel to one another, specifically when both operands are already present at the start of the method.

[0196] In steps 103 and 104, each data (A0 to AN and B0 to BN, respectively) is read from the memory 13 via the memory interface 15 so as to be loaded into the register 11. These read operations are possible with the help of the addresses obtained in steps 101 and 102. In the example described herein, step 103 involves a first operand "A", while step 104 involves a second operand "B".

[0197] In step 105, an instruction to perform a calculation operation is transmitted from the control unit 5 to the ALU 9. The execution instruction is constructed so as to trigger a basic calculation operation for the implementation of a processing operation by the ALU 9. In this case, the instruction does not contain any addressing instruction. The absence of any addressing instruction is understood here to mean that, compared to what usually happens, the instruction to perform a calculation operation transmitted by the control unit 5 is not included in a general instruction set combining both addressing instructions and instructions to perform a calculation operation. Therefore, after receiving the instruction, the ALU 9 is able to apply the instruction immediately by performing the basic calculation operation, without having to apply any instructions in advance to configure the memory interface 15, and therefore without having to check any mutual dependencies between the various received instructions. Figuratively, the ALU 9 then behaves as a calculation resource that implements a calculation operation (step 106 described below) independently of any complexity in terms of dependencies between the various instructions. By making the transmission of the calculation instruction (step 105) conditional on the previous execution of the addressing operation (steps 103 and 104), the validity of the data forming the operand on the register 11 is guaranteed. In practice, register 11 behaves as a first-in-first-out (or FIFO) buffer memory. Register 11 is filled and emptied according to the order of arrival of the data, here operands AN (step 103) and BN (step 104). If register 11 is not empty, step 106 is executed: register 11 is destacked from operands AN and BN. As a variant, register 11 is not operated in FIFO mode. In this case, data can be stored therein more permanently without the risk of being erased and can be reused later when necessary.

[0198] In step 106, after receiving an instruction to perform a computational operation, the ALU 9 performs all corresponding elementary operations once the operands are available on the registers 11. Thus, step 106 comprises receiving each operand from the registers 11 at the input of the ALU 9. Under the condition that the addressing operations 103, 104 have been correctly performed beforehand, step 106 may not involve any memory access operations (in read mode).

[0199] In step 107, the data forming the result of the processing operation are stored on register 11 at the output of ALU 9. Only the results of the processing operation are mentioned here, and they are not the results of each basic calculation operation. Specifically, if some results of the basic calculation operation are used as operands for other basic calculation operations in step 107, these (intermediate) results may become unnecessary at the end of the processing operation. In these cases, the intermediate results can be erased from register 11 at the end of step 107 (for example, by other data erasure, FIFO mode). As a variant, all data forming the results of the basic operation are stored on register 11 at the end of step 107 (mode other than FIFO).

[0200] In step 108, a memory address @CX is obtained for each of the data CX forming the result of the processing operation. This addressing operation makes it possible to determine the memory location at which each of the data forming the result will be stored. In the example described herein, step 108 is implemented after step 107 of writing the result to register 11 and before writing the result to memory 13 (step 109 described below). As a variant, step 107 may be implemented earlier during the method, specifically before step 106. Specifically, in particular when the form (specifically, the size) of the result data is known in advance, it is possible to address the result data even before calculating the result data. Obtaining the memory address @CX may include transmitting an addressing instruction from the control unit 5.

[0201] In step 109 , each data forming the result of the processing operation is written from the register 11 to the memory 13 via the memory interface 15 by means of the memory address obtained in step 108 for storage.

[0202] Figure 6 Some exemplary implementations of steps 101, 102, 106 and 108 are given in the form of computer pseudocode. These non-limiting examples represent the operations in the form of computation loops. The use of loops is particularly advantageous for limiting the number of necessary computation cycles and thus improving efficiency when the operations to be performed are substantially similar to each other (e.g., all are additions) and only the input data vary. In these cases, the computation instructions transmitted in step 105 may take the form of a loop that is repeated for each operation.

[0203] The time sequence of steps 101, 102, 106 and 108 is given by Figure 6 The arrow "t" in FIG. 1 is indicated. This sequence constitutes a non-limiting example. Figure 6It is shown that, compared with the use in the technical field, the addressing of the input data (operands) is implemented separately from the calculation operation itself. In other words, the addressing and the calculation operation are handled as two processes separated from each other, rather than being handled indiscriminately when receiving a general instruction in operation. Specifically, the step 106 of performing the basic operation can be started even when all operands have not yet been downloaded from the memory 13 to the register 11. Generally, the first cycle of step 106 can be started as soon as the corresponding first operand is valid for the calculation operation on the register 11. This cascaded implementation of the operation gives the system its asynchronous nature.

[0204] In some embodiments, ALU 9 performs (step 106) all basic computational operations of processing operations during continuous computational cycles. ALU 9 does not perform any memory access operations during these computational cycles. Therefore, the implementation of computational operations can be particularly fast. ALU 9 is exempted from any memory access operations during these cycles. In addition, from the perspective of ALU 9 performing computational operations, the way to obtain operands is similar to the call to memory 13, but operands are obtained more quickly and independently of memory interface 15, because operands are read directly from register 11 in practice. Memory access operations are implemented by another ALU (different from the ALU that performs computational operations). At least during a certain process, each ALU 9 has a fixed function: implement computational operations, or implement memory access operations. This allocation of fixed functions to each ALU 9 can be modified at the end of the implementation of the process in order to give the computing device flexibility. However, this often involves adapting the addressing path accordingly. In a preferred embodiment, therefore, the function of each ALU 9 is fixed between processes: the ALU is dedicated.

[0205] The methods and variations described above may take the form of a computing device comprising a processor or a collection of processors designed to implement the methods.

[0206] The invention is not limited to the examples of methods and devices described above by way of example only, but incorporates all variants that a person skilled in the art would be able to anticipate within the scope of the protection sought. The invention also relates to a set of processor-implementable machine instructions for obtaining such a computing device (e.g., a processor or a set of processors), to the implementation of this set of machine instructions on a processor, to a processor architecture management method implemented by a processor, to a computer program comprising a set of corresponding machine instructions, and to a recording medium on which this set of machine instructions is recorded in a computational manner.

[0207] The following pages of the original document description give some exemplary embodiments in the form of computer pseudo code. An example of a processing operation to be performed in the form of ten additions in the form of computer pseudo code:

[0208] Int A

[10] ,B

[10] ,C

[10]

[0209] for(i=0;i<10;i++)

[0210] {

[0211] C[i]=A[i]+B[i];

[0212] }

[0213] An example of a general instruction in the form of computer pseudocode for performing a processing operation consisting of ten additions:

[0214] @A,@B,@C

[0215] Addr0=@A

[0216] Addr1=@B

[0217] Addr2=@C

[0218] LOOP:

[0219] Load Addr0→reg0

[0220] Load Addr1→reg1

[0221] reg2=reg0+reg1

[0222] Store addr2→reg2

[0223] Addr0=Addr0+1

[0224] Addr1=Addr1+1

[0225] Addr2=Addr2+1

[0226] GOTO LOOP (10x)

[0227] According to one embodiment in which the addressing instructions and the calculation instructions are distinct from one another, an example of instructions in the form of computer pseudo code for performing a processing operation consisting of ten additions:

[0228] / / Step 101 / /

[0229] Addr = @A

[0230] LOOP

[0231] Load Addr

[0232] Addr=addr+1

[0233] GOTO LOOP(10x)

[0234] / / Step 102 / /

[0235] Addr = @B

[0236] LOOP

[0237] Load Addr

[0238] Addr = addr + 1

[0239] GOTO LOOP(10x)

[0240] / / Step 106 / /

[0241] LOOP

[0242] c = a + b

[0243] GOTO LOOP(10x)

[0244] / / Step 108 / /

[0245] Addr = @C

[0246] LOOP

[0247] Load Addr

[0248] Addr = addr + 1

[0249] GOTO LOOP(10x)

Claims

1. A data processing method, which can be decomposed into a set of basic operations to be performed by a computing device (1), the device (1) comprising: - a control unit (5); - at least one arithmetic logic unit (9); - a set of registers (11) capable of supplying data forming operands to the input of the first arithmetic logic unit (9) and capable of receiving data from the output of the arithmetic logic unit (9); - memory (13); - a memory interface (15), by means of which data (A0, A15) are transmitted and routed between the register (11) and the memory (13); The method comprises: a) obtaining (101, 102) the memory address (@A0, @A15) of each data missing from register (11) and forming an operand for at least one elementary operation to be performed, and; b) reading (103, 104) each data (A0, A15) from the memory (13) via the memory interface (15) by means of the obtained memory address (@A0, @A15) so as to load the data into the register (11), so that the data read during the reading operation are grouped together in the form of two, three, four or more than four data groups, and so that one or more data groups read during the reading operation are read in advance for one or more future computing operations, except for the computing operation immediately after the reading operation, and the data to be read in advance are pre-selected depending on the computing operation to be performed, thereby implementing a pre-fetching algorithm, which makes it possible to obtain all operands of the next computing operation to be performed in advance; c) transmitting (105) an instruction for executing a calculation operation from the control unit (5) to the first arithmetic logic unit (9), the instruction not containing any addressing instruction; d) upon receiving an instruction to perform a calculation operation, and once the corresponding operands are available on the register (11), performing all the elementary operations (106) by means of the first arithmetic logic unit (9) receiving at input each operand from the register (11); e) storing (107) data (C0, C15) forming the result of the processing operation in a register (11) at the output of the first arithmetic logic unit (9); f) obtaining (108) the memory address (@C0, @C15) of each data used to form the result of the processing operation; g) writing (109) each data (C0, C15) forming the result of the processing operation from the register (11) to the memory (13) for storage via the memory interface (15) with the aid of the obtained memory address (@C0, @C15).

2. The method according to claim 1, characterized in that The first arithmetic logic unit (9) performs all basic calculation operations of the processing operation during the continuous calculation cycle. The first arithmetic logic unit (9) does not perform any memory access operation during the calculation cycle.

3. The method according to claim 1, characterized in that At least one of the following steps includes an iterative loop: a) obtaining (101, 102) the memory address (@A0, @A15) of each data missing from register (11) and forming an operand for at least one elementary operation to be performed, and; d) after receiving an instruction to perform a calculation operation, performing all the basic operations (106) by means of a first arithmetic logic unit (9) receiving at input each operand from a register (11); f) Obtain (108) the memory address (@C0, @C15) of each data used to form the result of the processing operation.

4. The method according to claim 1, characterized in that: The device (1) further comprises at least one additional arithmetic logic unit separate from the first arithmetic logic unit (9) performing all basic operations (106), the additional arithmetic logic unit implementing the following operations: a) obtaining (101, 102) the memory address (@A0, @A15) of each data missing from register (11) and forming an operand for at least one basic operation to be performed; and b) reading (103, 104) each data (A0, A15) from the memory (13) via the memory interface (15) by means of the obtained memory address (@A0, @A15) so as to load the data into the register (11).

5. A computing device (1) for processing data, wherein the processing operation can be decomposed into a set of basic operations to be performed, the device (1) comprising: - a control unit (5); - at least one first arithmetic logic unit (9) among a plurality of arithmetic logic units; - a set of registers (11) capable of supplying data forming operands to the inputs of the arithmetic logic units (9, 10) and capable of receiving data from the outputs of the arithmetic logic unit (9); - memory (13); - a memory interface (15), by means of which data (A0, A15) are transmitted and routed between the register (11) and the memory (13); The computing device (1) is configured to: a) obtaining (101, 102) the memory address of each data missing from register (11) and forming an operand for at least one elementary operation to be performed, and; b) reading (103, 104) each data from the memory (13) via the memory interface (15) by means of the obtained memory address in order to load the data into the register (11), so that the data read during the reading operation are grouped together in the form of two, three, four or more than four data groups, and so that one or more data groups read during the reading operation are read in advance for one or more future computing operations, except for the computing operation to be performed immediately after the reading operation, and the data to be read in advance are pre-selected depending on the computing operation to be performed, thereby implementing a pre-fetching algorithm, which makes it possible to obtain all operands of the next computing operation to be performed in advance; c) transmitting (105) an instruction for executing a calculation operation from the control unit (5) to the first arithmetic logic unit (9), the instruction not containing any addressing instruction; d) upon receiving an instruction to perform a calculation operation, and once the operands are available on the register (11), performing all the elementary operations (106) by means of the first arithmetic logic unit (9) receiving at input each operand from the register (11); e) storing data (107) forming the result of the processing operation in a register (11) at the output of the first arithmetic logic unit (9); f) obtaining (108) a memory address of each data used to form a result of the processing operation; g) writing (109) each data forming the result of the processing operation from the register (11) to the memory (13) for storage via the memory interface (15) with the aid of the obtained memory address. 6 . A non-transitory computer-readable recording medium having recorded thereon a program for implementing the method according to claim 1 when the program is executed by a processor.

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