Multi-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuit

Abstract

A multi-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuit is disclosed. In one aspect, the multi-bit parallel SA flash ADC circuit includes a digital-to-analog converter (DAC) circuit that receives a reference voltage and a test bit code and generates a DAC analog signal. The SA flash ADC circuit includes parallel comparator stages, each of which includes one or more comparator circuits equal to two (2) to the power of the number of digital bits of the corresponding parallel comparator stage minus one (1). Each comparator circuit receives an analog input signal and a corresponding DAC analog signal, and generates a digital signal. If the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal of each comparator circuit is a logic high, and if the analog input signal has a smaller voltage, the digital signal of each comparator circuit is a logic low. The digital signal corresponding to each parallel comparator stage is used to generate a digital output signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to application No. 16 / 113,619, filed on August 27, 2018, entitled “MULTIPLE-BIT PARALLEL SUCCESSIVE APPROXIMATION (SA) FLASH ANALOG-TO-DIGITAL CONVERTER (ADC) CIRCUITS,” which is assigned to the assignee and is hereby expressly incorporated herein by reference. Technical Field

[0003] The disclosed technology generally relates to analog-to-digital converter (ADC) circuits, and in particular to successive approximation (SA) flash ADC circuits. Background Art

[0004] Processor-based systems employ analog-to-digital conversion of signals in conjunction with performing various functions. One method of implementing such analog-to-digital conversion is to use a flash analog-to-digital converter (ADC) circuit. The operation of the flash ADC circuit involves connecting multiple comparators in parallel to compare an input voltage signal with a series of analog signals generated in parallel from a reference voltage during the conversion process. Specifically, each comparator in the flash ADC circuit operates asynchronously so that each comparison is performed without the need for a reference clock signal. The flash ADC circuit uses the result of each comparison of the input voltage signal with the analog signal to generate a final value of the digital output signal.

[0005] For example, conventional flash ADC circuits use 2 N -1 comparator circuit, where N is the number of bits in the digital output signal. Additionally, the reference voltage is divided into 2 N -1 generated analog signals, the analog signals are distributed across the range of reference voltages. Each analog signal is provided to one input of a corresponding comparator circuit, and the input analog signal is provided to the other input of each comparator circuit. In this way, for each comparator circuit, if the generated analog signal has a voltage greater than the voltage of the input analog signal, the output of the corresponding comparator circuit has a logical low "0" value. On the contrary, if the generated analog signal has a voltage less than the voltage of the input analog signal, the output of the corresponding comparator circuit has a logical high "1" value. The output signal of each comparator circuit is used to create a digital output signal, which is a digital representation of the input voltage signal.

[0006] In this regard, conventional flash ADC circuits have relatively fast conversion times. However, since conventional flash ADC circuits are designed to generate digital output signals with more bits (i.e., a higher number of bits N), the number of circuit elements employed in conventional flash ADC circuits increases geometrically, resulting in more chip area being used and power being consumed. Therefore, it may be advantageous to trade off conversion time for chip area and power reduction. Summary of the invention

[0007] Various aspects disclosed in the specific embodiments include a multi-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuit. In one aspect, the multi-bit parallel SA flash ADC circuit is configured to generate a digital output signal having a number of digital bits, wherein the digital output signal is a digital representation of an analog input signal. In order to perform such conversion, the multi-bit parallel SA flash ADC circuit includes a multi-output digital-to-analog converter (DAC) circuit that receives a reference voltage and uses the reference voltage and the digital bits generated by the parallel comparator stages of the system comparison circuit to generate a plurality of DAC analog signals. Each of the parallel comparator stages includes a plurality of comparator circuits, the number of comparator circuits being equal to the number of digital output bits of the corresponding parallel comparator stage raised to the power of two (2) minus one (1). Each comparator circuit receives an analog input signal and a corresponding DAC analog signal, and generates a digital signal based on comparing the analog input signal and the DAC analog signal. In particular, if the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal of each comparator will have a logic high value, and if the analog input signal has a lesser voltage than the corresponding DAC analog signal, the digital signal of each comparator will have a logic low value. The system comparison circuit uses the digital signal from the comparator circuit of each parallel comparator stage to generate a digital bit corresponding to each parallel comparator stage, where one or more digital bits together generate a digital output signal. In the examples disclosed herein, for the same number of digital bits, the multi-bit parallel SA flash ADC circuit has a conversion time similar to that of a conventional flash ADC circuit.

[0008] In this regard, in an exemplary aspect, a multi-bit parallel SA flash ADC circuit is provided. The multi-bit parallel SA flash ADC circuit includes a DAC circuit configured to receive a reference voltage and generate a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage. The multi-bit parallel SA flash ADC circuit also includes a system comparison circuit, which includes a plurality of parallel comparator stages. Each of the plurality of parallel comparator stages includes one or more comparator circuits, wherein the number of the one or more comparator circuits of each parallel comparator stage is equal to the amount of the number of digital bits of the corresponding parallel comparator stage raised to the power of two (2) minus one (1). Each of the one or more comparator circuits is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal. If the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal has a logic high value, and if the analog input signal has a lower voltage than the corresponding DAC analog signal, the digital signal has a logic low value. The system comparison circuit is configured to generate one or more digital bits corresponding to each parallel comparator stage based on each corresponding digital signal, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

[0009] In another exemplary aspect, a multi-bit parallel SA flash ADC circuit is provided. The multi-bit parallel SA flash ADC circuit includes a device for converting a digital value into an analog value, which is configured to receive a reference voltage and generate a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage. The multi-bit parallel SA flash ADC circuit also includes a device for generating digital bits, which includes a plurality of devices for comparing values ​​in parallel. Each device for comparing values ​​in parallel includes a plurality of devices for comparing, wherein the number of devices for comparing in each device for comparing values ​​in parallel is equal to two (2) times the power of the number of digital bits of the corresponding device for comparing values ​​in parallel minus one (1). Each device for comparing is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal. If the analog input signal has a voltage greater than the corresponding DAC analog signal, the digital signal has a logical high value, and if the analog input signal has a voltage less than the corresponding DAC analog signal, the digital signal has a logical low value. The means for generating digital bits is configured to generate one or more digital bits corresponding to each means for comparing values ​​in parallel, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal.

[0010] In another exemplary aspect, a method for converting an analog input signal into a digital output signal is provided, wherein a plurality of digital bits of the digital output signal are determined in parallel. The method includes receiving a reference voltage and generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage. The method also includes receiving an analog input signal and generating one or more digital signals in a plurality of parallel comparator stages. Each digital signal is generated by comparing the analog input signal with a corresponding DAC analog signal, wherein if the analog input signal has a greater voltage than the corresponding DAC analog signal, each digital signal has a logical high value, and if the analog input signal has a smaller voltage than the corresponding DAC analog signal, each digital signal has a logical low value. The method also includes generating one or more digital bits corresponding to each parallel comparator stage based on one or more digital signals of the corresponding parallel comparator stage, wherein the one or more digital bits collectively generate a digital output signal, and the digital output signal is a digital representation of the analog input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a circuit diagram of an exemplary multi-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuit configured to convert an analog input signal into a digital output signal, wherein multiple bits of the digital output signal are generated in parallel;

[0012] Figure 2 is a circuit diagram of an exemplary two (2)-bit parallel four (4)-bit SA flash ADC circuit configured to convert an analog input signal into a four (4)-bit digital output signal, employing a single output digital-to-analog converter (DAC) circuit corresponding to each comparator circuit;

[0013] Figure 3 The diagram can be Figure 1 A flowchart of an exemplary process performed by a multi-bit parallel SA flash ADC circuit to convert an analog input signal into a digital output signal;

[0014] Figure 4 is a circuit diagram of an exemplary multi-bit parallel SA flash ADC circuit that employs a multi-output DAC circuit instead of a single output DAC circuit for each corresponding comparator circuit;

[0015] Figure 5 It can be targeted Figure 4 A circuit diagram of an exemplary resistor rotation circuit employed for each DAC stage of a multi-output DAC circuit;

[0016] Figure 6 is a circuit diagram of another exemplary multi-bit parallel SA flash ADC circuit that employs another multi-output DAC circuit instead of a single output DAC circuit for each corresponding comparator circuit;

[0017] Figure 7 Yes, it can include Figure 1 , Figure 2 , Figure 4 and Figure 6 A block diagram of an exemplary processor-based system for a multi-bit parallel SA flash ADC circuit; and

[0018] Figure 8 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components formed in an integrated circuit (IC), wherein the RF components may include a Figure 1 , Figure 2 , Figure 4 and Figure 6 Components of a multi-bit parallel SA flash ADC circuit. DETAILED DESCRIPTION

[0019] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0020] Various aspects disclosed in the specific embodiments include a multi-bit parallel successive approximation (SA) flash analog-to-digital converter (ADC) circuit. In one aspect, the multi-bit parallel SA flash ADC circuit is configured to generate a digital output signal having a number of digital bits, wherein the digital output signal is a digital representation of an analog input signal. In order to perform such conversion, the multi-bit parallel SA flash ADC circuit includes a multi-output digital-to-analog converter (DAC) circuit that receives a reference voltage and uses the reference voltage and the digital bits generated by the parallel comparator stages of the system comparison circuit to generate a plurality of DAC analog signals. Each of the parallel comparator stages includes one or more comparator circuits, the number of the one or more comparator circuits being equal to the number of digital output bits of the corresponding parallel comparator stage raised to the power of two (2) minus one (1). Each comparator circuit receives an analog input signal and a corresponding DAC analog signal, and generates a digital signal based on comparing the analog input signal and the DAC analog signal. In particular, if the voltage of the analog input signal is greater than the voltage of the corresponding DAC analog signal, the digital signal of each comparator will have a logic high value, and if the voltage of the analog input signal is less than the voltage of the corresponding DAC analog signal, the digital signal of each comparator will have a logic low value. The system comparison circuit uses the digital signals from one or more comparator circuits of each parallel comparator stage to generate a digital bit corresponding to each parallel comparator stage, wherein the one or more digital bits together generate a digital output signal. In the examples disclosed herein, for the same number of digital bits, the multi-bit parallel SA flash ADC circuit has a conversion time similar to that of a conventional flash ADC circuit.

[0021] in this regard, Figure 1is a circuit diagram of an exemplary multi-bit parallel SA flash ADC circuit 100 configured to convert an analog input signal VIN into a digital output signal DOUT having digital bits DG(A)-DG(1), wherein several of the digital bits DG(A)-DG(1) are generated in parallel. In various aspects described herein, the digital bit DG(A) (e.g., the highest numbered digital bit DG) is the most significant bit (MSB) of the digital output signal DOUT, and the digital bit DG(1) (e.g., the lowest numbered digital bit DG) is the least significant bit (LSB) of the digital output signal DOUT. To perform the conversion, the multi-bit parallel SA flash ADC circuit 100 employs a DAC circuit 102 configured to receive a reference voltage VREF, and in this regard, a plurality of test bit codes 104(1)(1)-104(B)(C) are used. As discussed in more detail below, each trial bit code 104(1)(1)-104(B)(C) includes a unique digital bit sequence having a value defined for one or more digital bits and enables a successive approximation property of the multi-bit parallel SA flash ADC circuit 100. The DAC circuit 102 is configured to generate a DAC analog signal 106(1)(1)-106(B)(C) based on a reference voltage VREF, the trial bit codes 104(1)(1)-104(B)(C), and a subset of digital bits DG(1)-DG(A) generated by parallel comparator stages 108(1)-108(B) of a system comparison circuit 109. The DAC analog signal 106(1)(1)-106(B)(C) is provided to each corresponding parallel comparator stage 108(1)-108(B). In this aspect, the DAC circuit 102 employs a DAC array 110(1)-110(B), each of which corresponds to a parallel comparator stage 108(1)-108(B) and includes a corresponding single-output DAC circuit 112(1)(1)-112(B)(C). However, as described below, the DAC circuit 102 in other aspects may employ a multi-output DAC circuit in place of the DAC array 110(1)-110(B). It should also be noted that the DAC array 110(1)-110(B) and its corresponding parallel comparator stage 108(1)-108(B) may each generate a different number of corresponding DAC analog signals 106(1)(1)-106(B)(C) and digital signals.

[0022] Continue to refer Figure 1, each of the parallel comparator stages 108(1)-108(B) includes a number C of corresponding comparator circuits 114(1)(1)-114(B)(C), where C is equal to the number D of digital bits DG(1)-DG(A) of the corresponding parallel comparator stages 108(1)-108(B) raised to the power of two (2) minus one (1) (i.e., C=(2^D)-1). In this example, A=B*D, so the digital bits DG(A-(B-1)D)-DG(1) have D bits. As used herein, the numbers A, B, C, and D are positive integers. For example, if the parallel comparator stage 108(1) corresponds to two (2) digital bits DG(A), DG(A-1) of the digital output signal DOUT, the parallel comparator stage 108(1) includes three (3) comparator circuits 114(1)(1)-114(1)(3) (e.g., (2^2)-1=3). As discussed in detail below, the number D can be the same in one or more parallel comparator stages 108(1)-108(B) so that the number C is the same in one or more parallel comparator stages 108(1)-108(B) and the DAC array 110(1)-110(B). Alternatively, the number D can be different in each parallel comparator stage 108(1)-108(B) so that the number C is different in each parallel comparator stage 108(1)-108(B) and the DAC array 110(1)-110(B). Each comparator circuit 114(1)(1)-114(B)(C) receives an analog input signal VIN and a corresponding DAC analog signal 106(1)(1)-106(B)(C), and generates a digital signal 116(1)(1)-116(B)(C) based on comparing the analog input signal VIN with the DAC analog signal 106(1)(1)-106(B)(C). In particular, if the analog input signal VIN has a greater voltage than the corresponding DAC analog signal 106(1)(1)-106(B)(C), the digital signal 116(1)(1)-116(B)(C) of each comparator circuit 114(1)(1)-114(B)(C) has a logic high "1" value, and if the analog input signal VIN has a lesser voltage than the corresponding DAC analog signal 106(1)(1)-106(B)(C), the digital signal 116(1)(1)-116(B)(C) of each comparator circuit 114(1)(1)-114(B)(C) has a logic low "0" value. The system comparison circuit 109 is configured to generate a digital bit DG(1)-DG(A) corresponding to each parallel comparator stage 108(1)-108(B), wherein the digital bits DG(1)-DG(A) collectively generate a digital output signal DOUT.In particular, in this aspect, the system comparison circuit 109 includes a thermometer to binary converter (TTB) circuit 118 configured to receive digital signals 116(1)(1)-116(B)(C) from the comparator circuits 114(1)(1)-114(B)(C) of each parallel comparator stage 108(1)-108(B). The TTB circuit 118 is further configured to generate digital bits DG(1)-DG(A) corresponding to each parallel comparator stage 108(1)-108(B) to generate a digital output signal DOUT.

[0023] Continue to refer Figure 1 , operational details of the multi-bit parallel SA flash ADC circuit 100 are now provided. Specifically, to convert an analog input signal VIN into a digital output signal DOUT, a parallel comparator stage 108(1) is configured to calculate the D most significant digital bits DG(A)-DG(A-D+1) of the digital output signal DOUT. To calculate the digital bits DG(A)-DG(A-D+1), test bit codes 104(1)(1)-104(1)(C) are provided to a DAC array 110(1), wherein corresponding test bit codes 104(1)(1)-104(1)(C) each represent a unique sequence of digital bits DG(A)-DG(A-D+1). Using the test bit codes 104(1)(1)-104(1)(C) and a reference voltage VREF, the DAC array 110(1) generates corresponding DAC analog signals 106(1)(1)-106(1)(C). In addition, the parallel comparator stage 108(1) compares each of the DAC analog signals 106(1)(1)-106(1)(C) with the analog input signal VIN to generate corresponding digital signals 116(1)(1)-116(1)(C), which are converted into digital bits DG(A)-DG(A-D+1) by stage 120(1) of the TTB circuit 118.

[0024] Continue to refer Figure 1It is important to note that the multi-bit parallel SA flash ADC circuit 100 is asynchronous (i.e., not controlled by a clock signal). Specifically, each DAC array 110(2)-110(B) is configured to receive the output of stage 120(1)-120(B) generated as the digital bits DG(1)-DG(A) generated in each previous parallel comparator stage 108(1)-108(B). In this manner, each DAC array 110(2)-110(B) generates a corresponding DAC analog signal 106(2)(1)-106(B)(C) in response to the stabilization of the digital bits DG(1)-DG(A) of the previous parallel comparator stage 108(1)-108(B). To this end, the parallel comparator stage 108(2) is configured to calculate the next D most significant digital bits DG(AD)-DG(A-2D+1) of the digital output signal DOUT. In order to calculate the digital bits DG(AD)-DG(A-2D+1), test bit codes 104(2)(1)-104(2)(C) are provided to the DAC array 110(2), wherein the test bit codes 104(2)(1)-104(2)(C) each represent a unique sequence of the digital bits DG(AD)-DG(A-2D+1). In addition, the digital bits DG(A)-DG(A-D+1) are also provided to the DAC array 110(2). Using the test bit codes 104(2)(1)-104(2)(C), the digital bits DG(A)-DG(A-D+1) and the reference voltage VREF, the DAC array 110(2) generates corresponding DAC analog signals 106(2)(1)-106(2)(C). In addition, parallel comparator stage 108(2) compares each of DAC analog signals 106(2)(1)-106(2)(C) with analog input signal VIN to generate corresponding digital signals 116(2)(1)-116(2)(C), which are converted into digital bits DG(AD)-DG(A-2D+1) by stage 120(2) of TTB circuit 118. The above sequence continues for the remaining digital bits DG(A-2D-1)-DG(1) using the remaining DAC arrays 110(3)-110(B), parallel comparator stages 108(3)-108(B), and stages 120(3)-120(B) of TTB circuit 118.

[0025] Continue to refer Figure 1As described above, the number D can be the same or vary for each parallel comparator stage 108(1)-108(B), so that the number C can also vary for each parallel comparator stage 108(1)-108(B) and DAC array 110(1)-110(B). For example, DAC array 110(1), parallel comparator stage 108(1), and stage 120(1) can correspond to the MSBs of the M number of digital bits DG(1)-DG(A). Therefore, DAC array 110(1) receives test bit codes 104(1)(1)-104(1)((2^M)-1), includes single output DAC circuits 112(1)(1)-112(1)((2^M)-1), and generates DAC analog signals 106(1)(1)-106(1)((2^M)-1). In addition, parallel comparator stage 108(1) includes (2^M)-1 comparator circuits 114(1)(1)-114(1)((2^M)-1) and generates digital signals 116(1)(1)-116(1)((2^M)-1). Stage 120(1) then generates the M number of MSBs of digital bits DG(1)-DG(A). DAC array 110(2), parallel comparator stage 108(2), and stage 120(2) correspond to the N number of digital bits within DG(1)-DG(A), while DAC array 110(3), parallel comparator stage 108(3), and stage 120(3) correspond to the P number of digital bits within DG(1)-DG(A). Furthermore, DAC array 110(B-1), parallel comparator stage 108(B-1), and stage 120(B-1) correspond to the Q number of digital bits within DG(1)-DG(A), while DAC array 110(B), parallel comparator stage 108(B), and stage 120(B) correspond to the R number of digital bits within DG(1)-DG(A). Configuring the multi-bit parallel SA flash ADC circuit 100 to implement different numbers of M, N, P, Q, and R provides the designer with the ability to customize the level of parallelism at a specific granularity based on the needs of a specific application.

[0026] Now describe Figure 1 To this end, specific aspects of the multi-bit parallel SA flash ADC circuit 100 are described below to provide additional explanation. Figure 2 1 is a circuit diagram of an exemplary two (2)-bit parallel four (4)-bit SA flash ADC circuit 200 configured to convert an analog input signal VIN into a four (4)-bit (i.e., digital bits DG(4)-DG(1)) digital output signal DOUT using a single output DAC circuit 112(1)(1)-112(2)(3) corresponding to each comparator circuit 114(1)(1)-114(2)(3). The two (2)-bit parallel four (4)-bit SA flash ADC circuit 200 includes a Figure 1The common elements of the multi-bit parallel SA flash ADC circuit 100 are utilized Figure 1 and Figure 2 The common component numbers in the drawings are referred to and therefore will not be repeated in this article.

[0027] Continue to refer Figure 2 In order to convert the analog input signal VIN into a digital output signal DOUT, the parallel comparator stage 108(1) is configured to calculate the two (2) most significant digital bits DG(4)-DG(3) of the digital output signal DOUT. In order to calculate the digital bits DG(4)-DG(3), three (3) test bit codes 104(1)(1)-104(1)(3) are provided to the DAC array 110(1). In particular, the input ports 202(4)-202(3) of the single output DAC circuit 112(1)(1) receive the test bit code 104(1)(1) including the bit sequence “11”. In addition, the input ports 202(4), 202(3) of the single output DAC circuit 112(1)(2) receive the test bit code 104(1)(2), the test bit code 104(1)(2) including the bit sequence "10" corresponding to the digital bits DG(4), DG(3), and the input ports 202(4), 202(3) of the single output DAC circuit 112(1)(3) receive the test bit code 104(1)(3), the test bit code 104(1)(3) including the bit sequence "01" corresponding to the digital bits DG(4), DG(3). In addition, the input port 202(2), 202(1) of each of the single output DAC circuits 112(1)(1)-112(1)(3) is electrically coupled to ground, which provides a logic low "0" value to each corresponding input port 202(2), 202(1). Each DAC circuit 112(1)(1)-112(1)(3) also includes a voltage input node 204 configured to receive a reference voltage VREF. Using the test bit codes 104(1)(1)-104(1)(3) and the reference voltage VREF, the DAC array 110(1) generates corresponding DAC analog signals 106(1)(1)-106(1)(3). In particular, the DAC circuit 102 is configured to generate DAC analog signals 106(1)(1)-106(1)(3) having corresponding values, where the corresponding values ​​are divisions of a voltage range between the reference voltage VREF and a ground signal. For example, if the reference voltage VREF is 1.0 V, the DAC analog signals 106(1)(1)-106(1)(3) are equal to 0.75 V, 0.50 V, and 0.25 V, respectively.

[0028] Continue to refer Figure 2, each of the DAC analog signals 106(1)(1)-106(1)(3) is provided to each corresponding comparator circuit 114(1)(1)-114(1)(3). In this manner, the parallel comparator stage 108(1) compares each of the DAC analog signals 106(1)(1)-106(1)(3) with the analog input signal VIN to generate a corresponding digital signal 116(1)(1)-116(1)(3). More specifically, the comparator circuit 114(1)(1) generates the digital signal 116(1)(1) by comparing the DAC analog signal 106(1)(1) with the analog input signal VIN, and the comparator circuit 114(1)(2) generates the digital signal 116(1)(2) by comparing the DAC analog signal 106(1)(2) with the analog input signal VIN. In addition, the comparator circuit 114(1)(3) generates a digital signal 116(1)(3) by comparing the DAC analog signal 106(1)(3) with the analog input signal VIN. For example, if VREF is 1.0V and if the analog input signal VIN is equal to 0.57V, and the DAC analog signals 106(1)(1)-106(1)(3) are equal to 0.75V, 0.5V, and 0.25V, respectively, then the digital signal 116(1)(1) has a logic 0 value, the digital signal 116(1)(2) has a logic 1 value, and the digital signal 116(1)(3) has a logic 1 value. The digital signals 116(1)(1)-116(1)(3) are converted into digital bits DG(4), DG(3) by the stage 120(1) of the TTB circuit 118. For example, the digital bits DG(4), DG(3) may have a value of "10". In this example, it may be that all of the DAC analog signals 106(1)(1)-106(1)(3) are “000”, “001”, “011”, or “111” because of how the digital signals 116(1)(1)-116(1)(3) generated by the comparator circuits 114(1)(1)-114(1)(3) generate the thermometer code based on which threshold value among the DAC analog signals 106(1)(1)-106(1)(3) the input VIN is greater than.To this end, TTB circuit 118 and stage 120(1) generate “00” for digital bits DG(4) and DG(3) in response to comparator output “000” of digital signal 116(1)(1)-116(1)(3); it generates “01” for digital bits DG(4) and DG(3) in response to comparator output “001” of digital signal 116(1)(1)-116(1)(3); it generates “10” for digital bits DG(4) and DG(3) in response to comparator output “011” of digital signal 116(1)(1)-116(1)(3); and it generates “11” for digital bits DG(4) and DG(3) in response to comparator output “111” of digital signal 116(1)(1)-116(1)(3).

[0029] For example, continue to refer to Figure 2In this regard, to generate digital bits DG(4), DG(3), stage 120(1) of TTB circuit 118 employs inverters 206(1)(1), 206(1)(2), AND-based gates 208(1)(1), 208(1)(2) (e.g., AND gates 208(1)(1), 208(1)(2)), and OR-based gates 210(1)(1), 210(1)(2) (e.g., OR gates 210(1)(1), 210(1)(2)). Digital signal 116(1)(1) (e.g., a value of 0) is provided to inverter 206(1)(1), causing inverter 206(1)(1) to generate inverted digital signal 116′(1)(1) (e.g., a value of 1), and inverted digital signal 116′(1)(1) is provided to AND gates 208(1)(1), 208(1)(2). Additionally, digital signal 116(1)(2) (e.g., a 1 value) is provided to AND gate 208(1)(1). In this example, AND gate 208(1)(1) generates an intermediate digital signal 212(1)(1), which has a logic high "1" value in this example. Intermediate digital signal 212(1)(1) (e.g., a 1 value) is provided to inverter 206(1)(2), where inverter 206(1)(2) generates an inverted intermediate digital signal 212'(1)(1) (e.g., a 0 value), which is provided to AND gate 208(1)(2). The inverted digital signal 116'(1)(1) is also provided to an AND gate 208(1)(2), wherein the AND gate 208(1)(2) generates an intermediate digital signal 212(1)(2), which in this example has a logic high "1" value if the digital signals 116(1)(1), 116(1)(2) each have a logic low "0" value and the digital signal 116(1)(3) has a logic high "1" value, and has a logic low "0" value otherwise. The digital signal 116(1)(1) (e.g., 0 value) and the intermediate digital signal 212(1)(1) (e.g., 1 value) are provided to an OR gate 210(1)(1), wherein the OR gate 210(1)(1) generates a digital bit DG(4) (e.g., 1 value) of the digital output signal DG(4). In addition, the digital signal 116(1)(1) (e.g., 0 value) and the intermediate digital signal 212(1)(2) (e.g., 0 value) are provided to the OR gate 210(1)(2), where the OR gate 210(1)(2) generates the digital bit DG(3) (e.g., 0 value) of the digital output signal DG(3).

[0030] Continue to refer Figure 2, the parallel comparator stage 108(2) is configured to calculate the two (2) least significant digital bits DG(2), DG(1) of the digital output signal DOUT in response to the digital bits DG(4), DG(3) settling to a stable value. To calculate the digital bits DG(2), DG(1), three (3) trial bit codes 104(2)(1)-104(2)(3) are provided to the DAC array 110(2), wherein each single output DAC circuit 112(2)(1)-112(2)(3) includes an input port 202(1)-202(4). Each DAC 112(2)(1)-112(2)(3) also includes a voltage input node 204 configured to receive a reference voltage VREF. The input port 202(4), 202(3) of each single output DAC circuit 112(2)(1)-112(2)(3) is configured to receive the generated digital bits DG(4), DG(3). However, the input ports 202(2), 202(1) of the single output DAC circuit 112(2)(1) receive the test bit code 104(2)(1), which includes the bit sequence "11" corresponding to the DAC inputs DG(2), DG(1). In addition, the input ports 202(2), 202(1) of the single output DAC circuit 112(2)(2) receive the test bit code 104(2)(2), which includes the bit sequence "10" corresponding to the DAC inputs DG(2), DG(1), and the input ports 202(2), 202(1) of the single output DAC circuit 112(2)(3) receive the test bit code 104(2)(3), which includes the bit sequence "01" corresponding to the digital bits DG(2), DG(1). The DAC array 110(2) uses the test bit codes 104(2)(1)-104(2)(3), the reference voltage VREF, and the digital bits DG(1)-DG(4) from the previous (one or more) parallel stages to generate corresponding DAC analog signals 106(2)(1)-106(2)(3). For example, the DAC analog signals 106(2)(1)-106(2)(3) in this example are equal to 0.6875V, 0.625V, and 0.5625V, respectively.

[0031] Continue to refer Figure 2, each of the DAC analog signals 106(2)(1)-106(2)(3) is provided to each corresponding comparator circuit 114(2)(1)-114(2)(3). In this manner, the parallel comparator stage 108(2) compares each of the DAC analog signals 106(2)(1)-106(2)(3) with the analog input signal VIN to generate a corresponding digital signal 116(2)(1)-116(2)(3). More specifically, the comparator circuit 114(2)(1) generates the digital signal 116(2)(1) (e.g., a logic 0 value) by comparing the DAC analog signal 106(2)(1) (e.g., a 0.6875V value) with the analog input signal VIN (0.57V), and the comparator circuit 114(2)(2) generates the digital signal 116(2)(2) (e.g., a logic 0 value) by comparing the DAC analog signal (e.g., a 0.625V value) with the analog input signal VIN. Additionally, comparator circuit 114(2)(3) generates digital signal 116(2)(3) (e.g., logic 1 value) by comparing DAC analog signal 106(2)(3) (e.g., 0.5625V value) with analog input signal VIN. Digital signals 116(2)(1)-116(2)(3) are converted into digital bits DG(2), DG(1) by stage 120(2) of TTB circuit 118.

[0032] For example, continue to refer to Figure 2In this regard, to generate digital bits DG(2), DG(1), stage 120(2) of TTB circuit 118 employs inverters 206(2)(1), 206(2)(2), AND-based gates 208(2)(1), 208(2)(2) (e.g., AND gates 208(2)(1), 208(2)(2)), and OR-based gates 210(2)(1), 210(2)(2) (e.g., OR gates 210(2)(1), 210(2)(2)). Digital signal 116(2)(1) (e.g., a value of 0) is provided to inverter 206(2)(1), causing inverter 206(2)(1) to generate complementary digital signal 116′(2)(1) (e.g., a value of 1), and complementary digital signal 116′(2)(1) is provided to AND gates 208(2)(1), 208(2)(2). In addition, digital signal 116(2)(2) (e.g., a 0 value) is provided to AND gate 208(2)(1). In this manner, AND gate 208(2)(1) generates an intermediate digital signal 212(2)(1), which has a logic high "1" value if digital signal 116(2)(1) has a logic low "0" value and digital signal 116(2)(2) has a logic high "1" value. Intermediate digital signal 212(2)(1) (e.g., a 0 value) is provided to inverter 206(2)(2), wherein inverter 206(2)(2) generates a complementary intermediate digital signal 212'(2)(1) (e.g., a 1 value), which is provided to AND gate 208(2)(2). The digital signal 116(2)(3) (e.g., a 1 value) is also provided to the AND gate 208(2)(2), wherein the AND gate 208(2)(2) generates an intermediate digital signal 212(2)(2), wherein if the digital signals 116(2)(1), 116(2)(2) each have a logic low "0" value and the digital signal 116(2)(3) has a logic high "1" value, the intermediate digital signal 212(2)(2) has a logic high "1" value, and otherwise has a logic low "0" value. The digital signal 116(2)(1) (e.g., a 0 value) and the intermediate digital signal 212(2)(1) (e.g., a 0 value) are provided to the OR gate 210(2)(1), wherein the OR gate 210(2)(1) generates the digital bit DG(2) (e.g., a 0 value) of the digital output signal DOUT. In addition, the digital signal 116(2)(1) (e.g., a value of 0) and the intermediate digital signal 212(2)(2) (e.g., a value of 1) are provided to the OR gate 210(2)(2), where the OR gate 210(2)(2) generates a digital bit DG(1) (e.g., a value of 1) of the digital output signal DOUT, such that in this example, the digital output signal DOUT is equal to "1001".

[0033] Figure 3 The diagram shows Figure 1 An exemplary process 300 is provided for use with a multi-bit parallel SA flash ADC circuit 100 to convert an analog input signal VIN into a digital output signal DOUT. The process 300 includes receiving a reference voltage VREF (block 302). The process 300 also includes receiving a plurality of test bit codes 104(1)(1)-104(B)(C), wherein each of the plurality of test bit codes 104(1)(1)-104(B)(C) includes a digital bit sequence having a value defined for one or more digital bits DG(1)-DG(A) (block 304). In addition, the process 300 includes generating a plurality of DAC analog signals 106(1)(1)-106(B)(C), wherein each DAC analog signal 106(1)(1)-106(B)(C) is based on the reference voltage VREF and a corresponding test bit code 104(1)(1)-104(B)(C) (block 306). Process 300 also includes receiving an analog input signal VIN (block 308). Process 300 also includes generating one or more digital signals 116(1)(1)-116(B)(C) in a plurality of parallel comparator stages 108(1)-108(B) (block 310). As described above, each digital signal 116(1)(1)-116(B)(C) is generated by comparing the analog input signal VIN with the corresponding DAC analog signal 106(1)(1)-106(B)(C), so that if the analog input signal VIN has a larger voltage than the corresponding DAC analog signal 106(1)(1)-106(B)(C), each digital signal 116(1)(1)-116(B)(C) has a logic high "1" value, and if the analog input signal VIN has a smaller voltage than the corresponding DAC analog signal 106(1)(1)-106(B)(C), each digital signal 116(1)(1)-116(B)(C) has a logic low "0" value. The process 300 also includes generating one or more digital bits DG(1)-DG(A) corresponding to each parallel comparator stage 108(1)-108(B) based on the digital signals 116(1)(1)-116(B)(C) of the corresponding parallel comparator stages 108(1)-108(B), wherein the one or more digital bits DG(1)-DG(A) collectively generate a digital output signal DOUT, the digital output signal DOUT being a digital representation of the analog input signal VIN (block 312). As described above, in this example, Figure 1The TTB circuit 118 in the embodiment is configured to receive the digital signals 116(1)(1)-116(B)(C) from the comparator circuits 114(1)(1)-114(B)(C) of each parallel comparator stage 108(1)-108(B). The TTB circuit 118 is further configured to generate digital bits DG(1)-DG(A) corresponding to each parallel comparator stage 108(1)-108(B) to generate a digital output signal DOUT.

[0034] As mentioned above, Figure 1 The DAC circuit 102 in the multi-bit parallel SA flash ADC circuit 100 can use a multi-output DAC circuit to replace the DAC array 110 (1)-110 (B), thereby reducing the overall area consumption. In this regard, Figure 4 An exemplary multi-bit parallel SA flash ADC circuit 400 is shown, which employs a multi-output DAC circuit 402 for the DAC circuit 102, rather than as shown in FIG. Figure 1 The multi-bit parallel SA flash ADC circuit 100 includes a single output DAC circuit 112(1)(1)-112(B)(C) for each corresponding comparator circuit 114(1)(1)-114(B)(C). The multi-bit parallel SA flash ADC circuit 400 in this aspect is a two (2)-bit parallel eight (8)-bit SA flash ADC circuit 400, wherein the multi-output DAC circuit 402 employs a DAC stage 404(1)-404(4) corresponding to each parallel comparator stage 108(1)-108(4). Other aspects employing the multi-output DAC circuit 402 may include any number of DAC stages 404(1)-404(B), wherein each DAC stage 404(1)-404(B) corresponds to a parallel comparator stage 108(1)-108(B). The multi-bit parallel SA flash ADC circuit 400 includes Figure 1 The common components of the multi-bit parallel SA flash ADC circuit 100 are utilized Figure 1 and Figure 4 The components are referred to by the same common component numbers and will therefore not be described in detail in this article.

[0035] Continue to refer Figure 4, each DAC stage 404(1)-404(4) is configured to generate a corresponding DAC voltage VDAC(1)-VDAC(3), wherein each DAC voltage VDAC(1)-VDAC(3) of each DAC stage 404(1)-404(4) is provided to a corresponding comparator circuit 114(1)(1)-114(4)(3) in each corresponding parallel comparator stage 108(1)-108(4). In particular, each DAC stage 404(1)-404(4) is configured to receive a corresponding top voltage VTOP(1)-VTOP(4) and a corresponding bottom voltage VBOT(1)-VBOT(4). Each DAC stage 404(1)-404(4) is further configured to generate each DAC voltage VDAC(1)-VDAC(3) by dividing a voltage range of each corresponding top voltage VTOP(1)-VTOP(4) and each corresponding bottom voltage VBOT(1)-VBOT(4). For example, reference voltage VREF is provided to DAC stage 404(1) as top voltage VTOP(1), and ground signal is provided to DAC stage 404(1) as bottom voltage VBOT(1). Therefore, DAC voltages VDAC(1)-VDAC(3) of DAC stage 404(1) are divisions of the range between reference voltage VREF and ground signal. In this manner, parallel comparator stage 108(1) generates digital signals 116(1)(1)-116(1)(3) based on each division of reference voltage VREF, such that digital bits DG(8), DG(7) are generated based on whether analog input voltage VIN is greater than or less than each corresponding DAC voltage VDAC(1)-VDAC(3). In this manner, DAC voltages VDAC(1)-VDAC(3) eliminate the need for reference voltage VREF. Figure 1 The need for the test bit codes 104(1)(1)-104(1)(3) discussed. Furthermore, while each DAC stage 404(1)-404(4) in this aspect is configured to generate a set of DAC voltages VDAC(1)-VDAC(3), other aspects may be configured to generate any number N of DAC voltages VDAC(1)-VDAC(N).

[0036] Continue to refer Figure 4, digital bits DG(8)-DG(3) are used to determine top voltages VTOP(2)-VTOP(4) and bottom voltages VBOT(2)-VBOT(4) for subsequent DAC stages 404(2)-404(4). For example, in response to digital bits DG(8), DG(7) reaching a stable state, DAC stage 404(1) provides top voltages VTOP(2) and bottom voltages VBOT(2) to DAC stage 404(2) from output nodes RA(1), RB(1). In addition, digital bits DG(6)-DG(5) are used by DAC stage 404(2) to determine top voltages VTOP(3) and bottom voltages VBOT(3) to be provided from output nodes RA(2), RB(2) to DAC stage 404(3). In addition, digital bits DG(4), DG(3) are used by DAC stage 404(3) to determine a top voltage VTOP(4) and a bottom voltage VBOT(4) to be provided to DAC stage 404(4) from output nodes RA(3), RB(3). Using digital bits DG(8), DG(7) in this manner generates a top voltage VTOP(2) and a bottom voltage VBOT(2) having a voltage range within which the analog input voltage VIN falls. Thus, top voltages VTOP(1)-VTOP(4) and bottom voltages VBOT(1)-VBOT(4) are generated so that the multi-bit parallel SA flash ADC circuit 400 can use successive approximation when generating digital bits DG(8)-DG(1). In addition, digital bits DG(6)-DG(5) are used by DAC stage 404(2) to determine a top voltage VTOP(3) and a bottom voltage VBOT(3) to be provided to DAC stage 404(3) from output nodes RA(2), RB(2). In addition, digital bits DG(4), DG(3) are used by DAC stage 404(3) to determine a top voltage VTOP(4) and a bottom voltage VBOT(4) to be provided from output nodes RA(3), RB(3) to DAC stage 404(4). Digital bits DG(2), DG(1) are not provided to DAC stage 404(4) because DAC stage 404(4) (i.e., final DAC stage 404(4) of multi-output DAC circuit 402) does not provide voltages to subsequent DAC stages. Instead, in this aspect, resistor 406 is electrically coupled to output nodes RA(4), RB(4) of DAC stage 404(4).

[0037] Continue to refer Figure 4It is noteworthy that certain aspects of the multi-bit parallel SA flash ADC circuit 400 can be designed so that the number D of digital bits DG(1)-DG(A) of each corresponding parallel comparator stage 108(1)-108(B) is equal to one (1). Therefore, the number C is equal to one (1) (e.g., C=(2^D)-1=(2^1)-1=1), so that each parallel comparator stage 108(1)-108(B) includes one (1) corresponding comparator circuit 114(1)(1)-114(B)(1). In such an aspect, the system comparison circuit 109 does not include the TTB circuit 118 because the digital signal 116(1)(1)-116(B)(1) of each corresponding comparator circuit 114(1)(1)-114(B)(1) is used as the corresponding digital bit DG(1)-DG(A).

[0038] With the adoption Figure 1 Compared to the DAC arrays 110(1)-110(B) described in the previous section, the use of the multi-output DAC circuit 402 as described above reduces the area consumption of the DAC circuit 102 because each DAC stage 404(1)-404(4) can use a ratio of Figure 1 Each DAC array 110(1)-110(B) can be implemented with fewer circuits. Figure 5 The diagram shows that Figure 4 An exemplary resistor rotation circuit 500 is employed in each DAC stage 404(1)-404(4) of the embodiment of the present invention. The resistor rotation circuit 500 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. The resistor rotation circuit 500 also includes a decoder circuit 502, which is configured to receive digital bits DG(2), DG(1) of the corresponding parallel comparator stage 108 and generate decoded signals DS(1)-DS(4) based on the digital bits DG(2), DG(1). In this aspect, the decoder circuit 502 is a one-hot decoder, wherein for any given value of the digital bits DG(2), DG(1), only one of the decoded signals DS(1)-DS(4) has a logic high "1" value. For example, the decoded signals DS(1)-DS(4) are generated according to the following logic functions: DS(1)=(inverted DG(2) AND inverted DG(1)); DS(2)=(inverted DG(2) AND DG(1)); DS(3)=(DG(2) AND inverted DG(1)); and DS(4)=DG(2) AND DG(1)). The resistor rotation circuit 500 also includes inverters 504(1)-504(4), which are configured to receive corresponding decoded signals DS(1)-DS(4) and generate corresponding inverted decoded signals DS'(1)-DS'(4).

[0039] Continue to refer Figure 5, resistor rotation circuit 500 also includes switches 506(1)-506(12), wherein a logic high "1" value closes switches 506(1)-506(12) and a logic low "0" value opens switches 506(1)-506(12). Switches 506(1)-506(4) are configured to receive corresponding inverted decoded signals DS'(1)-DS'(4). In addition, switches 506(5) and 506(7) are configured to receive decoded signal DS(4), switches 506(6) and 506(9) are configured to receive decoded signal DS(3), switches 506(8) and 506(11) are configured to receive decoded signal DS(2), and switches 506(10) and 506(12) are configured to receive decoded signal D(1). A resistor RADJ is also included, wherein a first node 508(1) is electrically coupled to a top voltage output node RA and a second node 508(2) is electrically coupled to a bottom voltage output node RB. The resistance of resistor RADJ can be adjusted so that the parallel combination of resistor RADJ and a desired resistance R_NEXT of the next DAC stage 404 is maintained at a desired constant value so that the resistor rotation circuit 500 generates a desired output. The resistance R_NEXT is equal to the sum of resistors 510(1)-510(4), and in this example, it is assumed that the resistance of switches 506(1)-506(4) is negligible in comparison. In addition, the resistor rotation circuit 500 includes resistors 510(1)-510(4) alternately coupled in series with corresponding switches 506(1)-506(4) and coupled in parallel with switches 506(5)-506(12). The resistance of resistor RADJ may be equal to the resistance of resistors 510(1)-510(4). In particular, a first node 512(1)(1) of resistor 510(1) is electrically coupled to switch 506(1), and a second node 512(1)(2) is electrically coupled to switches 506(2), 506(6), and 506(7). A first node 512(2)(1) of resistor 510(2) is electrically coupled to switch 506(2), and a second node 512(2)(2) is electrically coupled to a first node 512(3)(1) of resistor 510(3) and switches 506(8), 506(9). A first node 512(3)(1) of resistor 510(3) is electrically coupled to switches 506(8), 506(9), and a second node 512(3)(2) is electrically coupled to switch 506(3). A first node 512(4)(1) of resistor 510(4) is electrically coupled to switches 506(3), 506(10), and 506(11), and a second node 512(4)(2) is electrically coupled to switch 506(4). Note that switches 506(1)-506(12) may also be implemented using transistors with "sufficiently low" on-resistance.

[0040] Continue to refer Figure 5 , the above configuration causes the resistor rotation circuit 500 to generate DAC voltages VDAC(1)-VDAC(3), each of which is within a voltage range between the top voltage VTOP and the bottom voltage VBOT. In this aspect, the resistors 510(1)-510(4) each have approximately equal resistance (e.g., 2 kilo-ohms (kΩ)) such that the DAC voltages VDAC(1)-VDAC(3) are equal divisions of the voltage range between the top voltage VTOP and the bottom voltage VBOT. Additionally, if Figure 4 Using the resistor rotation circuit 500 for each DAC stage 404(1)-404(4), the resistance of the resistor 406 is eight (8) kilo-ohms (kΩ), and the resistor RADJ between the first node 508(1) and the second node 508(2) will have a value of 2.667 kΩ. For example, if the reference voltage VREF is equal to one (1.0) volt (V), then the DAC voltages VDAC(3)-VDAC(1) may be equal to 0.75 V, 0.5 V, and 0.25 V, respectively, regardless of the values ​​of the digital bits DG(2), DG(1). In addition, the above configuration causes the resistor rotation circuit 500 to generate a next-stage top voltage VTOP' on the top voltage output node TOP_OUT, and to generate a next-stage bottom voltage VBOT' on the bottom voltage output node BOT_OUT, wherein the next-stage top voltage VTOP' and the next-stage bottom voltage VBOT' are determined according to which of the switches 506(1)-506(12) is opened or closed based on the digital bits DG(2), DG(1). In addition, although the resistor rotation circuit 500 in this aspect is configured to generate DAC voltages VDAC(1)-VDAC(3), other aspects may be configured to generate any number N of DAC voltages VDAC(1)-VDAC(N).

[0041] Figure 6 Another exemplary multi-bit parallel SA flash ADC circuit 600 is shown. The circuit 600 uses another topology of a multi-output DAC circuit 602 instead of the Figure 1 The multi-bit parallel SA flash ADC circuit 100 includes a single output DAC circuit 112(1)(1)-112(B)(C) for each corresponding comparator circuit 114(1)(1)-114(B)(C). In this aspect, the multi-bit parallel SA flash ADC circuit 600 is a two (2)-bit parallel four (4)-bit SA flash ADC circuit 600. The multi-bit parallel SA flash ADC circuit 600 includes a single output DAC circuit 112(1)(1)-112(B)(C) for each corresponding comparator circuit 114(1)(1)-114(B)(C). Figure 4 The multi-bit parallel SA flash ADC circuit 400 and Figure 5 The resistor rotation circuit 500 has common components, and the common components utilize Figure 4 , Figure 5 and Figure 6 The common component numbers in the drawings are referred to and therefore will not be repeated in this article.

[0042] Continue to refer Figure 6 , the multi-output DAC circuit 602 includes resistors 604(1)-604(16) connected in series, wherein resistor 604(16) (i.e., top resistor 604(16)) is electrically coupled to a top voltage input node TOP configured to receive a top voltage VTOP, and resistor 604(1) (i.e., bottom resistor 604(1)) is electrically coupled to a bottom voltage input node BOT configured to receive a bottom voltage VBOT. In this aspect, each of the resistors 604(1)-604(16) has approximately the same resistance (e.g., 2 kΩ) such that the divided voltages VDIV(1)-VDIV(15) corresponding to each pair of the resistors 604(1)-604(16) are approximately equal divisions of the voltage range VTOP-VBOT. For example, if the top voltage VTOP is approximately equal to 1.0V and the bottom voltage VBOT is approximately equal to 0V, the resistors 604(1)-604(16) are configured to generate divided voltages VDIV(1)-VDIV(15) in increments of 0.0625V (e.g., 1 / 16V). Therefore, the divided voltage VDIV(1) corresponding to the resistors 604(1) and 604(2) is approximately equal to 0.0625V, the divided voltage VDIV(2) corresponding to the resistors 604(2) and 604(3) is approximately equal to 0.125V, and the divided voltage VDIV(15) corresponding to the resistors 604(15) and 604(16) is approximately equal to 0.9375V. In addition, the divided voltage VDIV(12) is provided to the comparator circuit 114(1)(1) in the parallel comparator stage 108(1), the divided voltage VDIV(8) is provided to the comparator circuit 114(1)(2) in the parallel comparator stage 108(1), and the divided voltage VDIV(4) is provided to the comparator circuit 114(1)(3) in the parallel comparator stage 108(1).

[0043] Continue to refer Figure 6, the multi-output DAC circuit 602 also includes switches 606(1)-606(12) electrically coupled to the parallel comparator stage 108(2). The decoder circuit 502 is configured to receive the digital bits DG(4), DG(3) corresponding to the parallel comparator stage 108(1) and generate decoded signals DS(4)-DS(1). Switches 606(1), 606(5) and 606(9) are configured to receive the decoded signal DS(4), and switches 606(2), 606(6) and 606(10) are configured to receive the decoded signal DS(3). In addition, switches 606(3), 606(7) and 606(11) are configured to receive the decoded signal DS(2), and switches 606(4), 606(8) and 606(12) are configured to receive the decoded signal DS(2). The divided voltages VDIV(15), VDIV(11), VDIV(7), and VDIV(3) are provided to switches 606(1)-606(4), respectively, wherein switches 606(1)-606(4) are electrically coupled to comparator circuit 114(2)(1) in parallel comparator stage 108(2). The divided voltages VDIV(14), VDIV(10), VDIV(6), and VDIV(2) are provided to switches 606(5)-606(8), respectively, wherein switches 606(5)-606(8) are electrically coupled to comparator circuit 114(2)(2) in parallel comparator stage 108(2). In addition, divided voltages VDIV(13), VDIV(9), VDIV(5), and VDIV(1) are provided to switches 606(9)-606(12), respectively, wherein switches 606(9)-606(12) are electrically coupled to comparator circuits 114(2)(3) in parallel comparator stage 108(2). Figure 1 Compared to the DAC arrays 110(1)-110(B)(C) described in the previous section, the use of the multi-output DAC circuit 602 as described above reduces the area consumption of the DAC circuit 102 because Figure 1 Compared to each DAC array 110(1)-110(B)(C) in FIG. 6 , the multi-output DAC circuit 602 can be implemented using fewer circuits.

[0044] Elements described herein are sometimes referred to as means for performing a particular function. To this end, DAC circuit 102 is sometimes referred to herein as “means for converting a digital value to an analog value configured to receive a reference voltage and generate a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage.” Parallel comparator stages 108(1)-108(B) are sometimes referred to herein as “multiple means for comparing values ​​in parallel.” Comparator circuits 114(1)(1)-114(B)(C) are sometimes referred to herein as “means for comparing values,” wherein “each means for comparing values ​​in parallel includes a plurality of means for comparing, wherein the number of means for comparing each means for comparing values ​​in parallel is equal to two (2) raised to the power of the number of digital bits of the corresponding means for comparing values ​​in parallel minus one (1).” Furthermore, “each means for comparing is configured to receive an analog input signal, receive a corresponding DAC analog signal, and generate a digital signal,” wherein “if the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal has a logic high value, and if If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the digital signal has a logic low value. "TTB circuit 118 is sometimes referred to herein as "a device for binary conversion, configured to receive digital signals from several devices for comparing values ​​in each of a plurality of devices for comparing values ​​in parallel and generate one or more digital bits corresponding to each device for comparing values ​​in parallel, wherein the one or more digital bits together generate a digital output signal, which is a digital representation of the analog input signal. "Multi-output DAC circuit 402 is sometimes referred to herein as "a multi-output device for converting digital values ​​into analog values." Resistor rotation circuit 500 is sometimes referred to herein as "a device for dividing voltage, configured to generate a corresponding number of DAC analog signals by generating a division of a voltage range."

[0045] The multi-bit parallel SA flash ADC circuits according to the various aspects disclosed herein may be provided or integrated in any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health products or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor helicopters.

[0046] in this regard, Figure 7 An example of a processor-based system 700 is shown, which may include Figure 1 , Figure 2 , Figure 4 and Figure 6 Elements of multi-bit parallel SA flash ADC circuits 100, 200, 400 and 600. In this example, the processor-based system 700 includes one or more central processing units (CPUs) 702, each of which includes one or more processors 704. The (one or more) CPUs 702 may have a cache memory 706 coupled to the (one or more) processors 704 for quick access to temporarily stored data. The (one or more) CPUs 702 are coupled to a system bus 708 and may enable the master devices and slave devices included in the processor-based system 700 to be coupled to each other. As is well known, the (one or more) CPUs 702 communicate with these other devices by exchanging address, control, and data information via the system bus 708. For example, the (one or more) CPUs 702 may communicate a bus transaction request to a memory controller 710, which is an example of a slave device. Although in Figure 7 Although not shown in the figure, multiple system buses 708 may be provided, each system bus 708 forming a different structure.

[0047] Other master devices and slave devices may be connected to the system bus 708. Figure 7As shown, these devices may include, for example, a memory system 712, one or more input devices 714, one or more output devices 716, one or more network interface devices 718, and one or more display controllers 720. (One or more) input devices 714 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. (One or more) output devices 716 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (One or more) network interface devices 718 can be any device configured to allow data exchange with a network 722. The network 722 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM The network interface device(s) 718 may be configured to support any type of communication protocol desired. The memory system 712 may include one or more memory units 724(0)-724(N).

[0048] The CPU(s) 702 may also be configured to access display controller(s) 720 via the system bus 708 to control information sent to display(s) 726. The display controller(s) 720 sends information to the display(s) 726 for display via the video processor(s) 728, which processes the information to be displayed into a format suitable for the display(s) 726. The display(s) 726 may include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0049] Figure 8 An exemplary wireless communication device 800 is shown, which includes radio frequency (RF) components formed in an integrated circuit (IC) 802, wherein the RF components may include Figure 1 , Figure 2 , Figure 4 and Figure 6 The components of the multi-bit parallel SA flash ADC circuits 100, 200, 400 and 600 in the embodiment of the present invention are shown in FIG. 8. To this end, the wireless communication device 800 may be provided in the IC 802. As an example, the wireless communication device 800 may include any one of the above-mentioned reference devices or be provided in any one of the above-mentioned reference devices. Figure 8As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include a memory for storing data and program codes. The transceiver 804 includes a transmitter 808 and a receiver 810 that support two-way communication. In general, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0050] The transmitter 808 or the receiver 810 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, for the receiver 810, the signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. The superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800 of FIG. 8 , the transmitter 808 and the receiver 810 are implemented using a direct conversion architecture.

[0051] In the transmit path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes DACs 812(1), 812(2) for converting the digital signals generated by the data processor 806 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0052] Within the transmitter 808, low pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from the low pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An up converter 818 up-converts the I and Q baseband signals using I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 822 via mixers 820(1), 820(2) to provide up-converted signals 824. A filter 826 filters the up-converted signals 824 to remove undesired signals caused by the frequency up-conversion and noise in the receive frequency band. A power amplifier (PA) 828 amplifies the up-converted signals 824 from the filter 826 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832 .

[0053] In the receive path, antenna 832 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate with a specific receive (RX) to TX duplexer frequency spacing so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Down-conversion mixers 838 (1), 838 (2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMPs) 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to the data processor 806. In this example, the data processor 806 includes ADCs 846(1), 846(2) for converting the analog input signals into digital signals for further processing by the data processor 806.

[0054] exist Figure 8 In the wireless communication device 800 of FIG. 8 , the TX LO signal generator 822 generates I and Q TX LO signals for frequency up-conversion, and the RX LO signal generator 840 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, the RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0055] Those skilled in the art will further understand that the various exemplary logic boxes, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as instructions stored in electronic hardware, memory or another computer-readable medium and executed by a processor or other processing device or a combination of the two. As an example, the master device and slave device described herein can be adopted in any circuit, hardware component, integrated circuit (IC) or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various exemplary components, boxes, modules, circuits and steps are generally described above with respect to their functions. How to implement such functions is related to specific applications, design choices and / or design constraints imposed on the entire system. The technician can implement the described functions in a changing manner for each specific application, but such implementation decisions should not be interpreted as causing departure from the scope of the present disclosure.

[0056] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0057] The various aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0058] It should also be noted that the operational steps described in any exemplary aspects of this article are described to provide examples and discussions. The described operations can be performed in many different sequences in addition to the illustrated sequence. In addition, the operations described in a single operational step can actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that it is obvious to those skilled in the art that the operational steps shown in the flow chart can be modified in many different ways. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be cited in the above entire specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination.

[0059] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but is consistent with the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-bit parallel successive approximation SA flash analog-to-digital converter ADC circuit, comprising: The digital-to-analog converter DAC circuit is configured as: receiving a reference voltage; as well as generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage; A system comparison circuit, comprising a plurality of parallel comparator stages, wherein each of the plurality of parallel comparator stages comprises: One or more comparator circuits, wherein: The number of the one or more comparator circuits of each parallel comparator stage is equal to an amount raised to the power of two to the number of digital bits of the corresponding parallel comparator stage minus one; and Each of the one or more comparator circuits is configured to: receiving an analog input signal; receiving a corresponding DAC analog signal; and Generates a digital signal where: If the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the digital signal has a logic low value; and the system comparison circuit being configured to generate one or more digital bits corresponding to each parallel comparator stage based on each corresponding digital signal, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal, wherein the DAC circuit comprises a plurality of DAC arrays, each DAC array in the plurality of DAC arrays corresponds to a parallel comparator stage in the plurality of parallel comparator stages and comprises a number of single-output DAC circuits, wherein: The number of single output DAC circuits of each DAC array is equal to the number of the one or more comparator circuits of the corresponding parallel comparator stage; Each single output DAC circuit in the DAC array corresponding to the most significant bit of the digital output signal is configured as: receiving a corresponding trial bit code comprising a digital bit sequence having values ​​defined for one or more digital bits corresponding to the digital output signal; and generating the corresponding DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and the corresponding test bit code; and Each single output DAC circuit of the plurality of DAC arrays except the DAC array corresponding to the most significant bit is configured as: receiving a corresponding test bit code and one or more digital bits for each parallel comparator stage; and The plurality of DAC analog signals are generated, wherein each DAC analog signal is based on the reference voltage, the corresponding test bit code, and corresponding one or more digital bits.

2. The multi-bit parallel SA flash ADC circuit of claim 1 , wherein the system comparison circuit further comprises a thermometer-to-binary (TTB) circuit configured to: receiving the digital signal from the one or more comparator circuits of each parallel comparator stage of the plurality of parallel comparator stages; and The one or more digital bits corresponding to each parallel comparator stage are generated, wherein the one or more digital bits collectively generate the digital output signal, the digital output signal being the digital representation of the analog input signal.

3. The multi-bit parallel SA flash ADC circuit of claim 1 , wherein the DAC circuit comprises a multi-output DAC circuit, the multi-output DAC circuit comprising a plurality of DAC stages, wherein: Each DAC stage in the plurality of DAC stages corresponds to a parallel comparator stage in the plurality of parallel comparator stages; and Each DAC stage of the plurality of DAC stages is configured as: receiving a corresponding top voltage and a corresponding bottom voltage, wherein voltage ranges of the corresponding top voltage and the corresponding bottom voltage are based on the reference voltage; as well as Based on the corresponding top voltage and the corresponding bottom voltage, a number of DAC analog signals are generated, wherein the number of the DAC analog signals is equal to the number of the one or more comparator circuits in each corresponding parallel comparator stage.

4. The multi-bit parallel SA flash ADC circuit of claim 3, wherein the system comparison circuit further comprises a thermometer-to-binary (TTB) circuit configured to: receiving the digital signal from the one or more comparator circuits of each parallel comparator stage of the plurality of parallel comparator stages; and The one or more digital bits corresponding to each parallel comparator stage are generated, wherein the one or more digital bits collectively generate the digital output signal, the digital output signal being the digital representation of the analog input signal. 5 . The multi-bit parallel SA flash ADC circuit of claim 3 , wherein the several DAC analog signals generated by each of the plurality of DAC stages have values ​​that are divisions of the voltage range.

6. The multi-bit parallel SA flash ADC circuit of claim 3, wherein each of the plurality of DAC stages comprises a resistor rotation circuit configured to generate a corresponding number of DAC analog signals by generating a division of the voltage range.

7. The multi-bit parallel SA flash ADC circuit of claim 6, wherein the resistor rotation circuit of each DAC stage comprises: a top voltage input node configured to receive the corresponding top voltage; a bottom voltage input node configured to receive the corresponding bottom voltage; The decoder circuit is configured as: receiving the one or more digital bits of the corresponding parallel comparator stage; and generating a number of decoded signals based on the one or more digital bits, wherein the number of decoded signals is equal to two raised to the power of the number of the one or more digital bits; A plurality of inverters, wherein each inverter is configured as: receiving a corresponding decoded signal; as well as generating a corresponding inverted decoding signal; Multiple switches, including: A plurality of switches are configured to receive the corresponding inverted decoded signals; and a plurality of switches configured to receive the corresponding decoded signals; as well as A plurality of resistors are alternately connected in series with the plurality of switches configured to receive the corresponding inverted decoded signals, wherein the plurality of resistors are arranged such that the plurality of resistors divide the voltage range into the plurality of DAC analog signals and the top voltage and the bottom voltage provided to the next DAC stage.

8. The multi-bit parallel SA flash ADC circuit of claim 1, comprising four parallel comparator stages, wherein each parallel comparator stage comprises three comparator circuits, such that the multi-bit parallel SA flash ADC circuit is configured to generate a twelve-bit digital output signal.

9. The multi-bit parallel SA flash ADC circuit of claim 1, comprising two parallel comparator stages, wherein each parallel comparator stage comprises three comparator circuits, such that the multi-bit parallel SA flash ADC circuit is configured to generate a six-bit digital output signal.

10. The multi-bit parallel SA flash ADC circuit of claim 1, integrated into an integrated circuit (IC).

11. The multi-bit parallel SA flash ADC circuit of claim 1 , integrated into a device selected from the group consisting of: Set-top boxes; Entertainment unit; Navigation equipment; Communication equipment; Fixed location data unit; Mobile location data unit; Global Positioning System (GPS) device; Mobile phone; Cellular telephones; smartphones; Session Initiation Protocol (SIP) phones; tablet computers; phablets; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multicopters.

12. A multi-bit parallel successive approximation SA flash analog-to-digital converter ADC circuit, comprising: The device for converting a digital value into an analog value is configured to: receiving a reference voltage; generating a plurality of analog-to-digital converter (DAC) analog signals, wherein each DAC analog signal is based on the reference voltage; Means for generating digital bits, comprising a plurality of means for comparing values ​​in parallel, wherein each means for comparing values ​​in parallel comprises: Several devices were used for comparison, among which: The number of means for comparing in each means for comparing values ​​in parallel is equal to an amount raised to the power of two to the number of digits in the corresponding means for comparing values ​​in parallel minus one; and Each device used for comparison was configured as: receiving an analog input signal; receiving a corresponding DAC analog signal; and Generate a digital signal; If the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the digital signal has a logic low value; the means for generating digital bits being configured to generate one or more digital bits corresponding to each means for performing parallel comparisons of values, wherein the one or more digital bits collectively generate a digital output signal that is a digital representation of the analog input signal, wherein the means for converting the digital value to the analog value comprises a plurality of DAC arrays, each DAC array of the plurality of DAC arrays corresponding to the means for comparing values ​​in parallel and comprising a number of single output means for converting the digital value to the analog value, wherein: the number of single output means of each DAC array for converting said digital value into said analog value is equal to the number of means for comparing in said corresponding means for comparing values ​​in parallel; Each single output device in the DAC array corresponding to the most significant bit of the digital output signal for converting the digital value to the analog value is configured to: receiving a trial bit code comprising a digital bit sequence having values ​​defined for the one or more digital bits corresponding to the digital output signal; and generating a corresponding plurality of DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and a corresponding test bit code; and Each single output device of the plurality of DAC arrays, except the DAC array corresponding to the most significant bit, for converting the digital value into the analog value is configured as: receiving a corresponding trial bit code and one or more of the one or more digital bits generated by the means for performing parallel comparison of values; and The plurality of DAC analog signals are generated, wherein each DAC analog signal is based on the reference voltage, the corresponding test bit code, and corresponding one or more digital bits.

13. The multi-bit parallel SA flash ADC circuit of claim 12, wherein the means for generating digital bits further comprises means for binary conversion configured to: receiving a digital signal from one or more comparator circuits of each of the plurality of parallel comparator stages; and One or more digital bits corresponding to each parallel comparator stage are generated, wherein the one or more digital bits collectively generate the digital output signal, the digital output signal being the digital representation of the analog input signal.

14. The multi-bit parallel SA flash ADC circuit of claim 12, wherein the means for converting the digital value to the analog value comprises a multi-output means for converting the digital value to the analog value, the multi-output means comprising a plurality of DAC stages, wherein: each DAC stage of said plurality of DAC stages corresponds to said means for comparing values ​​in parallel; and Each DAC stage of the plurality of DAC stages is configured as: receiving a corresponding top voltage and a corresponding bottom voltage, wherein voltage ranges of the corresponding top voltage and the corresponding bottom voltage are based on the reference voltage; as well as Based on the corresponding top voltage and the corresponding bottom voltage, a number of DAC analog signals are generated, wherein the number of the DAC analog signals is equal to the number of means for comparing in the corresponding means for comparing values ​​in parallel.

15. The multi-bit parallel SA flash ADC circuit of claim 13, wherein the comparison circuit further comprises a thermometer to binary (TTB) circuit configured to: receiving the digital signal from one or more comparator circuits of each of the plurality of parallel comparator stages; and The one or more digital bits corresponding to each parallel comparator stage are generated, wherein the one or more digital bits collectively generate the digital output signal, the digital output signal being the digital representation of the analog input signal. 16 . The multi-bit parallel SA flash ADC circuit of claim 14 , wherein the several DAC analog signals generated by each of the plurality of DAC stages have values ​​that are divisions of the voltage range.

17. The multi-bit parallel SA flash ADC circuit of claim 14, wherein each of the plurality of DAC stages comprises means for dividing a voltage, the means for dividing a voltage being configured to generate corresponding several DAC analog signals by generating a division of the voltage range.

18. A method for converting an analog input signal into a digital output signal, wherein a plurality of digital bits of the digital output signal are determined in parallel, the method comprising: receiving a reference voltage; generating a plurality of digital-to-analog converter (DAC) analog signals, wherein each DAC analog signal is based on the reference voltage; receiving the analog input signal; One or more digital signals are generated in multiple parallel comparator stages, where: Each digital signal is generated by comparing the analog input signal with a corresponding DAC analog signal; each digital signal has a logic high value if the analog input signal has a greater voltage than the corresponding DAC analog signal; and each digital signal having a logic low value if the analog input signal has a smaller voltage than the corresponding DAC analog signal; and generating one or more digital bits corresponding to each parallel comparator stage based on the one or more digital signals of the corresponding parallel comparator stage, wherein the one or more digital bits collectively generate a digital output signal, the digital output signal being a digital representation of the analog input signal, Wherein the DAC circuit includes a plurality of DAC arrays, the method further includes: receiving a trial bit code comprising a digital bit sequence having values ​​defined for the one or more digital bits corresponding to the digital output signal; and generating a plurality of DAC analog signals corresponding to most significant bits of the digital output signal, wherein each corresponding DAC analog signal is based on the reference voltage and a corresponding test bit code; and Remaining DAC analog signals not corresponding to the most significant bit of the digital output signal are generated, wherein each remaining DAC analog signal is based on the reference voltage, a corresponding trial bit code, and corresponding one or more digital bits.

19. The method according to claim 18, further comprising: receiving a corresponding top voltage and a corresponding bottom voltage, wherein voltage ranges of the corresponding top voltage and the corresponding bottom voltage are based on the reference voltage; as well as Based on the corresponding top voltage and the corresponding bottom voltage, a number of DAC analog signals are generated, wherein the number of the DAC analog signals is equal to the number of digital signals.

20. The method of claim 19, wherein the number of DAC analog signals have values ​​that are divisions of the voltage range.

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