Multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit

Abstract

A multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit is disclosed. In one aspect, the multi-bit parallel SAR ADC circuit includes a plurality of SAR controller circuits, each SAR controller circuit including a SAR register circuit. Each SAR register circuit receives and stores a corresponding digital bit, the digital bit being based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. The DAC circuit receives a reference voltage and generates a plurality of DAC analog signals using the reference voltage and a subset of the digital signals generated by the SAR controller circuit. A comparison circuit generates a digital bit corresponding to each SAR controller circuit, wherein the plurality of digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to application No. 16 / 113,720, filed on August 27, 2018, entitled “MULTIPLE-BIT PARALLEL SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) CIRCUITS,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The disclosed technology relates generally to analog-to-digital converter (ADC) circuits, and particularly to successive approximation register (SAR) ADC circuits. Background Art

[0004] Processor-based systems employ analog-to-digital conversion of signals associated with performing various functions. One method of implementing this analog-to-digital conversion is to use a successive approximation register (SAR) analog-to-digital converter (ADC) circuit. Operation of a SAR ADC circuit involves continuous comparison of an analog input signal with a series of generated analog signals during the conversion process. The SAR ADC circuit uses the result of each comparison of the analog input signal with the series of generated analog signals to generate the final value of the digital signal.

[0005] For example, in a SAR ADC circuit, in order to convert an analog input signal into a digital output signal, during the conversion process, during the first clock cycle of the clock signal, each bit of the digital signal is initially set to a logic low "0" value. While still in the first cycle of the clock signal during the conversion process, the SAR ADC circuit sets the most significant bit of the digital signal to a logic high "1" value, but keeps all the remaining bits of the digital signal at a logic low "0" value. The SAR ADC circuit converts the updated digital signal into a generated analog signal and compares the analog input signal with the generated analog signal. If the voltage of the generated analog signal is greater than the voltage of the analog input signal, the SAR ADC circuit changes the most significant bit from a logic high "1" value to a logic low "0" value. On the contrary, if the voltage of the generated analog signal is less than the voltage of the analog input signal, the SAR ADC circuit keeps the most significant bit set to a logic high "1" value. The SAR ADC circuit sets each bit of the digital signal in this manner one by one in each corresponding cycle of the conversion process and compares the corresponding generated analog signal with the analog input signal. Therefore, after the last cycle of the clock signal during the conversion process, the digital signal generated by the SAR ADC circuit is a digital representation of the analog input signal.

[0006] In this regard, conventional SAR ADC circuits have conversion times that are related to the number of bits of a digital output signal. However, as conventional SAR ADC circuits are designed to generate digital output signals having more bits, the number of circuit elements employed in conventional SAR ADC circuits and the associated conversion times are increased. Therefore, it would be advantageous to reduce or avoid an increase in conversion time as the number of bits in the digital output signal increases. Summary of the invention

[0007] Various aspects disclosed in the specific embodiments include a multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit. In one aspect, the multi-bit parallel SAR ADC circuit generates a digital output signal having N digital bits, wherein the digital output signal is a digital representation of an analog input signal. As a non-limiting example, to perform such conversion, the multi-bit parallel SAR ADC circuit includes M SAR controller circuits. For example, each SAR controller circuit may include one or more SAR register circuits. In response to a corresponding cycle of a clock signal, each SAR controller circuit provides a digital signal for a digital bit of the digital output signal. In response to a corresponding next cycle of the clock signal, each SAR register circuit receives and stores a corresponding digital bit and provides a digital signal associated with the digital bit. The multi-bit parallel SAR ADC circuit also includes a digital-to-analog converter (DAC) circuit that uses a reference voltage and a digital signal from a corresponding SAR controller circuit to generate a plurality of DAC analog signals. In addition, a comparison circuit receives the DAC analog signal and an analog input signal. The comparison circuit generates a digital bit corresponding to each SAR controller circuit, such that the comparison circuit generates M of the N digital bits in parallel. Each digital bit generated during the conversion process collectively forms a digital output signal. In this manner, the digital output signal includes N digital bits, the number of digital bits N being equal to the number of SAR controller circuits M multiplied by the number of SAR register circuits P in each SAR controller circuit (i.e., N=M*P). Generating the digital output signal by generating M digital bits in parallel as described above provides a faster conversion time compared to conventional SAR ADC circuits, even if the number of digital bits in the digital output signal is increased.

[0008] In this regard, on the one hand, a multi-bit parallel SAR ADC circuit is provided. The multi-bit parallel SAR ADC circuit includes a plurality of SAR controller circuits, wherein each of the plurality of SAR controller circuits includes a plurality of SAR register circuits. Each SAR register circuit is configured to receive a clock signal. In response to a corresponding cycle of the clock signal, each SAR register circuit is further configured to provide a digital signal. In response to a corresponding next cycle of the clock signal, each SAR register circuit is further configured to receive a corresponding digital bit, store the digital bit, and provide a digital signal associated with the digital bit, wherein the digital bit is based on a comparison of an analog input signal and a corresponding DAC analog signal. The multi-bit parallel SAR ADC circuit also includes a DAC circuit, which is configured to receive a reference voltage and receive a plurality of digital signals from the plurality of SAR controller circuits, wherein each digital signal corresponds to a digital bit of a digital output signal. The DAC circuit is further configured to generate a plurality of DAC analog signals, wherein each DAC analog signal is based on a reference voltage and a plurality of digital signals. The multi-bit parallel SAR ADC circuit also includes a comparison circuit configured to receive the plurality of DAC analog signals, receive an analog input signal, and generate a digital bit corresponding to each SAR controller circuit in the plurality of SAR controller circuits based on a comparison of each DAC analog signal with the analog input signal. Each digital bit generated collectively forms a digital output signal that is a digital representation of the analog input signal.

[0009] On the other hand, a multi-bit parallel SAR ADC circuit is provided. The multi-bit parallel SAR ADC circuit includes a plurality of devices for successively approximating digital values, wherein each of the plurality of devices for successively approximating digital values ​​includes a plurality of devices for storing digital values. Each device for storing digital values ​​is configured to receive a clock signal and receive a start signal indicating a conversion process. In response to a corresponding cycle of the clock signal, each device for storing digital values ​​is configured to provide a digital signal. In response to a corresponding next cycle of the clock signal, each device for storing digital values ​​is configured to receive a corresponding digital bit, store the digital bit, and provide a digital signal related to the digital bit, wherein the digital bit is based on a comparison of an analog input signal and a corresponding DAC analog signal. The multi-bit SAR ADC circuit also includes a device for converting a digital value into an analog value, the device being configured to receive a reference voltage and receive a plurality of digital signals from a plurality of SAR controllers, wherein each digital signal corresponds to a digital bit of a digital output signal. The device for converting a digital value into an analog value is also configured to generate a plurality of DAC analog signals, wherein each DAC analog signal is based on a reference voltage and a plurality of digital signals. The multi-bit parallel SAR ADC circuit also includes a device for comparing, the device being configured to receive a plurality of DAC analog signals, receive an analog input signal, and generate a digital bit corresponding to each of a plurality of devices for successive approximation of digital values ​​based on a comparison of each DAC analog signal with the analog input signal. Each digital bit generated collectively forms a digital output signal, the digital output signal being a digital representation of the analog input signal.

[0010] On the other hand, a method for converting an analog input signal into a digital output signal is provided, wherein a plurality of digital bits of the digital output signal are generated in parallel. The method includes receiving a clock signal. The method also includes: providing a digital signal in response to a corresponding cycle of the clock signal. The method also includes: receiving a corresponding digital bit in response to a corresponding next cycle of the clock signal, wherein the digital bit is based on a comparison of the analog input signal and a corresponding DAC analog signal. The method also includes, in response to a corresponding next cycle of the clock signal, storing the digital bit. The method also includes: providing a digital signal associated with the digital bit in response to a corresponding next cycle of the clock signal, and receiving a reference voltage. The method also includes generating a plurality of DAC analog signals, wherein each DAC analog signal is based on a reference voltage and a plurality of digital signals. The method also includes generating a corresponding digital bit based on a comparison of each corresponding DAC analog signal with the analog input signal, wherein each generated digital bit together forms a digital output signal, which is a digital representation of the analog input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a circuit diagram of an exemplary multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit configured to convert an analog input signal into a digital output signal, wherein multiple bits of the digital output signal are generated in parallel;

[0012] Figure 2 It shows that it can be Figure 1 A flowchart of an exemplary process performed by a multi-bit parallel SAR ADC circuit to convert an analog input signal into a digital output signal, wherein multiple digital bits of the digital output signal are generated in parallel;

[0013] Figures 3A to 3B A circuit diagram of an exemplary two (2)-bit parallel ten (10)-bit SAR ADC circuit employing a single output digital-to-analog converter (DAC) circuit is shown;

[0014] Figure 4 is Figure 3A and 3B A circuit diagram of an exemplary SAR register circuit employed in a multi-bit parallel SAR ADC circuit;

[0015] Figure 5A and 5B A circuit diagram of an exemplary multi-bit parallel SAR ADC circuit is shown, which uses a multi-output DAC circuit instead of a single output DAC circuit;

[0016] Figure 6 It can be used for Figure 5B a circuit diagram of an exemplary resistor rotator circuit for each stage of a multiple output DAC circuit of;

[0017] Fig. 7A and 7B A circuit diagram of an exemplary multi-bit parallel SAR ADC circuit is shown, employing a multi-output DAC circuit and a successive approximation (SA) flash-based comparison circuit;

[0018] Figure 8 It can be used for Fig. 7A and 7B a circuit diagram of an exemplary resistor rotator circuit for each DAC stage of a multi-output DAC circuit of;

[0019] Fig. 9 is a block diagram of an exemplary processor-based system that may include Figure 1 , 3A to 3B, 5A to 5B, and 7A to 7B; and

[0020] Fig.10is a block diagram of an exemplary wireless communication device including radio frequency (RF) components formed in an integrated circuit (IC), wherein the RF components may include an Figure 1 , 3A Elements of the multi-bit parallel SAR ADC circuits from 5A to 3B, 5A to 5B, and 7A to 7B. DETAILED DESCRIPTION

[0021] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" as used herein means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as being preferred or advantageous over other aspects.

[0022] Various aspects disclosed in the specific embodiments include a multi-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuit. In one aspect, the multi-bit parallel SAR ADC circuit generates a digital output signal having N digital bits, wherein the digital output signal is a digital representation of an analog input signal. As a non-limiting example, to perform such conversion, the multi-bit parallel SAR ADC circuit includes M SAR controller circuits. For example, each SAR controller circuit may include one or more SAR register circuits. In response to a corresponding cycle of a clock signal, each SAR controller circuit provides a digital signal for a digital bit of the digital output signal. In response to a corresponding next cycle of the clock signal, each SAR register circuit receives and stores a corresponding digital bit and provides a digital signal associated with the digital bit. The multi-bit parallel SAR ADC circuit also includes a digital-to-analog converter (DAC) circuit that uses a reference voltage and a digital signal from a corresponding SAR controller circuit to generate a plurality of DAC analog signals. In addition, a comparison circuit receives the DAC analog signal and an analog input signal. The comparison circuit generates a digital bit corresponding to each SAR controller circuit, such that the comparison circuit generates M of the N digital bits in parallel. Each digital bit generated during the conversion process collectively forms a digital output signal. In this manner, the digital output signal includes N digital bits, the number of digital bits N being equal to the number of SAR controller circuits M multiplied by the number of SAR register circuits P in each SAR controller circuit (i.e., N=M*P). Generating the digital output signal by generating M digital bits in parallel as described above provides a faster conversion time compared to conventional SAR ADC circuits, even if the number of digital bits in the digital output signal is increased.

[0023] At this point, Figure 1An exemplary multi-bit parallel SAR ADC circuit 100 is shown that is configured to convert an analog input signal VIN into a digital output signal DOUT, wherein M digital bits DG(N)-DG(1) of the digital output signal DOUT are generated in parallel. In various aspects described herein, the digital bit DG(N) (e.g., the highest numbered digital bit DG) is the most significant bit (MSB) of the digital output signal DOUT, and the digital bit DG(1) (e.g., the lowest numbered digital bit DG) is the least significant bit (LSB) of the digital output signal DOUT. To perform this conversion, the multi-bit parallel SAR ADC circuit 100 includes M SAR controller circuits 102(1)-102(M). In this non-limiting example, each of the SAR controller circuits 102(1)-102(M) includes P SAR register circuits 104(1)(1)-104(M)(P), but this is not required. The SAR register circuit can be any type of circuit capable of generating a digital signal corresponding to a received digital bit. SAR register circuits 104(1)(P)-104(1)(1) are in SAR controller circuit 102(1). SAR register circuits 104(M-1)(P)-104(M-1)(1) are in SAR controller circuit 102(M-1). SAR register circuits 104(M)(P)-104(M)(1) are in SAR controller circuit 102(M). Each of SAR register circuits 104(1)(1)-104(M)(P) is configured to receive a clock signal CLK. In response to a corresponding cycle of clock signal CLK, each SAR register circuit 104(1)(1)-104(M)(P) provides a digital signal 106(1)(1)-106(M)(P). In response to a corresponding next cycle of the clock signal CLK, each SAR register circuit 104(1)(1)-104(M)(P) receives and stores a digital bit DG(1)-DG(N) corresponding to the SAR controller circuit 102(1)-102(M) based on a comparison of the analog input signal VIN and the corresponding DAC analog signal 108(1)-108(A). In the above next cycle, each SAR register circuit 104(1)(1)-104(M)(P) also provides a digital signal 106(1)(1)-106(M)(P) related to the digital bit DG(1)-DG(N).

[0024] Continue to refer Figure 1The multi-bit parallel SAR ADC circuit 100 includes a DAC circuit 110 that receives a reference voltage VREF and digital signals 106(1)(1)-106(M)(P). As will be discussed in more detail below by way of example, the DAC circuit 110 generates a plurality of DAC analog signals 108(1)-108(A) based on the reference voltage VREF and the digital signals 106(1)(1)-106(M)(P) and a control signal CONTROL. The SAR register circuits 104(1)(1)-104(M)(P) of the SAR controller circuits 102(1), 102(2) generate the control signal CONTROL that communicates timing information to the DAC circuit 110, which is used to pass the specified digital signals 106(1)(5)-106(1)(1), 106(2)(5)-106(2)(1) from the SAR controller circuits 102(1), 102(2) to the comparison circuit 112. The control signal CONTROL SEL may be generated by another controller that controls the timing. Additionally, the comparison circuit 112 receives the DAC analog signals 108(1)-108(A) and the analog input signal VIN. Using the DAC analog signals 108(1)-108(A) and the analog input signal VIN, the comparison circuit 112 generates digital bits DG(1)-DG(M) corresponding to each SAR controller circuit 102(1)-102(M), such that the comparison circuit 112 generates M of the N digital bits DG(1)-DG(N) at each cycle of the clock signal CLK (i.e., in parallel), and the M of the N digital bits DG(1)-DG(N) are stored in the corresponding SAR register circuit 104(1)(1)-104(M)(P) during the conversion process. Each of the generated digital bits DG(1)-DG(N) collectively forms a digital output signal DOUT, which is a digital representation of the analog input signal VIN. In this manner, the digital output signal DOUT includes N digital bits DG(1)-DG(N), where the number N of digital bits DG(1)-DG(N) is equal to the number M of SAR controller circuits 102(1)-102(M) multiplied by the number P of bits stored in the SAR register circuits 104(1)(1)-104(M)(P) in each SAR controller circuit 102(1)-102(M) (i.e., N=M*P). As used herein, the numbers M, N, and P are positive integers. Generating the digital output signal DOUT by generating the M digital bits DG(1)-DG(N) in parallel as described above provides a faster conversion time compared to conventional SAR ADC circuits, even if the number of digital bits DG(1)-DG(N) in the digital output signal DOUT is increased.

[0025] Figure 2 It shows that it can be Figure 1 An example process 200 is provided for performing a multi-bit parallel SAR ADC circuit 100 to convert an analog input signal VIN into a digital output signal DOUT, wherein a plurality of M digital bits DG(1)-DG(M) (i.e., DG(1)-DG(N)) of an N-bit width digital output signal DOUT are generated in parallel. The process 200 includes each SAR register circuit 104(1)(1)-104(M)(P) receiving a clock signal CLK (block 202). Additionally, the process 200 includes each SAR register circuit 104(1)(1)-104(M)(P) providing a digital signal 106(1)(1)-106(M)(P) in response to a corresponding cycle of the clock signal CLK (block 204). Process 200 also includes each SAR register circuit 104(1)(1)-104(M)(P) receiving a corresponding digital bit DG(1)-DG(M) in response to a corresponding next cycle of the clock signal CLK, wherein the digital bit DG(1)-DG(M) is based on a comparison of the analog input signal VIN and the corresponding DAC analog signal 108(1)-108(A) (where A=2 M -1) (block 206). Process 200 also includes each SAR register circuit 104(1)(1)-104(M)(P) storing the digital bit DG(1)-DG(M) in response to a corresponding next cycle of the clock signal CLK (block 208). Process 200 also includes each SAR register circuit 104(1)(1)-104(M)(P) providing a digital signal 106(1)(1)-106(M)(P) related to the digital bit DG(1)-DG(M) in response to a corresponding next cycle of the clock signal CLK (block 210). In addition, process 200 includes the DAC circuit 110 receiving a reference voltage VREF (block 212). In addition, the process 200 includes the DAC circuit 110 generating a plurality of DAC analog signals 108(1)-108(A), wherein each DAC analog signal 108(1)-108(A) is based on a reference voltage VREF and a plurality of digital signals 106(1)(1)-106(M)(P) and a plurality of control signals CONTROL (block 214). The process 200 also includes the comparison circuit 112 generating a digital bit DG(1)-DG(M) corresponding to each SAR controller circuit 102(1)-102(M) based on a comparison of each DAC analog signal 108(1)-108(A) with an analog input signal VIN (block 216). In this manner, each digital bit DG(1)-DG(M) generated collectively forms a digital output signal DOUT(DG(1)-DG(N)), which is a digital representation of the analog input signal VIN.

[0026] Details of specific aspects of the multi-bit parallel SAR ADC circuit 100 are now described. In this regard, Figure 3A and 3B An exemplary two (2)-bit parallel ten (10)-bit SAR ADC circuit 300 is shown, which is configured to convert an analog input signal VIN into a digital output signal DOUT having ten (10) digital bits DG(10)-DG(1), wherein the DAC circuit 110 employs single output DAC circuits 302(1)-302(3). As shown below in Figure 5A and 5B As discussed in the beginning, other aspects of the multi-bit parallel SAR ADC circuit 100 disclosed herein may employ multiple output DAC circuits instead of single output DAC circuits 302(1)-302(3). The two (2)-bit parallel ten (10)-bit SAR ADC circuit 300 includes Figure 1 The common components of the multi-bit parallel SAR ADC circuit 100 are shown in FIG. Figure 1 as well as Figure 3A and 3B Common component numbers are used in the figure and therefore they are not repeated in this article.

[0027] refer to Figure 3A and 3B, the two (2)-bit parallel ten (10)-bit SAR ADC circuit 300 employs SAR controller circuits 102(1), 102(2), thereby allowing two (2) digital bits DG(1)-DG(10) of the digital output signal DOUT to be generated in parallel. Each SAR controller circuit 102(1), 102(2) employs five (5) SAR register circuits 104(1)(1)-104(2)(5), so that the conversion process can generate ten (10) digital bits DG(1)-DG(10) of the digital output signal DOUT in five (5) cycles of the clock signal CLK. In particular, the SAR register circuits 104(1)(5)-104(1)(1) of the SAR controller circuit 102(1) are configured to receive and store the corresponding digital bits DG(9), DG(7), DG(5), DG(3) and DG(1). Digital bit DG(9) is generated in a first clock cycle, then digital bit DG(7) is generated in a subsequent clock cycle, and so on, until digital bit DG(1) is finally generated. SAR register circuits 104(1)(5)-104(1)(1) are also configured to provide corresponding corresponding digital signals 106(1)(5)-106(1)(1) in multiple clock cycles. In particular, digital signals 106(1)(5)-106(1)(1) are generated in different clock cycles of clock signal CLK based on corresponding digital bits DG(9), DG(7), DG(5), DG(3), and DG(1) generated in corresponding clock cycles of clock signal CLK. For example, digital signal 106(1)(5) is generated for digital bit DG(9) in a first clock cycle, digital signal 106(1)(5) is generated for digital bit DG(7) in a subsequent clock cycle, and so on.

[0028] Continue to refer Figure 3A and 3BSAR register circuits 104(2)(1)-104(2)(5) of SAR controller circuit 102(2) are configured to receive and store corresponding digital bits DG(2), DG(4), DG(6), DG(8), and DG(10). SAR register circuits 104(2)(5)-104(2)(1) of SAR controller circuit 102(2) are configured to receive and store corresponding digital bits DG(10), DG(8), DG(6), DG(4), and DG(2). Digital bit DG(10) is generated in a first clock cycle, digital bit DG(8) is generated in a subsequent clock cycle, and so on, until digital bit DG(2) is finally generated. SAR register circuits 104(2)(5)-104(2)(1) are also configured to provide corresponding corresponding digital signals 106(2)(5)-106(2)(1) over multiple clock cycles. In particular, digital signals 106(2)(5)-106(2)(1) are generated in different clock cycles of clock signal CLK based on corresponding digital bits DG(10), DG(8), DG(6), DG(4), and DG(2) generated in corresponding clock cycles of clock signal CLK. For example, digital signal 106(2)(5) is generated for digital bit DG(10) in a first clock cycle, digital signal 106(2)(4) is generated for digital bit DG(8) in a subsequent clock cycle, and so on. Furthermore, as described in more detail below, in addition to receiving clock signal CLK and corresponding digital bits DG(1)-DG(10), each SAR register circuit 104(1)(1)-104(2)(5) is also configured to receive a select signal SEL. The select signal SEL is a signal used by the 2-bit parallel 10-bit SAR ADC circuit 300 to generate the test signals TRIAL(5)-TRIAL(1), which transmit timing information between the SAR controller circuits 102(1), 102(2) and the DAC circuit 110, which is used to pass the specified digital signals 106(1)(5)-106(1)(1), 106(2)(5)-106(2)(1) from the SAR controller circuits 102(1), 102(2) to the TTB circuit 314. The select signal SEL can be generated by another controller that controls the timing. The START signal starts the conversion process. In this regard, when the START signal is high, each SAR register circuit 104(1)(5)-104(2)(1) is reset. When the START signal goes low, then at the next rising edge of the clock signal CLK, the conversion process begins. Furthermore, the 2-bit parallel 10-bit SAR ADC circuit 300 further includes a SAR register circuit 303 configured to generate a completion signal DONE indicating that the conversion process is completed.

[0029] Continue to refer Figures 3A to 3B As described above, in this aspect, the DAC circuit 110 employs single output DAC circuits 302(1)-302(3). In particular, the number A of single output DAC circuits 302(1)-302(3) (i.e., three (3)) is equal to the number M of SAR controller circuits 102(1), 102(2) raised to the power of two (2) (e.g., two (2)) minus one (1) (i.e., A=(2^M)-1=(2^2)-1=3). Each single output DAC circuit 302(1)-302(3) is configured to generate a corresponding DAC analog signal 108(1)-108(3) based on a reference voltage VREF, digital bits DG(1)-DG(10), and corresponding test bit codes 304(1)-304(10). More specifically, each trial bit code 304 ( 1 )- 304 ( 10 ) includes a digital bit sequence having values ​​for a subset of digital bits DG( 1 )-DG( 10 ) corresponding to the digital output signal D OUT .

[0030] Continue to refer Figures 3A to 3B To generate the test bit codes 304(1)-304(10), the DAC circuit 110 includes a test bit circuit 306 configured to receive the digital signals 106(1)(1)-106(2)(5) and the test signals TRIAL(1)-TRIAL(5) from each corresponding SAR register circuit 104(1)(1)-104(2)(5), and to generate the test bit codes 304(1)-304(10) based on such values. For example, in this aspect, the test bit circuit 306 includes AND-based gates 308(1)-308(10) (e.g., AND gates 308(1)-308(10)). AND gates 308(1)-308(5) are configured to receive digital signals 106(1)(1)-106(1)(5) and test signals TRIAL(1)-TRIAL(5) respectively, and generate corresponding test bit codes 304(1)-304(5). Additionally, AND gates 308(6)-308(10) are configured to receive digital signals 106(2)(1)-106(2)(5) and test signals TRIAL(1)-TRIAL(5) respectively, and generate corresponding test bit codes 304(6)-304(10).

[0031] Continue to refer Figure 3A-3B, the single output DAC circuit 302(3) receives the digital signals 106(1)(1)-106(2)(5) and the reference voltage VREF, and generates the DAC analog signal 108(3) based on such values. In addition, the single output DAC circuit 302(2) receives the digital signals 106(1)(1)-106(1)(5) and the test bit codes 304(1)-304(5), and generates the DAC analog signal 108(2) based on such values. In addition, the single output DAC circuit 302(1) receives the digital signals 106(2)(1)-106(2)(5) and the test bit codes 304(6)-304(10), and generates the DAC analog signal 108(1) based on such values.

[0032] Continue to refer Figure 3A and 3B In this aspect, the comparison circuit 112 includes comparison circuits 310(1)-310(3). In particular, the number B of the comparison circuits 310(1)-310(3) (i.e., three (3)) is equal to the number A of the SAR controller circuits 102(1), 102(2) (e.g., two (2)) raised to the power of two (2) minus one (1) (i.e., B=(2^A)-1=(2^2)-1=3). Each comparison circuit 310(1)-310(3) is configured to receive an analog input signal VIN and a corresponding DAC analog signal 108(1)-108(3), and generate a corresponding comparator signal 312(1)-312(3). More specifically, if the analog input signal VIN has a voltage of a greater value than the corresponding DAC analog signal 108(1)-108(3), each corresponding comparator signal 312(1)-312(3) has a logic high "1" value. Alternatively, if the analog input signal VIN has a smaller voltage than the corresponding DAC analog signal 108(1)-108(3), each corresponding comparator signal 312(1)-312(3) has a logic low "0" value.

[0033] Continue to refer Figure 3A and 3B In this aspect, the comparison circuit 112 also includes a thermometer to binary (TTB) circuit 314 ( Figure 3B), the TTB circuit 314 is configured to receive the comparator signals 312(1)-312(3) from each comparison circuit 310(1)-310(3) and generate two digital bits in DOUT(DG(1)-DG(N)), shown as digital bits DG(X-1)-DG(X) corresponding to each SAR controller circuit 102(1), 102(2). For example, in the first clock cycle of the clock signal CLK, the TTB circuit 314 generates DG(9) and DG(8) in the digital signals 106(1)(5), 106(2)(5). For example, in this aspect, the TTB circuit 314 employs inverters 316(1), 316(2), AND-based gates 318(1), 318(2) (e.g., AND gates 318(1), 318(2)), and OR-based gates 320(1), 320(2) (e.g., OR gates 320(1), 320(2)). The comparator signal 312(3) is provided to the inverter 316(1) so that the inverter 316(1) generates an inverted comparator signal 312'(3) that is provided to the AND gates 318(1), 318(2). Additionally, the comparator signal 312(2) is provided to the AND gate 318(1). In this example, if the comparator signal 312(1) has a logic low "0" value and the AND comparator signal 312(2) has a logic high "1" value, the AND gate 318(1) generates an intermediate comparator signal 322(1) having a logic high "1" value. The intermediate comparator signal 322(1) is provided to the inverter 316(2), wherein the inverter 316(2) generates an inverted intermediate comparator signal 322'(1) which is provided to the AND gate 318(2). The inverted intermediate comparator signal 322'(1) is also provided to the AND gate 318(2), wherein if the comparator signals 312(1), 312(2) each have a logic low "0" value and the comparator signal 312(3) has a logic high "1" value, then the AND gate 318(2) generates the intermediate comparator signal 322(2) having a logic high "1" value, otherwise the AND gate 318(2) generates the intermediate comparator signal 322(2) having a logic low "0" value. Therefore, the possibilities of DAC analog signals 108(1)-108(3) are "000", "001", "011" or "111" because the manner in which DAC analog signals 108(1)-108(3) are generated by DAC circuits 302(1)-302(3) is based on the following thresholds in digital signals 106(1)(5)-106(2)(1) to generate thermometer codes: the input VIN is greater than the threshold.In this regard, for the digital signals 108(1)-108(3), the TTB circuit 314 generates "00" for the digital bits DG(X), DG(X-1) for the DAC analog signals 108(1)-108(3) being "000", "01" for the digital bits DG(X), DG(X-1) for the DAC analog signals 108(1)-108(3), "10" for the digital bits DG(X), DG(X-1) for the DAC analog signals 108(1)-108(3), and "11" for the digital bits DG(X), DG(X-1) for the DAC analog signals 108(1)-108(3). The comparator signal 312(3) and the intermediate comparator signal 322(1) are provided to the OR gate 320(1), where the OR gate 320(1) generates the digital bits DG(X). Additionally, comparator signal 312(3) and intermediate comparator signal 322(2) are provided to OR gate 320(2), where OR gate 320(2) generates digital bit DG(X-1). As discussed in more detail below, other aspects may employ comparison circuit 112 that includes a successive approximation (SA) flash-based comparator, where these aspects do not include TTB circuit 314.

[0034] Continue to refer Figure 3A and 3B, a non-limiting example will now be described. In this manner, the analog input signal VIN is approximately equal to 1.666478 volts (V) and the reference voltage VREF is equal to five (5) V. In a first cycle of the clock signal CLK, the SAR register circuits 104(1)(5), 104(2)(5) corresponding to the digital bits DG(9), DG(10) respectively provide signals of a logic high "1" value (e.g., which may be derived from the power supply voltage VDD), while the SAR register circuits 104(1)(1)-104(1)(4) and 104(2)(1)-104(2)(4) corresponding to the digital bits DG(1)-DG(8) each provide a logic low "0" value. As a result, the inputs of the single output DAC circuit 302(3) corresponding to the digital bits DG(10), DG(9) are signals of a logic high "1" value, while the inputs corresponding to the digital bits DG(8)-DG(1) receive a logic low "0" value. Similarly, during the first cycle of the clock signal CLK, the test bits TRIAL(5)-TRIAL(1) are provided by the inverters 324(5)-324(1) such that the test bits TRIAL(5) have a logic low "0" value, while the test bits TRIAL(4)-TRIAL(1) have a logic high "1" value. As a result, the input of the single output DAC circuit 302(2) receives a signal indicating a digital value of "1000000000". The input of the single output DAC circuit 302(3) receives a signal indicating a digital value of "0100000000". The input of the single output DAC 302(1) receives a signal indicating a digital value of "1100000000". For example, the inputs of the single output DAC circuits 302(1)-302(3) produce DAC outputs of 3.75 V, 2.5 V, and 1.25 V, respectively, as the DAC analog signals 108(1)-108(3).

[0035] Continue to refer Figure 3A and 3B , the single output DAC circuits 302(1)-302(3) generate corresponding DAC analog signals 108(1)-108(3), and the comparison circuit 112 generates a digital bit DG(10) having a logic low "0" value and a digital bit DG(9) having a logic high "1" value. In response to the next cycle of the clock signal CLK (e.g., the second cycle), the digital bits DG(9) and DG(10) are received and stored by the SAR register circuits 104(1)(5) and 104(2)(5), and the SAR register circuits 104(1)(5) and 104(2)(5) now provide stored values ​​for the digital signals 106(1)(5) and 106(2)(5). Similarly, in response to the second cycle of the clock signal CLK, the digital bits DG(7) and DG(8) (see Figure 3A) corresponding to the SAR register circuits 104(1)(4), 104(2)(4) respectively provide signals of a logic "1" high value, while the SAR register circuits 104(1)(5), 104(1)(3)-104(1)(1) and 104(2)(5), 104(2)(3)-104(2)(1) corresponding to the digital bits DG(10), DG(9) and DG(6)-DG(1) respectively provide signals of a logic low "0" value. The test bits TRIAL(1)-TRIAL(5) and the DAC analog signals 108(1)-108(3) change accordingly, so that the comparison circuit 112 generates a digital bit DG(8) having a logic low "0" value and a digital bit DG(7) having a logic high "1" value. In response to the next cycle (e.g., the third cycle) of the clock signal CLK, the SAR register circuits 104(2)(4), 104(1)(4) store the digital bits DG(8), DG(7), and the conversion process continues for the remaining digital bits DG(6)-DG(1). At the end of the fifth cycle of the clock signal CLK, the two(2)-bit parallel ten(10)-bit SAR ADC circuit 300 has generated and stored a digital output signal DOUT having digital bits DG(10)-DG(1) with a value of "0101010100". In this regard, the two (2)-bit parallel ten (10)-bit SAR ADC circuit 300 generates the digital output signal DOUT in five (5) cycles of the clock signal CLK using two digital bits DG(X), DG(X-1) of the digital output signal DOUT generated in each clock cycle of the clock signal CLK, instead of generating the digital output signal DOUT in ten (10) cycles as required by a conventional single-bit SAR ADC circuit.

[0036] Figure 4 An exemplary SAR register circuit 400 is shown, which may be used Figure 3A-3B In the 2-bit parallel 10-bit SAR ADC circuit 300 for each register circuit in the SAR register circuits 104(1)(1)-104(2)(5), to implement the above reference Figure 3A-3BThe functionality of the example. In this aspect, the SAR register circuit 400 includes a multiplexer circuit 402, a D flip-flop latch 404, AND gates 406(1), 406(2), an inverter 408, and a NAND latch 410. The SAR register circuit 400 also includes an input node D0 configured to receive a voltage of a logic "1" high value, and an input node D1 configured to receive a corresponding digital bit DG(X). In addition, the SAR register circuit 400 includes a start input node RB configured to receive a start signal START, a selection input node SEL, a selection output node SX, a hold input node HLD, a hold output node HX, a clock input node CLK_IN, and an output node Q.

[0037] Continue to refer Figure 4 , the multiplexer circuit 402 includes input nodes 412(1), 412(2) electrically coupled to input nodes D0, D1, respectively. The multiplexer circuit 402 also includes a select input 414 electrically coupled to a select input node SEL of the SAR register circuit 400. An output node 416 is electrically coupled to an input node 418 of the D flip-flop latch 404. In addition, the D flip-flop latch 404 includes a clock input node 420 electrically coupled to an output node 422 of the AND gate 406(1), a ready input node 424 electrically coupled to a start input node RB, and an output node 426 electrically coupled to an output node Q. An input node 428 of the inverter 408 is electrically coupled to a hold input node HLD, and an output node 430 of the inverter 408 is electrically coupled to an input node 432(1) of the NAND latch 410. An input node 432(2) of the NAND latch 410 is electrically coupled to the start input node RB. Input node 434(1) of AND gate 406(1) is electrically coupled to inverting output node 436 of NAND latch 410, and input node 434(2) of AND gate 406(1) is electrically coupled to clock input node CLK_IN. Input nodes 438(1)-438(3) of AND gate 406(2) are electrically coupled to input node D0, inverting output node 436, and inverting output node 440 of D flip-flop latch 404, and output node 442 of AND gate 406(2) is electrically coupled to holding output node HX.

[0038] As mentioned above, Figure 1 The DAC circuit 110 in the multi-bit parallel SAR ADC circuit 100 can use a multi-output DAC circuit to reduce the total area consumption. In this regard, Figure 5A and 5BAn exemplary multi-bit parallel SAR ADC circuit 500 is shown, wherein the DAC circuit 110 includes a multi-output DAC circuit 502. The multi-bit parallel SAR ADC circuit 500 may also be referred to as a two (2)-bit parallel ten (10)-bit SAR ADC circuit 500. The multi-bit parallel SAR ADC circuit 500 includes Figure 1 and 3A 3B to 3B of the corresponding multi-bit parallel SAR ADC circuit 100, 300, these common elements in Figure 1 , 3A 3B and 5A to 5B are denoted by common element numbers and therefore are not repeated herein.

[0039] Continue to refer Figure 5B , the multi-output DAC circuit 502 includes DAC stages 504(1)-504(4), switches 506(1)-506(10), and a voltage divider circuit 508 using resistors 510(1)-510(4). Additionally, in this aspect, the SAR controller circuit 102(2) is configured to provide enable signals 512(1)-512(5) and DAC select signals 514(1)-514(5) corresponding to each SAR register circuit 104(2)(1)-104(2)(5). Figure 4 The LCK signal in SAR register circuit 400 is derived from the output Q of NAND latch 410, and the LCK signal is coupled to latch enable signals 512(1)-512(5). In particular, enable signals 512(1)-512(5), each of which is generated by SAR register circuits 104(2)(1)-104(2)(5). Figure 5A The OR gate 516 in the embodiment performs a logic OR operation on the enable signal 512(5) to obtain the DAC select signal 514(5), which controls the DAC select signal 514(5). Figure 5B1-104) to provide an impedance / resistance between a terminal at voltage VREF and a ground input of the multi-output DAC circuit 502 that remains substantially constant regardless of the state of the control signal. When the enable signal 512(1)-514(4) to a given DAC stage 504(1)-504(4) is a logic "0" value, then that DAC stage 504(1)-504(4) presents an open circuit between its VTOP(1)-VTOP(4) and VBOT(1)-VBOT(4) terminals. The DAC select signals 514(1)-514(4) correspond to the value of each select input node SEL provided to each corresponding SAR register circuit 104(2)(1)-104(2)(4), and the DAC select signal 514(5) is provided as the output of an OR gate 516 that receives the enable signal 512(5) and the select signal SEL provided to the SAR register circuit 104(2)(5).

[0040] Continue to refer Figure 5A and 5B , each DAC stage 504(1)-504(4) is configured to receive a corresponding top voltage VTOP(1)-VTOP(4), a corresponding bottom voltage VBOT(1)-VBOT(4), and a corresponding digital bit DG(1)-DG(10). The load of the subsequent stages determines what voltage will appear at each of the top voltages VTOP(1)-VTOP(4) and the corresponding bottom voltage VBOT(1)-VBOT(4). Each DAC stage 504(1)-504(4) is also configured to generate a corresponding top output voltage VTO(1)-VTO(4) and a bottom output voltage VBO(1)-VBO(4) by dividing the voltage range of each corresponding top voltage VTOP(1)-VTOP(4) and each bottom voltage VBOT(1)-VBOT(4) based on the value of the digital bit DG(1)-DG(10). For example, the DAC stage 504(1) is configured to receive a reference voltage VREF as a top voltage VTOP(1), a ground signal as a bottom voltage VBOT(1), and digital bits DG(10), DG(9). The top output voltage VTO(1) and the bottom output voltage VBO(1) of the DAC stage 504(1) are generated by dividing a voltage range between the reference voltage VREF and the ground signal based on the values ​​of the digital bits DG(10), DG(9).

[0041] Continue to refer Figure 5A and 5B, the top output voltage VTO(1) and the bottom output voltage VBO(1) are provided to the DAC stage 504(2) as the top voltage VTOP(2) and the bottom voltage VBOT(2), respectively. The DAC stage 504(2) is also configured to receive the digital bits DG(8) and DG(7). Therefore, the top output voltage VTO(2) and the bottom output voltage VBO(2) of the DAC stage 504(2) are generated by dividing the voltage range between the top output voltage VTO(1) and the bottom output voltage VBO(1) based on the values ​​of the digital bits DG(8) and DG(7). In addition, the top output voltage VTO(2) and the bottom output voltage VBO(2) are provided to the DAC stage 504(3) as the top voltage VTOP(3) and the bottom voltage VBOT(3), respectively. The DAC stage 504(3) is also configured to receive the digital bits DG(6) and DG(5). Therefore, the top output voltage VTO(3) and the bottom output voltage VBO(3) of the DAC stage 504(3) are generated by dividing the voltage range between the top output voltage VTO(2) and the bottom output voltage VBO(2) based on the values ​​of the digital bits DG(6) and DG(5). In addition, the top output voltage VTO(3) and the bottom output voltage VBO(3) are provided to the DAC stage 504(4) as the top voltage VTOP(4) and the bottom voltage VBOT(4), respectively. The DAC stage 504(4) is also configured to receive the digital bits DG(4) and DG(3). Therefore, the top output voltage VTO(4) and the bottom output voltage VBOT(4) of the DAC stage 504(4) are generated by dividing the voltage range between the top output voltage VTO(3) and the bottom output voltage VBO(3) based on the values ​​of the digital bits DG(4) and DG(3).

[0042] Continue to refer Figure 5A and 5B, DAC select signals 514(1)-514(5) are provided to switches 506(1)-506(5) and 506(6)-506(10), respectively. Based on the values ​​of DAC select signals 514(1)-514(5), some combination of reference voltage VREF and top output voltages VTO(1)-VTO(4) are provided to input node 518(1) of voltage divider circuit 508. Additionally, based on the values ​​of DAC select signals 514(1)-514(5) that activate some combination of switches 506(6)-506(10), some combination of ground signal and bottom output voltages VBO(1)-VBO(4) are provided to input node 518(2) of voltage divider circuit 508. In this regard, resistors 510(1)-510(4) each have approximately equal resistance (e.g., two (2) kilo-ohms (kΩ)) such that voltage divider circuit 508 generates DAC analog signals 108(1)-108(3) as approximately equal components (e.g., components corresponding to a voltage range) of a voltage provided to voltage divider circuit 508. Voltage divider 508 may be connected directly between terminals of voltages VTOP(1) and VBOT(1) or between any pair of terminals of voltages VTOP(1)-VTOP(4) and VBOT(1)-VBOT(4).

[0043] DAC analog signals 108(1)-108(3) are used by comparison circuit 112 to generate a digital output signal DOUT having digital bits DG(1)-DG(10) in five (5) cycles of clock signal CLK, similar to reference signal DOUT. Figure 3A and 3B For example, Figure 5B The comparison circuit 112 and Figure 3B Common components between comparison circuits in the use common component numbers, which will not be described again.

[0044] As follows Fig. 7A and 7B As discussed initially, other aspects may include a successive approximation (SA) flash-based comparison circuit, rather than the comparison circuit 112 described herein. Employing a multi-output DAC circuit 502 allows the multi-bit parallel SAR ADC circuit 500 to generate the digital output signal DOUT in five (5) cycles of the clock signal CLK, rather than ten (10) cycles as required by a conventional single-bit SAR ADC circuit, but with less area consumption than the multi-bit parallel SAR ADC circuit 300. Figure 6 An exemplary resistor rotator circuit 600 is shown, which can be used in Figures 5A to 5BThe resistor rotator circuit 600 is configured to receive a top voltage VTOP at a top voltage input node TOP and a bottom voltage VBOT at a bottom voltage input node BOT. The resistor rotator circuit 600 also includes a decoder circuit 602 configured to receive a top voltage VTOP at a top voltage input node TOP and a bottom voltage VBOT at a bottom voltage input node BOT. Figures 5A to 5B DAC stages 504(1)-504(4) described in the foregoing receive digital bits DG(X), DG(X-1) at their corresponding input nodes S1, S0, and generate decoded signals DS(1)-DS(4) based on the digital bits DG(X), DG(X-1). In this aspect, decoder circuit 602 is a one-hot decoder, wherein only one of the decoded signals DS(1)-DS(4) has a logic high "1" value. For example, decoded signals DS(1)-DS(4) are generated according to the following logic functions: DS(1)=(inverted DG(X)AND inverted DG(X-1)); DS(2)=(inverted DG(X)AND DG(X-1)); DS(3)=(DG(X)AND inverted DG(X-1)); DS(4)=(DG(X)AND DG(X-1)). Each decoded signal DS(1)-DS(4) is provided to a corresponding AND gate 606(1)-606(4). Each AND gate 606(1)-606(4) also receives an AND signal via an enable input node EN. Figure 5A-5B 4 and generates corresponding resistor select signals 608(1)-608(4).

[0045] Continue to refer Figure 6, resistor rotator circuit 600 also includes switches 610(1)-610(8), wherein a logic high "1" value closes switches 610(1)-610(8) and a logic low "0" value opens switches 610(1)-610(8). Switches 610(1)-610(8) are used in conjunction with resistors 612(1)-612(6) to generate top output voltages VTO(1)-VTO(4) and bottom output voltages VBO(1)-VBO(4) at respective voltage output nodes RA, RB of corresponding DAC stages 504(1)-504(4). The voltage divider 508 in FIG. 5 is connected across any of the terminals of VTOP(1)-VTOP(4), VBOT(1)-VBOT(4), and RADJ in parallel with the total resistance of the voltage divider 508 produces an effective resistance equal to each of the resistors 612(1)-612(6) to provide an ideal resistance to the terminals for VTOP(1)-VTOP(4), VBOT(1)-VBOT(4). In particular, the resistor 612(1) includes a first node 614(1)(1) electrically coupled to the switch 610(1) and a second node 614(1)(2) electrically coupled to the switch 610(2). The resistor 612(2) includes a first node 614(2)(1) electrically coupled to the switch 610(2) and a second node 614(2)(2) electrically coupled to the switch 610(3). Resistor 612(3) includes a first node 614(3)(1) electrically coupled to switch 610(3) and a second node 614(3)(2) electrically coupled to switch 610(4). In addition, resistor 612(4) includes a first node 614(4)(1) electrically coupled to switch 610(5) and a second node 614(4)(2) electrically coupled to switch 610(6). Resistor 612(5) includes a first node 614(5)(1) electrically coupled to switch 610(6) and a second node 614(5)(2) electrically coupled to switch 610(7). Resistor 612(6) includes a first node 614(6)(1) electrically coupled to switch 610(7) and a second node 614(6)(2) electrically coupled to switch 610(8).

[0046] Continue to refer Figure 6, switches 610(1), 610(5) are configured to receive resistor selection signal 608(1), and switches 610(2), 610(6) are configured to receive resistor selection signal 608(2). In addition, switches 610(3), 610(7) are configured to receive resistor selection signal 608(3), and switches 610(4), 610(8) are configured to receive resistor selection signal 608(4). A resistor RADJ is also included, wherein a first node 616(1) is electrically coupled to a top voltage output node RA, and a second node 616(2) is electrically coupled to a bottom voltage output node RB. The resistance of resistor RADJ is adjusted so that the parallel combination of resistor RADJ and the desired resistance R_NEXT of the next DAC stage 504 is maintained at a desired constant value so that the resistor rotator circuit 600 generates a desired output, and the desired constant value is equal to the other resistors 612(1)-612(6). In this way, the above configuration causes the resistor rotator circuit 600 to generate corresponding top output voltages VTO(1)-VTO(4) and bottom output voltages VBO(1)-VBO(4) based on the digital bits DG(X), DG(X-1), depending on which switches 610(1)-610(8) are opened or closed.

[0047] As mentioned above, Figure 1 Aspects of the multi-bit parallel SAR ADC circuit 100 may include a comparison circuit 112 that employs a SA flash memory based comparison circuit, thereby eliminating the need for Figures 3A to 3B In this regard, Fig. 7A and 7B An exemplary three (3)-bit parallel twelve (12)-bit SAR ADC circuit 700 is shown that employs a multi-output DAC circuit 702 and a SA flash-based comparison circuit 704. Although not shown herein, other aspects employing the SA flash-based comparison circuit 704 may employ a DAC circuit including a single output DAC, rather than the multi-output DAC circuit 702 described herein. The three (3)-bit parallel twelve (12)-bit SAR ADC circuit 700 includes Figure 1 , 3A 3B and 5A to 5B, respectively, the common elements of the multi-bit parallel SAR ADC circuits 100, 300 and 500, which are Figure 1 , 3A 3B, 5A to 5B, and 7A to 7B are denoted by common element numbers and therefore are not repeated herein.

[0048] Continue to refer Fig. 7A and 7B, the three (3)-bit parallel twelve (12)-bit SAR ADC circuit 700 includes SAR controller circuits 102 (1)-102 (3), each SAR controller circuit includes four (4) SAR register circuits 104 (1) (1)-104 (3) (4). In this manner, the SAR register circuits 104 (1) (1)-104 (1) (4) correspond to digital bits DG (1), DG (4), DG (7) and DG (10), the SAR register circuits 104 (2) (1)-104 (2) (4) correspond to digital bits DG (2), DG (5), DG (8) and DG (11), and the SAR register circuits 104 (3) (1)-104 (3) (4) correspond to digital bits DG (3), DG (6), DG (9) and DG (12). Additionally, the DAC select signals 706(1)-706(4) correspond to the values ​​of each select input node SEL provided to each corresponding SAR register circuit 104(3)(1)-104(3)(4).

[0049] Continue to refer Fig. 7A and 7B, the multi-output DAC circuit 702 includes a selection circuit 708 using multiplexer circuits 710(1)-710(12). The multi-output DAC circuit 702 also includes DAC stages 712(1)-712(12). In this manner, the number of multiplexer circuits 710(1)-710(12) and the number of DAC stages 712(1)-712(12) are equal to the number of digital bits DG(1)-DG(12) in the digital output signal DOUT. In addition, each multiplexer circuit 710(1)-710(12) is configured to receive a corresponding digital bit DG(1)-DG(12). Multiplexer circuits 710(1), 710(4), 710(7), and 710(10) are configured to also receive comparator signal 714(1) from comparison circuit 716(1), and multiplexer circuits 710(2), 710(5), 710(8), and 710(11) are configured to also receive comparator signal 714(2) from comparison circuit 716(2). Multiplexer circuits 710(3), 710(6), 710(9), and 710(12) are configured to also receive comparator signal 714(3) from comparison circuit 716(3). Multiplexer circuits 710(1)-710(3) are configured to receive DAC select signal 706(4), and multiplexer circuits 710(4)-710(6) are configured to receive DAC select signal 706(3). Multiplexer circuits 710(7)-710(9) are configured to receive DAC select signal 706(2), and multiplexer circuits 710(10)-710(12) are configured to receive DAC select signal 706(1). DAC select signal 706(1)-706(4) selects between input values ​​of corresponding multiplexer circuits 710(1)-710(12) so that multiplexer circuits 710(1)-710(12) provide corresponding resistor select signals 718(1)-718(12).

[0050] Continue to refer Fig. 7A and 7B , and specific reference Figure 7B , DAC stages 712(1)-712(12) are configured to receive corresponding resistor selection signals 718(1)-718(12) on corresponding input nodes S0. In addition, DAC stages 712(1)-712(3) are configured to receive DAC selection signal 706(4), DAC stages 712(4)-712(6) are configured to receive DAC selection signal 706(3) on corresponding selection input nodes SEL. DAC stages 712(7)-712(9) are configured to receive DAC selection signal 706(2), and DAC stages 712(10)-712(12) are configured to receive DAC selection signal 706(1) on corresponding selection input nodes SEL. As shown in reference Figure 8Discussed in more detail, each DAC stage 712(1)-712(12) is configured to receive a top voltage VTOP and a bottom voltage VBOT at respective top input nodes TOP and bottom input nodes BOT, and to provide respective output voltages VTO, VBO at respective voltage output nodes RA, RB. As a result, DAC stages 712(1), 712(4), 712(7), and 712(10) provide DAC analog signals 720(1); DAC stages 712(2), 712(5), 712(8), and 712(11) provide DAC analog signals 720(2); and DAC stages 712(3), 712(6), 712(9), and 712(12) provide DAC analog signals 720(3). In addition, the DAC analog signals 720(1)-720(3) are provided to corresponding comparison circuits 716(1)-716(3), wherein the comparison circuits 716(1)-716(3) also receive the analog input signal VIN. It is important to note that the SA flash-based comparison circuit 704 includes a number of comparison circuits 716(1)-716(3), which is equal to the number of SAR controller circuits 102(1)-102(3).

[0051] Continue to refer Fig. 7A and 7B , each comparison circuit 716(1)-716(3) is configured to generate a corresponding comparator signal 714(1)-714(3), wherein each comparator signal 714(1)-714(3) is a corresponding digital bit DG(1)-DG(12) of a corresponding period of the clock signal CLK. In particular, if the analog input signal VIN has a larger voltage than the corresponding DAC analog signal 720(1)-720(3), each comparator signal 714(1)-714(3) has a logic high "1" value. Alternatively, if the analog input signal VIN has a smaller voltage than the corresponding DAC analog signal 720(1)-720(3), each comparator signal 714(1)-714(3) has a logic low "0" value. The use of the multi-output DAC circuit 702 and the flash-based comparison circuit 704 as described above allows the three (3)-bit parallel twelve (12)-bit SAR ADC circuit 700 to generate the digital output signal DOUT in four (4) cycles of the clock signal CLK, rather than the twelve (12) cycles generated by conventional SAR ADC circuits, while also reducing the area consumption in both the DAC and comparison circuit systems. For example, in Figure 3A and 3B The 3-bit parallel 12-bit SAR modeled after the two (2)-bit parallel ten (10)-bit SAR ADC circuit 300 in FIG. 3 will require 2 3 -1 = 7 comparators, even though it uses a multi-output DAC instead of individual single-output DACs, and Fig. 7A The three (3)-bit parallel twelve (12)-bit SAR ADC circuit 700 in Sum B requires only three (3) comparison circuits 716 ( 1 )-716 ( 3 ) to generate 3 bits per clock cycle.

[0052] Figure 8 An exemplary resistor rotator circuit 800 is shown. The resistor rotator circuit 800 may be used to Figure 7A-7B Each DAC stage 712(1)-712(12) of the multi-output DAC circuit 702 is configured to receive a top voltage VTOP on a top voltage input node TOP and a bottom voltage VBOT on a bottom voltage input node BOT. Additionally, the resistor rotator circuit 800 is configured to receive corresponding resistor select signals 718(1)-718(12) on an input node S0 and corresponding DAC select signals 706(1)-706(4) on a select input node SEL. In this manner, using Figure 8 The inverter 802, resistor 804, switches 806(1)-806(9), and resistor RADJ shown, corresponding DAC selection signals 706(1)-706(4) and resistor selection signals 718(1)-718(12) enable the resistor rotator circuit 800 to provide corresponding top voltage VTOP and bottom voltage VBOT at output nodes RA and RB, respectively. The inverter 802 is configured to receive the resistor selection signals 718(1)-718(12) at the corresponding input node S0 and invert these signals into complementary resistor selection signals 718B(1)-718B(12). Additionally, as shown Fig. 7A and 7B The corresponding DAC analog signals 720 ( 1 )- 720 ( 3 ) are shown provided via the output node DAC. Resistance RADJ in parallel with the equivalent resistance connected between the terminals of the VTO voltage and the BTO voltage produces an effective resistance equal to resistor 804 .

[0053] Elements described herein are sometimes referred to as means for performing a particular function. In this regard, SAR controller circuits 102(1)-102(M) are also referred to herein as "multiple means for successive approximation of digital values". SAR register circuits 104(1)(1)-104(M)(P) are also referred to herein as "multiple means for storing digital values". DAC circuit 110 is also referred to herein as "means for converting digital values ​​to analog values". Comparison circuit 112 is sometimes referred to herein as "means for comparing". Single output DAC circuits 302(1)-302(3) are sometimes referred to herein as "multiple single output means for converting digital values ​​to analog values". TTB circuit 314 is sometimes referred to herein as "means for converting to binary". Multiple output DAC circuits 502, 702 are sometimes referred to herein as "multiple output means for converting digital signals to analog signals". Resistor rotator circuits 600, 800 are sometimes referred to herein as "multiple means for dividing voltages".

[0054] The multi-bit parallel SAR ADC circuits according to the various aspects disclosed herein can be arranged in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), displays, computer displays, televisions, tuners, radios, satellite broadcasts, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotors.

[0055] At this point, Fig. 9 An example of a processor-based system 900 is shown, which may include a processor-based system 900 that uses Figure 1 , 3A3B, 5A to 5B, and 7A to 7B. In this example, the processor-based system 900 includes one or more central processing units (CPUs) 902, each of which includes one or more processors 904. The CPU 902 may have a cache memory 906 coupled to the processor 904 for quickly accessing temporarily stored data. The CPU 902 is coupled to a system bus 908 and may mutually couple master devices and slave devices included in the processor-based system 900. As is well known, the CPU 902 communicates with these other devices by exchanging address, control, and data information via the system bus 908. For example, the CPU 902 may transmit a bus transaction request to a memory controller 910, which is an example of a slave device. Although not shown in Fig. 9 Although not shown in FIG. 9 , multiple system buses 908 may be provided, each of which constitutes a different structure.

[0056] Other master devices and slave devices may be connected to the system bus 908. Fig. 9 As shown, as examples, these devices may include a storage system 912, one or more input devices 914, one or more output devices 916, one or more network interface devices 918, and one or more display controllers 920. Input device 914 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 916 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 918 may be any device configured to allow data exchange with network 922. Network 922 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH networks, and the like. TM Network and Internet. The network interface device 918 may be configured to support any type of communication protocol desired. The memory system 912 may include one or more memory units 924(0)-924(N).

[0057] The CPU 902 may also be configured to access a display controller 920 via the system bus 908 to control information sent to one or more displays 926. The display controller 920 sends information to the display 926 for display via one or more video processors 928, which process the information to be displayed into a format suitable for the display 926. The display 926 may include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0058] Fig.10 An exemplary wireless communication device 1000 is shown including radio frequency (RF) components formed in an integrated circuit (IC) 1002, where the RF components may include Figure 1 , 3A -3B, 5A-5B and 7A-7B of the multi-bit parallel SAR ADC circuits 100, 300, 500 and 700. In this regard, the wireless communication device 1000 can be provided in the IC 1002. As an example, the wireless communication device 1000 can include or be provided in any of the above-mentioned reference devices. Fig.10 As shown, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1006. The data processor 1006 may include a memory for storing data and program codes. The transceiver 1004 includes a transmitter 1008 and a receiver 1010 that support two-way communication. In general, the wireless communication device 1000 may include any number of transmitters 1008 and / or receivers 1010 for any number of communication systems and frequency bands. All or part of the transceiver 1004 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0059] The transmitter 1008 or the receiver 1010 may be implemented with a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, e.g., for the receiver 1010, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. The superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.10 In the wireless communication device 1000 in FIG. 1 , the transmitter 1008 and the receiver 1010 are implemented using a direct conversion architecture.

[0060] In the transmit path, the data processor 1006 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1008. In the exemplary wireless communication device 1000, the data processor 1006 includes digital-to-analog converters (DACs) 1012(1), 1012(2) to convert the digital signals generated by the data processor 1006 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0061] Within the transmitter 1008, low pass filters 1014(1), 1014(2), respectively, filter the I and Q analog output signals to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers AMPs 1016(1), 1016(2), respectively, amplify the signals from the low pass filters 1014(1) 1014(2) and provide I and Q baseband signals. An upconverter 1018 upconverts the I and Q baseband signals using I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 1022 via mixers 1020(1), 1020(2) to provide upconverted signals 1024. A filter 1026 filters the upconverted signals 1024 to remove unwanted signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 1028 amplifies the upconverted signals 1024 from the filter 1026 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1030 and transmitted through an antenna 1032 .

[0062] In the receive path, antenna 1032 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 1030 and provided to a low noise amplifier (LNA) 1034. The duplexer or switch 1030 is designed to operate with a specific receive (RX) to TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1034 and filtered by filter 1036 to obtain the desired RF input signal. Down-conversion mixers 1038 (1) and 1038 (2) mix the output of filter 1036 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1040 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMPs) 1042(1), 1042(2) and further filtered by low pass filters 1044(1), 1044(2) to obtain I and Q analog input signals, which are provided to the data processor 1006. In this example, the data processor 1006 includes ADCs 1046(1), 1046(2) to convert the analog input signals into digital signals for further processing by the data processor 1006.

[0063] exist Fig.10In the wireless communication device 1000 of the embodiment of the present invention, the TX LO signal generator 1022 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1040 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1048 receives timing information from the data processor 1006 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1022. The RX PLL circuit 1050 receives timing information from the data processor 1006 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1040.

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein can be used in any circuit, hardware component, integrated circuit (IC) or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been generally described in terms of function above. How to implement such a function depends on a specific application, design selection and / or the design constraints imposed on the entire system. The technician can implement the described function in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0065] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0066] The various aspects disclosed herein may be implemented as hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In an alternative, the storage medium may be an integral part of the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0067] It should also be noted that the operational steps described in any exemplary aspects of this article are described to provide examples and discussions. The described operations can be performed in many different orders except for the order shown. In addition, the operations described in a single operational step can actually be performed in many different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flow chart can be modified in many different ways, which is very clear to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols and chips that can be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles or any combination thereof.

[0068] The previous description of the disclosure is provided to enable those skilled in the art to make or use the invention. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the present invention is not intended to be limited to the examples and designs described herein, but is consistent with the widest range consistent with the principles and novel features disclosed herein.

Claims

1. A multi-bit parallel successive approximation register SAR analog-to-digital converter ADC circuit, comprising: A plurality of SAR controller circuits, wherein each SAR controller circuit of the plurality of SAR controller circuits comprises a plurality of SAR register circuits, wherein each SAR register circuit is configured to: receiving a clock signal; providing a digital signal related to a power supply voltage in response to corresponding cycles of the clock signal; and In response to a corresponding next cycle of the clock signal: receiving a corresponding digital bit, wherein the digital bit is based on a comparison of an analog input signal and a corresponding digital-to-analog converter DAC analog signal; storing the digital digits; and providing said digital signal associated with said digital bit; The DAC circuit is configured as: receiving a reference voltage; receiving a plurality of digital signals from the plurality of SAR controller circuits, wherein each digital signal corresponds to a digital bit of a digital output signal; and generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage and the plurality of digital signals; as well as The comparison circuit is configured as: Receiving the plurality of DAC analog signals; receiving the analog input signal; as well as generating the digital bit corresponding to each SAR controller circuit of the plurality of SAR controller circuits based on a comparison of each DAC analog signal with the analog input signal, wherein each generated digital bit collectively forms the digital output signal, the digital output signal being a digital representation of the analog input signal, The DAC circuit comprises: The test bit circuit is configured as: receiving the digital signal from each SAR register circuit of each SAR controller circuit; receiving a test signal from each SAR register circuit of a subset of the plurality of SAR controller circuits; and A plurality of test bit codes are generated based on the digital signal and the test signal, wherein each test bit code includes a digital bit sequence having values ​​corresponding to the digital output signal for a subset of the digital bits.

2. The multi-bit parallel SAR ADC circuit according to claim 1, wherein the DAC circuit further comprises: a plurality of single output DAC circuits, the number of the single output DAC circuits being equal to the number of the plurality of SAR controller circuits raised to the power of two minus one, wherein each single output DAC circuit is configured as: receiving the plurality of trial bit codes; and generating a corresponding DAC analog signal among the plurality of DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and a corresponding test bit code; as well as The comparison circuit comprises: a plurality of comparison circuits, the number of the comparison circuits being equal to the number of the plurality of SAR controller circuits raised to the power of two minus one, wherein each comparison circuit is configured to: receiving the analog input signal and the corresponding DAC analog signal; and Generates a comparator signal where: If the analog input signal has a greater voltage than the corresponding DAC analog signal, the comparator signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the comparator signal has a logic low value; and Thermometer to Binary (TTB) circuit, configured as: receiving the comparator signal from each comparison circuit; and The digital bits corresponding to each SAR controller circuit are generated based on the comparator signal from each comparison circuit.

3. The multi-bit parallel SAR ADC circuit of claim 1 , wherein the DAC circuit comprises a multi-output DAC circuit, the multi-output DAC circuit being configured to: receiving a top voltage and a bottom voltage, wherein voltage ranges of the top voltage and the bottom voltage are based on the reference voltage; and The plurality of DAC analog signals are generated based on the top voltage and the bottom voltage. 4 . The multi-bit parallel SAR ADC circuit of claim 3 , wherein each of the plurality of DAC analog signals has a value that is a component of the voltage range.

5. The multi-bit parallel SAR ADC circuit of claim 3, wherein the multi-output DAC circuit comprises a plurality of resistor rotator circuits configured to generate the plurality of DAC analog signals by generating a plurality of components of the voltage range.

6. The multi-bit parallel SAR ADC circuit according to claim 3, wherein the comparison circuit comprises: a plurality of comparison circuits, the number of the comparison circuits being equal to the number of the plurality of SAR controller circuits raised to the power of two minus one, wherein each comparison circuit is configured to: receiving the analog input signal and the corresponding DAC analog signal; and Generates a comparator signal where: If the analog input signal has a greater voltage than the corresponding DAC analog signal, the comparator signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the comparator signal has a logic low value; and Thermometer to Binary (TTB) circuit, configured as: receiving the comparator signal from each comparison circuit; and The digital bits corresponding to each SAR controller circuit are generated based on the comparator signal from each comparison circuit.

7. The multi-bit parallel SAR ADC circuit according to claim 3, wherein the comparison circuit comprises a plurality of comparison circuits, the number of the comparison circuits being equal to the number of the plurality of SAR controller circuits, wherein each comparison circuit is configured as: receiving the analog input signal and the corresponding DAC analog signal; and Generates a comparator signal where: The comparator signal is the corresponding digital bit; If the analog input signal has a greater voltage than the corresponding DAC analog signal, the comparator signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the comparator signal has a logic low value.

8. The multi-bit parallel SAR ADC circuit of claim 1 , comprising two SAR controller circuits, wherein each SAR controller circuit comprises five SAR register circuits, such that the multi-bit parallel SAR ADC circuit is configured to generate the digital output signal having ten digital bits.

9. The multi-bit parallel SAR ADC circuit of claim 1 , comprising three SAR controller circuits, wherein each SAR controller circuit comprises four SAR register circuits, such that the multi-bit parallel SAR ADC circuit is configured to generate the digital output signal having twelve digital bits.

10. The multi-bit parallel SAR ADC circuit of claim 1, integrated into an integrated circuit (IC).

11. The multi-bit parallel SAR ADC circuit of claim 1 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; a motor vehicle; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

12. A multi-bit parallel successive approximation register SAR analog-to-digital converter ADC circuit, comprising: A plurality of means for successive approximation of digital values, wherein each of the plurality of means for successive approximation of the digital values ​​comprises a plurality of means for storing the digital values, wherein each means for storing the digital values ​​is configured to: receiving a clock signal; receiving a start signal indicating a conversion process; providing a digital signal related to a power supply voltage in response to corresponding cycles of the clock signal; and In response to a corresponding next cycle of the clock signal: receiving a corresponding digital bit, wherein the digital bit is based on a comparison of an analog input signal and a corresponding digital-to-analog converter DAC analog signal; storing the digital digits; and providing a digital signal associated with the digital bit; The device for converting a digital value into an analog value is configured to: receiving a reference voltage; receiving a plurality of digital signals from a plurality of SAR controllers, wherein each digital signal corresponds to the digital bit of the digital output signal; and generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage and the plurality of digital signals; as well as The devices used for comparison were configured as follows: Receiving the plurality of DAC analog signals; receiving the analog input signal; as well as generating the digital bit corresponding to each of the plurality of means for successive approximation of the digital value based on a comparison of each DAC analog signal with the analog input signal, wherein each of the generated digital bits collectively forms the digital output signal, the digital output signal being a digital representation of the analog input signal, wherein: The means for converting the digital value into the analog value comprises: The device for generating a test bit code is configured to: receiving said digital signal from each means for storing said digital value of each means for successive approximation of said digital value; and A plurality of trial bit codes are generated, wherein each trial bit code includes a digital bit sequence having values ​​for the digital bits corresponding to the digital output signal.

13. The multi-bit parallel SAR ADC circuit of claim 12, wherein the means for converting the digital value into the analog value further comprises: a plurality of single output devices for converting the digital value into an analog value, the number of the single output devices for converting being equal to the number of the plurality of devices for successive approximation of the digital value raised to the power of two minus one, wherein each single output device for converting is configured to: receiving the plurality of trial bit codes; as well as generating corresponding DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and a corresponding test bit code; as well as The device for comparing comprises: a plurality of means for performing comparison, the number of means for performing comparison being equal to the number of the plurality of means for successively approximating the digital value raised to the power of two minus one, wherein each means for performing comparison is configured to: receiving the analog input signal and the corresponding DAC analog signal; and Generates a comparator signal where: If the analog input signal has a greater voltage than the corresponding DAC analog signal, the comparator signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the comparator signal has a logic low value; and The device used for converting to binary is configured as: receiving the comparator signal from the plurality of means for performing comparisons; and The digital bits corresponding to each means for successive approximation of the digital value are generated.

14. The multi-bit parallel SAR ADC circuit according to claim 12, wherein the means for converting the digital value into the analog value comprises a multi-output means for converting the digital signal into an analog signal, the multi-output means being configured to: receiving a top voltage and a bottom voltage, wherein voltage ranges of the top voltage and the bottom voltage are based on the reference voltage; and The plurality of DAC analog signals are generated based on the top voltage and the bottom voltage, wherein the number of DAC analog signals is equal to the number of means for performing comparison in the means for comparing. 15 . The multi-bit parallel SAR ADC circuit of claim 14 , wherein each of the plurality of DAC analog signals has a value that is a component of the voltage range.

16. The multi-bit parallel SAR ADC circuit of claim 14, wherein the multi-output means for converting the digital signal into the analog signal comprises a plurality of means for dividing the voltage, wherein each means for dividing the voltage is configured to generate the corresponding DAC analog signal by generating a component of the voltage range.

17. The multi-bit parallel SAR ADC circuit of claim 14, wherein the means for comparing comprises: a plurality of means for performing comparison, the number of means for performing comparison being equal to two raised to the power of the number of means for successive approximation minus one, wherein each means for performing comparison is configured to: receiving the analog input signal and the corresponding DAC analog signal; and Generate the digital signal, wherein: If the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the digital signal has a logic low value; and The device used for converting to binary is configured as: receiving said digital signal from said means for performing a comparison; and The digital bits corresponding to each means for successive approximation are generated.

18. The multi-bit parallel SAR ADC circuit of claim 14, wherein the means for comparing comprises a plurality of means for performing comparison, the number of the means for performing comparison being equal to the number of the plurality of means for successive approximation, wherein each means for performing comparison is configured to: receiving the analog input signal and the corresponding DAC analog signal; and Generate the digital signal, wherein: The digital signal is the corresponding digital bit; If the analog input signal has a greater voltage than the corresponding DAC analog signal, the digital signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the digital signal has a logic low value.

19. A method for converting an analog input signal into a digital output signal, wherein a plurality of digital bits of the digital output signal are generated in parallel, the method comprising: receiving a clock signal; providing a digital signal in response to corresponding cycles of the clock signal; In response to a corresponding next cycle of the clock signal, receiving a corresponding digital bit, wherein the digital bit is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal; storing the digital bit in response to the corresponding next cycle of the clock signal; providing the digital signal associated with the digital bit in response to the corresponding next cycle of the clock signal; receiving a reference voltage; generating a plurality of DAC analog signals, wherein each DAC analog signal is based on the reference voltage and a plurality of digital signals; generating the corresponding digital bit based on a comparison of each corresponding DAC analog signal with the analog input signal, wherein each generated digital bit collectively forms the digital output signal, the digital output signal being a digital representation of the analog input signal; and A plurality of trial bit codes are generated, wherein each trial bit code includes a digital bit sequence having values ​​for the digital bits corresponding to the digital output signal.

20. The method according to claim 19, further comprising: generating the corresponding DAC analog signals, wherein each corresponding DAC analog signal is based on the reference voltage and a corresponding test bit code; Generates a comparator signal where: If the analog input signal has a greater voltage than the corresponding DAC analog signal, the comparator signal has a logic high value; and If the analog input signal has a smaller voltage than the corresponding DAC analog signal, the comparator signal has a logic low value; and The digital bit corresponding to each SAR controller circuit of a plurality of SAR controller circuits is generated based on the comparator signal from each comparison circuit.

21. The method of claim 19, further comprising: receiving a top voltage and a bottom voltage, wherein voltage ranges of the top voltage and the bottom voltage are based on the reference voltage; as well as The plurality of DAC analog signals are generated based on the top voltage and the bottom voltage.

22. The method according to claim 21, further comprising: The corresponding plurality of DAC analog signals are generated by generating components of the voltage range.

Images