Method of forming an integrated circuit device

Abstract

Methods of forming integrated circuit devices are provided. The methods can include forming dummy channel regions and active regions of a substrate, forming a bottom source / drain region on the active regions, forming a gate electrode on opposing side surfaces of the dummy channel regions, and forming a first spacer and a second spacer on the opposing side surfaces of the dummy channel regions, respectively. The gate electrode can include a first portion on one of the opposing side surfaces of the dummy channel regions and a second portion between the bottom source / drain region and the first spacer. The methods can also include forming a bottom source / drain contact by displacing the first portion of the gate electrode with a conductive material. The bottom source / drain contact can electrically connect the second portion of the gate electrode to the bottom source / drain region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of electronics, and more particularly, to vertical field effect transistor (VFET) devices. BACKGROUND

[0002] Due to the high scalability of VFET devices, various structures and fabrication processes for VFET devices have been researched. Accordingly, it would be beneficial to develop fabrication processes that improve the performance and / or reliability of VFET devices. SUMMARY

[0003] According to some embodiments of the inventive concepts, a method of forming an integrated circuit device can include forming dummy channel regions on a substrate and then forming active regions. The dummy channel regions can be provided adjacent to corners of the active regions. Since the dummy channel regions are formed prior to the active regions, the active regions can have corners that are identical or similar in shape to each other. After the active regions are formed, the method can further include forming gate structures and spacers on side surfaces of the dummy channel regions. The dummy channel regions can be removed to form bottom source / drain contacts, or can be converted to be part of the bottom source / drain contacts. Due to the spacers formed on the side surfaces of the dummy channel regions, the bottom source / drain contacts can be self-aligned between the spacers.

[0004] According to some embodiments of the inventive concepts, a method of forming an integrated circuit device can include forming dummy channel regions and active regions of a substrate; forming bottom source / drain regions on the active regions; forming a gate electrode on opposite side surfaces of the dummy channel regions; and forming first and second spacers on the opposite side surfaces of the dummy channel regions, respectively. The gate electrode can include a first portion on one of the opposite side surfaces of the dummy channel regions and a second portion between the bottom source / drain regions and the first spacer. The method can further include forming a bottom source / drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source / drain contact can electrically connect the second portion of the gate electrode to the bottom source / drain regions.

[0005] According to some embodiments of the inventive concepts, a method of forming an integrated circuit device can include forming a bottom source / drain region on an active region of a substrate, forming a bottom spacer on the bottom source / drain region, forming a gate electrode on the bottom spacer, and forming a first spacer and a second spacer on the bottom spacer. A portion of the gate electrode can be between the bottom spacer and the first spacer. The method can also include forming a bottom source / drain contact between the first spacer and the second spacer. The bottom source / drain contact can contact both the gate electrode and the bottom source / drain region. The bottom source / drain contact includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, and both the first semiconductor layer and the second semiconductor layer include an impurity element of a first conductivity type.

[0006] According to some embodiments of the inventive concepts, an integrated circuit device can include a bottom source / drain region on an active region of a substrate and a plurality of spacers on the bottom source / drain region. The plurality of spacers can be spaced apart from each other and can include a first spacer and a second spacer. The integrated circuit device can also include a bottom spacer extending between the bottom source / drain region and the plurality of spacers, a gate electrode between the bottom spacer and the first spacer, and a bottom source / drain contact between the first spacer and the second spacer. The bottom source / drain contact can contact both the first spacer and the second spacer and can electrically connect the gate electrode to the bottom source / drain region. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a circuit diagram of a 6T SRAM.

[0008] Figure 2 is a schematic diagram of a 6T SRAM of Figure 1

[0009] Figures 3 to 8 are views illustrating a method of forming a 6T SRAM according to some embodiments of the inventive concepts. Figure 2 Figure 3 and Figure 6 are plan views, Figure 4 and Figure 5 are cross-sectional views taken along lines A-A' and B-B' of Figure 3 , respectively, Figure 7 and Figure 8 are cross-sectional views taken along lines C-C' and D-D' of Figure 6 , respectively.

[0010] Figure 9 and Figure 10 are views illustrating a method of forming a 6T SRAM according to some embodiments of the inventive concepts. Figure 1 and Figure 2 ​​The flowchart of the 6T SRAM method.

[0011] Figures 11 to 30 This is a view illustrating a method for forming a 6T SRAM according to some embodiments of the concept of the present invention. Figure 11 , Figure 14 , Figure 17 and Figure 20 It's a floor plan. Figure 12 and Figure 13 They are respectively along Figure 11 The sectional view taken by lines E-E' and F-F'. Figure 15 and Figure 16 They are respectively along Figure 14 The sectional view taken by lines G-G' and H-H'. Figure 18 and Figure 19 They are respectively along Figure 17 The sectional view taken by lines I-I' and J-J'. Figure 21 , Figure 23 , Figure 25 , Figure 27 and Figure 29 It is along Figure 20 A cross-sectional view taken by line K-K'. Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 30 It is along Figure 20 A sectional view taken by line L-L'.

[0012] Figures 31 to 36 It shows the formation Figure 1 and Figure 2 A cross-sectional view of the 6T SRAM method shown. Figure 31 , Figure 33 and Figure 35 It is along Figure 20 A cross-sectional view taken by line K-K'. Figure 32 , Figure 34 and Figure 36 It is along Figure 20 A sectional view taken by line L-L'.

[0013] Figures 37 to 39 It shows the formation Figure 1 and Figure 2 A view of the method for using 6T SRAM. Figure 37 It's a floor plan. Figure 38 and Figure 39 It is along Figure 37 A sectional view taken by line M-M'.

[0014] Figure 40 and Figure 41 It is along Figure 20a cross-sectional view taken along the line L-L' of FIG. 1. DETAILED DESCRIPTION

[0015] Various standard cells can be used to form integrated circuit devices. One example of a standard cell is a six-transistor static random access memory (6T SRAM) cell. Referring to Figure 1 , the 6T SRAM can include a first cell including three transistors (i.e., a first pull-up transistor PUR, a first pull-down transistor PDR, and a first gate transistor PGR) and a second cell including three transistors (i.e., a second pull-up transistor PUL, a second pull-down transistor PDL, and a second gate transistor PGL). Each of the transistors of the first and second cells can be a VFET. In Figure 1 , WL refers to a word line, both BL and BLB refer to a bit line, VDD refers to a first operating voltage, and GND refers to a second operating voltage (e.g., a ground voltage).

[0016] Referring to Figure 2 , the three transistors of the first cell can be on a first active region. Each of the three transistors of the first cell can be adjacent to a corresponding one of a first corner, a second corner, and a third corner of the first active region, and a node contact QB can be adjacent to a fourth corner of the first active region. The three transistors of the second cell can be on a second active region. Each of the three transistors of the second cell can be adjacent to a corresponding one of a first corner, a second corner, and a third corner of the second active region, and a node contact Q can be adjacent to a fourth corner of the second active region.

[0017] Each of the node contact Q and the node contact QB can be a conductive contact, rather than a transistor, and thus the node contact Q and the node contact QB can not include a channel region (e.g., 12 in Figure 29 and Figure 30 . Thus, a channel region can not be provided adjacent to the fourth corner of the first active region and the fourth corner of the second active region.

[0018] Referring to Figure 1 and Figure 2 , each of the first pull-down transistor PDR, the first gate transistor PGR, the second pull-down transistor PDL, and the second gate transistor PGL can be an N-type transistor and can include an N-type bottom source / drain region. Each of the first pull-up transistor PUR and the second pull-up transistor PUL can be a P-type transistor and can include a P-type bottom source / drain region.

[0019] Referring to Figure 3 , Figure 4 and Figure 5The channel regions 12 can be formed on the substrate 10 by etching the substrate 10 with the mask layer 14 as an etch mask. To illustrate the mask layer 14, Figure 3 The liner layer 16 is not shown. Each channel region 12 can be a channel region of one of the six transistors of the 6T SRAM. The mask layer 14 can include a material that has etch selectivity with respect to the substrate 10. For example, the mask layer 14 can include a photoresist material, a hard mask material, and / or a silicon layer including nitrogen and / or oxygen therein. Figure 2

[0020] Each channel region 12 can protrude from an upper surface 10u of the substrate 10 in a third direction D3. The third direction D3 can be a vertical direction that is perpendicular to the upper surface 10u of the substrate 10. Some of the channel regions 12 can be spaced apart from each other in a first horizontal direction D1 that is parallel to the upper surface 10u of the substrate 10, and some of the channel regions 12 can be spaced apart from each other in a second horizontal direction D2 that is parallel to the upper surface 10u of the substrate 10. The first horizontal direction D1 can intersect the second horizontal direction D2. In some embodiments, the first horizontal direction D1 can be perpendicular to the second horizontal direction D2. In some embodiments, the third direction D3 can be perpendicular to both the first horizontal direction D1 and the second horizontal direction D2.

[0021] After the six channel regions 12 are formed, the liner layer 16 can be formed on the mask layer 14, the channel regions 12, and the substrate 10. In some embodiments, the liner layer 16 can have a uniform thickness along a surface of the mask layer 14, a surface of the channel regions 12, and the upper surface 10u of the substrate 10, as shown in Figure 4 and Figure 5 .

[0022] The liner layer 16 can include a material that has etch selectivity with respect to the substrate 10. For example, the liner layer 16 can include a SiN layer and / or a SiON layer. In some embodiments, the liner layer 16 can be a SiN layer. The substrate 10 can include one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 10 can be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor-on-insulator (SOI) substrate. The channel regions 12 can include the same material as the substrate 10.

[0023] Referring to Figure 6 , Figure 7 and Figure 8 , the active mask layer 18 can be formed on the substrate 10, and then the liner layer 16 and the substrate 10 can be etched to form the first active region 22_1 and the second active region 22_2 on the substrate 10. To illustrate the mask layer 14, Figure 6 the liner layer 16 is not shown, and​Figure 6 Only the outline of the active mask layer 18 is shown. Each active mask layer 18 may have four corners with the same or similar shapes in the plan view. For example, each active mask layer 18 may be as follows: Figure 6 The planar view shown has a rectangular shape. Active mask layer 18 refers to the layer used for patterning active regions (e.g., ...). Figure 6 , Figure 7 and Figure 8 The mask layers 22_1 and 22_2 in the middle.

[0024] like Figure 6 As shown, each of the first active region 22_1 and the second active region 22_2 can have a rounded corner 22_1r or 22_2r, since no channel region 12 is formed adjacent to the rounded corner 22_1r or 22_2r. Due to the rounded corners 22_1r and 22_2r, each of the first active region 22_1 and the second active region 22_2 can have an area smaller than the area of ​​each active mask layer 18. Therefore, only a portion of the subsequently formed bottom source / drain contact 82 can overlap with the underlying first active region 22_1 or second active region 22_2, and the contact resistance between the bottom source / drain contact 82 and the underlying first active region 22_1 or second active region 22_2 can be increased compared to when the bottom source / drain contact 82 completely overlaps with the underlying first active region 22_1 or second active region 22_2.

[0025] Still refer to Figure 6 , Figure 7 and Figure 8 The field isolation layer 24 can be formed on the side surfaces of the first active region 22_1 and the second active region 22_2. Due to the rounded corners 22_1r of the first active region 22_1 and 22_2r of the second active region 22_2, the field isolation layer 24 may include a rounded portion 24r that overlaps with the active mask layer 18. The bottom source / drain contact 82 may overlap with and contact the rounded portion 24r of the field isolation layer 24, such as... Figure 6 As shown.

[0026] According to some embodiments of the present invention, a method for forming an integrated circuit device may include forming an active region (e.g. Figures 17 to 19 All four corner adjacent trench areas (e.g., 22_1 or 22_2) in the middle Figure 13 and Figure 14 12 and 12d in the middle), and then one of the channel regions (e.g. Figure 12 and Figure 13 The 12d in the middle can be removed to form the bottom source / drain contact (e.g. Figure 27or be converted into part of the bottom source / drain contact (e.g., 82 in Figure 35

[0027] Referring to Figure 9 , a method of forming an integrated circuit device according to some embodiments of the inventive concepts can include forming a channel region and an active region (block 100), forming a gate electrode and a spacer (block 200), and then forming a bottom source / drain contact (block 300).

[0028] Referring to Figures 10 to 13 , forming a channel region and an active region (block 100 in Figure 9 ) can include forming a mask layer 14 on the substrate 10 (block 110) and forming the channel region 12 by etching the substrate 10 using the mask layer 14 as an etch mask (block 120). The channel region 12 can include a dummy channel region 12d that will not be a VFET. The dummy channel region 12d can be removed to form the bottom source / drain contact (e.g., 82 in Figure 27 ) or can be converted into part of the bottom source / drain contact (e.g., 82 in Figure 35 ) during subsequent processes. Throughout the specification, removing a layer X can mean etching the layer X using a wet etch process and / or a dry etch process.

[0029] Forming a channel region and an active region (block 100 in Figure 9 ) can also include forming a liner layer 16 on the mask layer 14, the channel region 12, and the substrate 10 (block 130). The liner layer 16 can have a uniform thickness along the surfaces of the mask layer 14 and the channel region 12 and along the upper surface 10u of the substrate 10, as shown in Figure 12 and Figure 13 .

[0030] Referring to Figure 10 and Figures 14 to 19 , forming a channel region and an active region (block 100 in Figure 9 ) can also include forming an active mask layer 18 on the substrate 10 and forming a first active region 22_1 and a second active region 22_2 by etching the substrate 10 using the active mask layer 18 as an etch mask (block 140). For example, the active mask layer 18 can be a photoresist layer. To show the mask layer 14, Figure 14 the liner layer 16 is not shown, and Figure 14 only the outline of the active mask layer 18 is shown.

[0031] Referring to Figure 17 ​The four channel regions 12 can be formed adjacent to four corners of each of the first and second active regions 22_1 and 22_2, and thus the four corners of each of the first and second active regions 22_1 and 22_2 can have the same or similar shape in a plan view. Although Figure 17 The four corners of each of the first and second active regions 22_1 and 22_2 are illustrated as right-angled corners, but in some embodiments, the four corners can be rounded corners. Even when the four corners are rounded corners, the four corners can have the same or similar shape.

[0032] Referring to Figures 17 to 19 The field isolation layer 24 can be formed on the side surfaces of the first and second active regions 22_1 and 22_2, and a first bottom source / drain region 32 having a first conductivity type (e.g., P-type) and a second bottom source / drain region 34 having a second conductivity type (e.g., N-type) can be formed on each of the first and second active regions 22_1 and 22_2. The mask layer 14 and the liner layer 16 can be removed after the first and second active regions 22_1 and 22_2 are formed. The first bottom source / drain region 32 can include an impurity element (e.g., B, Al, and / or Ga) of the first conductivity type, and the second bottom source / drain region 34 can include an impurity element (e.g., P and / or As) of the second conductivity type.

[0033] Referring to Figure 9 and Figures 20 to 22 Forming the gate electrodes and spacers (block 200 in Figure 9 ) can include forming the gate electrodes 44_1, 44_2, 44_3, 44_4, or 44_5 and the spacers 48 on the side surfaces of the channel regions 12. For simplicity of illustration, Figure 20 Some elements illustrated in Figure 21 and Figure 22 are illustrated, but not all elements. For example, the spacers 48 are not illustrated in Figure 20

[0034] The spacers 48 can include an insulating material having etching selectivity with respect to an insulating layer (e.g., 62 in Figure 21 and Figure 22 ). For example, the spacers 48 can include a SiN layer and / or a SiON layer. In some embodiments, the spacers 48 can be a SiN layer. A pair of the spacers 48 on the side surface of a single channel region 12 can be spaced apart from each other by a first distance d1 in the first horizontal direction D1, as illustrated in Figure 21

[0035] Referring to Figure 1 and Figures 20 to 22 ​​, the gate electrodes 44_1, 44_2, 44_3, 44_4, and 44_5 can include a first gate electrode 44_1 that is common to the second pull-up transistor PUL and the second pull-down transistor PDL, and a first portion 44_1f of the first gate electrode 44_1 can be formed on a side surface of the dummy channel region 12d. The first gate electrode 44_1 can also include a second portion 44_1s between the spacer 48 and the first bottom source / drain region 32. The first gate electrode 44_1 can extend as shown from the first active region 22_1 onto the second active region 22_2, and can be a monolithic conductive layer or can include a monolithic conductive layer. Figure 20

[0036] Referring to Figure 21 and Figure 22 the method can further include forming a gate insulator 42 between the gate electrode 44_1, 44_2, 44_3, 44_4, or 44_5 and the channel region 12, and forming a bottom spacer 36 that separates the first bottom source / drain region 32 and the second bottom source / drain region 34 from the gate electrode 44_1, 44_2, 44_3, 44_4, or 44_5.

[0037] In some embodiments, the gate insulator 42 can include, for example, silicon oxide and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide). In some embodiments, the gate electrode 44_1, 44_2, 44_3, 44_4, or 44_5 can include a metallic layer (e.g., W, Ti, Cu, and / or Co). In some embodiments, the gate electrode 44_1, 44_2, 44_3, 44_4, or 44_5 can also include a work function layer, which can include a metal nitride (e.g., TiN, TaN, TiAlN, TaAlN), TiAl, TaC, TiC, and / or HfSi.

[0038] The method can further include forming a first top source / drain region 52 and a second top source / drain region 54, and forming a top spacer 46 that is formed on the gate electrode 44_1, 44_2, 44_3, 44_4, or 44_5 and separates the gate electrode 44_1, 44_2, 44_3, 44_4, or 44_5 from the first top source / drain region 52 or the second top source / drain region 54. The first top source / drain region 52 can include an impurity element of a first conductivity type (e.g., B, Al, and / or Ga) therein, and thus can have the first conductivity type. The second top source / drain region 54 can include an impurity element of a second conductivity type (e.g., P and / or As), and thus can have the second conductivity type.

[0039] ​Each of the first and second top source / drain regions 52, 54 can be formed by performing an epitaxial growth process that employs the channel region 12 as a seed layer, and can include a semiconductor material. In some embodiments, each of the first and second top source / drain regions 52, 54 can contact the spacers 48, as shown in Figure 21 and Figure 22 .

[0040] For example, each of the bottom and top spacers 36, 46 can include an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride). In some embodiments, the bottom and top spacers 36, 46 can include different materials.

[0041] An insulating layer 62 can be formed on the first and second top source / drain regions 52, 54. The insulating layer 62 can include an insulating material (e.g., a silicon layer including oxygen and / or nitrogen or a low dielectric layer having a lower dielectric constant than silicon dioxide).

[0042] Referring to Figure 23 and Figure 24 , a second mask layer 72 can be formed on the insulating layer 62, and a first opening 74 can be formed by removing a portion of the insulating layer 62, the first top source / drain region 52 on the dummy channel region 12d, the top spacer 46 adjacent to the dummy channel region 12d, the dummy channel region 12d, a first portion 44_1f of the first gate electrode 44_1, and the gate insulator 42 between the first portion 44_1f of the first gate electrode 44_1 and the dummy channel region 12d using the second mask layer 72 as an etching mask. In some embodiments, a portion of the first bottom source / drain region 32 can be removed to form the first opening 74.

[0043] In some embodiments, the first opening 74 can expose side surfaces of the spacer 48 that the dummy channel region 12d was originally located between. In some embodiments, the first opening 74 can expose entire side surfaces of the spacer 48 that the dummy channel region 12d was originally located between, as shown in Figure 23 and Figure 24 . In some embodiments, the first opening 74 can also expose a side surface of a second portion 44_1s of the first gate electrode 44_1. In some embodiments, the side surfaces of the spacer 48 and the side surface of the second portion 44_1s of the first gate electrode 44_1 exposed by the first opening 74 can be perpendicularly aligned with each other, as shown in Figure 23 and Figure 24 .

[0044] In some embodiments, the spacers 48 can include a material having etch selectivity with respect to the insulating layer 62, so that the first openings 74 and the bottom source / drain contacts (e.g., 82 in Figure 27 ) can be self-aligned between the spacers 48 even if the second mask layer 72 is misaligned.

[0045] Referring to Figure 25 and Figure 26 , second openings 76 exposing the first top source / drain regions 52 or the second top source / drain regions 54 can be formed in the insulating layer 62.

[0046] Referring to Figure 27 and Figure 28 , the bottom source / drain contacts 82, the first contacts 84, and the second contacts 86 can be formed by forming conductive layers in the first openings 74 and the second openings 76. The first contacts 84 can contact the first top source / drain regions 52, and the second contacts 86 can contact the second top source / drain regions 54. In some embodiments, upper surfaces of the bottom source / drain contacts 82, the first contacts 84, and the second contacts 86 can be coplanar with each other.

[0047] The bottom source / drain contacts 82 can contact the second portion 44_1s of the first gate electrode 44_1 and the first bottom source / drain region 32, so that the second portion 44_1s of the first gate electrode 44_1 can be electrically connected to the first bottom source / drain region 32. Accordingly, the bottom source / drain contacts 82 can be part of the node contact QB in Figure 1 and Figure 2 , and the first gate electrode 44_1 shared by the second pull-up transistor PUL and the second pull-down transistor PDL can be electrically connected to the first bottom source / drain region 32 through the bottom source / drain contacts 82. Figure 1 and Figure 2 , the bottom source / drain contacts of the node contact Q can be formed to have the same or similar structure as the bottom source / drain contacts 82 in Figure 27 and Figure 28 .

[0048] In some embodiments, the bottom source / drain contacts 82 can be formed to fill the first openings 74 and can contact side surfaces of the spacers 48, as shown in Figure 27 and Figure 28 .

[0049] Referring to Figure 29 and Figure 30 , second openings 76 exposing the first top source / drain regions 52 or the second top source / drain regions 54 can be formed in the insulating layer 62.In some embodiments, the upper portion of the bottom source / drain contact 82 can be removed such that the upper surface of the bottom source / drain contact 82 is recessed toward the substrate 10 relative to the upper surface of the spacer 48 in which the bottom source / drain contact 82 is formed. Therefore, the upper surface of the bottom source / drain contact 82 can be closer to the substrate 10 than the upper surface of the spacer 48.

[0050] Figure 31 and Figure 32 The intermediate structure shown can be compared with the reference. Figures 3 to 19 The processes described are the same as or similar to those formed during the formation of the top source / drain region (e.g., ...). Figure 21 and Figure 22 Before (52 and 54) in the diagram, insulating layer 62 and second mask layer 72 can be formed on substrate 10. Second mask layer 72 can expose a portion of insulating layer 62, such as... Figure 31 and Figure 32 As shown.

[0051] Reference Figure 33 and Figure 34 A portion of the insulating layer 62, the top spacer 46, the first portion 44_1f of the first gate electrode 44_1, and a portion of the gate insulating layer 42 can be removed to form a first contact opening 74' that exposes a portion of the dummy channel region 12d and the bottom spacer 36. An impurity element of a first conductivity type can be added to the dummy channel region 12d via, for example, an ion implantation process to transform the dummy channel region 12d into the first portion 82_1 of the bottom source / drain contact 82.

[0052] Reference Figure 35 and Figure 36 When the first top source / drain region 52 and / or the second top source / drain region 54 are formed, the second portion 82_2 of the bottom source / drain contact 82 can be formed in the first contact opening 74'. An epitaxial growth process can be performed to form the second portion 82_2 of the bottom source / drain contact 82, the first top source / drain region 52, and the second top source / drain region 54. The second portion 82_2 of the bottom source / drain contact 82 can be grown using the first portion 82_1 of the bottom source / drain contact 82 as a seed layer, and each of the first top source / drain region 52 and the second top source / drain region 54 can be grown using the channel region 12 as a seed layer.

[0053] In some embodiments, the upper surface of the bottom source / drain contact 82, the upper surface of the first top source / drain region 52, and the upper surface of the second top source / drain region 54 may be coplanar with each other, such as... Figure 35 and Figure 36The upper surface of the bottom source / drain contact 82, the upper surface of the first top source / drain region 52, and the upper surface of the second top source / drain region 54 can be coplanar with the upper surface of the spacer 48, as shown. In some embodiments, the bottom source / drain contact 82, the first contact 84, and the second contact 86 in Figure 35 and Figure 36 may be formed on the intermediate structure shown in Figure 27 and Figure 28 . Figure 35 and Figure 36 .

[0054] Figures 37 to 39 The 6T SRAM shown can be formed by processes that are the same as or similar to those described with reference to Figures 3 to 30 . With reference to Figure 37 and Figure 38 , the second bottom source / drain region 34 can have a length in the second horizontal direction D2 that is longer than a length of the second bottom source / drain region 34 in Figure 17 , and the bottom source / drain contact 82 can overlap and contact a portion of the second bottom source / drain region 34.

[0055] With reference to Figure 39 , an upper portion of the bottom source / drain contact 82 can be removed so that an upper surface of the bottom source / drain contact 82 can be recessed toward the substrate 10 relative to an upper surface of the spacer 48. Thus, the upper surface of the bottom source / drain contact 82 can be closer to the substrate 10 than the upper surface of the spacer 48.

[0056] Figure 40 The intermediate structure shown can be formed by processes that are the same as or similar to those described with reference to Figures 3 to 26 , and then a third mask layer 78 can be formed thereon. The third mask layer 78 can expose a single spacer 48 that was originally adjacent to the dummy channel region (e.g., 12d in Figure 22 .

[0057] With reference to Figure 41 , the single spacer in the spacers 48 can be removed until a third portion 44_1t of the first gate electrode 44_1 is exposed. Thereafter, the third mask layer 78 can be removed and a conductive layer can be formed to form the bottom source / drain contact 82, the extension portion 82e of the bottom source / drain contact 82, the first contact 84, and the second contact 86. The extension portion 82e of the bottom source / drain contact 82 can improve the electrical connection between the bottom source / drain contact 82 and the first gate electrode 44_1 by contacting the third portion 44_1t of the first gate electrode 44_1.

[0058] Example embodiments are described above with reference to the accompanying drawings. Many different forms and implementations are possible, and it is contemplated to be within the scope of the disclosure. Accordingly, the disclosure should not be construed as limited to the examples set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0059] Here, example embodiments of the inventive concept are described with reference to cross-sectional and / or plan views that are schematic cross-sectional and / or plan views of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, example embodiments of the inventive concept should not be construed as limited to the particular shapes of the regions and elements as illustrated, but are to include deviations in shapes that result from, for example, manufacturing. Thus, the example embodiments of the inventive concept are to be understood as not necessarily limited by the particular shape illustrated, but as including deviations in shapes that result from, for example, manufacturing.

[0060] Unless specifically defined otherwise, all terms (including technical and scientific terms) used herein are to be interpreted according to their ordinary meaning in the technical field of the inventive concept. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] It will be understood that references herein to "element A is vertically over element B" (or similar language) means that element A is positioned over element B with a vertical line intersecting both element A and element B. It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the inventive concept.

[0063] It should be noted that in some alternative implementations, the functions / acts described in the blocks of the flow diagrams herein can occur out of the order described in the flow diagrams. For example, two blocks shown in succession can in fact be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality / acts involved. Also, the functionality of a given block can be separated into multiple blocks and / or the functionality of two or more blocks can be combined into a single block, without departing from the scope of the present inventive concept. Finally, additional blocks can be added / inserted between the blocks shown in the flow diagrams, and / or blocks / operations can be omitted without departing from the scope of the present inventive concept.

[0064] The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other implementations falling within the true spirit and scope of the present inventive concept. Thus, to the maximum extent allowed by law, the scope of the present inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited to the abovementioned detailed description.

[0065] This application claims priority to U.S. Provisional Application Serial No. 62 / 913,261, filed October 10, 2019, in the U.S. Patent and Trademark Office, and entitled “Forming Self-Aligned Contacts in SRAM Active Area Employing Fin Structures,” and U.S. Application Serial No. 16 / 798,482, filed February 24, 2020, in the U.S. Patent and Trademark Office, and entitled “Integrated Circuit Device Including Vertical Field Effect Transistor (VFET) and Method of Forming the Same,” the disclosures of which are incorporated by reference herein in their entireties.

Claims

1. A method of forming an integrated circuit device, the method comprising: forming a dummy channel region and an active region of a substrate; forming a bottom source / drain region on the active region; forming a gate electrode on opposite side surfaces of the dummy channel region; forming a first spacer and a second spacer on the opposite side surfaces of the dummy channel region, respectively, wherein the gate electrode includes a first portion on one of the opposite side surfaces of the dummy channel region and a second portion between the bottom source / drain region and the first spacer; and forming a bottom source / drain contact by replacing the first portion of the gate electrode with a conductive material, wherein the bottom source / drain contact electrically connects the second portion of the gate electrode to the bottom source / drain region.

2. The method of claim 1, wherein forming the bottom source / drain contact comprises: forming a contact opening between the first spacer and the second spacer by removing the dummy channel region and the first portion of the gate electrode, wherein the contact opening exposes a portion of the bottom source / drain region; and forming the bottom source / drain contact in the contact opening.

3. The method of claim 2, wherein the contact opening exposes a side surface of the first spacer and a side surface of the second spacer.

4. The method of claim 2, further comprising forming a top source / drain region on the dummy channel region, wherein forming the contact opening further comprises removing the top source / drain region.

5. The method of claim 1, wherein the conductive material of the bottom source / drain contact comprises a metal.

6. The method of claim 1, wherein an upper surface of the bottom source / drain contact is closer to the substrate than upper surfaces of the first spacer and the second spacer.

7. The method of claim 1, wherein the bottom source / drain contact contacts a side surface of the first spacer and a side surface of the second portion of the gate electrode, and the side surface of the first spacer and the side surface of the second portion of the gate electrode are vertically aligned with each other.

8. The method of claim 1, wherein forming the bottom source / drain contact comprises: forming a contact opening between the first spacer and the second spacer by removing the first portion of the gate electrode, wherein the contact opening exposes the dummy channel region; adding an impurity element to the dummy channel region; and then forming a semiconductor layer comprising the impurity element in the contact opening, wherein the bottom source / drain contact includes the dummy channel region to which the impurity element is added and the semiconductor layer.

9. The method of claim 8, wherein the bottom source / drain region includes the impurity element.

10. The method of claim 8, wherein an upper surface of the semiconductor layer is coplanar with upper surfaces of the first spacer and the second spacer.

11. The method of claim 1, wherein forming the dummy channel region and the active region comprises: forming a mask layer on the substrate; forming the dummy channel region protruding from an upper surface of the substrate by etching the substrate using the mask layer as a first etch mask; forming a liner layer extending over the dummy channel region and the upper surface of the substrate; forming an active mask layer on the dummy channel region and the liner layer; and forming the active region by etching the liner layer and the substrate using the active mask layer as a second etch mask.

12. A method of forming an integrated circuit device, the method comprising: forming a bottom source / drain region on an active region of a substrate; forming a bottom spacer on the bottom source / drain region; forming a gate electrode on the bottom spacer; forming a first spacer and a second spacer on the bottom spacer, wherein a portion of the gate electrode is between the bottom spacer and the first spacer; and forming a bottom source / drain contact between the first spacer and the second spacer, wherein the bottom source / drain contact contacts both the gate electrode and the bottom source / drain region.

13. The method of claim 12, further comprising forming a dummy channel region and the active region on the substrate prior to forming the bottom spacer, wherein forming the gate electrode comprises forming the gate electrode on opposite side surfaces of the dummy channel region, wherein the gate electrode comprises a first portion on one of the opposite side surfaces of the dummy channel region and a second portion between the bottom source / drain region and the first spacer, and wherein forming the bottom source / drain contact comprises replacing the first portion of the gate electrode with a conductive material.

14. The method of claim 13, wherein forming the dummy channel region and the active region comprises: forming a mask layer on the substrate; forming the dummy channel region protruding from an upper surface of the substrate by etching the substrate using the mask layer as a first etch mask; forming a liner layer extending over the mask layer, the dummy channel region, and the upper surface of the substrate; forming an active mask layer on the dummy channel region and the liner layer; and forming the active region by etching the liner layer and the substrate using the active mask layer as a second etch mask.

15. The method of claim 12, wherein the bottom source / drain contact contacts both the first spacer and the second spacer.

16. The method of claim 13, wherein the first spacer comprises a side surface facing the second spacer, and wherein the side surface of the first spacer is perpendicularly aligned with a side surface of the second portion of the gate electrode.

17. The method of claim 12, wherein the bottom source / drain contact comprises a metallic layer.

18. The method of claim 17, wherein an upper surface of the bottom source / drain contact is closer to the substrate than an upper surface of the first spacer.

19. The method of claim 12, wherein the bottom source / drain contact comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, and both the first semiconductor layer and the second semiconductor layer comprise an impurity element of a first conductivity type.

20. The method of claim 19, wherein an upper surface of the bottom source / drain contact and an upper surface of the first spacer are coplanar with each other.

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