A semiconductor structure and a method for manufacturing the same

Abstract

The embodiment of the present invention relates to the field of memory manufacturing, and discloses a semiconductor structure and manufacturing method, including: providing a substrate, the substrate including an array area and a peripheral area; forming a first gate structure in the substrate in the array area; forming a dummy gate structure on the surface of the substrate in the peripheral area; forming a capacitor structure on the first gate structure; after forming the capacitor structure, removing the dummy gate structure in the peripheral area to form a groove; forming a second gate structure in the groove; the second gate structure includes, the second gate structure includes a high dielectric constant gate dielectric layer and a metal gate layer stacked in sequence. By replacing the peripheral area transistor with a high dielectric constant metal gate structure, the power consumption of the peripheral area of ​​DRAM can be reduced; at the same time, because the manufacturing process is to replace the gate of the peripheral area with the metal gate structure after forming the capacitor structure, it can effectively prevent the high temperature formation process that exists when forming the capacitor structure from affecting the electrical performance of the peripheral area transistor.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of memory manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] DRAM (Dynamic Random Access Memory) is the most common system memory. With the continuous development of semiconductor technology, the performance requirements for DRAM are getting higher and higher.

[0003] However, the inventors of the present invention have found that the gate structure of the transistors in the peripheral region of the current DRAM structure adopts a polysilicon gate structure, which has the problem of excessive power consumption in the peripheral region and an excessively large area in the peripheral region. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which replaces the gate structure of the transistor in the peripheral area of ​​the current DRAM structure from a polysilicon gate structure to a metal gate structure with a high dielectric constant, thereby reducing the power consumption of the DRAM peripheral area.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including an array area and a peripheral area; forming a first gate structure in the substrate in the array area; forming a dummy gate structure on the surface of the substrate in the peripheral area; forming a capacitor structure on the interlayer dielectric layer on the first gate structure; after the capacitor structure is formed, removing the dummy gate structure in the peripheral area to form a groove; forming a second gate structure in the groove, the second gate structure including a high dielectric constant gate dielectric layer and a metal gate layer stacked in sequence.

[0006] An embodiment of the present invention also provides a semiconductor structure, including: a substrate, the substrate including an array area and a peripheral area; a first gate structure, located in the substrate in the array area; a second gate structure, located on the substrate in the peripheral area, the second gate structure including a high dielectric constant gate dielectric layer and a metal gate layer stacked in sequence; and a capacitor structure, located on the first gate structure.

[0007] Compared with the prior art, the embodiments of the present invention replace the polysilicon gate structure of the transistors in the peripheral area of ​​the current DRAM structure with a metal gate structure with a high dielectric constant. By replacing the polysilicon gate structure of the transistors in the peripheral area with a metal gate structure with a high dielectric constant, the power consumption of the DRAM peripheral area can be reduced; at the same time, since the polysilicon gate structure in the peripheral area is replaced with a metal gate structure with a high dielectric constant after the capacitor structure is formed in the manufacturing process, the electrical performance of the transistors in the peripheral area can be effectively prevented from being affected by the high temperature formation process when the capacitor structure is formed.

[0008] In addition, before forming the capacitor structure on the first gate structure, it also includes: forming a first interlayer dielectric layer on the top surface of the peripheral area and the array area; after forming the first interlayer dielectric layer, forming a capacitor structure on the first interlayer dielectric layer on the first gate structure.

[0009] In addition, after forming the capacitor structure and before removing the dummy gate structure in the peripheral area, the method specifically includes: forming a second interlayer dielectric layer covering the capacitor structure in the peripheral area and the array area.

[0010] In addition, the process step of removing the dummy gate structure in the peripheral region also includes: etching and removing the second interlayer dielectric layer located on the top of the dummy gate structure; etching and removing the dummy gate structure to form a groove.

[0011] In addition, the process steps of forming the second gate structure in the groove include: forming a high dielectric constant gate dielectric layer at the bottom and sidewalls of the groove; forming a metal gate layer on the high dielectric constant gate dielectric layer, and the metal gate structure fills the groove.

[0012] Specifically, a metal gate layer is formed on a gate dielectric layer, and the process step of the metal gate layer filling the groove includes: forming a first metal gate layer on the gate dielectric layer; forming a second metal gate layer on the first metal gate layer, the second metal gate layer filling the groove, and the resistivity of the second metal gate layer is less than the resistivity of the first metal gate layer. The purpose of this is: how to form a metal gate structure with a high dielectric constant in the groove formed above, because the metal gate structure with a high dielectric constant consumes less power than the polysilicon gate structure, so a DRAM using a peripheral transistor using a metal gate structure with a high dielectric constant can reduce the power consumption of the DRAM peripheral area.

[0013] In addition, a dummy gate structure is formed in the peripheral region, specifically including: forming a dummy gate structure with the same width in the peripheral region according to the preset width of the second gate structure to be formed. The purpose of this is: under the condition of playing the same electrical function, the metal gate structure with a high dielectric constant has a smaller width than the polysilicon gate structure. Therefore, when forming the dummy gate structure, it is set according to the preset width of the second gate structure, so that the area occupied by the peripheral region is smaller, and the corresponding array area is larger. The ratio of the array area to the peripheral area will increase, which improves the problem of the current DRAM peripheral area being too large.

[0014] Additionally, the first gate structure includes a metal gate structure.

[0015] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages: reducing the power consumption of the DRAM peripheral area; improving the current problem of the DRAM peripheral area being too large; and at the same time, in the manufacturing process, effectively preventing the high temperature formation process when forming the capacitor structure from affecting the electrical performance of the peripheral area transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0017] Figure 1-Figure 8 A schematic cross-sectional structure diagram corresponding to each step in the method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0018] Fig. 9 A specific formation process of the second gate structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0019] Fig.10 A schematic diagram of a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In the current DRAM structure, the gate structure of the transistor in the peripheral area adopts a polysilicon gate structure, which has the problem of excessive power consumption in the peripheral area.

[0021] If the gate structure of the transistors in the peripheral area of ​​the DRAM structure is improved, the gate structure of the transistors in the peripheral area of ​​the current DRAM structure is replaced by a metal gate structure with a high dielectric constant from a polysilicon gate structure, the power consumption of the DRAM peripheral area can be reduced; at the same time, because the manufacturing process replaces the polysilicon gate structure in the peripheral area with a metal gate structure with a high dielectric constant after the capacitor structure is formed, it can effectively prevent the high temperature formation process that exists when forming the capacitor structure from affecting the electrical performance of the transistors in the peripheral area.

[0022] To solve the above problems, an embodiment of the present invention provides a semiconductor structure manufacturing method, including: providing a substrate, the substrate including an array area and a peripheral area; forming a first gate structure in the substrate in the array area; forming a dummy gate structure on the surface of the substrate in the peripheral area; forming a capacitor structure on the first gate structure; after forming the capacitor structure, removing the dummy gate structure in the peripheral area to form a groove; forming a second gate structure in the groove; the second gate structure includes a high dielectric constant gate dielectric layer and a metal gate layer stacked in sequence. In this way, the power consumption of the DRAM peripheral area can be reduced; at the same time, in the manufacturing process, it can effectively prevent the high temperature formation process that exists when forming the capacitor structure from affecting the electrical performance of the transistor in the peripheral area.

[0023] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and quoted from each other without contradiction.

[0024] The first embodiment of the present invention relates to a method for manufacturing a semiconductor structure. The core of this embodiment is to improve the gate structure of transistors in the peripheral area of ​​the DRAM structure, and replace the gate structure of the transistors in the peripheral area of ​​the current DRAM structure with a metal gate structure with a high dielectric constant.

[0025] The implementation details of the semiconductor structure manufacturing method of this embodiment are specifically described below. The following content is only provided for the convenience of understanding the implementation details and is not necessary for implementing this solution.

[0026] refer to Figure 1 , a substrate 101 is provided, and the substrate 101 includes an array region 110 and a peripheral region 100 .

[0027] The array region 110 is used to manufacture capacitor structures and array transistors having a first gate structure; the peripheral region 100 is used to manufacture control circuits, including peripheral transistors having a second gate structure.

[0028] An isolation structure is formed in the substrate of the array region 110 and the peripheral region 100, and the isolation structure plays an isolation role. Specifically, in the present embodiment, the isolation structure adopts a shallow trench isolation groove. It should be noted that the use of the shallow trench isolation groove in the isolation structure is only an example of the isolation structure of the present embodiment, and does not constitute a limitation. In other embodiments, the isolation structure can also flexibly use other structures according to actual needs, which are not exemplified here.

[0029] A well region is formed in the substrate 101 adjacent to the isolation trench 103 , and the well region includes a first well region 102 and a second well region 112 .

[0030] The first well region 102 is located between adjacent isolation trenches 103 in the peripheral region 100; the second well region 112 is located between adjacent isolation trenches 103 in the array region 110. It should be noted that when the peripheral transistor is NMOS, the first well region 102 is a P well; when the peripheral transistor is PMOS, the first well region 102 is an N well. Similarly, when the array transistor is NMOS, the second well region 112 is a P well; when the array transistor is PMOS, the second well region 112 is an N well.

[0031] refer to Figure 2 , a dummy gate structure 201 is formed on the surface of the substrate 101 in the peripheral region 100 , and a first gate structure 300 is formed in the substrate 101 in the array region 110 .

[0032] In this embodiment, the dummy gate structure 201 of the peripheral region 100 and the first gate structure 300 of the array region 110 are formed in different process steps respectively.

[0033] A dummy gate structure 201 is formed on the first well region 102 on the peripheral region 100. Specifically, the dummy gate structure 201 is manufactured using a gate-first process. After the dummy gate structure 201 is manufactured, a sidewall 204 is formed on the sidewall of the dummy gate 201, and doped regions are formed in the substrate 101 on both sides of the dummy gate structure 201, which serve as a source 202 and a drain 203 of the peripheral transistor, respectively.

[0034] The first gate structure 300 is formed on the second well region 112 in the array region 110. Specifically, the first gate structure 300 is made by a buried gate process. After the first gate structure 300 is made, the source and drain of the array transistor are formed in the second well region 112.

[0035] It should be noted that, in this embodiment, the dummy gate structure 201 is a polysilicon gate structure, and the first gate structure 300 is a metal gate structure. In other embodiments, the first gate structure may also be a polysilicon gate structure, and accordingly, the dummy gate structure in the peripheral region and the first gate structure in the array region may be formed in the same process step.

[0036] The dummy gate structure 201 on the peripheral transistor on the peripheral region 100 will be replaced by the second gate structure after the capacitor structure is subsequently formed. Therefore, the width of the dummy gate structure 201 can be determined according to the preset width of the second gate structure to be formed, and the width of the dummy gate structure is the same as the preset width. In the case of achieving the same electrical function, a metal gate structure with a high dielectric constant, i.e., the second gate structure, is used, and the width of the gate structure required is smaller than the width of the gate structure when a polysilicon gate structure is used.

[0037] Since the width of the second gate structure of the peripheral transistor is smaller, the size of its peripheral region 100 can be correspondingly reduced; the area of ​​the corresponding array region 110 will become larger, and the area ratio of the array region 110 to the peripheral region 100 will be larger, thereby improving the utilization rate of the DRAM array area and solving the problem of excessively large peripheral area in the current DRAM structure.

[0038] refer to Figure 3 , a first interlayer dielectric layer 401 is formed on the top surface of the peripheral region 100 and the array region 110. It should be noted that in this figure and the subsequent cross-sectional diagrams, the source and drain of the array transistor are not shown. At the same time, it should be clear to those skilled in the art that the corresponding drawings only show the structure and manufacturing of the corresponding parts, and do not limit the proportions of the components in the drawings.

[0039] In this embodiment, the first interlayer dielectric layer 401 is a single-layer structure. It should be noted that the single-layer structure of the first interlayer dielectric layer 401 in this embodiment is only an example of this embodiment and does not constitute a limitation. In other embodiments, the first interlayer dielectric layer can be set to a multi-layer structure, which can be flexibly set according to specific applications.

[0040] The first interlayer dielectric layer 401 further includes a capacitor contact window 307 located in the first interlayer dielectric layer 401. In this embodiment, the capacitor contact window 307 can be formed before the first interlayer dielectric layer 401 is formed, specifically as follows: the first interlayer dielectric layer 401 is set at the height of the capacitor contact window 307 to cover the top surface of the entire array area 110 and the peripheral area 100.

[0041] In other embodiments, the capacitor contact window 307 can also be formed after the first interlayer dielectric layer 401 is formed, by etching the first interlayer dielectric layer 401 to form a capacitor contact through hole, then filling the capacitor contact through hole with a conductive material, and then etching the conductive material in the capacitor contact through hole so that its top surface is flush with the top surface of the first interlayer dielectric layer 401, thereby forming the capacitor contact window 307.

[0042] Before forming the first interlayer dielectric layer 401, a bit line structure 301 and a word line structure may also be formed. Two first gate structures 300 are formed between two adjacent isolation grooves 103 in the second well region 112 as buried word line structures, i.e., gate structures of array transistors, and corresponding sources and drains are formed in the second well region 112; a bit line structure 301 is formed on the second well region 112 between the two buried word line structures, and a capacitor contact window 307 is formed on the second well region 112 between the buried word line structure and the isolation groove 103.

[0043] refer to Figure 4 After forming the first interlayer dielectric layer 401 , it is necessary to form a third interlayer dielectric layer 402 on the first interlayer dielectric layer 401 for subsequent manufacturing of a capacitor structure.

[0044] Specifically, a third interlayer dielectric layer 402 is formed on the first interlayer dielectric layer 401 to cover the capacitor contact window 307 and the top surface of the first interlayer dielectric layer 401 , and then the third interlayer dielectric layer 402 is etched to form a capacitor groove to expose the top surface of the capacitor contact window 307 .

[0045] It should be noted that the first interlayer dielectric layer 401 and the third interlayer dielectric layer 402 may be made of the same material or different materials. Figure 5 After forming the third interlayer dielectric layer 402 , a capacitor structure 500 is formed in the capacitor groove in the third interlayer dielectric layer 402 .

[0046] refer to Figure 5 The capacitor structure 500 is located on the top surface of the capacitor contact window 307 , and the capacitor structure 500 is connected to one end of the source or drain of the array transistor through the capacitor contact window 307 .

[0047] The capacitor structure includes: a first electrode plate 501, a capacitor dielectric layer 502 and a second electrode plate 503 which are stacked in sequence.

[0048] A first electrode plate 501 is formed on the top surface of the capacitor contact window 307 and the sidewall of the third interlayer dielectric layer 402 .

[0049] In this embodiment, the material of the first electrode plate 501 is a metal nitride. It is understandable that the material of the first electrode plate 501 is a metal nitride, which is only a specific example of this embodiment and does not constitute a limitation. Any other material that can be used as a capacitor electrode plate can be used as the first electrode in the present invention, such as silver, copper and other metals, which are not listed here one by one.

[0050] Specifically, in the present embodiment, the material of the first electrode plate 501 is titanium nitride. Since titanium nitride has good electrical conductivity and chemical stability, the use of titanium nitride as the first electrode plate 501 can ensure that the capacitor structure has good electrical properties and the stability of the capacitor structure. It is understandable that the material of the first electrode plate 501 is titanium nitride, which is only an example of the material of the first electrode plate 501 in the present embodiment, and does not constitute a limitation. In other embodiments of the present invention, the first electrode plate 501 may also be other materials such as zirconium nitride, which are not listed one by one here, and can be used flexibly according to actual needs.

[0051] A capacitor dielectric layer 502 is formed on the surface of the first electrode plate 501 and the surface of the third interlayer dielectric layer 402 .

[0052] In this embodiment, the material of the capacitor dielectric layer 502 is oxide. It should be noted that the material of the capacitor dielectric layer 502 is oxide, which is only an example of the material of the capacitor dielectric layer 502 in this embodiment, and does not constitute a limitation. In other embodiments of the present invention, the capacitor dielectric layer 502 may also be other materials, such as silicon nitride, boron nitride, etc., which are not listed here one by one.

[0053] Specifically, in this embodiment, the material of the capacitor dielectric layer 502 is zirconium dioxide. Since zirconium dioxide has a high dielectric constant and good insulation, the use of zirconium dioxide as the capacitor dielectric layer 502 can make the capacitance value larger. In addition, zirconium dioxide has stable chemical properties, which can effectively improve the stability of the capacitor structure.

[0054] A second electrode plate 503 is formed on the surface of the capacitor dielectric layer 502 .

[0055] The material of the second electrode plate 503 is the same as that of the first electrode plate 501 , and will not be described here one by one. Specifically, in this embodiment, the material of the second electrode plate 503 is titanium nitride.

[0056] Continue to refer Figure 5 After forming the capacitor structure 500 , a conductive layer 504 is manufactured on the capacitor structure. The conductive layer 504 is used to manufacture electrodes to connect the capacitor structure 500 .

[0057] It should be noted that the capacitor structure 500 is connected to the source or drain of the array transistor through the capacitor contact window 307. Accordingly, if the capacitor structure 500 is connected to the source of the array transistor, the drain of the array transistor will be connected to the bit line structure 301 to form a DRAM structure in which a capacitor is connected to a transistor; if the capacitor structure 500 is connected to the drain of the array transistor, the source of the array transistor will be connected to the bit line structure 301 to form a DRAM structure in which a capacitor is connected to a transistor.

[0058] After forming the capacitor structure 500 and before removing the dummy gate structure in the peripheral area, a second interlayer dielectric layer 403 covering the capacitor structure 500 is further formed on the peripheral area 100 and the array area 110 to protect the capacitor structure 500. The material of the second interlayer dielectric layer includes borophosphosilicate glass, namely BPSG.

[0059] refer to Figure 6 , removing the dummy gate structure 201 in the peripheral region 100 to form a groove 601; specifically including: etching and removing the first interlayer dielectric layer 401 located on the top of the dummy gate structure 201 and etching and removing the dummy gate structure 201.

[0060] Specifically, refer to Figure 6 , the second interlayer dielectric layer 403 , the third interlayer dielectric layer 402 and the first interlayer dielectric layer located on the top of the dummy gate structure 201 are etched and removed.

[0061] The second interlayer dielectric layer 403 , the third interlayer dielectric layer 402 and the first interlayer dielectric layer 401 located on the top of the dummy gate structure 201 are removed by etching, and the height of the interlayer dielectric layer after etching is consistent with the height of the dummy gate structure 201 .

[0062] refer to Figure 7 , the dummy gate structure 201 is removed by etching to form a groove 601 .

[0063] Specifically, the method of etching to form the groove 601 includes: forming a patterned photoresist layer, the patterned photoresist layer covers the second interlayer dielectric layer 403 of the array area 110, and is also located on a portion of the substrate of the peripheral area 100; using the patterned photoresist layer as a mask, etching and removing the pseudo gate structure 201 of the peripheral area 100 to form the groove 601, and removing the patterned photoresist layer.

[0064] refer to Figure 8 , a second gate structure 602 is formed in the groove 601 .

[0065] Specifically, refer to Fig. 9 The process steps for forming the second gate structure 602 in the groove 601 include: forming a high dielectric constant gate dielectric layer 801 at the bottom and sidewalls of the groove; forming a metal gate layer on the gate dielectric layer, the metal gate layer fills the groove, and the second gate structure 602 is formed in the groove 601.

[0066] In this embodiment, the material of the high dielectric constant gate dielectric layer 801 is a high dielectric constant material, such as elements with high dielectric constants such as Hf, La, Ti and Zr or their oxides, and dopants such as Si and N may also be used.

[0067] A metal gate layer is formed on the high-k gate dielectric layer 801, and the metal gate layer fills the groove to complete the formation of the second gate structure 602 in the groove 601, specifically including:

[0068] A first metal gate layer 802 is formed on the high-k gate dielectric layer 801 .

[0069] It should be noted that if applied to an NMOS tube, the material of the first metal gate layer 802 is a low work function material; if applied to a PMOS tube, the material of the first metal gate layer 802 is a high work function material. In this embodiment, taking the application to a PMOS tube as an example, the material of the first metal gate layer 802 is a high work function material, and it can also be applied to an NMOS tube in other embodiments, and can be used flexibly according to actual needs. It should also be noted that the high work function material includes elements with high work functions such as Ti or Ta or their nitrides, and alloys of Ti, Al or other elements can also be used.

[0070] A second metal gate layer 803 is formed on the first metal gate layer 802, and the second metal gate layer 803 fills the remaining groove position after the first metal gate layer 802 is formed, and the second gate structure 602 is formed in the groove 601. The resistivity of the second metal gate layer 803 is less than the resistivity of the first metal gate layer 801, and is used to reduce the resistance of the entire second gate structure 602, thereby reducing the power consumption of the DRAM peripheral transistors by reducing the resistance.

[0071] After the second gate structure is formed, the high dielectric constant gate dielectric layer and the metal gate layer on the sidewall 204 and the top of the groove 601 are etched away.

[0072] Specifically, after the second metal gate layer 803 is manufactured, the high dielectric constant gate dielectric layer 801, the first metal gate layer 802 and the second metal gate layer 803 on the top surface of the first interlayer dielectric layer 401 are removed by etching, so that the gate structure of the peripheral transistor on the peripheral area 100 is replaced.

[0073] refer to Fig.10 After completing the replacement of the gate structure of the peripheral transistor on the peripheral area 100, a second interlayer dielectric layer 403 is formed on the substrate 101 of the peripheral area 100, and the height of the second interlayer dielectric layer 403 formed in the peripheral area is consistent with the height of the interlayer dielectric layer 403 formed in the array area 110.

[0074] After the second interlayer dielectric layer 403 is formed in the peripheral area 100, the second interlayer dielectric layer 403 and the first interlayer dielectric layer 401 in the peripheral area 100 are etched to form a through hole 901, which respectively exposes the source 202, the drain 203 and the second metal gate layer in the second gate structure 602 of the peripheral transistor.

[0075] Compared with the existing technology, the peripheral transistors used in DRAM use a second gate structure (i.e., a metal gate structure with a high dielectric constant) which has a lower EOT value than the polysilicon gate structure, i.e., its equivalent oxide thickness is thinner, which can effectively reduce the gate capacitance of the transistor and thus obtain a larger state current.

[0076] At the same time, a low EOT value can improve the threshold voltage Vt of the transistor. At the same time, since the width of the second gate structure of the peripheral transistor is smaller than that of the polysilicon gate structure, the size of the peripheral transistor can be made smaller. On the same substrate, the area of ​​the array area is larger, so that the area ratio of the array area to the peripheral area is high, thereby increasing the proportion of the array area in the DRAM, thereby improving the utilization efficiency of the array area of ​​the DRAM.

[0077] In addition, compared with the polysilicon gate structure, the gate oxide thickness of the second gate structure is thicker in a physical sense, which can effectively reduce the leakage current of the gate channel.

[0078] In addition, the metal gate material of the second gate structure uses a material with a lower resistivity, which can effectively reduce the resistance of the metal gate, thereby reducing the power consumption of the DRAM peripheral transistors.

[0079] The second gate structure of the first embodiment of the present invention is formed by etching away the polysilicon gate structure in the peripheral area after the capacitor structure is manufactured, and then adopting the gate-last process, which can effectively prevent the high temperature formation process when forming the capacitor structure from affecting the electrical performance of the transistor in the peripheral area.

[0080] The above-mentioned various steps are divided only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this patent. Adding insignificant modifications to the process or introducing insignificant designs that do not change the core design of the process are all within the protection scope of this patent.

[0081] A second embodiment of the present invention relates to a semiconductor structure, referring to Fig.10 ,include:

[0082] The substrate 101 includes an array region 110 and a peripheral region 100 .

[0083] The first gate structure 300 is located in the substrate 101 in the array region 110 .

[0084] The second gate structure 602 is located on the substrate 101 in the peripheral region 100 .

[0085] The capacitor structure 500 is located on the first gate structure 300 , specifically, on the first interlayer dielectric layer 401 on the first gate structure 300 .

[0086] Specifically, the first gate structure 300 includes a metal gate structure.

[0087] Specifically, the second gate structure 602 specifically includes: a high dielectric constant gate dielectric layer, located on the substrate 101 of the peripheral area 100; a first metal gate layer, located on the top surface of the high dielectric constant gate dielectric layer; a second metal gate layer, located on the top surface of the first metal gate layer; wherein the resistivity of the second metal gate layer is less than the resistivity of the first metal gate layer.

[0088] Specifically, the interlayer dielectric layer includes a first interlayer dielectric layer 401, a second interlayer dielectric layer 403 and a third interlayer dielectric layer 402. The first interlayer dielectric layer 401 is used to cover the word line and bit line structure on the array area 110, and is used to form a DRAM structure in which a capacitor is connected to an array transistor. The third interlayer dielectric layer 402 is used to form a capacitor groove, and a capacitor structure 500 is formed in the capacitor groove. The second interlayer dielectric layer 403 covers the entire substrate 101, protects the capacitor structure 500 and the array transistor on the array area 110, and etches a through hole 901, which respectively exposes the source 202, the drain 203 of the peripheral transistor and the second metal gate layer in the second gate structure 602.

[0089] Specifically, the capacitor structure 500 includes a first electrode plate 503, a second electrode plate 502 and a capacitor dielectric layer 501. The first electrode plate 503 is located on the side wall of the capacitor contact window 307, i.e., the third interlayer dielectric layer 502. The capacitor dielectric layer 501 is located on the surface of the first electrode plate 503 and the third interlayer dielectric layer 502. The third electrode plate 502 is located on the surface of the capacitor dielectric layer 501. A conductive layer 504 is also formed on the capacitor structure 500 for manufacturing an electrode connected to the capacitor structure 500.

[0090] The gate structure of the peripheral transistor is made of the second gate structure 602, that is, a metal gate structure with a high dielectric constant. Compared with the polysilicon gate structure, the metal gate structure with a high dielectric constant has a lower EOT value, that is, its equivalent oxide thickness is thinner, which can effectively reduce the gate capacitance of the transistor, thereby obtaining a larger state current. At the same time, the low EOT value can improve the threshold voltage Vt of the transistor, and can make the size of the peripheral transistor smaller. On the same substrate, the area of ​​the array area is larger, so that the area ratio of the array area to the peripheral area is high, and the proportion of the array area in the semiconductor structure is increased, thereby improving the utilization efficiency of the array area of ​​the semiconductor structure.

[0091] In addition, compared with the dummy gate structure, the gate oxide thickness of the second gate structure is thicker in a physical sense, which can effectively reduce the leakage current of the gate channel.

[0092] In addition, the metal gate material of the second gate structure uses a material with a low resistivity, which can effectively lower the resistance of the second gate structure and reduce the power consumption of the peripheral area.

[0093] In order to highlight the innovative part of the present invention, the present embodiment does not introduce structures that are not closely related to solving the technical problems proposed by the present invention, but this does not mean that there are no other structures in the present embodiment.

[0094] Since the first embodiment and the present embodiment correspond to each other, the present embodiment can be implemented in conjunction with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in the present embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in the present embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in the present embodiment can also be applied in the first embodiment.

[0095] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present invention, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a first gate structure in the substrate in the array region; forming a dummy gate structure on the surface of the substrate in the peripheral region; forming a capacitor structure on the first gate structure; After forming the capacitor structure, removing the dummy gate structure in the peripheral area to form a groove; forming a second gate structure in the groove, the second gate structure comprising a high dielectric constant gate dielectric layer and a metal gate layer stacked in sequence; Before forming the capacitor structure on the first gate structure, the method further includes: forming a first interlayer dielectric layer on the peripheral region and the top surface of the array region; After forming the first interlayer dielectric layer, forming the capacitor structure on the first interlayer dielectric layer on the first gate structure; the capacitor structure includes: a first electrode plate, a capacitor dielectric layer and a second electrode plate stacked in sequence.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After forming the capacitor structure and before removing the dummy gate structure in the peripheral area, the method further includes: A second interlayer dielectric layer covering the capacitor structure is formed in the peripheral region and the array region.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The process step of removing the dummy gate structure in the peripheral region includes: The second interlayer dielectric layer located on the top of the dummy gate structure is removed by etching; and the dummy gate structure is removed by etching to form a groove.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process step of forming the second gate structure in the groove includes: The high dielectric constant gate dielectric layer is formed at the bottom and sidewall of the groove; a metal gate layer is formed on the high dielectric constant gate dielectric layer, and the metal gate layer completely fills the groove.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The process step of forming a metal gate layer on the gate dielectric layer, wherein the metal gate layer fills the groove, comprises: forming a first metal gate layer on the gate dielectric layer; A second metal gate layer is formed on the first metal gate layer, the second metal gate layer completely fills the groove, and the resistivity of the second metal gate layer is less than the resistivity of the first metal gate layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of a dummy gate structure on the peripheral region specifically includes: According to the preset width of the second gate structure to be formed, the dummy gate structure with the same width is formed in the peripheral region.

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