Semiconductor structure and method for manufacturing the same

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and a seed layer located on the substrate, wherein the substrate includes a base material and a composite material layer encapsulating the base material. The semiconductor structure also includes an epitaxial layer located on the seed layer. The semiconductor structure also includes a semiconductor element located on the epitaxial layer, and an interlayer dielectric layer located on the epitaxial layer and covering the semiconductor element. The semiconductor structure further includes a through-hole structure that at least passes through the composite material layer of the substrate and contacts the base material to enhance the electrical performance of the semiconductor element.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure with a through-hole structure and a manufacturing method thereof. Background Art

[0002] In recent years, semiconductor structures have developed rapidly in the fields of computers, consumer electronics, etc. At present, semiconductor structure technology has been widely accepted in the product market of metal oxide semiconductor field effect transistors, with a high market share. Semiconductor structures are used in various electronic applications, such as high-power devices, personal computers, mobile phones, digital cameras and other electronic devices. These semiconductor structures are generally manufactured by depositing an insulating layer or dielectric layer, a conductive layer material and a semiconductor layer material on a semiconductor substrate, and then patterning the various material layers using a photolithography process. Therefore, circuit devices and components are formed on the semiconductor substrate.

[0003] Among these devices, high-electron mobility transistors (HEMTs) have advantages such as high output power and high breakdown voltage, so they are widely used in high-power applications. Although existing semiconductor structures and their formation methods can cope with their originally intended uses, they still have problems that need to be overcome in various technical aspects of their structures and methods. Summary of the invention

[0004] Some embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a substrate and a seed layer located on the substrate, wherein the substrate includes a base material and a composite material layer encapsulating the base material. The semiconductor structure also includes an epitaxial layer located on the seed layer. The semiconductor structure also includes a semiconductor element located on the epitaxial layer, and an interlayer dielectric layer located on the epitaxial layer and covering the semiconductor element. The semiconductor structure further includes a through-hole structure that at least passes through the composite material layer of the substrate and contacts the base material.

[0005] Some embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising providing a substrate, the substrate comprising a substrate and a composite material layer sealing the substrate. The above-mentioned manufacturing method also comprises forming a seed layer on the substrate, and forming an epitaxial layer on the seed layer. The above-mentioned manufacturing method also comprises forming a semiconductor element on the epitaxial layer, and forming an interlayer dielectric layer on the epitaxial layer, wherein the interlayer dielectric layer covers the semiconductor element. The above-mentioned manufacturing method further comprises forming a through hole structure at least passing through the composite material layer of the substrate and contacting the substrate.

[0006] In order to make the features and advantages of the embodiments of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1K Schematic cross-sectional views of various intermediate stages of a process for forming a semiconductor structure according to some embodiments of the present invention.

[0008] FIG. 2A to FIG. 2C Further explanation of the formation Figure 1G One of the applicable processes for the opening shown.

[0009] Figure 3 A partial enlarged schematic diagram of a through hole structure in a semiconductor structure according to some embodiments of the present invention is shown.

[0010] Figure 4 Schematic diagram of an active region, a peripheral region and a scribe line of a semiconductor structure according to some embodiments of the present invention.

[0011] Explanation of symbols:

[0012] 102~Substrate;

[0013] 102 M ~ Composite material layer;

[0014] 1021~first oxide layer;

[0015] 1022~polysilicon layer;

[0016] 1023~second oxide layer;

[0017] 1024~nitride layer;

[0018] 102 C ~ substrate;

[0019] 104~seed layer;

[0020] 106~buffer layer;

[0021] 108~channel layer;

[0022] 110~Barrier layer;

[0023] 111~Epitaxial layer;

[0024] 112P~ doped III-V semiconductor layer;

[0025] 112~gate electrode;

[0026] 114~first insulating layer;

[0027] 115~second insulating layer;

[0028] S D ~Semiconductor components;

[0029] IL M ~Interlayer dielectric layer;

[0030] 116~source electrode;

[0031] 118~drain electrode;

[0032] 124~third insulating layer;

[0033] 130~Multi-layer mask;

[0034] 132~first mask layer;

[0035] 134~second mask layer;

[0036] 136~patterned third mask layer;

[0037] 210~Etching process;

[0038] 210A, 210B, 230A, 230B, 230C, 250~ etching steps;

[0039] 140A, 140B, 140B1, 140B2, 140C, 140D ~ opening;

[0040] 143~through hole structure;

[0041] 150~Metal layer;

[0042] 152V, 154V~guide hole;

[0043] 152M, 154M, 156~Metal part;

[0044] W ~ width;

[0045] H ~ depth;

[0046] A P ~Surrounding area;

[0047] A A ~ Active area;

[0048] A S1 , A S2 , A D ~ area;

[0049] L S ~ Cutting Road. DETAILED DESCRIPTION

[0050] The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to represent the relationship between the different embodiments discussed.

[0051] Furthermore, spatially relative terms such as "below", "beneath", "below", "above", "upper" and other similar terms may be used in the following description to simplify the relationship of one element or component to other elements or components as shown in the figures. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0052] Some variations of the embodiments are described below. In the various drawings and illustrated embodiments, similar reference numerals are used to indicate similar elements. It is understood that additional steps may be provided before, during, or after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

[0053] Embodiments of the present invention provide semiconductor structures and methods for manufacturing the same. In some embodiments, the semiconductor structure has a through-hole structure that passes through at least the composite material layer of the substrate and contacts the substrate. In some embodiments, the through-hole structure may include an insulating material to serve as an isolation for a certain active region or one or more semiconductor elements in the active region. In some other embodiments, the through-hole structure may include a conductive material, such as a metal conductor or polysilicon, to serve as a certain active region A. AOr it can be used for grounding and heat dissipation of one or more semiconductor elements in the active region, thereby improving the electrical performance of the semiconductor element. Furthermore, according to the manufacturing method proposed in some embodiments, a through-hole structure with a small size and sufficient depth can be produced, that is, a through-hole structure with a high aspect ratio, so that the through-hole structure of the embodiment can be formed without affecting the area of ​​the original semiconductor structure very much or almost at all, and the electrical performance of the applied semiconductor structure can be significantly improved. In some of the following embodiments, a high-electron mobility transistor (HEMT) is used as an example of a semiconductor structure, but it is not limited to this. Some embodiments of the present invention can also be used for other types of semiconductor devices.

[0054] Figures 1A to 1K Schematic cross-sectional views of various intermediate stages of a process for forming a semiconductor structure according to some embodiments of the present invention. Figure 1A , providing a substrate 102. According to some embodiments, the substrate 102 includes a base material 102 C and encapsulate the substrate 102 C A composite material layer 102 M For example, the composite material layer 102 M Covering the substrate 102 C In some embodiments, the substrate 102 C The ceramic material includes a metal inorganic material. In some embodiments, the substrate 102 C The substrate 102 may include silicon carbide, aluminum nitride (AlN), sapphire substrate or other suitable materials. The sapphire substrate is aluminum oxide. In some embodiments, the substrate 102 is covered with C The composite material layer 102 around M It may include a single or multiple insulating material layer and / or other suitable material layers, such as a semiconductor layer. The insulating material layer is, for example, an oxide, a nitride, a nitride oxide, or other suitable insulating materials. The semiconductor layer is, for example, a polysilicon layer. To simplify the diagram, Figures 1A to 1K Only a single insulating material layer 102 is shown. M , in order to clearly illustrate the process of the through-hole structure.

[0055] Next, refer to Figure 1A , a seed layer 104 is formed on the substrate 102 , and an epitaxial layer 111 is formed on the seed layer 104 .

[0056] In some embodiments, the seed layer 104 may be formed of silicon (Si) or other suitable materials. In some embodiments, the method of forming the seed layer 104 may include a selective epitaxy growth (SEG) process, a chemical vapor deposition (CVD) process, a molecular beam epitaxy process (MBE), a solid-phase epitaxial recrystallization (SPER) step after depositing a doped amorphous semiconductor (e.g., Si), a method of directly transferring a seed, or other suitable processes. The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, or other suitable processes.

[0057] In some embodiments, the epitaxial layer 111 of the high electron mobility transistor structure includes a buffer layer 106, a channel layer 108, and a barrier layer 110.

[0058] In some embodiments, the buffer layer 106 is epitaxially grown on the seed layer 104. The buffer layer 106 can help reduce the strain of a subsequent channel layer 108 formed above the buffer layer 106 and prevent defects from forming in the upper channel layer 108. In some embodiments, the material of the buffer layer 106 is AlN, GaN, AlxGa1-xN (1 < x < 1), a combination of the foregoing, or a similar material. In some embodiments, the buffer layer 106 may be formed by a hydride vapor phase epitaxy (HVPE) method, a molecular beam epitaxy (MBE) method, a metalorganic chemical vapor deposition (MOCVD) method, a combination of the foregoing methods, or a similar method. Although in the embodiments shown as Figure 1A the buffer layer 106 is a single-layer structure, in some other embodiments, the buffer layer 106 may also be a multi-layer structure.

[0059] Next, a channel layer 108 is epitaxially formed on the buffer layer 106. In some embodiments, the channel layer 108 includes an undoped group III-V semiconductor material. For example, the channel layer 108 may be formed of undoped gallium nitride (GaN), but the present invention is not limited thereto. In some other embodiments, the channel layer 108 includes AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable group III-V materials, or a combination of the above. In some embodiments, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metalorganic chemical vapor deposition (MOCVD), other suitable methods, or a combination of the above methods may be used to form the channel layer 108.

[0060] After that, a barrier layer 110 is epitaxially formed on the channel layer 108. In some embodiments, the barrier layer 110 includes an undoped group III-V semiconductor material. For example, the barrier layer 110 is formed of undoped aluminum gallium nitride (AlxGa1-xN, where 0 < x < 1), but the present invention is not limited thereto. In some other embodiments, the barrier layer 110 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable group III-V materials, or a combination of the above. For example, molecular beam epitaxy, metalorganic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the above methods may be used to form the barrier layer 110 on the channel layer 108.

[0061] In some embodiments, the channel layer 108 and the barrier layer 110 include different materials to form a heterojunction interface between the channel layer 108 and the barrier layer 110. Through the band gap difference of the heteromaterial, a two-dimensional electron gas (2DEG) (not shown) can be formed on this heterojunction interface. For a semiconductor structure formed according to some embodiments, such as a high electron mobility transistor (HEMT), the two-dimensional electron gas can be used as a conductive carrier.

[0062] In addition, in some embodiments, the epitaxial layer 111 is a gallium nitride-containing composite layer. However, the present invention is not limited thereto. Furthermore, in addition to the aforementioned buffer layer 106, channel layer 108, and barrier layer 110, the epitaxial layer 111 may also include other layer films; for example, in some other embodiments, a carbon-doped layer may be formed between the buffer layer 106 and the channel layer 108 to improve the breakdown voltage of the semiconductor structure.

[0063] Refer to Figure 1BIn some embodiments, a semiconductor element S is formed on the epitaxial layer 111. D and an interlayer dielectric layer IL M , and the interlayer dielectric layer IL M Covering semiconductor element S D .

[0064] In some embodiments, the semiconductor device S D The gate electrode, the source electrode 116 and the drain electrode 118 are respectively formed on two opposite sides of the gate electrode. Figure 1B An enhanced mode (ie normally-off) high electron mobility transistor is used as an example of a semiconductor device S D As described above, a doped III-V semiconductor layer 112P is further included below the gate electrode 112 .

[0065] like Figure 1B As shown, a doped III-V semiconductor layer 112P is formed on the barrier layer 110. In some embodiments, the doped III-V semiconductor layer 112P may include appropriate dopants, such as P-type doped gallium nitride. In some other embodiments, the doped III-V semiconductor layer 112P may include P-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), deep indium gallium (InGaAs), other suitable III-V materials or combinations thereof. In addition, the formation method of the doped III-V semiconductor layer 112P may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial process, ion implantation or in-situ doping process.

[0066] Afterwards, if Figure 1B As shown, according to some embodiments, a first insulating layer 114 is formed on the epitaxial layer 111 and conformably covers the doped III-V semiconductor layer 112P. In some embodiments, the first insulating layer 114 can be made of silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. Furthermore, the first insulating layer 114 can be formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a high-density plasma chemical vapor deposition (HDPCVD) process or a combination thereof.

[0067] like Figure 1BAs shown, a gate electrode 112 is formed on the first insulating layer 114, and the gate electrode 112 is connected to the doped III-V semiconductor layer 112P. In some embodiments, the gate electrode 112 may include a metal material, a metal silicide, polysilicon, other appropriate conductive materials, or a combination thereof. A Schottky contact is formed between the gate electrode 112 and the doped III-V semiconductor layer 112P. In some embodiments, the gate electrode 112 may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (such as sputtering), or a similar process.

[0068] In some embodiments, a second insulating layer 115 is formed on the first insulating layer 114, and the second insulating layer 115 conformably covers the gate electrode 112, such as Figure 1B The process and material of the second insulating layer 115 may be similar or the same as the process and material of the first insulating layer 114, and will not be described again here.

[0069] Then, a source electrode 116 and a drain electrode 118 are formed on opposite sides of the gate electrode 112. Figure 1B As shown, the source electrode 116 and the drain electrode 118 are located on the channel layer 108 and are in electrical contact with the channel layer 108. In some embodiments, the source electrode 116 and the drain electrode 118 include a conductive material, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi2, a combination of the foregoing, or the like. In some embodiments, the source electrode 116 and the drain electrode 118 can be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (such as sputtering), electron beam evaporation, or the like. In some embodiments, after depositing the material layer to form the source electrode 116 and the drain electrode 118, a high temperature thermal process such as a rapid thermal annealing process is further performed to form a source-drain ohmic contact.

[0070] Next, in some embodiments, as Figure 1B As shown, a third insulating layer 124 is formed on the second insulating layer 115, and the third insulating layer 124 conformably covers the source electrode 116 and the drain electrode 118. The process and material of the third insulating layer 124 may be similar or the same as the process and material of the first insulating layer 114, and will not be repeated here. Figure 1B The first insulating layer 114, the second insulating layer 115 and the third insulating layer 124 constitute the interlayer dielectric layer IL M , to cover the semiconductor element S D .

[0071] Afterwards, a through hole structure is fabricated, which at least passes through the composite material layer 102 of the substrate 102. M and the substrate 102 C As can be seen from the following description, the opening of the through hole structure needs to pass through many stacked material layers, such as the interlayer dielectric layer IL M , epitaxial layer 111, seed layer 104 and composite material layer 102 M , so as to expose the substrate 102 C In some embodiments, the opening of the through hole structure is formed by combining multiple mask layers.

[0072] Figure 1C to Figure 1G The present invention is an example of how to use a multi-layer mask to form an opening of a through-hole structure. Figure 1C In some embodiments, the interlayer dielectric layer IL M A multi-layer mask 130 is formed on the top of the interlayer dielectric layer IL M A first mask layer 132 formed on the film, a second mask layer 134 formed on the first mask layer 132 , and a patterned third mask layer 136 formed on the second mask layer 134 .

[0073] According to some embodiments, the first mask layer 132, the second mask layer 134, and the third mask layer 136 of the multi-layer mask 130 include different materials. In some embodiments, the third mask layer 136 is, for example, a patterned photoresist layer.

[0074] In some embodiments, the second mask layer 134 includes, for example, oxide, nitride, oxynitride, or other suitable dielectric materials. Furthermore, the second mask layer 134 may be formed by a chemical vapor deposition process (e.g., a high-density plasma chemical vapor deposition process), a spin coating process, an atomic layer deposition process, or a combination thereof. In some embodiments, the second mask layer 134 is thinner than the interlayer dielectric layer IL M More dense.

[0075] In some embodiments, the interlayer dielectric layer IL M The first mask layer 132 between the second mask layer 134 is made of a material different from that of the second mask layer 134 and the interlayer dielectric layer IL M The etching gas used in the subsequent etching process also has etching selectivity for the materials of the first mask layer 132 and the second mask layer 134. For example, the etching gas that can etch and remove the second mask layer 134 does not etch the first mask layer 132 or etches very little. In some embodiments, the first mask layer 132 can be used as an etching stop layer when removing the second mask layer 134. In some embodiments, the first mask layer 132 includes a metal compound, such as a metal nitride.

[0076] Next, in some embodiments, the patterned third mask layer 136 is used to perform an etching process 210 on the underlying material layer, including etching the second mask layer 134, the first mask layer 132, and the interlayer dielectric layer IL M , in the interlayer dielectric layer IL M An opening is formed in the epitaxial layer 111 to expose the epitaxial layer 111. Figure 1D and Figure 1E The example illustrates how to form an opening exposing the epitaxial layer 111 .

[0077] In some embodiments, a two-stage etching step may be performed to form an opening that exposes the epitaxial layer 111. Figure 1D and Figure 1E As shown, an etching process including a first etching step 210A and a second etching step 210B is performed, and the first etching step 210A and the second etching step 210B can be performed in-situ in the same etching chamber.

[0078] Reference Figure 1D , a first etching step 210A is performed to etch the second mask layer 134 using a first etching gas to form an opening 140A. The opening 140A exposes the surface of the first mask layer 132.

[0079] In some embodiments, after the first etching step 210A is completed, the substrate is not removed from the etching chamber, but the second etching step 210B is continuously performed in the etching chamber. In some embodiments, the second etching step 210B and the first etching step 210A use different etching gases.

[0080] Reference Figure 1E , performing a second etching step 210B, using a second etching gas to etch the first mask layer 132 and the interlayer dielectric layer IL along the opening 140A M Etching is performed to form an opening 140B. The opening 140B exposes the epitaxial layer 111, for example, exposes the surface of the barrier layer 110. According to some embodiments, the first etching gas and the second etching gas have different fluorine-carbon ratios. In some embodiments, the fluorine-carbon ratio of the first etching gas is less than the fluorine-carbon ratio of the second etching gas. For example, C4F8 is used as the first etching gas and CF4 is used as the second etching gas.

[0081] After the opening 140B is formed, an ashing process may be performed to remove the patterned third mask layer 136 on the second mask layer 134. Figure 1F shown.

[0082] Then, if Figure 1GAs shown, after removing the patterned third mask layer 136, the epitaxial layer 111 and the seed layer 104 are etched along the opening 140B using the second mask layer 134 as an etching mask to form an opening 140C. The opening 140C exposes the substrate 102, for example, exposes the composite material layer 102 of the substrate 102. M surface.

[0083] According to some embodiments, the process of etching through the epitaxial layer 111 and the seed layer 104 to form the opening 140C may include multiple etching steps. FIG. 2A to FIG. 2C Further explanation of the formation Figure 1G One of the applicable processes is shown for the opening 140C.

[0084] Refer to Figure 1F and Figure 2A In some embodiments, the second mask layer 134 is used as an etching mask and an appropriate etching gas is selected. Figure 1F The opening 140B is etched into the epitaxial layer 111. Furthermore, in some embodiments, a cleaning step may be performed after the etching step is completed.

[0085] According to some embodiments, along the opening 140B ( Figure 1F ) The first and second etching steps 230A are performed on the epitaxial layer 111 to etch the barrier layer 110 and the channel layer 108 to form an opening 140B1. Figure 2A shown.

[0086] Next, a third etching step 230B is performed along the opening 140B1 to etch the buffer layer 106 to form an opening 140B2. Figure 2B shown.

[0087] Then, a fourth etching step 230C is performed along the opening 140B2 to etch the seed layer 104 to form the opening 140C. Figure 2C shown. Figure 2C The structure shown is Figure 1G The structures shown are the same.

[0088] During the etching process, the etching gas and the etched material layer will generate a large number of reaction products. In order to avoid excessive reaction products from clogging the opening during the etching process, causing etching stop and ultimately resulting in poor hole opening, a cleaning step can be performed to remove residual products, depending on the etching situation, for example, after each etching step is completed.

[0089] In some embodiments, the epitaxial layer 111 is a composite layer containing GaN, and the etching gas includes, for example, chlorine (Cl2), boron chloride (BCl3) and argon (Ar) or other suitable gases to perform multiple etching steps on the GaN composite layer. Taking the epitaxial layer 111 with a thickness of about 5 μm as an example, three or more etching steps can be performed, but the present invention does not impose many restrictions on the number of etching steps. In actual application, the number of times the epitaxial layer 111 is etched can be determined based on the material, number of layers and etching conditions (such as etching gas type, flow rate, plasma source and bias power, etc.) contained in the epitaxial layer 111. In addition, in some embodiments, after the etching step, the residual products can be removed by high-power plasma and argon respectively.

[0090] Refer to Figure 1G The above process has formed an opening 140C exposing the substrate 102. Next, a process is performed to extend the opening 140C downward to further etch through the composite material layer 102 of the substrate 102. M , so as to expose the substrate 102 C .

[0091] Reference Figure 1H In some embodiments, after the opening 140C is formed, an etching process 250 is performed to remove the second mask layer 134 by etching, and the etching process 250 simultaneously etches through the composite material layer 102 along the opening 140C. M , thereby exposing the substrate 102 C In some embodiments, dry etching may be performed to remove the second mask layer 134 .

[0092] In some embodiments, the etching gas used to remove the second mask layer 134 does not etch the first mask layer 132, so after the second mask layer 134 is completely removed, the first mask layer 132 remains on the interlayer dielectric layer IL M In one example, the second mask layer 134 may be dry-etched using an etching gas with a fluorine-to-carbon ratio of less than 4 (eg, C4F8).

[0093] Next, refer to Fig. 1I After removing the second mask layer 134, the interlayer dielectric layer IL is removed. M In some embodiments, wet etching may be performed to remove the first mask layer 132 .

[0094] According to the processes of some of the above embodiments, the multi-layer mask 130 is used to form the opening 140D with a high aspect ratio, such as Fig. 1I As shown, the opening 140D is continuously etched through the interlayer dielectric layer IL M , the epitaxial layer 111 and the composite material layer 102 of the substrate 102 M, and the substrate 102 is exposed C .

[0095] Afterwards, if Figure 1J As shown, a suitable material is filled into the opening 140D to form a through-hole structure 143. The through-hole structure 143 at least passes through the composite material layer 102 of the substrate 102. M and contacting the substrate 102 C . The material filled into the opening 140D can be appropriately selected according to the requirements of the actual application structure. For example, in some embodiments, a conductive material is filled into the opening 140D, and the through-hole structure 143 formed at this time can provide heat dissipation or grounding. Conductive materials are, for example, conductor materials or semiconductor materials. In some embodiments, the through-hole structure 143, for example, includes Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi2, a combination of the foregoing, or a similar conductive material. In some embodiments, the through-hole structure 143, for example, includes polycrystalline silicon. In some other embodiments, the through-hole structure 143 also includes a barrier layer (barrier layer) or an adhesion layer (not shown) first deposited on the side wall of the opening 140D, and then the conductive material is filled to form the through-hole structure 143.

[0096] For example, in some other embodiments, one or more insulating materials are filled in the opening 140D, and the through-hole structure 143 formed at this time can provide an isolation effect. In some embodiments, the through-hole structure 143, for example, includes nitride, oxide, or a combination thereof. In some embodiments, the material of the through-hole structure 143 can be formed by atomic layer deposition, chemical vapor deposition, spin-on glass (SOG), flow chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition, or similar processes to form the through-hole structure 143. In some other embodiments, the through-hole structure 143 may include a liner on the sidewall of the opening 140D.

[0097] Due to the processes proposed in some of the above embodiments, a through hole structure 143 with a small size and a sufficient depth H can be formed to penetrate the interlayer dielectric layer IL. M , the epitaxial layer 111 and the composite material layer 102 of the substrate 102 M , and the substrate 102 C Therefore, when the embodiment is applied, the through hole structure 143 only occupies a small area, and can even be arranged in the existing space without affecting the area of ​​the original semiconductor structure. In some embodiments, the through hole structure 143 is formed in the interlayer dielectric layer IL M The dimensions of the top surface, e.g. Figure 1JThe width W shown may be in the range of 1 μm-5 μm. In some other embodiments, the width W of the through hole structure 143 is in the range of 1 μm-3 μm. In addition, in some embodiments, the aspect ratio (H / W) of the through hole structure is in the range of about 1.6 to about 8.

[0098] like Figure 1K As shown, in some embodiments, after forming the through hole structure 143, related devices of the device to be formed (such as HEMT) can be continuously fabricated on the source electrode 116, the drain electrode 118 and the through hole structure 143. For example, a metal layer 150 is formed on the source electrode 116, the drain electrode 118 and the through hole structure 143, and other metal layers and intermetallic dielectric layers (not shown) are continuously fabricated on the metal layer 150. According to some embodiments, the through hole structure 143 is in direct contact with the metal layer 150 of the semiconductor structure.

[0099] In some embodiments, holes (not shown) are formed in the third insulating layer 124 to expose the source electrode 116 and the drain electrode 118. A metal material is then deposited on the third insulating layer 124 to fill the holes, and a patterning process is performed to form a plurality of vias and a plurality of metal portions. Figure 1K As shown, in some embodiments, a via 152V and a metal portion 152M are formed on the source electrode 116, a via 154V and a metal portion 154M are formed on the drain electrode 118, and a metal portion 156 is formed on the through-hole structure 143. The vias 152V, 154V, the metal portions 152M, 154M, and 156 constitute the aforementioned metal layer 150.

[0100] In some embodiments, metal layer 150 may be referred to as a first metal layer (M1). Figure 1K Only the first metal layer and an insulating layer 124 are used as examples, but in the subsequent process, multiple intermetallic dielectric layers (not shown in the figure) and multiple metal layers (not shown in the figure) are alternately stacked and formed on the first metal layer. Each intermetallic dielectric layer also has a guide hole connecting adjacent metal layers. In some embodiments, the through-hole structure 143 containing conductive material is in direct contact with the metal layer 150 and is electrically connected to the guide hole above the metal layer 150 and other metal layers, thereby providing a heat dissipation / grounding path.

[0101] Figure 3 A partial enlarged schematic diagram of a through hole structure in a semiconductor structure of some embodiments of the present invention is shown. In some embodiments, the composite material layer 102 of the substrate 102 M The composite material layer 102 may include multiple insulating layers and semiconductor layers such as polysilicon. MThe semiconductor structure includes at least two insulating layers and a polysilicon layer located between the at least two insulating layers, and the conductive through-hole structure 143 can be electrically connected to the polysilicon layer. According to some embodiments, if the through-hole structure 143 of the semiconductor structure includes a conductive material and is in direct contact with the metal layer 150, the through-hole structure 143 can make the substrate 102 of the substrate 102 C Heat dissipation and composite material layer 102 M The polysilicon layer is used for grounding.

[0102] like Figure 3 As shown, the composite material layer 102 M The structure includes a first oxide layer 1021, a polysilicon layer 1022, a second oxide layer 1023 and a nitride layer 1024. Figure 3 Only the composite material layer 102 is shown M On the substrate 102 C The composite material layer 102 of the embodiment M Each material layer of the substrate 102 surrounds and covers all surfaces (including the upper and lower surfaces and all sides) of the previously formed material layer in a sealed manner. C The surface of the sealing substrate 102 C The polysilicon layer 1022 covers the surface of the first oxide layer 1021 to seal the first oxide layer 1021 and the substrate 102 C The second oxide layer 1023 covers the surface of the polysilicon layer 1022 and seals the previously formed polysilicon layer 1022, the first oxide layer 1021 and the substrate 102 C The nitride layer 1024 covers the surface of the second oxide layer 1023 and seals the second oxide layer 1023, the polysilicon layer 1022, the first oxide layer 1021 and the substrate 102 C .

[0103] In some embodiments, Figure 1K and Figure 3 As shown, through the composite material layer 102 M The through hole structure 143 is connected to the metal layer 150 and the substrate 102 at the top and bottom respectively. C Direct contact. If the through-hole structure 143 includes a conductive material, the through-hole structure 143 in contact with the polysilicon layer 1022 can release the parasitic charge generated by the plasma etching process and accumulated in the polysilicon layer 1022, so the through-hole structure 143 can be used as a grounding. When the semiconductor structure is operated at a high voltage (for example, the operating voltage is above 600V), the through-hole structure 143 provides a parasitic charge release path, thereby solving the problem of parasitic charge moving arbitrarily under high voltage and affecting the electrical performance of the semiconductor structure. Furthermore, even if the substrate 102 CThe composite material layer 102 contains a ceramic material with good thermal conductivity, but due to the multi-layer structure M Sealing the substrate 102 C , so that the substrate 102 C It is difficult to dissipate heat, so in the embodiment, the metal layer 150 and the substrate 102 C If the through hole structure 143 in direct contact is filled with a material with good thermal conductivity, the substrate 102 can also be provided with C For heat dissipation.

[0104] In addition, the through hole structure 143 of the embodiment can be implemented in a variety of different application modes. For example, in some embodiments, the through hole structure 143 can be used for isolation (including insulating materials) or grounding / heat dissipation (including conductive materials) of a certain active area. In some other embodiments, the through hole structure 143 can be used for isolation (including insulating materials) or grounding / heat dissipation (including conductive materials) of one or more semiconductor elements. Therefore, the area and position of the through hole structure 143 can be adjusted according to the requirements of the application device.

[0105] Figure 4 Schematic diagram of an active region, a peripheral region and a cutting path of a semiconductor structure according to some embodiments of the present invention. Figure 4 As shown, the peripheral area A P Located in active zone A A Around, and the surrounding area A P Including cutting line L S .Although Figure 4 Only one active area A is shown A A region in D For explanation, however, in actual application, each active area A A Contains multiple regions A D . Each area A D One or more semiconductor devices are provided.

[0106] In some embodiments, the through hole structure 143 may be disposed in the active region A. A Peripheral, for example, set in area A S1 As active area A A The area A is used for isolation, grounding, or heat dissipation. S1 Located on Cutting Road L S With active area A A At this time, the through hole structure 143 can also prevent the chip from moving along the cutting path L. S The cracks generated during die sawing enter the active area A A , and prevent moisture from entering the active area A from the cutting section A , thereby improving the active zone A AFurthermore, if the through hole structure 143 includes a conductive material and is electrically connected to the upper metal layer and grounded, the active area A can be shielded from the outside world. A Signal interference may be caused by the semiconductor components installed inside.

[0107] In some other embodiments, the through hole structure 143 may be disposed in the active region A. A Inner area A D The periphery, for example, is set in area A S2 and area A D One or more semiconductor elements are disposed, and the through hole structure 143 can be used for the isolation or grounding and heat dissipation of the semiconductor elements.

[0108] In addition, set in area A S1 and / or Region A S2 The top view pattern of the through hole structure 143 (not shown) can be a continuous pattern, such as a closed pattern surrounding the active area A. A and / or Region A D , or it may include several separated segments arranged in area A S1 and / or Region A S2 The actual top view pattern of the through hole structure 143 can be changed and adjusted according to the application requirements, and the present invention does not impose any restrictions on this.

[0109] In summary, the semiconductor structure provided in some embodiments of the present invention has a composite material layer 102 that at least passes through the substrate 102. M and contacting the substrate 102 C Furthermore, in some embodiments, the through hole structure 143 may include an insulating material to serve as a certain active region A. A or one or more semiconductor components S D In some other embodiments, the through hole structure 143 may include a conductive material, such as a metal conductor or polysilicon, to serve as a certain active region A. A or one or more semiconductor components S D grounding (e.g., releasing the accumulated M The parasitic charge of the semiconductor layer) and the substrate 102 C The purpose of heat dissipation is to improve the electrical performance of the semiconductor device. A Peripheral and located at the cutting line L S With active area A A It can also prevent cracks that may be generated when the wafer is cut from entering the active area A. A , and prevent moisture from entering the active area A from the cutting section A, thereby improving the active zone A A Furthermore, according to the manufacturing method of the semiconductor structure provided in some embodiments, the through hole structure 143 can successively pass through the epitaxial layer 111, the seed layer 104 and the composite material layer 102. M According to some other manufacturing methods proposed in the embodiments, the through hole structure 143 may continuously penetrate the interlayer dielectric layer IL M , epitaxial layer 111, seed layer 104 and composite material layer 102 M Therefore, the manufacturing method of the semiconductor structure proposed in the embodiment can form a through-hole structure 143 with a small size and a sufficient depth H (high aspect ratio). For example, the width W of the through-hole structure 143 can be reduced to about 5 μm or less. Therefore, the through-hole structure 143 of the embodiment can be formed with little or no impact on the area of ​​the original semiconductor structure, and the electrical performance of the applied semiconductor structure can be significantly improved.

[0110] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a base material and a composite material layer sealing the base material, wherein the composite material layer covers the upper surface, the lower surface and all the side surfaces of the base material; a seed layer located on the substrate; an epitaxial layer located on the seed layer; a semiconductor element located on the epitaxial layer; an interlayer dielectric layer, located on the epitaxial layer and covering the semiconductor device; as well as A through hole structure at least passes through the composite material layer of the substrate and contacts and stops at the upper surface of the substrate.

2. The semiconductor structure according to claim 1, characterized in that: The through hole structure includes a conductive material.

3. The semiconductor structure according to claim 2, characterized in that: The composite material layer comprises at least two insulating layers and a polysilicon layer located between the at least two insulating layers, and the through hole structure is electrically connected to the polysilicon layer.

4. The semiconductor structure according to claim 1, characterized in that The through hole structure includes an insulating material.

5. The semiconductor structure according to claim 1, characterized in that: The through hole structure passes through the epitaxial layer and the seed layer, and successively passes through the composite material layer of the substrate.

6. The semiconductor structure according to claim 5, characterized in that: The through hole structure further passes through the interlayer dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that: The invention further comprises a patterned metal layer on the interlayer dielectric layer, and the through hole structure is connected to the patterned metal layer.

8. The semiconductor structure according to claim 1, characterized in that: The aspect ratio of the through hole structure is in the range of 1.6 to 8.

9. The semiconductor structure according to claim 1, characterized in that: The substrate includes a ceramic material.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base material and a composite material layer sealing the base material, the composite material layer covering the upper surface, the lower surface and all side surfaces of the base material; forming a seed layer on the substrate; forming an epitaxial layer on the seed layer; forming a semiconductor device on the epitaxial layer; forming an interlayer dielectric layer on the epitaxial layer, wherein the interlayer dielectric layer covers the semiconductor device; as well as A through hole structure is formed to at least pass through the composite material layer of the substrate and contact and stop at the upper surface of the substrate.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The formed through-hole structure includes a conductive material.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The composite material layer comprises at least two insulating layers and a polysilicon layer located between the at least two insulating layers, and the formed through-hole structure is electrically connected to the polysilicon layer.

13. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The formed through hole structure includes an insulating material.

14. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The formed through-hole structure passes through the epitaxial layer and the seed layer, and then passes through the composite material layer of the substrate.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The formed through-hole structure further passes through the interlayer dielectric layer.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The method further includes forming a patterned metal layer above the interlayer dielectric layer, wherein the through hole structure is connected to the patterned metal layer.

17. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The step of forming the through hole structure passing through the interlayer dielectric layer comprises: forming a first mask layer on the interlayer dielectric layer; forming a second mask layer on the first mask layer; forming a patterned third mask layer on the second mask layer; Etching the second mask layer, the first mask layer and the interlayer dielectric layer with the patterned third mask layer to form an opening to expose the epitaxial layer; and The patterned third mask layer is removed.

18. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: The first mask layer, the second mask layer and the patterned third mask layer include different materials.

19. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: etching the second mask layer using a first etching gas; and Etching the first mask layer and the interlayer dielectric layer using a second etching gas; The first etching gas and the second etching gas have different fluorine-carbon ratios.

20. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: After removing the patterned third mask layer, the method further comprises: The second mask layer is used as an etching mask to etch the epitaxial layer and the seed layer along the opening to expose the substrate.

21. The method for manufacturing a semiconductor structure according to claim 20, characterized in that: The etching of the epitaxial layer and the seed layer includes multiple etching steps, and a cleaning step is performed after each etching step is completed.

22. The method for manufacturing a semiconductor structure according to claim 20, characterized in that: After the opening exposes the substrate, the method further comprises: Etching to remove the second mask layer, and etching through the composite material layer along the opening to expose the substrate; and The first mask layer is removed.

23. The method for manufacturing a semiconductor structure according to claim 22, characterized in that: Dry etching is performed to remove the second mask layer, and wet etching is performed to remove the first mask layer.

24. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: The aspect ratio of the through hole structure is in the range of 1.6 to 8.

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