Phase-locked loop circuit and clock generator including the same

Abstract

A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include: a voltage-controlled delay line that routes a feedback signal to generate delay information; a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delayed reference clock signals, each delayed reference clock signal being delayed by a different corresponding delay time; and a digital-to-time converter (DTC) configured to generate a selected reference clock signal based on the plurality of delayed reference clock signals and output the selected reference clock signal to the sub-sampling PLL circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0125676, filed on October 10, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to phase-locked loops (PLLs) and clock generators having PLLs, and more particularly to PLLs including subsampling PLLs for fractional-frequency-based phase locking of a clock. Background Art

[0004] A PLL, such as one found in a clock generator, is a circuit that generates a phase-locked clock signal. For example, this clock signal can be used to send data in a transmitter or recover data in a receiver. In this regard, PLLs can be categorized as, for example, ring PLLs or inductor-capacitor (LC) PLLs.

[0005] Recently, the technology of locking the phase of the clock by subsampling has been applied to PLL to improve noise characteristics. For example, a subsampling PLL may include a phase detector and a voltage-controlled oscillator (VCO), wherein the phase detector subsamples the output of the VCO using a reference clock. Another technology involves fractional frequency division, which uses a fractional frequency divider in the feedback path. However, since the frequency divider does not perform frequency division on the clock during the subsampling operation, this limits the performance of the fractional frequency division operation. A technology for implementing fractional frequency division operation during the subsampling operation by using a digital-to-time converter has been introduced to address this limitation. However, due to limited resolution and quantization noise, using this method will reduce the performance of the clock generator. Summary of the Invention

[0006] Embodiments of the inventive concept provide a phase-locked loop (PLL) and a clock generator including the PLL, wherein the PLL includes a fractional frequency division control circuit having high resolution in fractional frequency phase-locked control of a clock and capable of reducing quantization noise.

[0007] According to one aspect of the present invention, a phase-locked loop (PLL) circuit is provided, comprising: a voltage-controlled oscillator configured to generate an output clock signal; a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and perform a fractional frequency division-based phase-locked operation based on the output clock signal; and a fractional frequency division control circuit configured to provide a selected reference clock signal for the fractional frequency division-based phase-locked operation to the sub-sampling PLL circuit. The fractional frequency division control circuit includes: a voltage-controlled delay line configured to route the feedback signal to generate delay information; a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock to generate a plurality of delayed reference clock signals, each delayed reference clock signal being delayed by a different corresponding delay time; and a digital-to-time converter (DTC) configured to generate a selected reference clock signal based on the plurality of delayed reference clock signals and output the selected reference clock signal to the sub-sampling PLL circuit.

[0008] According to another aspect of the inventive concept, a phase-locked loop (PLL) circuit is provided, comprising: a voltage-controlled oscillator configured to generate an output clock signal; a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and perform a phase-locked operation based on fractional frequency division based on the output clock signal; and a fractional frequency division control circuit configured to provide a selection reference clock signal for the phase-locked operation based on fractional frequency division to the sub-sampling PLL circuit, wherein the fractional frequency division control circuit is further configured to: generate delay information related to a constant delay time within one cycle of the feedback signal by performing a delay operation using a feedback signal having a first frequency; generate, based on the delay information, a plurality of delayed reference clock signals that are gradually delayed by as much as the delay time by using a reference clock signal having a second frequency; and generate a selection reference clock signal by using the plurality of delayed reference clock signals.

[0009] According to another aspect of the inventive concept, a clock generator is provided, including: a voltage-controlled oscillator configured to generate an output clock signal; an auxiliary phase-locked loop (PLL) circuit configured to perform an integer-frequency-based phase-locked operation on the output clock signal; a sub-sampling PLL circuit configured to perform a fractional-frequency-based phase-locked operation on the output clock signal after the integer-frequency-based phase-locked operation; and a fractional-frequency-division control circuit configured to provide a selected reference clock signal for the fractional-frequency-based phase-locked operation to the sub-sampling PLL circuit, wherein the fractional-frequency-division control circuit includes: a voltage-controlled delay line configured to route a feedback signal to generate delay information; a replica voltage-controlled delay line having the delay information applied thereto and including the same characteristics as the voltage-controlled delay line and configured to route the reference clock signal to generate a plurality of delayed reference clock signals, each delayed reference clock signal being delayed by a different corresponding delay time; and a digital-to-time converter (DTC) configured to generate a selected reference clock signal based on the plurality of delayed reference clock signals and output the selected reference clock signal to the sub-sampling PLL circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals represent like elements or features, and in which:

[0011] Figure 1 is a block diagram of a clock generator according to an embodiment;

[0012] Figure 2 is a flowchart for describing a phase-locked operation of a phase-locked loop (PLL) circuit according to an embodiment;

[0013] Figure 3A and Figure 3B is a detailed block diagram of a clock generator according to an embodiment;

[0014] Figure 4 According to the embodiment Figure 3A or Figure 3B Circuit diagram of the transconductance circuit;

[0015] Figure 5 is a flowchart for describing a method of performing sub-sampling PLL based on fractional frequency division of a PLL circuit according to an embodiment;

[0016] Figure 6 is a timing diagram for describing a delayed output clock signal having passed through a voltage-controlled delay line and a delayed reference clock signal having passed through a replica voltage-controlled delay line according to an embodiment;

[0017] Figure 7 is a block diagram for describing the operation of a delay locked loop (DLL) circuit according to an embodiment;

[0018] Figure 8A is a block diagram of a DLL circuit according to an embodiment, and Figure 8B is used to describe Figure 8A A graph showing the operation of the DLL circuit;

[0019] Figure 9 and Figure 10 is a detailed block diagram of a digital-to-time converter according to an embodiment;

[0020] Figure 11 is a block diagram of a wireless communication device according to an embodiment;

[0021] Figure 12 is a schematic diagram illustrating a communication device including a clock generator for performing a phase-locked operation on a clock according to an embodiment; and

[0022] Figure 13 is a block diagram of an Internet of Things (IoT) device according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram of a clock generator 1 according to an embodiment. Clock generator 1 may include a phase-locked loop (PLL) circuit PLL_CKT, wherein the PLL circuit PLL_CKT may include a fractional frequency division control circuit 10, an auxiliary PLL circuit 20, a subsampling PLL circuit 30, and a voltage-controlled oscillator (VCO) 40. According to some embodiments, VCO 40 may be implemented in various configurations, such as a ring oscillator or an inductor-capacitor (LC) oscillator, which may be used as examples below. Hereinafter, for ease of description, phase delay and time delay may be used interchangeably. Hereinafter, "PLL x" and "DLL y" will refer to "PLL circuit x" and "DLL circuit y," respectively, where "x" or "y" is the previously designated icon for the circuit element in question. Thus, for example, "PLL 20" will refer to PLL circuit 20, while "DLL 14" will refer to DLL circuit 14.

[0025] The auxiliary PLL 20 may perform a first phase-locked operation by receiving an output clock signal (more generally, an "oscillation signal") from the VCO 40. Hereinafter, the first phase-locked operation may refer to a phase-locked operation for achieving a difference between the phase of the output clock signal and the phase of the reference clock signal that falls within a specific locking range, which facilitates a second phase-locked operation for the output clock signal of the sub-sampling PLL 30. Therefore, the first phase-locked operation may be referred to as an auxiliary phase-locked operation prior to the second phase-locked operation of the sub-sampling PLL 30. In this document, the first phase-locked operation performed by the auxiliary PLL 20 may be referred to as an auxiliary PLL operation. According to an embodiment, the first phase-locked operation may be a phase-locked operation based on integer division. In this case, the integer division ratio of the first phase-locked operation may be adjusted to a fractional division ratio that is approximately equal to a target fractional division ratio, wherein the adjustment is performed by the fractional division control circuit 10 described below. In this regard, the auxiliary PLL 20 may include a divider having a configuration in which the division ratio is adjusted by the fractional division control circuit 10. Although Figure 1 The auxiliary PLL 20 is shown applying a specific control voltage signal directly to the VCO 40, but other circuit arrangements are also possible. For example, as described below Figure 3A As shown, the auxiliary PLL 20 a may share one loop filter 106 with the sub-sampling PLL 30 a , and thus may apply a specific control voltage signal V ctrl to the VCO 101 through the loop filter 106 .

[0026] The sub-sampling PLL 30 can receive an output clock signal (the first phase-locked output clock from the auxiliary PLL 20) from the VCO 40 in a feedback path. Therefore, the output clock signal in the feedback path can be referred to as a feedback signal in this document. The sub-sampling PLL 30 can use the feedback signal to perform sub-sampling. The sub-sampling PLL 30 can perform a phase-locked operation (or a second phase-locked operation) based on fractional frequency division on the feedback signal, and the sub-sampling PLL 30 can receive a selected reference clock signal for the locking operation based on fractional frequency division from the fractional frequency division control circuit 10. Hereinafter, the fractional frequency division control circuit 10 according to an embodiment will be described.

[0027] The fractional frequency division control circuit 10 may include a digital time converter (DTC) 12, a delay locked loop (DLL) circuit 14, a voltage controlled delay line 16, and a replica voltage controlled delay line 18. The voltage controlled delay line 16 may receive an output clock signal as a feedback signal from the VCO 40, and may output a feedback signal delayed up to a maximum phase based on the received feedback signal. The maximum phase may vary depending on the type of input / output signal of the VCO 40 or the target fractional frequency division ratio. As an example, when the input / output signal of the VCO 40 is a single-ended signal, the maximum phase may be 360 ​​degrees, and as another example, when the input / output signal of the VCO 40 is a differential signal, the maximum phase may be 180 degrees. Although it is assumed that the internal signal of the PLL PLL_CKT is a single-ended signal for ease of description below, other types of signals are available. For example, the internal signal of the PLL PLL_CKT may alternatively be a differential signal. According to an embodiment, the voltage-controlled delay line 16 may include a plurality of first delay elements connected in series to each other, and the voltage-controlled delay line 16 may have a configuration designed according to the number of phases that the selected reference clock signal provided to the sub-sampling PLL 30 may have. For example, as the number of phases that the selected reference clock signal may have increases, the number of first delay elements included in the voltage-controlled delay line 16 may also increase.

[0028] According to an embodiment, the DLL 14 may be connected to the voltage-controlled delay line 16 and may generate delay information by locking the delay of the feedback signal delayed by the voltage-controlled delay line 16. For example, the DLL 14 may generate the delay information by performing a delay locking operation on the feedback signal passing through the voltage-controlled delay line 16. The delay information may be used to control the time delay (or phase delay) of the feedback signal (or the output clock signal of the VCO 40) at a first frequency (or high frequency). In other words, the delay information may be used to control the feedback signal to be delayed by a maximum value of a constant delay time corresponding to one cycle of the feedback signal passing through the voltage-controlled delay line 16. For example, the delay information may include bias voltages for a plurality of first delay elements included in the voltage-controlled delay line 16. The bias voltages may be applied to the delay elements to allow the delay elements to constantly delay the signal by a target delay time, regardless of changes in the operating environment or process, voltage, and temperature (PVT) conditions of the clock generator 1 or the PLL PLL_CKT. The DLL 14 may provide the delay information to the replica voltage-controlled delay line 18. DLL 14 can perform a delay locking operation to prevent harmonic locking, thereby generating accurate delay information. For example, when the phase of the delayed feedback signal falls within a specific locking range by adjusting the degree of delay of the feedback signal caused by voltage-controlled delay line 16, DLL 14 can begin an operation to lock the delay of the feedback signal.

[0029] According to one embodiment, a replica voltage-controlled delay line 18, which is a replica of the voltage-controlled delay line 16, may include a plurality of second delay elements having the same configuration or characteristics as the plurality of first delay elements included in the voltage-controlled delay line 16. Delay information received from the DLL 14 may be applied to the replica voltage-controlled delay line 18, and the replica voltage-controlled delay line 18 may generate a plurality of delayed reference clock signals by receiving a reference clock signal, each delayed reference clock signal being delayed by a different respective delay time. Each of the plurality of delayed reference clock signals may be delayed by a different respective amount. The reference clock signal may have a second frequency that is lower than the first frequency (or high frequency) of the feedback signal (or the output clock signal of the VCO 40), and the ratio of the first frequency of the output clock signal (or the feedback signal) phase-locked by the subsampling PLL 30 to the second frequency of the reference clock signal may have a target fractional division ratio. For example, the replica voltage-controlled delay line 18 may include a plurality of second delay elements connected in series and having delay information applied thereto to delay the received signal by the same delay time as the plurality of first delay elements of the voltage-controlled delay line 16. The received signal may be delayed by the same amount as the plurality of first delay elements of the voltage-controlled delay line 16. The replica voltage-controlled delay line 18 may output a plurality of delayed reference clock signals that are gradually delayed by as much as the delay time from the received reference clock signal to the DTC 12. For example, the plurality of delayed reference clock signals may be output to the DTC 12 through corresponding output terminals of the plurality of second delay elements of the replica voltage-controlled delay line 18.

[0030] According to an embodiment, the DTC 12 may receive multiple delayed reference clock signals from the replica voltage-controlled delay line 18, generate a selected reference clock signal based on the multiple delayed reference clock signals, and output the selected reference clock signal to the subsampling PLL 30. The DTC 12 may generate the selected reference clock signal with a phase adjusted based on a target fractional division ratio. For example, the DTC 12 may select one of the multiple delayed reference clock signals and generate the selected reference clock signal by finely adjusting the delay of the selected delayed reference clock signal. The fine delay range of the selected delayed reference clock signal in the DTC 12 may correspond to a constant delay time between the multiple delayed reference clock signals. For example, the fine delay range of the selected delayed reference clock signal in the DTC 12 may be limited to the constant delay time. The DTC 12 may generate an A-bit signal (where A is an integer of 1 or greater) for internally selecting one of the multiple delayed reference clock signals, and may also generate a B-bit signal (where B is an integer of 1 or greater) for adjusting the delay of the selected delayed reference clock signal. The number of bits of the A-bit signal may be greater than the number of bits of the B-bit signal, lower than the number of bits of the B-bit signal, or the same as the number of bits of the B-bit signal.

[0031] According to the above embodiment, the output clock signal of the VCO 40 may be phase-locked by the subsampling PLL 30 and output to a sampling block (eg, an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC)).

[0032] It should be noted here that Figure 1 The illustrated implementation example of the clock generator 1 is merely an example. A minimum configuration to which the inventive concept can be applied can be designed in various other ways.

[0033] The PLL circuit PLL_CKT according to the embodiment can generate delay information through the voltage-controlled delay line 16 by receiving the output clock signal as a feedback signal from the VCO 40, and can use the multiple delayed reference clock signals generated by providing the delay information to the replica voltage-controlled delay line 18 in a phase-locked operation based on fractional frequency division, thereby effectively improving the resolution of the phase of the selected reference clock signal. Because the selected reference clock signal is generated by using the output clock signal from the VCO 40, the jitter of the output clock signal can be reflected in the selected reference clock signal. The overall jitter performance of the PLL PLL_CKT can be improved by reducing the timing skew between the selected reference clock signal received by the sub-sampling PLL circuit 30 and the output clock signal of the VCO 40.

[0034] Figure 21 is a flowchart for describing the phase locking operation of the PLL circuit according to the embodiment. Figure 1 To describe Figure 2 .

[0035] refer to Figure 2 In operation S100, the PLL circuit PLL_CKT may perform a first phase-locking operation on the output clock signal output from the VCO 40 by using the auxiliary PLL circuit 20. According to an embodiment, the first phase-locking operation may be a phase-locking operation based on integer frequency division. However, in other embodiments, the first phase-locking operation may be a phase-locking operation based on fractional frequency division, and the fractional frequency division ratio of the first phase-locking operation may be adjusted by the fractional frequency division control circuit 10. The auxiliary PLL circuit 20 may perform a first phase-locking operation for locking the phase of the output clock signal of the VCO 40, and may perform the first phase-locking operation to achieve a phase difference between the divided output clock signal and the reference clock signal within a specific range (hereinafter referred to as a "dead zone"). When the phase difference between the divided output clock signal and the reference clock signal is within the dead zone, the auxiliary PLL circuit 20 may be deactivated.

[0036] In operation S110, the PLL PLL_CKT may perform a second phase locking operation on the output clock signal output from the VCO 40 by using the sub-sampling PLL circuit 30. According to an embodiment, the second phase locking operation may be a phase locking operation based on fractional frequency division, and the fractional frequency division ratio of the second phase locking operation may be adjusted by the fractional frequency division control circuit 10. For example, the sub-sampling PLL 30 may receive a selected reference clock signal from the fractional frequency division control circuit 10 and may thus perform the second phase locking operation based on the selected reference clock signal.

[0037] The fractional frequency division control circuit 10 according to the embodiment can receive an output clock signal from the VCO 40 and can generate delay information at the frequency of the output clock signal by using the DLL 14 and the voltage-controlled delay line 16. The fractional frequency division control circuit 10 can apply the delay information to the replica voltage-controlled delay line 18 and can generate a plurality of delayed reference clock signals from the reference clock signal by using the replica voltage-controlled delay line 18. The fractional frequency division control circuit 10 can generate a selected reference clock signal from the plurality of delayed reference clock signals by using the DTC 12 and can output the selected reference clock signal to the sub-sampling PLL 30.

[0038] Figure 3A and Figure 3B is a detailed example block diagram of the clock generator 100 according to various embodiments. Figure 3A and Figure 3BThe signals are simply shown in , but in some embodiments, the VCO 101 may output differential signals having opposite phases to each other via two lines, and the clock generator 100 may be implemented to perform a phase-locked operation by using the differential signals. Figure 3B Shows that it can be Figure 3A Additional signals and signal paths implemented in the clock generator 100.

[0039] refer to Figure 3A The clock generator 100 may include an auxiliary PLL circuit 20a, an FFD control circuit 10a, a sub-sampling PLL circuit 30a (which are Figure 1 10 and 30 in the accompanying drawings) and VCO 101. Auxiliary PLL circuit 20a may include a frequency divider 102, a phase frequency detector 103, a dead-zone circuit 104, and a charge pump 105. Subsampling PLL circuit 30a may include a loop filter 106, a sampler 107, a transconductance ("Gm") circuit 108, and a pulse generator 109. FFD control circuit 10a may include a voltage-controlled delay line 110, a DLL circuit 111, a replica voltage-controlled delay line 112, and a DTC 113a.

[0040] The clock generator 100 and Figure 1 The clock generator 1 in the example is slightly different in that: Figure 1 The auxiliary PLL circuit 20 and the sub-sampling PLL circuit 30 can share the loop filter 106, and the loop filter 106 serves as Figure 3A A portion of the sub-sampling PLL circuit 30a is included.

[0041] The VCO 101 may provide an output clock signal VCO_clk to a frequency divider 102, wherein the frequency divider 102 may divide the output clock signal VCO_clk and provide the divided clock DIV_clk to a phase frequency detector 103. The frequency divider 102 may be implemented as an integer frequency divider. The phase frequency detector 103 may receive each of the reference clock signal Ref_clk and the divided clock DIV_clk and may provide a detection result to the dead zone circuit 104 by detecting the phase difference (“phase offset”) between the reference clock signal Ref_clk and the divided clock DIV_clk. Although Figure 3AThe phase frequency detector 103 is shown as receiving the reference clock signal Ref_clk from the DTC 113a, but in other examples, the reference clock signal Ref_clk can be received via a different path. The dead zone circuit 104 can determine whether the phase difference between the reference clock signal Ref_clk and the divided clock DIV_clk is within a preset dead zone. When the phase difference is within the dead zone, the dead zone circuit 104 can work together with other circuits of the auxiliary PLL circuit 20a to complete the first phase lock operation and deactivate the auxiliary PLL circuit 20a. When the phase difference is outside the dead zone, the dead zone circuit 104 can provide the detection result received from the phase frequency detector 103 to the charge pump 105. Based on the detection result, the charge pump 105 can generate a control voltage signal Vctrl and provide the control voltage signal Vctrl to the VCO 101. As described above, the first phase-locking operation can be repeated using the frequency divider 102, the phase frequency detector 103, the dead-zone circuit 104, and the charge pump 105 until the phase difference between the reference clock signal Ref_clk and the divided clock DIV_clk falls within the dead-zone. Subsequently, in order to finely phase-lock the output clock signal VCO_clk, the clock generator 100 can perform a second phase-locking operation using a subsampling PLL circuit.

[0042] For example, the VCO 101 may provide the output clock signal VCO_clk phase-locked by the first phase-locking operation (and thus may be referred to herein as a feedback signal) to the sampler 107 in a feedback path. The sampler 107 may receive each of the output clock signal VCO_clk and the reference clock signal Ref_clk, and may generate a sampled voltage signal V_sam by sampling the output clock signal VCO_clk based on the reference clock signal Ref_clk. Figure 3A It is shown that the sampler 107 receives the reference clock signal Ref_clk from the DTC 113a, but the present invention is not limited to this, and the reference clock signal Ref_clk can be received through another path. The sampler 107 can be called a sub-sampling phase detector. The transconductance circuit 108 can receive the sampled voltage signal V_sam, can convert the sampled voltage signal V_sam into a sampled current signal I_sam based on the pulse signal Pul received from the pulse generator 109, and can output the sampled current signal I_sam to the loop filter 106. The loop filter 106 can generate a control voltage signal Vctrl by filtering the sampled current signal I_sam. The pulse generator 109 can receive the selected reference clock signal Ref_clk_sel from the DTC 113a, and can generate the pulse signal Pul based on the selected reference clock signal Ref_clk_sel. The following reference Figure 4A detailed example configuration of the pulse generator 109 is described, and an operation of generating the selection reference clock signal Ref_clk_sel will be described hereinafter.

[0043] The voltage-controlled delay line 110 may receive the output clock signal VCO_clk from the VCO 101 and, based on the output clock signal VCO_clk, output the following: (i) a first delayed output clock signal VCO_clk_Φ1 that is identical to the output clock signal VCO_clk (thereby effectively routing the output clock signal VCO_clk therethrough), and (ii) a second delayed output clock signal VCO_clk_Φn that has a specific phase difference Φn-Φ1 relative to the first delayed output clock signal VCO_clk_Φ1. The voltage-controlled delay line 110 may include a plurality of first delay elements connected in series, and the second delayed output clock signal VCO_clk_Φn may be a signal generated by sequentially passing the output clock signal VCO_clk through all of the plurality of first delay elements.

[0044] The DLL circuit 111 can perform a delay locking operation using the first and second delayed output clock signals VCO_clk_Φ1 and VCO_clk_Φn received from the voltage-controlled delay line 110, and thus can generate delay information VDLL regarding the output clock signal VCO_clk. For example, when the number of first delay elements in the voltage-controlled delay line 110 is "K," the delay information VDLL may include information for controlling each of the first delay elements to delay the signal by up to (Φn-Φ1) / K degrees. The delay information VDLL may be a bias voltage applied to each of the plurality of first delay elements in the voltage-controlled delay line 110. For example, when the second delayed output clock signal VCO_clk_Φn has a phase difference of 360 degrees relative to the first delayed output clock signal VCO_clk_Φ1, and the number of first delay elements in the voltage-controlled delay line 110 is 32, the delay information VDLL may include information for controlling each of the first delay elements to delay the signal by up to 11.25 degrees (a time delay corresponding to the 11.25-degree phase difference).

[0045] DLL circuit 111 can provide delay information VDLL to replica voltage-controlled delay line 112. Replica voltage-controlled delay line 112, a replica of voltage-controlled delay line 16, can include a plurality of second delay elements having the same configuration or characteristics as the plurality of first delay elements included in voltage-controlled delay line 110. Delay information VDLL received from DLL circuit 111 can be applied to replica voltage-controlled delay line 112. Replica voltage-controlled delay line 112 can receive a reference clock signal Ref_clk and, based on the reference clock signal Ref_clk, generate a plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn; and can output the plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn to DTC 113a. The delay time units in replica voltage-controlled delay line 112, to which delay information VDLL is applied, can be the same as or similar to the delay time units in voltage-controlled delay line 110. For example, assuming that the delay time unit of the voltage-controlled delay line 110 is a delay time corresponding to a phase difference of 11.25 degrees relative to the output clock signal VCO_clk, the delay time unit in the replica voltage-controlled delay line 112 to which the delay information VDLL is applied may be the same as or similar to the delay time corresponding to the phase difference of 11.25 degrees relative to the output clock signal VCO_clk. In this regard, the n-th delayed reference clock signal Ref_clk_Φn generated by delaying the reference clock signal Ref_clk the longest through the replica voltage-controlled delay line 112 may be delayed from the reference clock signal Ref_clk by a delay time corresponding to a phase difference of 360 degrees relative to the output clock signal VCO_clk.

[0046] The DTC 113a may generate a selection reference clock signal Ref_clk_sel based on a coarse frequency value (FCV) and a fine frequency value (FFV) from a plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn output from the replica voltage-controlled delay line 112. For example, the FCV and the FFV may be bit data, and assuming that the FCV and the FFV are A-bit data and B-bit data, respectively, the DTC 113a may generate the selection reference clock signal Ref_clk_sel for a phase-locked operation based on fractional frequency division in [Equation 1].

[0047] FCV, FFV, and frequency division information DIV_N described below are external input signals from the outside, which are applied to determine the frequency of the PLL itself, and can be adjusted to allow the PLL to cover a wide bandwidth.

[0048] [Equation 1]

[0049]

[0050] In [Equation 1], F VCO_clk Refers to the frequency of the output clock signal VCO_clk, F Ref_clk is the frequency of the reference clock signal Ref_clk, and N is a specific integer division ratio. For example, N may correspond to the integer division ratio of the frequency divider 102. VCO_clk and F Ref_clk The reference clock signal Ref_clk_sel can be generated based on FCV and FFV to have a target fractional division ratio. For example, the integer division ratio can be determined by adjusting N for a PLL with a target fractional division ratio, and the fractional division ratio can be determined by adjusting FCV (A-bit data) and FFV (B-bit data).

[0051] refer to Figure 3B According to an embodiment, the DTC 113b may also receive division information DIV_N indicating an integer division ratio N of the frequency divider 102, and thus may provide a division ratio control signal DIV_CS to the frequency divider 102 to perform a division operation at a fractional division ratio close to a target fractional division ratio. The DTC 113b may provide the division ratio control signal DIV_CS to the frequency divider 102 during the first phase lock operation using the auxiliary PLL circuit 20a, and the frequency divider 102 may be configured to change the division ratio based on the division ratio control signal DIV_CS.

[0052] although Figure 3A and Figure 3B The charge pump 105 and the transconductance circuit 108 are shown as separate configurations, but this is merely an embodiment, and thus the inventive concept is not limited thereto, and the transconductance circuit 108 of the clock generator 100 may replace the charge pump 105 .

[0053] Figure 4 According to the embodiment Figure 3A or Figure 3B 108 is a circuit diagram of the transconductance circuit 108.

[0054] refer to Figure 4The transconductance circuit 108 may include a first current source IS1 and a second current source IS2 as well as a first switch circuit SW1 and a second switch SW2. The first current source IS1 may generate a positive current signal by converting a positive sampled voltage signal V_samP received from the sampler 107. The second current source IS2 may generate a negative current signal by converting a negative sampled voltage signal V_samN received from the sampler 107. The first switch circuit SW1 and the second switch circuit SW2 may receive a pulse signal pul from the pulse generator 109 and perform switching operations in response to the pulse signal pul. Therefore, the transconductance circuit 108 may generate a sampled current signal I_sam and output the sampled current signal I_sam to the loop filter 106. For example, the sampled current signal I_sam of the transconductance circuit 108 may be determined by the amplitude of the positive current signal of the first current source IS1, the amplitude of the negative current signal of the second current source IS2, and the duty cycle of the pulse signal pul. For example, when it is assumed that the duty cycle of the pulse signal pul is 20%, the amplitude of the sampling current signal I_sam may be as much as 20% of the amplitude of the positive current signal of the first current source IS1 .

[0055] Figure 5 is a flowchart for describing a method of performing sub-sampling PLL based on fractional frequency division of a PLL circuit according to an embodiment.

[0056] refer to Figure 5 In operation S200, the PLL circuit may obtain delay information about an output clock signal from a VCO using a voltage-controlled delay line. In operation S210, the PLL circuit may apply the delay information to a replica voltage-controlled delay line. In operation S220, the PLL circuit may generate a selection reference clock signal based on a plurality of delayed reference clock signals generated by the replica voltage-controlled delay line. In operation S230, the PLL circuit may perform a phase-locked operation based on fractional frequency division by performing subsampling PLL using the selection reference clock signal.

[0057] Figure 6 is a timing diagram for describing the delayed output clock signal VCO_clk_D having passed through the voltage-controlled delay line and the delayed reference clock signal Ref_clk_D having passed through the replica voltage-controlled delay line according to an embodiment. Figure 3A Provide a description.

[0058] refer to Figure 6As described above, the voltage-controlled delay line 110 may include a plurality of first delay elements, and as the output clock signal VCO_clk sequentially passes through the plurality of first delay elements, the output clock signal VCO_clk may be gradually delayed to a first time t1 (or a first phase Φ1), a second time t2 (or a second phase Φ2), a third time t3 (or a third phase Φ3), ..., an (m-1)th time t(m-1) (or an (m-1)th phase Φ(m-1)), an mth time tm (or an mth phase Φm), and the like. Figure 3A As shown, the voltage-controlled delay line 110 can be configured to output the final delayed second delayed output clock signal VCO_clk_Φn and the first delayed output clock signal VCO_clk_Φ1 having the same phase as the output clock signal VCO_clk to the DLL circuit 111. The delay information VDLL generated by the DLL circuit 111 can be used to control the replica voltage-controlled delay line 112 to gradually delay the reference clock signal Ref_clk by as much as the same delay time as the voltage-controlled delay line 110.

[0059] The replica voltage-controlled delay line 112 may include a plurality of second delay elements, and as delay information VDLL is applied to the plurality of second delay elements and the reference clock signal Ref_clk sequentially passes through the plurality of second delay elements, the reference clock signal Ref_clk may be progressively delayed to a first time t1, a second time t2, a third time t3, ..., the (m-1)th time t(m-1), the mth time tm, and so on. The replica voltage-controlled delay line 112 may be configured to output a plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. As described above, as delay information VDLL is applied to the replica voltage-controlled delay line 112, the reference clock signal Ref_clk may be sequentially delayed by a plurality of more fragmented delay times. Thus, the resolution of selecting the phase of the reference clock signal may be improved, and further, the increase in circuit complexity may not be increased.

[0060] Figure 7 is a block diagram for describing the operation of the DLL circuit 111 a according to the embodiment. Figure 7The DLL circuit 111a may include a phase frequency detector 111a_1 and a charge pump 111a_2. The voltage-controlled delay line 110a may include a plurality of first delay elements D11 to Dn1. The replica voltage-controlled delay line 112a may include a plurality of second delay elements D12 to Dn2. The replica voltage-controlled delay line 112a, which is a replica of the voltage-controlled delay line 110a, may include a plurality of second delay elements D12 to Dn2 having the same configuration or characteristics as the plurality of first delay elements D11 to Dn1 included in the voltage-controlled delay line 110a. For example, the number of second delay elements D12 to Dn2 may be the same as the number of first delay elements D11 to Dn1.

[0061] The voltage-controlled delay line 110a can receive a first delayed output clock signal VCO_clk_Φ1 and output a second delayed output clock signal VCO_clk_Φn, which is delayed by a plurality of first delay elements D11 to Dn1, to the DLL circuit 111a. For example, the first delayed output clock signal VCO_clk_Φ1 can be the same signal as the output clock signal output from the VCO, and the second delayed output clock signal VCO_clk_Φn can have a specific phase difference (e.g., 360 degrees) relative to the first delayed output clock signal VCO_clk_Φ1. The phase frequency detector 111a_1 can receive the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn and provide a detection result DR to the charge pump CP by detecting the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn. Based on the detection result DR, the charge pump CP can adjust the delay information (or bias voltage) VDLL and provide the delay information VDLL to the plurality of first delay elements D11 to Dn1. The DLL circuit 111a can repeat the above-described delay locking operation until the phases of the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn are the same.

[0062] DLL circuit 111a can provide delay information VDLL generated by repeated delay locking operations to multiple second delay elements D12 to Dn2 of replica voltage-controlled delay line 112a. Replica voltage-controlled delay line 112a can gradually delay the received reference clock signal Ref_clk and output each of multiple delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. The multiple delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn can be used to generate a selected reference clock signal required for a fractional frequency division-based phase-locked operation using a subsampling PLL.

[0063] Figure 8A is a block diagram of a DLL circuit 111b according to an embodiment, Figure 8B is used to describe Figure 8A A graph of the operation of the DLL circuit 111b.

[0064] refer to Figure 8A DLL circuit 111b may include a first switch SW1, a second switch SW2, a phase frequency detector 111b_1, a charge pump 111b_2, a lock detector 111b_3, and a state machine 111b_4. Before performing a delay lock operation using charge pump 111b_2, DLL circuit 111b may adjust the delay of the second delayed output clock signal VCO_clk_Φn to fall within a specific lock range, thereby preventing harmonic lock. For example, phase frequency detector 111b_1 may receive the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn from voltage-controlled delay line 110, detect the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn, and provide a first detection result DR1 to lock detector 111b_3. Lock detector 111b_3 can be activated in response to first activation signal EN1, can detect whether the phase of the second delayed output clock signal VCO_clk_Φn falls within a specific lock range based on first detection result DR1, and can provide lock detection result LDR to state machine 111b_4. Based on lock detection result LDR, state machine 111b_4 can provide delay control signal DL to voltage-controlled delay line 110. Based on lock detection result LDR, state machine 111b_4 can also generate second activation signal EN2 and provide second activation signal EN2 to first switch SW1 and second switch SW2.

[0065] For example, when the phase of the second delayed output clock signal VCO_clk_Φn does not fall within the specific locking range, the state machine 111b_4 may generate a second activation signal EN2 having a high level and may generate a new delay control signal DL for adjusting the delay of the second delayed output clock signal VCO_clk_Φn differently from before. The phase frequency detector 111b_1, the lock detector 111b_3, and the state machine 111b_4 may repeat the above operations until the phase of the second delayed output clock signal VCO_clk_Φn falls within the specific locking range.

[0066] As another example, when the phase of the second delayed output clock signal VCO_clk_Φn falls within a specific locking range, the state machine 111b_4 can generate a second activation signal EN2 having a low level and can stop adjusting the delay of the second delayed output clock signal VCO_clk_Φn. Subsequently, the phase frequency detector 111b_1 can detect the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn and provide a second detection result DR2 to the charge pump 111b_2. Based on the second detection result DR2, the charge pump 111b_2 can generate delay information VDLL.

[0067] Further references Figure 8BDuring the interval "t0" to "t1", the state machine 111b_4 may generate a second activation signal EN2 having a high level and a delay control signal DL having a value "D1". In this regard, the phase frequency detector 111b_1 may detect the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn and provide a first detection result DR1 to the lock detector 111b_3. Based on the first detection result DR1, the lock detector 111b_3 may detect that the phase of the second delayed output clock signal VCO_clk_Φn does not fall within the lock range and may provide a lock detection result LDR to the state machine 111b_4. During the interval "t1" to "t2", the state machine 111b_4 may generate a second activation signal EN2 having a high level and a delay control signal DL having a value "D2". In this regard, the phase frequency detector 111b_1 can detect the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn, whose delay has been adjusted, and provide a first detection result DR1 to the lock detector 111b_3. Based on the first detection result DR1, the lock detector 111b_3 can detect that the phase of the second delayed output clock signal VCO_clk_Φn does not fall within the lock range and can provide a lock detection result LDR to the state machine 111b_4. During the interval "t2" to "t3", the state machine 111b_4 can generate a second activation signal EN2 having a high level and a delay control signal DL having a value "D3". The phase frequency detector 111b_1 can detect the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the second delayed output clock signal VCO_clk_Φn, whose delay has been adjusted, and provide the first detection result DR1 to the lock detector 111b_3. Based on the first detection result DR1, the lock detector 111b_3 can detect that the phase of the second delayed output clock signal VCO_clk_Φn does not fall within the lock range and can provide the lock detection result LDR to the state machine 111b_4. During the interval "t3" to "t4", the state machine 111b_4 can generate the second activation signal EN2, which has a high level at the beginning, and the delay control signal DL having a value "D4". The phase frequency detector 111b_1 can detect the phase difference between the first delayed output clock signal VCO_clk_Φ1 and the delayed second delayed output clock signal VCO_clk_Φn, and provide the first detection result DR1 to the lock detector 111b_3. Based on the first detection result DR1, the lock detector 111b_3 can detect that the phase of the second delayed output clock signal VCO_clk_Φn falls within the lock range and can provide the lock detection result LDR to the state machine 111b_4.The state machine 111b_4 may generate the second activation signal EN2 transitioning to a low level after a specific time from ' t3 ', and the DLL circuit 111b may perform a delay locking operation for generating delay information VDLL in response to the second activation signal EN2 having a low level.

[0068] Figure 9 and Figure 10 is a detailed block diagram of the DTC 113 a according to an embodiment.

[0069] refer to Figure 9 , the DTC 113 a may include a delta-sigma modulator 113 a_1 , a frequency state machine 113 a_2 , a multiplexer 113 a_3 , and a fine time control circuit 113 a_4 .

[0070] The delta-sigma modulator 113a_1 can receive the FFV and generate a digital sequence (DS) based on the FFV, and provide the DS to the frequency state machine 113a_2. The FFV can be used to specify a desired frequency synthesis ratio to perform a phase-locked operation according to a target fractional frequency division ratio. The delta-sigma modulator 113a_1 can generate the DS at the same time-averaged ratio corresponding to the FFV.

[0071] The frequency state machine 113a_2 may receive the DS and FCV and may generate a phase control signal (PCS) for controlling the phase of the reference clock signal Ref_clk_sel based on the DS and FCV. The frequency state machine 113a_2 may provide the most significant bit (MSB) portion of the PCS to the multiplexer 113a_3. MSB (hereinafter referred to as the first phase control signal), and can provide the least significant bit (LSB) portion of the PCS to the fine time control circuit 113a_4 LSB (hereinafter referred to as the second phase control signal).

[0072] The multiplexer 113 a_3 may receive a plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn and may select a first phase control signal PCS based on the first phase control signal PCS. MSB , selects one of the plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn, and provides the selected delayed reference clock signal Ref_clk_Φm to the fine time control circuit 113a_4. In this regard, the first phase control signal PCS may be implemented using bit data matching the number of the plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. MSBFor example, when the number of the plurality of delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn is 32, the first phase control signal PCS may be implemented using 5-bit data. MSB .

[0073] The fine time control circuit 113a_4 can receive the selected delayed reference clock signal Ref_clk_Φm and the second phase control signal PCS LSB and can be based on the second phase control signal PCS LSB , by finely adjusting the delay time (or phase) of the selected delayed reference clock signal Ref_clk_Φm, a selected reference clock signal Ref_clk_sel is generated. The delay adjustment range of the selected delayed reference clock signal Ref_clk_Φm adjusted by the fine time control circuit 113a_4 can be limited to the constant delay time between the multiple delayed reference clock signals Ref_clk_Φ1 to Ref_clk_Φn. For example, when the delay time between the first delayed reference clock signal Ref_clk_Φ1 and the second delayed reference clock signal Ref_clk_Φ2 is "5", the delay adjustment range can be limited to "5".

[0074] Due to the continuous updating of the PCS, timing issues may occur in the frequency state machine 113a_2. Therefore, to solve the above problem, the delta-sigma modulator 113a_1 can be synchronized with the selected reference clock signal Ref_clk_sel output from the fine timing control circuit 113a_4 to generate the DS, and the frequency state machine 113a_2 can be synchronized with the nth delayed reference clock signal Ref_clk_Φn to generate the PCS.

[0075] Further references Figure 10 , DTC 113b may include a delta-sigma modulator 113b_1, a frequency state machine 113b_2, a multiplexer 113b_3 and a fine time control circuit 113b_4. Figure 9 The frequency state machine 113b_2 further performs additional operations compared to the frequency state machine 113a_2.

[0076] The frequency state machine 113b_2 can also receive an instruction indicating the auxiliary PLL circuit ( Figure 3A The frequency division information DIV_N of the integer frequency division ratio of the frequency divider 102 can be generated accordingly. Figure 3AThe frequency divider 102 of the auxiliary PLL circuit performs a frequency division ratio control signal DIV_CS at a fractional frequency division ratio close to the target fractional frequency division ratio. For example, during the first phase lock operation using the auxiliary PLL circuit, the frequency state machine 113b_2 may generate the frequency division ratio control signal DIV_CS and provide the frequency division ratio control signal DIV_CS to the auxiliary PLL circuit. Figure 3A ) divider 102. In this regard, ( Figure 3A The frequency divider 102 may include a configuration capable of changing a frequency division ratio based on a frequency division ratio control signal DIV_CS.

[0077] Figure 11 1 is a block diagram of a wireless communication device 1000 according to an embodiment. The wireless communication device 1000 may include a digital signal processor 1100, a DAC 1200, an ADC 1300, a radio frequency integrated circuit (RFIC) 1400, a front-end module 1500, and an antenna 1600. The digital signal processor 1100 may process signals including information to be transmitted or received according to a set communication scheme. For example, the digital signal processor 1100 may process signals according to a communication scheme such as orthogonal frequency division multiplexing (OFDM), orthogonal frequency division multiple access (OFDMA), wideband code division multiple access (WCDMA), or high-speed packet access plus (HSPA+).

[0078] The DAC 1200 may convert a digital signal including information to be transmitted into an analog signal and may provide the converted transmission signal to the RFIC 1400 . The ADC 1300 may convert an analog signal received from the RFIC 1400 into a digital signal and may provide the converted digital signal to the digital signal processor 1100 .

[0079] The RFIC 1400 may include a first mixer 1410, a second mixer 1420, and a PLL circuit 1430. The RFIC 1400 may generate a radio frequency (RF) signal by up-converting the frequency of a transmission signal in a baseband received from the DAC 1200 using the first mixer 1410 and the PLL 1430. The RFIC 1400 may generate a baseband signal by down-converting the frequency of a reception signal in an RF band received from the front-end module 1500 using the second mixer 1420 and the PLL 1430. Figures 1 to 10 The described embodiments can all be applied to the PLL 1430 .

[0080] The front-end module 1500 may include an amplifier, a duplexer, etc. The front-end module 1500 may amplify the RF transmit signal provided from the RFIC 1400 and may transmit the amplified signal through the antenna 1600. In some embodiments, the wireless communication device 1000 may include a plurality of antennas 1600, and the front-end module 1500 may separate the RF transmit signal for each frequency band and provide the separated RF transmit signal to the antenna 1600 corresponding thereto.

[0081] Figure 12 is a schematic diagram illustrating a communication device including a clock generator for performing a phase-locked operation on a clock according to an embodiment.

[0082] refer to Figure 12 According to an embodiment, the home appliance 2100, the home appliance 2120, the entertainment device 2140, and the access point (AP) 2200 may each include a clock generator for performing a phase-locked operation on the clock. In some embodiments, the home appliance 2100, the home appliance 2120, the entertainment device 2140, and the AP 2200 may configure an Internet of Things (IoT) network system. Figure 12 The communication devices shown in FIG are merely examples, and it will be understood that Figure 12 Other communication devices not shown in the figure may also include the wireless communication device according to the embodiment.

[0083] Figure 13 is a block diagram of an IoT device 3000 according to an embodiment.

[0084] IoT device 3000 may include an application processor 3100, a transceiver 3200, a memory

[0085] 3300 , display 3400 , sensor 3500 and input / output (I / O) device 3600 .

[0086] IoT device 3000 can communicate with external entities via transceiver 3200. Transceiver 3200 can be a modem communication interface that can access, for example, a wired local area network (LAN), a wireless short-range communication interface (e.g., Bluetooth, Wireless Fidelity (Wi-Fi), and Zigbee), a power line communication (PLC), or a mobile cellular network (e.g., third generation (3G), long term evolution (LTE), etc.). Transceiver 3200 can include a clock generator according to the above-described embodiments.

[0087] The application processor 3100 may control the overall operation of the IoT device 3000 and the operations configured by the IoT device 3000. The application processor 3100 may perform various operations. In some embodiments, the application processor 3100 may include a single core or may include multiple cores.

[0088] Sensor 3500 may be, for example, an image sensor for sensing images. Sensor 3500 may be connected to application processor 3100 and may transmit generated image information to application processor 3100. Sensor 3500 may be a biometric sensor for sensing biometric information. Sensor 3500 may be any sensor, such as an illumination sensor, an acoustic sensor, or an acceleration sensor.

[0089] The display 3400 can display the internal status information of the IoT device 3000. The display 3400 may include a touch sensor (not shown). In addition, the display 3400 may include input or output functions and the appearance of a user interface. The user can control the IoT device 3000 through the touch sensor and the user interface.

[0090] The input / output device 3600 may include an input unit such as a touchpad, a keyboard, input buttons, etc., and an output unit such as a display, a speaker, etc. The memory 3300 may store control instruction codes, control data, or user data for controlling the IoT device 3000. The memory 3300 may include at least one of a volatile memory and a non-volatile memory.

[0091] The IoT device 3000 may further include a power supply unit including a battery for internal power supply or receiving power supply from an external source. In addition, the IoT device 3000 may further include a storage device. The storage device may be a non-volatile medium such as a hard disk drive (HDD), a solid-state drive (SSD), an embedded multimedia card (eMMC), or a universal flash storage device (UFS). The storage device may store user information provided by the input / output device 3600 and various pieces of sensing information collected by the sensor 3500.

[0092] The output clock signal may be used for at least some of the above components of the IoT device 3000, for example, the application processor 3100, the transceiver 3200, the memory 3300, the display 3400, the sensor 3500, and the input / output device 3600, and the output clock signal may be generated by the embodiment of the present inventive concept (for example, the above combination). Figures 1 to 10 A clock generator (of those embodiments described) is generated.

[0093] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A phase-locked loop (PLL) circuit, comprising: a voltage-controlled oscillator configured to generate an output clock signal; a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and perform a phase-locked operation based on fractional frequency division based on the output clock signal; as well as a fractional frequency division control circuit configured to provide a selected reference clock signal for the fractional frequency division-based phase-locked operation to the sub-sampling PLL circuit, Wherein, the fractional frequency division control circuit includes: a voltage-controlled delay line configured to route the feedback signal and generate delay information based on the feedback signal; a replica voltage-controlled delay line having the delay information applied thereto and configured to route the reference clock signal to generate a plurality of delayed reference clock signals, each delayed reference clock signal being delayed by a different respective delay time; and The digital-to-time converter (DTC) is configured to generate the selected reference clock signal according to the plurality of delayed reference clock signals and output the selected reference clock signal to the sub-sampling PLL circuit.

2. The PLL circuit according to claim 1, wherein The replica voltage-controlled delay line includes a plurality of delay elements having the same characteristics as the plurality of delay elements included in the voltage-controlled delay line.

3. The PLL circuit according to claim 1, wherein The value of the frequency of the reference clock signal is obtained by applying a target fractional frequency division ratio to the frequency of the output clock signal phase-locked by the sub-sampling PLL circuit.

4. The PLL circuit according to claim 1, wherein The fractional frequency division control circuit further includes a delay locked loop (DLL) circuit connected to the voltage-controlled delay line and configured to generate the delay information by locking a delay of the feedback signal having passed through the voltage-controlled delay line.

5. The PLL circuit according to claim 4, wherein: The delay information includes bias voltages of a plurality of delay elements included in the voltage-controlled delay line.

6. The PLL circuit according to claim 4, wherein: The DLL circuit is connected to the replica voltage-controlled delay line and is further configured to provide the delay information to the replica voltage-controlled delay line.

7. The PLL circuit according to claim 4, wherein: The voltage-controlled delay line includes a plurality of first delay elements connected in series and each configured to delay a received signal by the same delay time to output a delayed feedback signal having a specific phase shift relative to the feedback signal.

8. The PLL circuit according to claim 7, wherein: The replica voltage-controlled delay line includes a plurality of second delay elements, which are connected in series and configured to delay a received signal by the same delay time as the plurality of first delay elements of the voltage-controlled delay line, and the plurality of second delay elements are further configured to output the plurality of delayed reference clock signals gradually delayed from the reference clock signal to the DTC through respective output terminals of the plurality of second delay elements.

9. The PLL circuit according to claim 4, wherein: The DLL circuit is further configured to start an operation for locking the delay of the feedback signal when the phase of the delayed feedback signal falls within a specific locking range by adjusting the degree of delay of the feedback signal caused by the voltage-controlled delay line to prevent harmonic locking.

10. The PLL circuit according to claim 1, wherein The DTCs include: a multiplexer configured to select a delayed reference clock signal from the plurality of delayed reference clock signals and output the selected delayed reference clock signal; and A fine time control (FTC) circuit is configured to generate the selected reference clock signal by adjusting a delay of the delayed reference clock signal output from the multiplexer.

11. The PLL circuit according to claim 10, wherein: The number of bits of the first bit signal received for the selection operation of the multiplexer is greater than the number of bits of the second bit signal received for the adjustment operation of the FTC circuit.

12. The PLL circuit according to claim 10, wherein: The delay adjustment range of the FTC circuit corresponds to a constant delay time between the plurality of delayed reference clock signals.

13. The PLL circuit according to claim 10, further comprising: an auxiliary PLL circuit configured to perform a phase locking operation based on integer frequency division on the output clock signal before a phase locking operation based on fractional frequency division of the sub-sampling PLL circuit, The DTC is configured to adjust the frequency division ratio in the integer-frequency division-based phase-locked operation to generate an output clock signal whose frequency is approximately equal to the target fractional frequency division ratio of the fractional-frequency division-based phase-locked operation within a specific range.

14. A phase-locked loop (PLL) circuit, comprising: a voltage-controlled oscillator configured to generate an output clock signal; a sub-sampling PLL circuit configured to receive the output clock signal as a feedback signal and perform a phase-locked operation based on fractional frequency division based on the output clock signal; as well as The fractional frequency division control circuit is configured as follows: providing a selected reference clock signal for the fractional frequency division based phase locked operation to the sub-sampling PLL circuit; when the feedback signal has a first frequency, generating delay information related to a constant delay time within one cycle of the feedback signal by performing a delay operation using the feedback signal; generating, based on the delay information, a plurality of delayed reference clock signals gradually delayed by as much as the delay time by using a reference clock signal having a second frequency; as well as The selected reference clock signal is generated using the plurality of delayed reference clock signals.

15. The PLL circuit according to claim 14, wherein: When the phase of the output clock signal is locked by the fractional frequency division-based phase lock operation, the first frequency and the second frequency include a target fractional frequency division ratio.

16. The PLL circuit according to claim 14, wherein: The fractional frequency division control circuit includes a digital time converter DTC, and the DTC includes: a multiplexer configured to select a delayed reference clock signal from the plurality of delayed reference clock signals and output the selected delayed reference clock signal; and A fine time control (FTC) circuit is configured to generate the selected reference clock signal by adjusting a delay of the delayed reference clock signal output from the multiplexer.

17. The PLL circuit according to claim 16, wherein: The DTC further includes a delta-sigma modulator and a frequency state machine, wherein the delta-sigma modulator is configured to generate a first bit signal for a selection operation of the multiplexer and a second bit signal for fine time control.

18. The PLL circuit according to claim 14, wherein: The fractional frequency division control circuit includes: a voltage-controlled delay line configured to receive the feedback signal to generate the delay information; and a replica voltage-controlled delay line configured to receive the reference clock signal to generate the plurality of delayed reference clock signals. wherein the replica voltage-controlled delay line includes the same configuration as that of the voltage-controlled delay line to perform a gradual delay operation up to a delay time the same as that of the voltage-controlled delay line when the delay information is applied to the replica voltage-controlled delay line.

19. The PLL circuit according to claim 18, wherein: The delay information includes bias voltages of a plurality of delay elements included in the voltage-controlled delay line.

20. A clock generator comprising: a voltage-controlled oscillator configured to generate an output clock signal; an auxiliary phase-locked loop (PLL) circuit configured to perform a phase-locked operation based on integer frequency division on the output clock signal; a sub-sampling PLL circuit configured to perform a phase locking operation based on fractional frequency division on the output clock signal after the phase locking operation based on integer frequency division; as well as a fractional frequency division control circuit configured to provide a selected reference clock signal for the fractional frequency division-based phase-locked operation to the sub-sampling PLL circuit, Wherein, the fractional frequency division control circuit includes: a voltage-controlled delay line configured to route a feedback signal to generate delay information; a replica voltage-controlled delay line having the delay information applied thereto and comprising the same characteristics as the voltage-controlled delay line, and configured to route a reference clock signal to generate a plurality of delayed reference clock signals delayed by different respective delay times; and The digital-to-time converter (DTC) is configured to generate the selected reference clock signal according to the plurality of delayed reference clock signals and output the selected reference clock signal to the sub-sampling PLL circuit.

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