Frequency divider, frequency division method and device

Abstract

This invention provides a frequency divider, a frequency division method, and an apparatus. The frequency divider includes: a first counting unit capable of acquiring a clock input signal, a first set signal, and a first reset signal; a second counting unit capable of acquiring a clock input signal, a second set signal, and a second reset signal; a control unit generating a first output signal based on the first counting signal and generating a second output signal based on the second counting signal. This invention solves the problem in related technologies where multi-mode frequency dividers cannot achieve a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients. It achieves a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients.

Description

Technical Field

[0001] This invention relates to the field of communications, and more specifically, to a frequency divider, a frequency division method, and an apparatus. Background Technology

[0002] Multi-modulus dividers (MMDs) are commonly used in high-speed phase-locked loop (PLL) circuits. They divide the high-frequency clock output from the PLL and input it to a phase frequency detector (PFD) for comparison with a reference clock frequency, or divide the high-frequency clock output from the PLL and transmit it to digital circuits.

[0003] With the development of integrated circuits and the increasing speed requirements of systems, the output frequency of PLLs is getting higher and higher, requiring multi-mode dividers to operate at higher frequencies, which in turn further increases the operating frequency requirements of digital circuits. When the multi-mode divider outputs a clock to the digital circuit, at the same frequency, the closer the clock duty cycle is to 50%, the easier it is to synthesize the digital circuit and the greater the design margin. Therefore, given the current high speed requirements for digital circuits, the clock output by the multi-mode divider needs to have a good duty cycle.

[0004] The duty cycle of the output clock of a traditional multi-mode frequency divider generally varies with the division factor. Within the range of continuous division by the multi-mode frequency divider, it cannot be guaranteed that the clock duty cycle for all division factors will be close to 50%. Related technologies typically employ the following methods to improve the output clock duty cycle of a multi-mode frequency divider: 1) Adding a divide-by-two circuit to the multi-mode frequency divider to achieve a 50% duty cycle clock output; however, this scheme cannot achieve continuous division, only even-number division; 2) Extending the pulse width of the output clock of the multi-mode frequency divider; however, this scheme can only improve the clock duty cycle for specific division factors and is not applicable to all division factors.

[0005] Regarding the issue that multi-mode frequency dividers cannot achieve a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients, no effective solution has yet been proposed in the aforementioned technologies. Summary of the Invention

[0006] This invention provides a frequency divider, frequency division method, and apparatus to at least solve the problem in related technologies that multi-mode frequency dividers cannot achieve a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary frequency division coefficients.

[0007] According to one embodiment of the present invention, a frequency divider is provided, comprising:

[0008] The first counting unit is configured to acquire a clock input signal, a first set signal, and a first reset signal, and to count according to the clock input signal, the first set signal, and the first reset signal to output a first counting signal;

[0009] The second counting unit is configured to acquire a clock input signal, a second set signal, and a second reset signal, and to count according to the clock input signal, the second set signal, and the second reset signal to output a second counting signal;

[0010] The control unit is configured to generate a first output signal based on the first counting signal and to generate a second output signal based on the second counting signal; the control unit is further configured to configure a second reset signal based on the first output signal and to configure the first reset signal based on the second output signal.

[0011] Wherein, the first reset signal is the inverted signal of the second reset signal; the modulus of both the first counting unit and the second counting unit is N, where N is a natural number.

[0012] According to another embodiment of the present invention, a frequency division method is also provided, applied to the frequency divider in the above embodiments, the method comprising:

[0013] The system acquires a clock input signal, a first set signal, and a first reset signal, and counts them using a first counting unit to output a first counting signal.

[0014] The system acquires a clock input signal, a second set signal, and a second reset signal, and counts them using a second counting unit to output a second counting signal.

[0015] A first output signal is generated based on the first counting signal, and a second output signal is generated based on the second counting signal; a second reset signal is configured based on the first output signal, and a first reset signal is configured based on the second output signal.

[0016] Wherein, the first reset signal is the inverted signal of the second reset signal, and the modulus of both the first counting unit and the second counting unit is N, where N is a natural number.

[0017] According to another embodiment of the present invention, a service transmission apparatus is also provided, applied to the frequency divider in the above embodiments, the apparatus comprising:

[0018] The first acquisition module is used to acquire a clock input signal, a first set signal, and a first reset signal, and to count the clock input signal, the first set signal, and the first reset signal using a first counting unit to output a first counting signal.

[0019] The second acquisition module is used to acquire a clock input signal, a second set signal, and a second reset signal, and to count the clock input signal, the second set signal, and the second reset signal using a second counting unit to output a second counting signal.

[0020] An output module is configured to generate a first output signal based on the first counting signal, and to generate a second output signal based on the second counting signal, and to configure a second reset signal based on the first output signal, and to configure the first reset signal based on the second output signal.

[0021] Wherein, the first reset signal is the inverted signal of the second reset signal, and the modulus of both the first counting unit and the second counting unit is N, where N is a natural number.

[0022] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0023] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0024] Through this invention, the first counting unit in the frequency divider can acquire a clock input signal, a first set signal, and a first reset signal, and count according to the clock input signal, the first set signal, and the first reset signal to output a first counting signal; the second counting unit can acquire a clock input signal, a second set signal, and a second reset signal, and count according to the clock input signal, the second set signal, and the second reset signal to output a second counting signal; furthermore, the control unit generates a first output signal according to the first counting signal and generates a second output signal according to the second counting signal; the control unit is also configured to configure the second reset signal according to the first output signal and configure the first reset signal according to the second output signal; wherein, the first reset signal is the inverted signal of the second reset signal; the modulus of both the first counting unit and the second counting unit is N, where N is a natural number. Therefore, this invention can solve the problem in related technologies where multi-mode frequency dividers cannot achieve a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients, thereby achieving a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0026] Figure 1 This is a functional schematic diagram (a) of a frequency divider provided according to an embodiment of the present invention;

[0027] Figure 2 This is a functional schematic diagram (II) of a frequency divider provided according to an embodiment of the present invention;

[0028] Figure 3 This is an internal configuration diagram of the first counting unit provided according to an embodiment of the present invention;

[0029] Figure 4 This is an internal configuration diagram of the second counting unit provided according to an embodiment of the present invention;

[0030] Figure 5 This is a circuit diagram of a frequency divider provided according to a specific embodiment of the present invention;

[0031] Figure 6 This is an internal circuit diagram of a first programmable counting circuit provided according to a specific embodiment of the present invention;

[0032] Figure 7This is a signal waveform diagram of a frequency divider performing a 2N+2 frequency division according to a specific embodiment of the present invention;

[0033] Figure 8 This is a signal waveform diagram of a frequency divider performing a 2N+3 frequency division according to a specific embodiment of the present invention;

[0034] Figure 9 This is a flowchart of a frequency division method provided according to an embodiment of the present invention;

[0035] Figure 10 This is a structural block diagram of a frequency division device provided according to an embodiment of the present invention. Detailed Implementation

[0036] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0038] Example 1

[0039] This embodiment provides a frequency divider. Figure 1 This is a functional schematic diagram (I) of a frequency divider provided according to an embodiment of the present invention, as shown below. Figure 1 As shown, the frequency divider in this embodiment includes:

[0040] The first counting unit 102 is configured to acquire a clock input signal, a first set signal, and a first reset signal, and to count according to the clock input signal, the first set signal, and the first reset signal to output a first counting signal;

[0041] The second counting unit 104 is configured to acquire a clock input signal, a second set signal, and a second reset signal, and to count according to the clock input signal, the second set signal, and the second reset signal to output a second counting signal;

[0042] The control unit 106 is configured to generate a first output signal based on a first counting signal and to generate a second output signal based on a second counting signal; the control unit is also configured to configure a second reset signal based on the first output signal and to configure a first reset signal based on the second output signal.

[0043] Wherein, the first reset signal is the inverted signal of the second reset signal; the modulus of both the first counting unit and the second counting unit is N, where N is a natural number.

[0044] It should be further explained that both the first counting unit and the second counting unit in the above embodiments can be implemented by a programmable timer; the clock input signal and the first set signal acquired by the first counting unit can be provided by the circuit or chip where the frequency divider is located in this embodiment according to the actual signal processing object. The first reset signal acquired by the first counting unit can be a preset reset signal of the circuit or chip at the initial moment, and then after the control unit generates the second output signal according to the second counting signal, the second output signal can be used as the first reset signal. In the first counting unit, the clock input signal is the object to be frequency divided, the first set signal indicates that the first counting unit sets the corresponding counting bit, and the first reset signal indicates whether the first counting unit should be cleared and reset.

[0045] The clock input signal acquired by the second counting unit can be provided by the circuit or chip containing the frequency divider in this embodiment, based on the actual signal processing object. The second set signal acquired by the second counting unit can be obtained by the circuit or chip containing the frequency divider in this embodiment, or it can be obtained by processing the first set signal. The second reset signal acquired by the second counting unit can be a preset reset signal of the circuit or chip at the initial moment. Then, after the control unit generates the first output signal based on the first counting signal, the first output signal can be used as the second reset signal. In the second counting unit, the clock input signal is the object to be frequency divided, the second set signal indicates that the second counting unit sets the corresponding counting bit, and the second reset signal indicates whether the second counting unit should be cleared and reset.

[0046] The first counting signal output by the first counting unit is used to indicate the pulse state output by the first counting unit during the counting process. Similarly, the second counting signal output by the second counting unit is used to indicate the pulse state output by the second counting unit during the counting process. The control unit is configured to generate a first output signal based on the first counting signal and a second output signal based on the second counting signal. That is, the control unit is instructed to output the first output signal and the second output signal respectively based on the corresponding pulse states output by the first counting unit and the second counting unit. The first output signal and the second output signal are the output signals obtained after frequency division processing of the clock input signal.

[0047] When generating the first output signal and the second output signal, the control unit can also be configured to configure the second reset signal according to the first output signal and configure the first reset signal according to the second output signal. That is, the control unit is instructed to send the first output signal as the second reset signal to the second counting unit for reset processing, and to send the second output signal as the first set signal to the first counting unit for reset processing.

[0048] The aforementioned first reset signal is the inverted signal of the second reset signal; that is, the first reset signal is "0" and the second reset signal is "1", or vice versa. The fact that the first reset signal is the inverted signal of the second reset signal indicates that at any given time, only one of the first and second counting units is in the set counting state, while the other is in the cleared reset state; that is, the first and second counting units work alternately. To achieve this, an RS flip-flop can be set in the control unit so that the first and second output signals generated by the control unit based on the first and second counting signals are inverted signals.

[0049] In this embodiment, the frequency divider performs continuous frequency division of the clock input signal by alternating counting between the first counting unit and the second counting unit during the frequency division process.

[0050] In this embodiment, the frequency divider has a first counting unit that acquires a clock input signal, a first set signal, and a first reset signal, and counts according to these signals to output a first counting signal. A second counting unit acquires a clock input signal, a second set signal, and a second reset signal, and counts according to these signals to output a second counting signal. Furthermore, a control unit generates a first output signal based on the first counting signal and a second output signal based on the second counting signal. The control unit is also configured to configure the second reset signal based on the first output signal and the first reset signal based on the second output signal. The first reset signal is the inverted version of the second reset signal. The modulus of both the first and second counting units is N, where N is a natural number. Therefore, this invention solves the problem in related technologies where multi-mode frequency dividers cannot achieve a duty cycle of approximately 50% for the output clock while ensuring continuous output and arbitrary division ratios. This invention achieves a duty cycle of approximately 50% for the output clock while ensuring continuous output and arbitrary division ratios.

[0051] In an optional embodiment, the frequency divider in this embodiment is configured as follows:

[0052] Divide the clock input signal by 2N+2, or divide the clock input signal by 2N+3.

[0053] It should be further explained that, since N is any natural number, the above 2N+2 indicates any even number calculated based on N being any natural number, and the above 2N+3 indicates any odd number calculated based on N being any natural number. Therefore, in this embodiment, the frequency divider divides the clock input signal by 2N+2, indicating that the frequency divider in this embodiment performs even-number division on the clock input signal according to the division requirements; in this embodiment, the frequency divider divides the clock input signal by 2N+3, indicating that the frequency divider in this embodiment performs odd-number division on the clock input signal according to the division requirements.

[0054] It should be further explained that when the frequency divider in this embodiment performs a 2N+2 division on the clock input signal, the alternating counting of the first and second counting units with a division factor of N ensures that the duty cycle of the output clock signal is (N+1) / (2N+2), i.e., the duty cycle is always 50%. When the frequency divider in this embodiment performs a 2N+3 division on the clock input signal, the alternating counting of the first and second counting units with a division factor of N ensures that the duty cycle of the output divided signal is (N+1) / (2N+3). This duty cycle approaches 50% as the value of N increases. That is, when performing odd-number division, the frequency divider in this embodiment can make the duty cycle infinitely close to 50%.

[0055] In an alternative embodiment, the control unit 106 is further configured to:

[0056] Acquire the first set signal and the CTRL signal, and generate the second set signal based on the first set signal and the CTRL signal.

[0057] In an optional embodiment, the control unit 106 includes an adder 1062, wherein the adder 1062 is configured to acquire a first set signal and a CTRL signal, and accumulate the first set signal and the CTRL signal to generate a second set signal.

[0058] Figure 2 This is a functional schematic diagram (II) of a frequency divider provided according to an embodiment of the present invention. The adder configuration in the control unit in the above optional embodiment is as follows: Figure 2 As shown.

[0059] In an optional embodiment, the frequency divider in this embodiment is configured as follows:

[0060] When the CTRL signal indicates "0", the clock input signal is divided by 2N+2; or when the CTRL signal indicates "1", the clock input signal is divided by 2N+3.

[0061] It should be further explained that, in the above optional embodiments, the adder in the control unit can also control the division coefficient of the frequency divider in this embodiment, that is, divide the clock input signal by 2N+2 or 2N+3. Specifically, the adder can superimpose the first set signal corresponding to the first counting unit. If the CTRL signal indicates "0", then the first set signal of the first counting unit is the same as the second set signal of the second counting unit, thereby making the counting objects of the first counting unit and the second counting unit both 0 to N+1.

[0062] If the CTRL signal indicates "1", then the second set signal of the second counting unit is the first set signal plus 1.

[0063] In an optional embodiment, the control unit 106 is further configured to perform logical processing on the first counting signal to generate a first output signal, and to perform logical processing on the second counting signal to generate a second output signal.

[0064] It should be further noted that the logic processing performed by the control unit on the first counting signal and the second counting signal can be implemented, for example, by an RS flip-flop.

[0065] In an alternative embodiment, Figure 3 This is an internal configuration diagram of the first counting unit provided according to an embodiment of the present invention. The internal structure of the first counting unit is as follows: Figure 3 As shown, the first counting unit 102 includes:

[0066] The first trigger subunit 1022 is composed of multiple D flip-flops connected in series. The first trigger subunit is configured to acquire a clock input signal, a first set signal and a first reset signal, and output a first trigger output signal according to the acquired clock input signal, first set signal and first reset signal.

[0067] NAND gate subunit 1024 is configured to acquire a first trigger output signal and a logic input signal, and output a first logic output signal based on the first trigger output signal and the logic input signal;

[0068] The second trigger subunit 1026 is configured to output a first counting signal according to a first logic output signal; the second trigger subunit is also configured to configure a logic input signal according to the first counting signal.

[0069] It should be further explained that the number of multiple D flip-flops in the first trigger subunit mentioned above corresponds to the first set signal that operates in relation to the first counting unit. The first set signal can be represented as C <m:0>The C <m:0>The binary code is used to indicate that the first counting unit should perform the setting process on the control bits from 0 to M. The multiple D flip-flops in the first trigger subunit of the first counting unit correspond to the setting process of the control bits from 0 to M. Therefore, M+1 D flip-flops need to be set in the first trigger subunit.

[0070] Each of the aforementioned D flip-flops is equipped with an input terminal, a set terminal, a reset terminal, and an output terminal. The M+1 D flip-flops are connected in series, meaning that the output and input terminals of any two adjacent D flip-flops are interconnected. Each of the M+1 D flip-flops corresponds to a control bit. The D flip-flop at control bit 0 is used to acquire the clock input signal. The set terminal of each D flip-flop is set according to the control signal of the corresponding control bit in the first set signal input. The reset terminal of each D flip-flop is reset according to the corresponding first reset signal input.

[0071] The first trigger subunit is set by multiple D flip-flops under the control of the first set signal. The first trigger output signal is then processed by the NAND gate subunit and the second trigger subunit in sequence to realize the counting process of the first counting unit and output the first counting signal.

[0072] The aforementioned NAND gate subunit may specifically include a NAND logic gate circuit to perform a logic output on the first trigger output signal input to the first trigger subunit. The logic input signal of the aforementioned NAND gate subunit may be a preset signal or a signal provided by the second trigger subunit. In the process of implementing the output of the first counting signal, the aforementioned second trigger subunit is also configured to configure a logic input signal according to the first counting signal, specifically instructing the second trigger subunit to send the output first counting signal as the logic input signal of the NAND gate subunit to the NAND gate subunit.

[0073] In an alternative embodiment, Figure 4 This is an internal configuration diagram of the second counting unit provided according to an embodiment of the present invention. The internal structure of the second counting unit is as follows: Figure 4 As shown, the second counting unit 104 includes:

[0074] The third trigger subunit 1042 is composed of multiple D flip-flops connected in series. The third trigger subunit is configured to acquire a clock input signal, a second set signal and a second reset signal, and output a second trigger output signal according to the acquired clock input signal, second set signal and second reset signal.

[0075] NAND gate subunit 1044 is configured to acquire a second trigger output signal and a logic input signal, and output a second logic output signal based on the second trigger output signal and the logic input signal;

[0076] The fourth trigger subunit 1046 is configured to output a second counting signal according to the second logic output signal; the second trigger subunit is also configured to configure a logic input signal according to the second counting signal.

[0077] It should be further noted that the internal structure of the second counting unit is the same as that of the first counting unit. Specifically, in the second counting unit, the third trigger subunit has the same circuit structure as the first trigger subunit in the first counting unit of the optional embodiment, and the fourth trigger subunit has the same circuit structure as the second trigger subunit in the second counting unit of the optional embodiment. Therefore, the internal structure and operation of the second counting unit in the optional embodiment correspond to those of the first counting unit, and will not be described again here.

[0078] To further illustrate the working principle of the frequency divider in this embodiment, the following describes the working method of the frequency divider in this embodiment through specific embodiments; Figure 5 This is a circuit diagram of a frequency divider provided according to a specific embodiment of the present invention, such as... Figure 5 As shown, the frequency divider in this specific embodiment consists of a first programmable counting circuit 201, a second programmable counting circuit 202, an RS flip-flop circuit 203, and an adder circuit 204.

[0079] In this specific embodiment, the inputs of the overall circuit containing the frequency divider include the clock input signal CLKIN and the set signal C. <m:0>In addition to the CTRL signal, the overall circuit outputs a first output signal DIVOUTP and a second output signal DIVOUTN. The aforementioned CLKIN is input to the input terminals of the first programmable counter circuit and the second programmable counter circuit, respectively. <m:0>As the first set signal input to the set terminal of the first programmable counter circuit, C <m:0>It is also input into the adder circuit.

[0080] Both the first and second programmable counting circuits include an input terminal, a set terminal, a reset terminal, and an output terminal. The clock input signal CLKIN is input to the input terminals of both the first and second programmable counting circuits. The set signal C... <m:0>As the first set signal input to the set terminal of the first programmable counter circuit, the second output signal DIVOUTN is configured as the output of the overall circuit and also serves as the first reset signal of the first programmable counter circuit, input to the reset terminal of the first programmable counter circuit; similarly, the first output signal DIVOUTP is configured as the output of the overall circuit and also serves as the second reset signal of the second programmable counter circuit, input to the reset terminal of the second programmable counter circuit.

[0081] The above adder is used to input the set signal (i.e., the first set signal) C. <m:0>And the CTRL signal, and according to C <m:0>And the CTRL signal generates the second set signal C1 <m:0>As can be seen from the working principle of the adder, C1 <m:0> ＝C <m:0>+CTRL. Therefore, the second set signal C1 input to the set terminal of the second programmable counter circuit. <m:0>The first set signal C <m:0>Superimposed with the CTRL signal.

[0082] The first programmable counter circuit calculates the clock input signal CLKIN and the first set signal C based on the above-mentioned clock input signal CLKIN and the first set signal C. <m:0>During the counting process using the first reset signal DIVOUTN, the output terminal outputs the first counting signal CLK_R to the RS flip-flop. The second programmable counting circuit then uses the clock input signal CLKIN and the second set signal C1 as input. <m:0>During the counting process of the second reset signal, the output terminal outputs the second counting signal CLK_S to the RS flip-flop.

[0083] The first programmable counting circuit and the second programmable counting circuit have the same internal circuit structure. Taking the first programmable counting circuit as an example, the first programmable counting circuit contains M+1 settable and resettable D flip-flops (DFF) circuits, that is... Figure 5 As shown in Figures 301 to 303, the D port of each DFF circuit is connected to the Qn port, so that each DFF circuit constitutes a frequency divider circuit, and M+1 DFF circuits are connected in series, that is, the output Q of the previous stage DFF circuit is connected to the input CLK of the next stage DFF circuit.

[0084] The clock input signal CLKIN of the first programmable counter circuit is connected to the input CLK of the DFF circuit 301, and the first set signal C of the set terminal of the first programmable counter circuit is connected to the clock input signal CLKIN of the DFF circuit 301. <m:0>Each of the M+1 DFF circuits is connected to its set input; the reset input of each of the M+1 DFF circuits receives the first reset signal DIVOUTN. The overall output signal of the M+1 DFF circuits is CLK. <m:0>Connected to the logic gate NAND circuit 304 and input to the IN gate of NAND circuit 304. <m:1>Input terminal; simultaneously, the IN terminal of the NAND circuit. <0> The input terminal is also connected to the first counting signal CLK_R, meaning the NAND circuit counts based on CLK. <m:0>Along with CLK_R, the first logic output signal is output to the DFF circuit 305. The DFF circuit 305 generates the corresponding first counting signal CLK_R based on the first logic output signal and the clock input signal CLKIN of the first programmable counter circuit. The internal structure of the second programmable counter circuit is basically the same as that of the first programmable counter circuit, so it will not be described again here.

[0085] During the counting process, the first programmable counting circuit can achieve a maximum of 2. M+1 The count is -1 clock cycle, M+1 is the number of the first programmable counting circuit DFF circuits mentioned above (excluding the DFF circuit 305 used to output CLK_R); as explained in the previous embodiments, M is related to the set signal C <m:0>Since it is related, I will not go into details here.

[0086] It should be further explained that the first programmable counting circuit contains M+1 DFF circuits. During the actual counting process, the first programmable counting circuit also calls some of these DFF circuits. Therefore, for the first programmable counting circuit with a modulus of N, i.e., 1... <N<2 M+1 -1, N is the binary value C <m:0>Convert to decimal value.

[0087] In the aforementioned frequency divider, the R input terminal of the RS flip-flop corresponds to the input of the first counting signal CLK_R, and the S input terminal corresponds to the input of the second counting signal CLK_S. After the RS flip-flop performs logical processing on the first counting signal CLK_R and the second counting signal CLK_S, it outputs the first output signal DIVOUTP through the Q output terminal and the second output signal DIVOUTN through the QN output terminal. According to the logic principle of the RS flip-flop, the first output signal DIVOUTP and the second output signal DIVOUTN are opposite signals, that is, the first output signal DIVOUTP is 1 and the second output signal DIVOUTN is 0, or the first output signal DIVOUTP is 0 and the second output signal DIVOUTN is 1.

[0088] The aforementioned first output signal DIVOUTP and second output signal DIVOUTN are the frequency-divided signals output by the frequency divider in this specific embodiment after dividing the clock input signal CLKIN at different counting stages. In this specific embodiment, the frequency division process of the frequency divider can be referred to the following steps:

[0089] S1, In the initial state, DIVOUTP = 1 and DIVOUTN = 0 are set, and a first reset signal and a second reset signal are provided to the first programmable counting circuit and the second programmable counting circuit respectively according to the above DIVOUTP = 1 and DIVOUTN = 0. That is, the first reset signal of the first programmable counting circuit corresponds to DIVOUTN = 0, and the second reset signal of the second programmable counting circuit corresponds to DIVOUTP = 1. Thus, in the initial state, the first programmable counting circuit can start counting from 0, corresponding to CLK_R = 0, and the second programmable counting circuit remains in the cleared reset state, corresponding to CLK_S = 0.

[0090] S2, when the first programmable counter circuit continues counting to N (i.e., counting within the range of 0 to N-1, as in the following steps), CLK_R flips, CLK_R = 1. At this time, CLK_S remains 0. CLK_R = 1 causes the corresponding output DIVOUTP of the RS flip-flop circuit to flip, and the corresponding DIVOUTN also flips, i.e., DIVOUTP = 0, DIVOUTN = 1. Based on DIVOUTP = 0 and DIVOUTN = 1, the first reset signal and the second reset signal are configured respectively, such that the first reset signal corresponds to DIVOUTN = 1, and the second reset signal corresponds to DIVOUTP = 0. Thus, in this state, the first programmable counter circuit is reset to zero, CLK_R = 0, and the second programmable counter circuit starts counting from 0, CLK_S = 0.

[0091] S3, depending on the value assigned to the CTRL signal, when the second programmable counter circuit counts to N or N+1 (CTRL is 0, so the second programmable counter circuit counts to N; CTRL is 1, so the second programmable counter circuit counts to N+1), CLK_S = 1. This causes the corresponding output DIVOUTN of the RS flip-flop circuit to flip, and the corresponding DIVOUTP will also flip, i.e., DIVOUTP = 1 and DIVOUTN = 0. The first reset signal and the second reset signal are then configured again according to DIVOUTP = 1 and DIVOUTN = 0, so that the counting state of the first programmable counter unit and the second programmable counter unit repeats the above step S1.

[0092] As can be seen from S1 to S3 above, the first programmable counting circuit and the second programmable counting circuit in the frequency divider of this specific embodiment can cyclically execute S1 to S3 above, thereby realizing continuous frequency division processing.

[0093] Figure 7 This is a waveform diagram of a frequency divider performing a 2N+2 frequency division according to a specific embodiment of the present invention. When performing a 2N+2 frequency division on the clock input signal, the CTRL signal is 0, and the waveform changes of the first counting signal CLK_R, the second counting signal CLK_S, and the first output signal DIVOUTP and the second output signal DIVOUTN are as follows: Figure 6 As shown.

[0094] Figure 8 This is a waveform diagram of a frequency divider performing a 2N+3 frequency division according to a specific embodiment of the present invention. When performing a 2N+3 frequency division on the clock input signal, the CTRL signal is 1, and the waveform changes of the first counting signal CLK_R, the second counting signal CLK_S, and the first output signal DIVOUTP and the second output signal DIVOUTN are as follows: Figure 7 As shown.

[0095] Example 2

[0096] This embodiment provides a frequency division method. Figure 9 This is a flowchart of a method provided according to an embodiment of the present invention, such as... Figure 9 As shown, the frequency division method in this embodiment includes:

[0097] S202, acquire the clock input signal, the first set signal and the first reset signal, and count them according to the clock input signal, the first set signal and the first reset signal through the first counting unit, so as to output the first counting signal;

[0098] S204: Acquire the clock input signal, the second set signal, and the second reset signal, and count them using the second counting unit to output the second counting signal;

[0099] S206, generate a first output signal based on a first counting signal, generate a second output signal based on a second counting signal, configure a second reset signal based on the first output signal, and configure a first reset signal based on the second output signal;

[0100] The first reset signal is the inverted version of the second reset signal, and the modulus of both the first and second counting units is N, where N is a natural number.

[0101] The frequency division method in this embodiment can acquire a clock input signal, a first set signal, and a first reset signal, and count based on these signals to output a first count signal; acquire a clock input signal, a second set signal, and a second reset signal, and count based on these signals to output a second count signal; further, it generates a first output signal based on the first count signal and a second output signal based on the second count signal; the control unit is also configured to configure the second reset signal based on the first output signal and the first reset signal based on the second output signal; wherein the first reset signal is the inverted signal of the second reset signal; the modulus of both the first and second counting units is N, where N is a natural number. Therefore, the frequency division method in this embodiment can solve the problem in related technologies where multi-mode frequency dividers cannot achieve a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients, thus achieving a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients.

[0102] It should be further noted that the above steps S202 to S206 can be repeated.

[0103] The other optional technical solutions and their effects in this embodiment of the frequency division method are all the same as those in Embodiment 1, so they will not be described again here.

[0104] In an optional embodiment, the frequency division method described above includes:

[0105] Divide the clock input signal by 2N+2, or divide the clock input signal by 2N+3.

[0106] In an optional embodiment, before acquiring the clock input signal, the second set signal, and the second reset signal in step S204 above, the method further includes:

[0107] Acquire the first set signal and the CTRL signal, and generate the second set signal based on the first set signal and the CTRL signal.

[0108] In an optional embodiment, the above-mentioned acquisition of the first set signal and the CTRL signal, and the generation of the second set signal based on the first set signal and the CTRL signal, includes:

[0109] Acquire the first set signal and the CTRL signal, and accumulate the first set signal and the CTRL signal to generate the second set signal.

[0110] In an optional embodiment, the frequency division method further includes:

[0111] When the CTRL signal indicates "0", the clock input signal is divided by 2N+2; or when the CTRL signal indicates "1", the clock input signal is divided by 2N+3.

[0112] In an optional embodiment, step S206 above, generating a first output signal based on a first counting signal and generating a second output signal based on a second counting signal, includes:

[0113] The first counting signal is logically processed to generate a first output signal, and the second counting signal is logically processed to generate a second output signal.

[0114] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0115] Example 3

[0116] This embodiment provides a frequency division device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated. Figure 9 This is a structural block diagram of a frequency division device provided according to an embodiment of the present invention, such as... Figure 9 As shown, the frequency division device in this embodiment further includes:

[0117] The first acquisition module 302 is used to acquire a clock input signal, a first set signal and a first reset signal, and to count the clock input signal, the first set signal and the first reset signal through a first counting unit to output a first counting signal;

[0118] The second acquisition module 304 is used to acquire the clock input signal, the second set signal and the second reset signal, and to count the clock input signal, the second set signal and the second reset signal through the second counting unit to output the second counting signal;

[0119] The output module 306 is configured to generate a first output signal based on a first counting signal, and generate a second output signal based on a second counting signal, and configure a second reset signal based on the first output signal, and configure a first reset signal based on the second output signal.

[0120] The first reset signal is the inverted version of the second reset signal, and the modulus of both the first and second counting units is N, where N is a natural number.

[0121] The frequency divider in this embodiment can acquire a clock input signal, a first set signal, and a first reset signal, and count based on these signals to output a first count signal; acquire a clock input signal, a second set signal, and a second reset signal, and count based on these signals to output a second count signal; further, it generates a first output signal based on the first count signal and a second output signal based on the second count signal; the control unit is also configured to configure the second reset signal based on the first output signal and the first reset signal based on the second output signal; wherein the first reset signal is the inverted signal of the second reset signal; the modulus of both the first and second counting units is N, where N is a natural number. Therefore, the frequency divider in this embodiment can solve the problem in related technologies where multi-mode frequency dividers cannot achieve a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients, thus achieving a duty cycle of the output clock close to 50% while ensuring continuous output and arbitrary division coefficients.

[0122] The other optional technical solutions and technical effects of the frequency division device in this embodiment are all corresponding to the frequency division method in Embodiment 2, so they will not be described again here.

[0123] In an optional embodiment, the frequency division device further includes:

[0124] Divide the clock input signal by 2N+2, or divide the clock input signal by 2N+3.

[0125] In an optional embodiment, before acquiring the clock input signal, the second set signal, and the second reset signal, the second acquisition module 304 further includes:

[0126] Acquire the first set signal and the CTRL signal, and generate the second set signal based on the first set signal and the CTRL signal.

[0127] In an optional embodiment, the above-mentioned acquisition of the first set signal and the CTRL signal, and the generation of the second set signal based on the first set signal and the CTRL signal, includes:

[0128] Acquire the first set signal and the CTRL signal, and accumulate the first set signal and the CTRL signal to generate the second set signal.

[0129] In an optional embodiment, the frequency division device further includes:

[0130] When the CTRL signal indicates "0", the clock input signal is divided by 2N+2; or when the CTRL signal indicates "1", the clock input signal is divided by 2N+3.

[0131] In an optional embodiment, the second acquisition module 304 described above, which generates a first output signal based on a first counting signal and a second output signal based on a second counting signal, includes:

[0132] The first counting signal is logically processed to generate a first output signal, and the second counting signal is logically processed to generate a second output signal.

[0133] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0134] Example 4

[0135] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0136] Optionally, in this embodiment, the computer-readable storage medium described above may be configured to store a computer program for performing the following steps:

[0137] S1, acquire the clock input signal, the first set signal and the first reset signal, and count them according to the clock input signal, the first set signal and the first reset signal through the first counting unit to output the first counting signal;

[0138] S2, acquire the clock input signal, the second set signal and the second reset signal, and count them according to the clock input signal, the second set signal and the second reset signal through the second counting unit to output the second counting signal;

[0139] S3, generate a first output signal based on the first counting signal, generate a second output signal based on the second counting signal, configure a second reset signal based on the first output signal, and configure a first reset signal based on the second output signal;

[0140] The first reset signal is the inverted version of the second reset signal, and the modulus of both the first and second counting units is N, where N is a natural number.

[0141] Optionally, in this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0142] Example 5

[0143] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0144] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0145] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0146] S1, acquire the clock input signal, the first set signal and the first reset signal, and count them according to the clock input signal, the first set signal and the first reset signal through the first counting unit to output the first counting signal;

[0147] S2, acquire the clock input signal, the second set signal and the second reset signal, and count them according to the clock input signal, the second set signal and the second reset signal through the second counting unit to output the second counting signal;

[0148] S3, generate a first output signal based on the first counting signal, generate a second output signal based on the second counting signal, configure a second reset signal based on the first output signal, and configure a first reset signal based on the second output signal;

[0149] The first reset signal is the inverted version of the second reset signal, and the modulus of both the first and second counting units is N, where N is a natural number.

[0150] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0151] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0152] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention. < / m:0>

Claims

1. A frequency divider, characterized by, The frequency divider comprises: a first counting unit configured to obtain a clock input signal, a first set signal and a first reset signal, and count according to the clock input signal, the first set signal and the first reset signal to output a first counting signal; a second counting unit configured to obtain a clock input signal, a second set signal and a second reset signal, and count according to the clock input signal, the second set signal and the second reset signal to output a second counting signal; a control unit configured to generate a first output signal according to the first counting signal, and generate a second output signal according to the second counting signal; the control unit is further configured to configure the second reset signal according to the first output signal, and configure the first reset signal according to the second output signal; wherein the first reset signal is an inverse signal of the second reset signal; the first counting unit and the second counting unit have a modulus of N, and the N is a natural number; the frequency divider is configured to divide the clock input signal by 2N+2 to adjust the duty cycle of the output clock signal through the alternative counting of the first counting unit and the second counting unit with a frequency division coefficient of N, or divide the clock input signal by 2N+3 to adjust the duty cycle of the output frequency division signal through the alternative counting of the first counting unit and the second counting unit with a frequency division coefficient of N.

2. The frequency divider of claim 1, wherein, The control unit is further configured to: obtain the first set signal and a CTRL signal, and generate the second set signal according to the first set signal and the CTRL signal.

3. The frequency divider of claim 2, wherein, The control unit comprises an adder, wherein the adder is configured to obtain the first set signal and the CTRL signal, and accumulate the first set signal and the CTRL signal to generate the second set signal.

4. The frequency divider of claim 2 or 3, wherein, The frequency divider is configured to: divide the clock input signal by 2N+2 when the CTRL signal indicates "0", or divide the clock input signal by 2N+3 when the CTRL signal indicates "1".

5. The frequency divider of claim 1, wherein, The control unit is further configured to perform logical processing on the first counting signal to generate the first output signal, and perform logical processing on the second counting signal to generate the second output signal.

6. The frequency divider of claim 1, wherein, The first counting unit comprises: a first trigger sub-unit composed of a plurality of D flip-flops connected in series; the first trigger sub-unit is configured to obtain the clock input signal, the first set signal and the first reset signal, and output a first trigger output signal according to the obtained clock input signal, the first set signal and the first reset signal; an NAND gate sub-unit configured to obtain the first trigger output signal and a logical input signal, and output a first logical output signal according to the first trigger output signal and the logical input signal; The second trigger sub-unit is configured to output a first count signal according to the first logic output signal; and the second trigger sub-unit is further configured to configure the logic input signal according to the first count signal.

7. The frequency divider of claim 1, wherein, The second count unit comprises: The third trigger sub-unit is composed of a plurality of D flip-flops connected in series; the third trigger sub-unit is configured to acquire the clock input signal, the second set signal and the second reset signal, and output a second trigger output signal according to the clock input signal, the second set signal and the second reset signal; The NAND gate sub-unit is configured to acquire the second trigger output signal and the logic input signal, and output a second logic output signal according to the second trigger output signal and the logic input signal; The fourth trigger sub-unit is configured to output a second count signal according to the second logic output signal; and the second trigger sub-unit is further configured to configure the logic input signal according to the second count signal.

8. A frequency division method characterized by, The method applied to the frequency divider in any one of claims 1 to 7 comprises: acquiring a clock input signal, a first set signal and a first reset signal, and counting through a first count unit according to the clock input signal, the first set signal and the first reset signal to output a first count signal; acquiring a clock input signal, a second set signal and a second reset signal, and counting through a second count unit according to the clock input signal, the second set signal and the second reset signal to output a second count signal; generating a first output signal according to the first count signal, and generating a second output signal according to the second count signal, and configuring the second reset signal according to the first output signal, and configuring the first reset signal according to the second output signal; wherein the first reset signal is an inverse signal of the second reset signal, and the first count unit and the second count unit are both of N modulus, and the N is a natural number; performing 2N+2 frequency division on the clock input signal to adjust the duty cycle of the output clock signal through the alternative counting of the first count unit and the second count unit with a frequency division coefficient of N, or performing 2N+3 frequency division on the clock input signal to adjust the duty cycle of the output frequency division signal through the alternative counting of the first count unit and the second count unit with a frequency division coefficient of N.

9. The method of claim 8, wherein, Before the acquiring of the clock input signal, the second set signal and the second reset signal, the method further comprises: acquiring the first set signal and a CTRL signal, and generating the second set signal according to the first set signal and the CTRL signal.

10. The method of claim 9, wherein, The acquiring of the first set signal and the CTRL signal, and the generating of the second set signal according to the first set signal and the CTRL signal, comprises: acquiring the first set signal and the CTRL signal, and accumulating the first set signal and the CTRL signal to generate the second set signal.

11. The method according to claim 9 or 10, characterized in that, The method further comprises: In the case that the CTRL signal indicates "0", the clock input signal is divided by 2N+2; or in the case that the CTRL signal indicates "1", the clock input signal is divided by 2N+3.

12. The method of claim 8, wherein, The generating a first output signal according to the first count signal and generating a second output signal according to the second count signal comprises: The first count signal is logically processed to generate the first output signal, and the second count signal is logically processed to generate the second output signal.

13. A frequency dividing device, characterized by comprising: The frequency divider is arranged in any one of claims 1 to 7, and the device comprises: The first obtaining module is configured to obtain a clock input signal, a first set signal and a first reset signal, and to count according to the clock input signal, the first set signal and the first reset signal by a first counting unit to output a first count signal; The second obtaining module is configured to obtain a clock input signal, a second set signal and a second reset signal, and to count according to the clock input signal, the second set signal and the second reset signal by a second counting unit to output a second count signal; The output module is configured to generate a first output signal according to the first count signal, and to generate a second output signal according to the second count signal, and to configure the second reset signal according to the first output signal, and to configure the first reset signal according to the second output signal; The first reset signal is an inverse signal of the second reset signal, the first counting unit and the second counting unit are both N, and N is a natural number; The frequency dividing device further comprises: dividing the clock input signal by 2N+2 to adjust the duty cycle of the output clock signal by the alternative counting of the first counting unit and the second counting unit with a frequency dividing coefficient of N, or dividing the clock input signal by 2N+3 to adjust the duty cycle of the output frequency dividing signal by the alternative counting of the first counting unit and the second counting unit with a frequency dividing coefficient of N.

14. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program is arranged to execute the method in any one of claims 8 to 12 when running. 15.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is arranged to execute the computer program to execute the method in any one of claims 8 to 12.

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