Display device and method of driving the same

Abstract

The present invention relates to a display device and a method for driving the same. The display device includes: a display unit including a plurality of pixels for displaying an image based on a driving voltage; a data driver for supplying data signals to the plurality of pixels; a gamma voltage generator for supplying a plurality of grayscale voltages to the data driver; and a reference voltage generator for supplying a first reference voltage and a second reference voltage to the gamma voltage generator. The gamma voltage generator generates the plurality of grayscale voltages by dividing the first reference voltage and the second reference voltage, and the reference voltage generator generates a sensing driving voltage by measuring the driving voltage from the display unit, and generates the first reference voltage and the second reference voltage by utilizing the sensing driving voltage and the reference driving voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0128711, filed on October 16, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] Aspects of example embodiments of the present disclosure relate to a display device and a method of driving the display device. Background Art

[0004] With the development of multimedia, the importance of display devices is increasing. Therefore, various display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices have been developed.

[0005] The display device includes a display unit and a driver. The display unit includes a plurality of pixels. The driver includes a scan driver that supplies a scan output signal to the pixels and a data driver that supplies a data voltage to the pixels. The data driver converts digital image data received from a timing controller into an analog data signal according to (e.g., based on) a grayscale voltage (e.g., a grayscale level).

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] One or more example embodiments of the present disclosure are directed to a display device that compensates for a change in a drive voltage (e.g., a change or deviation) by controlling a reference voltage. For example, a drive voltage for driving a pixel may be provided to a display. When the drive voltage changes (e.g., is changed), the drive current may change (e.g., may be changed), and therefore, an undesirable pattern (e.g., a crosstalk pattern) may be identified on the display screen. This drive voltage may change (e.g., may be changed) due to the resistance of the line and / or the capacitance between the lines, or may change (e.g., may be changed) due to a difference in the data voltages provided to adjacent pixels.

[0008] According to one or more exemplary embodiments of the present disclosure, a display device includes: a display unit including a plurality of pixels configured to display an image based on a driving voltage; a data driver configured to provide data signals to the plurality of pixels; a gamma voltage generator configured to provide a plurality of grayscale voltages to the data driver; and a reference voltage generator configured to provide a first reference voltage and a second reference voltage to the gamma voltage generator. The gamma voltage generator is configured to generate the plurality of grayscale voltages by dividing the first reference voltage and the second reference voltage, and the reference voltage generator is configured to generate a sensing driving voltage by measuring the driving voltage from the display unit, and to generate the first reference voltage and the second reference voltage by using the sensing driving voltage and the reference driving voltage.

[0009] In example embodiments, the display device may further include: a timing controller configured to compare data voltage information of adjacent pixel rows to generate data offset information and provide the data offset information to a reference voltage generator, and the reference voltage generator may be configured to control the first reference voltage and the second reference voltage according to the data offset information, the sensing driving voltage, and the reference driving voltage.

[0010] In an example embodiment, the timing controller may include: an image processor configured to convert first image data into second image data; a memory configured to receive the second image data from the image processor and store the second image data; and a comparator configured to receive first data voltage information of a first pixel row of the second image data and second data voltage information of a second pixel row of the second image data adjacent to the first pixel row from the memory, and output data offset information according to a difference between the first data voltage information and the second data voltage information.

[0011] In an example embodiment, the comparator may include: a first data average calculator configured to divide the first data voltage information into a plurality of first data voltage blocks and calculate the first average data voltage information by calculating the average value of each first data voltage block in the plurality of first data voltage blocks; a second data average calculator configured to divide the second data voltage information into a plurality of second data voltage blocks and calculate the second average data voltage information by calculating the average value of each second data voltage block in the plurality of second data voltage blocks; a first adder configured to add the first average data voltage information to calculate the first added data voltage information; a second adder configured to add the second average data voltage information to calculate the second added data voltage information; and an offset provider configured to generate data offset information according to a difference between the first added data voltage information and the second added data voltage information.

[0012] In example embodiments, a time point at which the memory provides the first data voltage information to the comparator may be earlier than a time point at which the memory provides the first data voltage information to the data driver.

[0013] In example embodiments, the memory may be configured to provide second data voltage information of a second pixel row to the comparator at a point in time when the memory provides first data voltage information of the first pixel row to the data driver, and the second pixel row may be the next pixel row adjacent to the first pixel row.

[0014] In an example embodiment, the reference voltage generator may be configured to control at least one of a time delay, a conversion rate, and a gain of the first reference voltage and the second reference voltage according to an offset level of the data offset information, and the offset level of the data offset information may increase as the difference in data voltage information of adjacent pixel rows increases, and may decrease as the difference in data voltage information of adjacent pixel rows decreases.

[0015] In example embodiments, the reference voltage generator may be configured to control the voltage change time points of the first reference voltage and the second reference voltage to be earlier as the offset level increases.

[0016] In example embodiments, the reference voltage generator may be configured to control slew rates of the first reference voltage and the second reference voltage to increase as the offset level increases.

[0017] In example embodiments, the reference voltage generator may be configured to control gains of the first reference voltage and the second reference voltage to increase as the offset level increases.

[0018] In example embodiments, the timing controller may be further configured to: generate distance offset information according to a separation distance between the plurality of pixels and the data driver; and provide the distance offset information to the reference voltage generator, and the reference voltage generator may be configured to control the first reference voltage and the second reference voltage according to the data offset information, the distance offset information, the sensing drive voltage, and the reference drive voltage.

[0019] In example embodiments, the reference voltage generator may be configured to control at least one of a time delay, a slew rate, and a gain of the first reference voltage and the second reference voltage according to an offset level of the distance offset information, and the offset level of the distance offset information may increase as the separation distance increases, and may decrease as the separation distance decreases.

[0020] In example embodiments, the reference voltage generator may include a first differential amplifier configured to output a first reference voltage according to a difference between the sensing drive voltage and the reference drive voltage; and a second differential amplifier configured to output a second reference voltage according to the difference between the sensing drive voltage and the reference drive voltage.

[0021] In example embodiments, the reference driving voltage may be a target driving voltage for normally driving the plurality of pixels.

[0022] According to one or more example embodiments of the present disclosure, a method of driving a display device includes: generating a sensing driving voltage by measuring a driving voltage supplied to a display unit including a plurality of pixels; generating data offset information by comparing data voltage information of adjacent pixel rows; generating a first reference voltage and a second reference voltage based on the sensing driving voltage, a reference driving voltage, and the data offset information; and generating a plurality of grayscale voltages by dividing the first reference voltage and the second reference voltage.

[0023] In example embodiments, generating the first reference voltage and the second reference voltage may include controlling at least one of a time delay, a conversion rate, and a gain of the first reference voltage and the second reference voltage according to an offset level of data offset information, and the offset level may increase as a difference in data voltage information of adjacent pixel rows increases, and may decrease as a difference in data voltage information of adjacent pixel rows decreases.

[0024] In example embodiments, the control time points of the first reference voltage and the second reference voltage may be controlled to be earlier as the offset level increases.

[0025] In example embodiments, slew rates of the first reference voltage and the second reference voltage may be controlled to increase as the offset level increases.

[0026] In example embodiments, gains of the first reference voltage and the second reference voltage may be controlled to increase as the offset level increases.

[0027] In an example embodiment, generating data offset information may include: dividing first data voltage information of a first pixel row into a plurality of first data voltage blocks; dividing second data voltage information of a second pixel row adjacent to the first pixel row into a plurality of second data voltage blocks; calculating first average data voltage information of each first data voltage block in the plurality of first data voltage blocks; calculating second average data voltage information of each second data voltage block in the plurality of second data voltage blocks; calculating first added data voltage information by adding the first average data voltage information; calculating second added data voltage information by adding the second average data voltage information; and generating data offset information based on the first added data voltage information and the second added data voltage information.

[0028] According to one or more exemplary embodiments of the present disclosure, a display device may measure a driving voltage supplied to each pixel and may generate a reference voltage according to (e.g., based on) the measured sensing driving voltage and a previously stored reference driving voltage to compensate for a change in the driving voltage. Thus, the display quality of the display device may be improved.

[0029] According to one or more example embodiments of the present disclosure, a display device may generate data offset information by comparing data voltages corresponding to adjacent pixel rows, and may generate a reference voltage according to (e.g., based on) the data offset information, thereby effectively compensating for a change in a driving voltage.

[0030] According to one or more example embodiments of the present disclosure, distance offset information may be generated according to the distance between each pixel and the data driver, and a reference voltage may be generated according to (eg, based on) the distance offset information, thereby effectively compensating for a change in the driving voltage.

[0031] However, aspects and features of the present disclosure are not limited to the above-described aspects and features, and various other aspects and features may be described in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art from the following detailed description of example embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0034] Figure 2A The diagram is included in Figure 1 a circuit diagram of an example of a pixel in a display device;

[0035] Figure 2B It is an icon Figure 2A FIG. 1 is a diagram of an exemplary driving method of a pixel of FIG. 1 ;

[0036] Figure 3 The diagram is included in Figure 1 A diagram of a data driver in a display device;

[0037] Figure 4 The diagram is included in Figure 1 FIG. 1 is a diagram of a gamma voltage generator in a display device;

[0038] Figure 5 The diagram is included in Figure 1 FIG. 1 is a diagram showing an example of a reference voltage generator in a display device;

[0039] Figure 6The diagram is included in Figure 5 FIG. 1 is a diagram showing an example of a reference voltage compensator in a reference voltage generator;

[0040] Figure 7 is a diagram illustrating a display device according to another embodiment of the present disclosure;

[0041] Figure 8 The diagram is included in Figure 7 FIG. 1 is a diagram of a timing controller in a display device;

[0042] Figure 9 The diagram is included in Figure 8 Diagram of the comparator in the timing controller;

[0043] Figure 10 The diagram is included in Figure 7 A diagram of a reference voltage generator in a display device;

[0044] Figure 11 The diagram is included in Figure 10 FIG. 1 is a diagram of an offset compensator in a reference voltage generator;

[0045] Figure 12 The diagram is through Figure 11 a diagram of an example of time delay compensation of a first compensator;

[0046] Figure 13 The diagram is through Figure 11 a diagram of an example of slew rate compensation of a second compensator;

[0047] Figure 14 The diagram is through Figure 11 FIG. 1 is a diagram illustrating an example of gain compensation of a third compensator;

[0048] Figure 15 is a diagram illustrating a display device according to another embodiment of the present disclosure;

[0049] Figure 16 The diagram is included in Figure 15 A diagram of a reference voltage generator in a display device;

[0050] Figure 17 is used for illustration purposes only. Figure 16 A diagram of an offset compensator in a reference voltage generator; and

[0051] Figures 18 and 19 is a flowchart illustrating a method of driving a display device according to one or more embodiments. DETAILED DESCRIPTION

[0052] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, the present disclosure can be embodied in various different forms and should not be construed as being limited to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be exhaustive and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, unnecessary processes, elements and techniques for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise noted, throughout the drawings and written description, the same reference numerals refer to the same elements, and therefore, the descriptions of the same reference numerals may not be repeated.

[0053] In the accompanying drawings, for clarity, the relative sizes of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below", "below", "down", "beneath", "above" and "on" may be used herein to describe the relationship between an element or feature as illustrated in the accompanying drawings relative to another (some) element or feature. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as "below" or "below" or "below" of other elements or features will then be positioned as "above" other elements or features. Therefore, the example terms "below" and "below" can cover both above and below orientations. The device can be positioned additionally (e.g., rotated 90 degrees or positioned in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0054] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Thus, a first element, first component, first region, first layer, or first segment described below could be referred to as a second element, second component, second region, second layer, or second segment without departing from the spirit and scope of the present disclosure.

[0055] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0056] The terms used herein are used to describe the purpose of specific embodiments and are not intended to limit the present disclosure. As used herein, the "one" in the singular is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprise", "include", "have" indicate the existence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their combinations. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...", when located after a list of elements, modify the list of entire elements and do not modify the individual elements in the list.

[0057] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "in use," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized." Furthermore, the term "exemplary" is intended to refer to an example or illustration.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0059] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0060] refer to Figure 1 , a display device 10 according to an embodiment may include a display unit (eg, display panel) 100 , a gate driver 200 , a data driver 300 , a timing controller 400 , a power supply 500 , a gamma voltage generator 600 , and a reference voltage generator 700 .

[0061] The display unit 100 can display an image. For example, the display unit 100 can be implemented as a display panel. The display unit 100 can include various display elements, for example, such as organic light-emitting elements (for example, organic light-emitting diodes (OLEDs)). Hereinafter, for convenience, the display device 10 including an organic light-emitting element as a display element will be described in more detail. However, the present disclosure is not limited thereto, and any suitable type of display device (for example, such as a liquid crystal display (LCD) device, an electrophoretic display (EPD) device, and / or an inorganic light-emitting display device, etc.) can be applied as the display element included in the display device 10.

[0062] The display unit 100 may include data lines D1 to Dm (where m is a positive integer), scan lines (or gate lines) S1 to Sn (where n is a positive integer), and pixels PX. The pixels PX may be arranged at (e.g., within or on) regions divided by the data lines D1 to Dm and the scan lines S1 to Sn. The pixels PX may be electrically connected to the data lines D1 to Dm and the scan lines S1 to Sn.

[0063] For example, the pixel PX placed at the first row and the first column (e.g., in the first row and the first column or on the first row and the first column) can be connected to the first data line D1 and the first scan line S1. In another example, the pixel PX placed at the nth row and the mth column (e.g., in the nth row and the mth column or on the nth row and the mth column) can be connected to the mth data line Dm and the nth scan line Sn.

[0064] However, the pixel PX is not limited thereto. For example, the pixel PX may be connected to a scan line corresponding to an adjacent row (e.g., a scan line corresponding to a previous row of the row including the corresponding pixel PX, and a scan line corresponding to a subsequent row of the row including the corresponding pixel PX). In addition, the pixel PX may be electrically connected to a first power line and a second power line to receive a first drive voltage VDD and a second drive voltage VSS. Here, the first drive voltage VDD and the second drive voltage VSS may be voltages for driving the pixel PX. Hereinafter, the drive voltage for driving the pixel PX may be referred to as the first drive voltage VDD.

[0065] In response to a scan signal supplied through a corresponding scan line, the pixel PX may emit light having a brightness corresponding to a data signal supplied through a corresponding data line. Figure 2A and Figure 2B A more detailed configuration and operation of the pixel PX are described.

[0066] The gate driver (or scan driver) 200 may generate a scan signal (or gate signal) according to (e.g., based on) a gate control signal GCS and may provide the scan signal to the scan lines S1 to Sn. Here, the gate control signal GCS may be a signal for controlling the operation of the gate driver 200 and may include a start signal and / or a clock signal, etc. For example, the gate driver 200 may use a clock signal to sequentially generate and output a scan signal corresponding to the start signal (e.g., a scan signal having a waveform that is the same as or substantially the same as (or similar to) the waveform of the start signal). The gate driver 200 may be implemented as a shift register, but the present disclosure is not limited thereto. The gate driver 200 may be formed at (e.g., in or on) an area of ​​the display unit 100 (e.g., an area of ​​the display panel 100), or may be implemented as an integrated circuit (IC) and may be mounted on a flexible circuit board to be connected to the display unit 100.

[0067] The data driver 300 may be implemented as an integrated circuit (e.g., a driver IC) or may be mounted on a flexible circuit board to be connected to the display unit 100. The data driver 300 may generate data signals according to (e.g., based on) image data DATA2, a data control signal DCS, and grayscale voltages V0 to V255 (or gamma voltages), and may provide the data signals to the data lines D1 to Dm in pixel row units (e.g., in pixel row units). Here, the data control signal DCS may be a signal for controlling the operation of the data driver 300 and may include a load signal, a start signal, and / or a clock signal, etc.

[0068] The timing controller 400 may receive input image data DATA1 (e.g., RGB data) and input control signals from an external source (e.g., a graphics processor). The input image data DATA1 may include a grayscale value (e.g., grayscale level) corresponding to each pixel PX. The input control signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and / or a data enable signal DE.

[0069] The timing controller 400 may generate image data DATA2 according to (e.g., based on) the input image data DATA1, and may generate a gate control signal GCS and a data control signal DCS according to (e.g., based on) the input control signal. The timing controller 400 may provide the gate control signal GCS to the gate driver 200, and may provide the data control signal DCS and the image data DATA2 to the data driver 300.

[0070] The power supply 500 may provide a first driving voltage VDD and a second driving voltage VSS to the display unit 100. The first driving voltage VDD may have a value (e.g., a voltage level) higher than that of the second driving voltage VSS. The first driving voltage VDD may be provided to one side of the display unit 100. In this case, due to the resistance of the internal lines of the display unit 100 and / or the capacitance generated between the lines, the first driving voltage VDD provided from one side of the display unit 100 to the area adjacent to the other side facing the display unit 100 may have a value (e.g., a voltage level) lower than that of the first driving voltage VDD provided to the one side of the display unit 100. In some embodiments, the power supply 500 may further supply an initialization voltage to the display unit 100.

[0071] The gamma voltage generator (e.g., gray voltage generator) 600 may receive a first reference voltage VG1, a second reference voltage VG2, and an input maximum brightness value DBVI. The gamma voltage generator 600 may generate a plurality of gray voltages V0 to V255 for a plurality of grays according to (e.g., based on) the first reference voltage VG1, the second reference voltage VG2, and the input maximum brightness value DBVI, and may provide the plurality of gray voltages V0 to V255 to the data driver 300.

[0072] The plurality of gray voltages V0 to V255 generated by the gamma voltage generator 600 may be intermediate voltages between the first reference voltage VG1 and the second reference voltage VG2. The plurality of gray voltages V0 to V255 may vary in response to the provided first reference voltage VG1 and the second reference voltage VG2. For example, when the first reference voltage VG1 and the second reference voltage VG2 increase at a constant rate, the plurality of gray voltages V0 to V255 may also increase at the same or substantially the same rate.

[0073] In addition, the gamma voltage generator 600 can receive an input maximum brightness value DBVI and can provide a grayscale voltage V0 to V255 corresponding to the input maximum brightness value DBVI. Hereinafter, for ease of description, a total of 256 grayscales are described, for example, from 0 grayscale level (e.g., minimum grayscale level) to 255 grayscale levels (e.g., maximum grayscale level), but the present disclosure is not limited thereto, and when grayscale values ​​exceeding 8 bits are represented, the total grayscale can include more grayscale levels. As used herein, the minimum grayscale level can refer to the darkest grayscale level, and the maximum grayscale level can refer to the brightest grayscale level.

[0074] The maximum brightness value may be the brightness value of light emitted from a pixel corresponding to the maximum grayscale level. For example, the maximum brightness value may be the brightness value of white light generated when the pixels forming a dot emit light corresponding to a grayscale level of 255. The unit of the brightness value may be nits. The maximum brightness value may be manually set by a user operating the display device 10, or may be automatically set by an algorithm associated with an illuminance sensor. The set maximum brightness value may be represented as an input maximum brightness value DBVI.

[0075] The reference voltage generator 700 may receive a reference drive voltage VDD_R, a compensation selection signal VCS, a standard voltage VRF, and / or a sensing drive voltage VDD_S. The reference voltage generator 700 may generate and / or control a first reference voltage VG1 and a second reference voltage VG2 according to (e.g., based on) the reference drive voltage VDD_R, the compensation selection signal VCS, the standard voltage VRF, and / or the sensing drive voltage VDD_S, and may provide the first reference voltage VG1 and the second reference voltage VG2 to the gamma voltage generator 600. The first reference voltage VG1 may have a value (e.g., a voltage level) higher than the value of the first drive voltage VDD, and the second reference voltage VG2 may have a value (e.g., a voltage level) lower than the value of the first drive voltage VDD, but the first reference voltage VG1 and the second reference voltage VG2 are not limited thereto. For example, in another embodiment, both the first reference voltage VG1 and the second reference voltage VG2 may have a value (e.g., a voltage level) lower than the value of the first drive voltage VDD.

[0076] The reference driving voltage VDD_R may be a target driving voltage value for normally driving the pixels PX of the display unit 100 , and the sensing driving voltage VDD_S may be a voltage value obtained by measuring the first driving voltage VDD supplied or substantially supplied to the display unit 100 .

[0077] As described above, the first driving voltage VDD generated by the power supply 500 and supplied to the display unit 100 may be delayed due to the resistance of the line for transmitting the first driving voltage VDD to each of the pixels PX and / or the capacitance between other lines, and thus a voltage drop may occur. In other words, the driving voltage supplied to each of the pixels PX may be different from the first driving voltage VDD (e.g., may have a voltage level different from that of the first driving voltage VDD).

[0078] Therefore, the reference voltage generator 700 can determine the driving voltage detected from each pixel PX in the pixels PX as the sensing driving voltage VDD_S. The reference voltage generator 700 can compare the reference driving voltage VDD_R for normally driving each pixel PX in the pixels PX with the sensing driving voltage VDD_S to generate a first reference voltage VG1 and a second reference voltage VG2. In other words, the first reference voltage VG1 and the second reference voltage VG2 generated by the reference voltage generator 700 can compensate for the amount of change (e.g., the amount of variation or the amount of deviation) in the first driving voltage VDD in the display unit 100 to normally drive each pixel PX in the pixels PX.

[0079] The following will refer to Figure 5 The detailed configuration and operation method of the reference voltage generator 700 are described in more detail.

[0080] Still refer to Figure 1 , the timing controller 400 is shown as being implemented independently of the data driver 300 (e.g., separately), but the present disclosure is not limited thereto. For example, in another embodiment, the timing controller 400 may be implemented together with the data driver 300 (e.g., integrally) as an integrated circuit (e.g., as one integrated circuit) (e.g., as a timing controller embedded driver (TED)).

[0081] also, Figure 1 The gamma voltage generator 600 and the reference voltage generator 700 are shown as being implemented independently of the data driver 300 and / or the timing controller 400 (e.g., separately), but the present disclosure is not limited thereto. For example, the gamma voltage generator 600 and the reference voltage generator 700 may be implemented as an integrated circuit (e.g., as one integrated circuit) together with the data driver 300 and / or the timing controller 400 (e.g., integrally), or the gamma voltage generator 600 and the reference voltage generator 700 may be included in the data driver 300 and / or the timing controller 400 and may be partially or entirely implemented as software.

[0082] Figure 2A The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device. Figure 2B It is an icon Figure 2A FIG. 1 is a diagram of an exemplary driving method for a pixel of FIG.

[0083] refer to Figure 2A and Figure 2B , the pixel PXij can be connected to the scan line Si and the data line Dj (where i and j are integers). The scan line Si can be Figure 1 Any one of the scan lines S1 to Sn, and the data line Dj can be Figure 1 Any one of the data lines D1 to Dm.

[0084] The pixel PXij may include a light emitting element LD, a plurality of transistors T1 and T2 , and a storage capacitor Cst.

[0085] In this embodiment, the transistor is shown as a P-type transistor, for example, a P-type metal oxide semiconductor (PMOS). However, the present disclosure is not limited thereto, and as will be known to those skilled in the art, the pixel circuit can be configured to perform the same or substantially the same function using an N-type transistor (for example, an N-type metal oxide semiconductor (NMOS)).

[0086] The first electrode (eg, anode electrode) of the light emitting element LD may be connected to the first driving voltage line VDDL through the first transistor T1, and the second electrode (eg, cathode electrode) of the light emitting element LD may be connected to the second driving voltage line VSSL. The first driving voltage line VDDL may be used to provide Figure 1 The first driving voltage line VDD, and the second driving voltage line VSSL may be used to provide Figure 1 A line of the second driving voltage VSS.

[0087] A first electrode of a first transistor (e.g., a driving transistor) T1 may be connected to a first driving voltage line VDDL, and a second electrode of the first transistor T1 may be connected to a first electrode of the light-emitting element LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may control the amount of driving current supplied to the light-emitting element LD in accordance with the voltage of the first node N1.

[0088] A first electrode of a second transistor (eg, a switching transistor) T2 may be connected to the data line Dj, and a second electrode of the second transistor T2 may be connected to the first node N1. A gate electrode of the second transistor T2 may be connected to the scan line Si.

[0089] One electrode of the storage capacitor Cst may be connected to the first node N1, and the other electrode of the storage capacitor Cst may be connected to the first driving voltage line VDDL. The storage capacitor Cst may be charged with a voltage corresponding to the data signal of one frame supplied to the first node N1, and may maintain or substantially maintain the charged voltage until the data signal of the next frame is supplied.

[0090] When a scan signal having a turn-on level (e.g., a low level) is supplied to the gate electrode of the second transistor T2 through the scan line Si, the second transistor T2 can connect the data line Dj and one electrode of the storage capacitor Cst to each other. Therefore, corresponding to (e.g., according to) the data voltage DATAij applied through the data line Dj and the first driving voltage VDD of the first driving voltage line VDDL (e.g., see Figure 1 ) can be written (eg, can be stored) in the storage capacitor Cst. The data voltage DATAij can be Figure 1 corresponds to one of the grayscale voltages V0 to V255.

[0091] The first transistor T1 allows a driving current (eg, a driving current determined by a voltage written to the storage capacitor Cst) to flow from the first driving voltage line VDDL to the second driving voltage line VSSL. The light emitting element LD may emit light having a brightness corresponding to the amount of the driving current.

[0092] For convenience, Figure 2A A pixel circuit having a relatively simple structure is shown, which includes a second transistor T2 for transmitting a data signal to the pixel PXij, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a drive current corresponding to the data signal to the light-emitting element LD. However, the present disclosure is not limited thereto, and as will be known to those skilled in the art, the structure of the pixel circuit may be variously modified and implemented. For example, in other embodiments, the pixel circuit may further include various transistors, such as a compensation transistor for compensating for the threshold voltage of the first transistor T1, an initialization transistor for initializing the first node N1 or the anode electrode of the light-emitting element LD, and / or a light-emission control transistor for controlling the light-emission time of the light-emitting element LD.

[0093] Figure 3 The diagram is included in Figure 1 A diagram of a data driver in a display device.

[0094] refer to Figure 3 , the data driver 300 may include a shift register 310 , a latch 320 , a digital-to-analog converter (DAC) 330 , and an output buffer 340 .

[0095] The shift register 310 may receive a horizontal start signal STH and a data clock signal DCLK from the timing controller 400. The horizontal start signal STH and the data clock signal DCLK may be included in the timing controller 400. Figure 1The shift register 310 may generate a sampling signal by shifting the horizontal start signal STH in synchronization with the data clock signal DCLK.

[0096] The latch 320 may latch the image data DATA2 in response to the sampling signal DATA2. The latch 320 may output the latched image data DATA2 in response to the load signal LOAD.

[0097] The digital-to-analog converter 330 may convert the latched image data DATA2 in a digital format into a corresponding data signal in an analog format according to (eg, based on) the gray voltages V0 to V255 .

[0098] The output buffer 340 may output the data signal to the data lines D1 to Dm. In an embodiment, the output buffer 340 may include a voltage follower and may output the transmitted data signal as is. In another embodiment, the output buffer 340 may include an amplifier and may amplify and output the transmitted data signal.

[0099] Figure 3 The data driver 300 is illustrated as including a shift register 310, a latch 320, a digital-to-analog converter 330, and an output buffer 340. However, the structure of the data driver 300 is not limited thereto, and the data driver 300 may include other configurations as would be known to those skilled in the art.

[0100] Figure 4 The diagram is included in Figure 1 FIG. 1 is a diagram of a gamma voltage generator in a display device.

[0101] refer to Figure 4 , the gamma voltage generator 600 may include a selection value provider (selector) 610, a gamma voltage output unit (e.g., a gamma voltage output circuit) 620, resistor strings (R strings) RS1 to RS11, multiplexers (MUX) MX1 to MX12, and resistors R1 to R10.

[0102] The selection value provider 610 may provide the multiplexers MX1 to MX12 with selection values ​​according to the input maximum brightness value DBVI. The selection values ​​according to the input maximum brightness value DBVI may be pre-stored in a memory element such as a register, for example.

[0103] The resistor string RS1 can generate an intermediate voltage between the first reference voltage VG1 and the second reference voltage VG2. The multiplexer MX1 ​​can select one of the intermediate voltages provided from the resistor string RS1 according to a selection value and output a third reference voltage VT. The multiplexer MX2 can select one of the intermediate voltages provided from the resistor string RS1 according to a selection value and output a 255 grayscale voltage V255.

[0104] The resistor string RS11 may generate an intermediate voltage of the third reference voltage VT and the 255 gray voltage V255. The multiplexer MX12 may select one of the intermediate voltages provided from the resistor string RS11 according to a selection value and may output the 203 gray voltage V203.

[0105] The resistor string RS10 may generate an intermediate voltage of the third reference voltage VT and the 203 gray voltage V203. The multiplexer MX11 may select one of the intermediate voltages provided from the resistor string RS10 according to a selection value and may output a 151 gray voltage V151.

[0106] The resistor string RS9 may generate an intermediate voltage of the third reference voltage VT and the 151 gray voltage V151. The multiplexer MX10 may select one of the intermediate voltages provided from the resistor string RS9 according to a selection value and may output the 87 gray voltage V87.

[0107] The resistor string RS8 may generate an intermediate voltage of the third reference voltage VT and the 87 gray voltage V87. The multiplexer MX9 may select one of the intermediate voltages provided from the resistor string RS8 according to a selection value and may output the 51 gray voltage V51.

[0108] The resistor string RS7 may generate an intermediate voltage of the third reference voltage VT and the 51 gray voltage V51. The multiplexer MX8 may select one of the intermediate voltages provided from the resistor string RS7 according to a selection value and may output the 35 gray voltage V35.

[0109] The resistor string RS6 may generate an intermediate voltage of the third reference voltage VT and the 35 gray voltage V35. The multiplexer MX7 may select one of the intermediate voltages provided from the resistor string RS6 according to a selection value and may output the 23 gray voltage V23.

[0110] The resistor string RS5 may generate an intermediate voltage of the third reference voltage VT and the 23 gray voltage V23. The multiplexer MX6 may select one of the intermediate voltages provided from the resistor string RS5 according to a selection value and may output the 11 gray voltage V11.

[0111] The resistor string RS4 may generate an intermediate voltage of the first reference voltage VG1 and the 11 gray voltage V11. The multiplexer MX5 may select one of the intermediate voltages provided from the resistor string RS4 according to a selection value and may output the 7 gray voltage V7.

[0112] The resistor string RS3 may generate an intermediate voltage of the first reference voltage VG1 and the 7 gray voltage V7. The multiplexer MX4 may select one of the intermediate voltages provided from the resistor string RS3 according to a selection value and may output the 1 gray voltage V1.

[0113] The resistor string RS2 may generate an intermediate voltage of the first reference voltage VG1 and the 1 gray voltage V1. The multiplexer MX3 may select one of the intermediate voltages provided from the resistor string RS2 according to a selection value and may output a zero gray voltage V0.

[0114] The grayscales 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 described above may be referred to as reference grayscales. Furthermore, the grayscale voltages V0, V1, V7, V11, V23, V35, V51, V87, V151, V203, and V255 generated by multiplexers MX2 to MX12 may be referred to as reference grayscale voltages. The number of reference grayscales and the grayscale numbers corresponding to the reference grayscales may be set differently depending on the product.

[0115] The gamma voltage output unit 620 can divide the reference gray voltages V0, V1, V7, V11, V23, V35, V51, V87, V151, V203, and V255 to generate all of the gray voltages V0 to V255. For example, the gamma voltage output unit 620 can divide the reference gray voltages V1 and V7 to generate gray voltages V2 to V6.

[0116] Figure 5 The diagram is included in Figure 1 FIG. 1 is a diagram of an example of a reference voltage generator in a display device.

[0117] refer to Figure 1 and Figure 5 , the reference voltage generator 700 may include an initial voltage generator 710 and a reference voltage compensator 720 .

[0118] The initial voltage generator 710 may generate the first and second initial reference voltages VIG1 and VIG2 according to (eg, based on) the standard voltage VRF. In an embodiment, the standard voltage VRF may be the same or substantially the same as the first driving voltage VDD, but the present disclosure is not limited thereto.

[0119] The first initial reference voltage VIG1 and the second initial reference voltage VIG2 may be voltage values ​​(e.g., voltage levels) determined during a gamma voltage setting process performed during product production. During the gamma voltage setting process, the display device 10 may be connected to a separate test device instead of the power supply 500 and may receive a test drive voltage from the test device. The display device 10 may determine the first initial reference voltage VIG1 and the second initial reference voltage VIG2 corresponding to the test drive voltage, and may set the initial grayscale voltage according to (e.g., based on) the first initial reference voltage VIG1 and the second initial reference voltage VIG2. For example, during the gamma voltage setting process, the display device 10 may set the initial grayscale voltage so that the luminance of each grayscale of the grayscale of the pixel PX becomes a predetermined gamma curve (e.g., a 2.2 gamma curve) according to (e.g., based on) the first initial reference voltage VIG1 and the second initial reference voltage VIG2.

[0120] After product production, the power supply 500 may be connected to the display device 10 to provide the first driving voltage VDD. A change (e.g., deviation) may occur between the first driving voltage VDD provided by the power supply 500 and the test driving voltage of the test equipment during the gamma voltage setting process. For example, the resistance of the connector used to connect the display device 10 and the test equipment to each other during the gamma voltage setting process may be different from the resistance of the connector used to connect the display device 10 and the power supply 500 to each other after product production.

[0121] Since a change (e.g., deviation) in the driving voltage occurs after product production, the reference voltage compensator 720 may receive the reference driving voltage VDD_R and the sensing driving voltage VDD_S and may compensate for the first initial reference voltage VIG1 and the second initial reference voltage VIG2. The reference voltage compensator 720 may generate the first reference voltage VG1 and the second reference voltage VG2 by compensating for the first initial reference voltage VIG1 and the second initial reference voltage VIG2.

[0122] Will refer to Figure 6 The reference voltage compensator 720 is described in more detail.

[0123] Figure 6 The diagram is included in Figure 5 FIG. 1 is a diagram of an example of a reference voltage compensator in a reference voltage generator.

[0124] refer to Figure 6 , the reference voltage compensator 720 may include a first reference voltage compensator 720a and a second reference voltage compensator 720b.

[0125] The first reference voltage compensator 720 a may output a first reference voltage VG1 by compensating the first initial reference voltage VIG1 .

[0126] The first reference voltage compensator 720 a may include a first differential amplifier 7201 and a plurality of resistors Ra, Rb, Rc, and Rd.

[0127] The first initial reference voltage VIG1 may be applied to the first input terminal (+) of the first differential amplifier 7201 through the resistor Rc, and the sense drive voltage VDD_S may be applied to the first input terminal (+) of the first differential amplifier 7201 through the resistor Rd. In addition, the reference drive voltage VDD_R may be applied to the second input terminal (-) of the first differential amplifier 7201 through the resistor Ra, and the first reference voltage VG1 may be applied to the second input terminal (-) of the first differential amplifier 7201 through the resistor Rb.

[0128] The first reference voltage VG1 may be output as a value proportional to a difference between a voltage of a first input terminal (+) and a voltage of a second input terminal (-) of the first differential amplifier 7201. In other words, the first reference voltage VG1 may be output as a voltage proportional to a value obtained by adding a difference between the sensing driving voltage VDD_S and the reference driving voltage VDD_R to the first initial reference voltage VIG1.

[0129] The resistors Ra, Rb, Rc, and Rd of the first reference voltage compensator 720a may have the same or substantially the same value (e.g., resistance value) as each other, but the present disclosure is not limited thereto. For example, the resistance values ​​of the resistors Ra, Rb, Rc, and Rd may be different from each other, and thus, the voltage value of the first reference voltage VG1 output by the first differential amplifier 7201 may be adjusted.

[0130] The second reference voltage compensator 720 b may output a second reference voltage VG2 by compensating the second initial reference voltage VIG2 .

[0131] The second reference voltage compensator 720 b may include a second differential amplifier 7202 and a plurality of resistors Re, Rf, Rg, and Rh.

[0132] The second initial reference voltage VIG2 may be applied to the first input terminal (+) of the second differential amplifier 7202 through the resistor Rg, and the sense drive voltage VDD_S may be applied to the first input terminal (+) of the second differential amplifier 7202 through the resistor Rh. In addition, the reference drive voltage VDD_R may be applied to the second input terminal (-) of the second differential amplifier 7202 through the resistor Re, and the second reference voltage VG2 may be applied to the second input terminal (-) of the second differential amplifier 7202 through the resistor Rf.

[0133] Therefore, the second reference voltage VG2 can be output as a value proportional to the difference between the voltage of the first input terminal (+) and the voltage of the second input terminal (-) of the second differential amplifier 7202. In other words, the second reference voltage VG2 can be output as a voltage proportional to a value obtained by adding the difference between the sensing drive voltage VDD_S and the reference drive voltage VDD_R to the second initial reference voltage VIG2.

[0134] The resistors Re, Rf, Rg, and Rh of the second reference voltage compensator 720a may have the same or substantially the same value (e.g., resistance value) as each other, but the present disclosure is not limited thereto. For example, the resistance values ​​of the resistors Re, Rf, Rg, and Rh may be different from each other, and thus, the voltage value of the second reference voltage VG2 output by the second differential amplifier 7202 may be adjusted.

[0135] The first reference voltage compensator 720a and the second reference voltage compensator 720b may further include a first selector 7203 and a second selector 7204, respectively. Based on a compensation selection signal VCS, the first selector 7203 may select and output one of the first initial reference voltage VIG1 and the first reference voltage VG1, and the second selector 7204 may select and output one of the second initial reference voltage VIG2 and the second reference voltage VG2. The compensation selection signal VCS provided to the first selector 7203 and the second selector 7204 may be the same signal. Therefore, the reference voltage compensator 720 may output the first reference voltage VG1 and the second reference voltage VG2 together, or may output the first initial reference voltage VIG1 and the second initial reference voltage VIG2 together.

[0136] Figure 6 The structure of the reference voltage compensator 720 shown in FIG. 7 may be an example of one of various suitable structures, and therefore, the reference voltage compensator 720 is not limited to Figure 6 The structure shown in .

[0137] like Figure 2A As shown in , the amount of driving current flowing through the light emitting element LD may be determined by a first driving voltage VDD applied through a first driving voltage line VDDL connected to the first electrode of the first transistor T1 and a data voltage DATAij applied through a data line Dj connected to the gate electrode of the first transistor T1 via a second transistor T2. When the first driving voltage VDD varies (e.g., is changed or deviates) due to various reasons (e.g., such as line resistance and / or capacitance between lines), an intended driving current may not flow through the light emitting element LD, and therefore, an undesirable pattern may be recognized by the display device.

[0138] The reference voltage generator 700 of the display device 10 can generate a first reference voltage VG1 and a second reference voltage VG2 by reflecting the difference between a sensed driving voltage VDD_S obtained by measuring the first driving voltage VDD supplied to each of the pixels PX and a driving voltage VDD_R for normal operation of each of the pixels PX. Grayscale voltages V0 to V255 can be generated according to (e.g., based on) the first reference voltage VG1 and the second reference voltage VG2, and data signals can be generated according to (e.g., based on) the grayscale voltages V0 to V255. In other words, a change amount (e.g., a variation amount or a deviation amount) of the first driving voltage VDD can be compensated by the first reference voltage VG1 and the second reference voltage VG2, and the display quality of the display device 10 can be improved.

[0139] Hereinafter, another embodiment of the display device will be described. In the following description of one or more embodiments, the configuration and / or elements that are the same or substantially the same as those of one or more previously described embodiments may be referred to by the same reference numerals, and therefore, redundant descriptions of the configuration and / or elements may be simplified or may not be repeated, and the differences in the configuration and / or elements may be mainly described.

[0140] Figures 7 to 14 One or more embodiments may differ from one or more of the above-described embodiments in that the reference voltage generator may further receive data offset information from the timing controller and may generate the first reference voltage and the second reference voltage according to (e.g., based on) the data offset information.

[0141] Figure 7 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0142] refer to Figure 7 , the timing controller 401 of the display device 11 may further provide data offset information OS to the reference voltage generator 701. The data offset information OS may be information obtained by comparing data voltage values ​​of adjacent pixel rows.

[0143] The reference voltage generator 701 may receive the data offset information OS and may generate a first reference voltage VG1 ′ and a second reference voltage VG2 ′ according to (eg, based on) the data offset information OS.

[0144] The gamma voltage generator 600 may generate gray voltages V0' to V255' according to (e.g., based on) a first reference voltage VG1' and a second reference voltage VG2'. The data driver 300 may generate data signals according to (e.g., based on) the gray voltages V0' to V255' and may provide the data signals to the data lines D1 to Dm in pixel row units (e.g., in pixel row units).

[0145] Figure 8 The diagram is included in Figure 7 Figure 2 is a diagram of a timing controller in a display device.

[0146] refer to Figure 7 and Figure 8 , the timing controller 401 may include an image processor 410 , a memory 420 and a comparator 430 .

[0147] The image processor 410 may convert the input image data DATA1 into image data DATA2. The image data DATA2 may be data obtained by converting the input image data DATA1 to correspond to the pixel arrangement of the display unit 100. The image data DATA2 may include a plurality of portions (e.g., slices or segments) of data voltage information. The data voltage information may include grayscale information of each of the data signals provided to the data lines D1 to Dm in units of pixel rows (e.g., in pixel row units). For example, the data voltage information may include (e.g., may be) grayscale information of each pixel row in the pixel rows.

[0148] The memory 420 may receive the image data DATA2 from the image processor 410 and may store (eg, temporarily store) the image data DATA2. In an embodiment, the memory 420 may sequentially receive portions of the data voltage information from the image processor 410 in order of pixel rows.

[0149] The memory 420 may provide the stored image data DATA2 to the data driver 300. For example, the memory 420 may provide a plurality of parts of the data voltage information to the data driver 300 sequentially.

[0150] In addition, the memory 420 can provide the stored image data DATA2 to the comparator 430 and can sequentially provide data voltage information of pixel rows. For example, the image data DATA2 provided from the memory 420 to the comparator 430 may include first data voltage information DVa and second data voltage information DVb. The first data voltage information DVa may include (e.g., may be) data voltage information corresponding to a first pixel row among the pixels PX arranged at the display unit 100 (e.g., in the display unit 100 or on the display unit 100), and the second data voltage information DVb may include (e.g., may be) data voltage information corresponding to a second pixel row adjacent to the first pixel row. In other words, the first data voltage information DVa and the second data voltage information DVb may include (e.g., may be) data corresponding to adjacent pixel rows. Here, the first pixel row may be any pixel row among the pixel rows of the display unit 100, and the second pixel row (e.g., the next pixel row) may be a pixel row placed next to (e.g., adjacent to) the first pixel row, but the present disclosure is not limited thereto.

[0151] The memory 420 may provide the image data DATA2 to the data driver 300 and the comparator 430 in units of pixel rows (e.g., in pixel row units). In addition, the memory 420 may sequentially provide a plurality of portions of the data voltage information. The data voltage information provided by the memory 420 to the comparator 430 and the data voltage information provided by the memory 420 to the data driver 300 concurrently (e.g., simultaneously or at the same time) may be data voltage information of different pixel rows. For example, the pixel row for which the data voltage information (e.g., the second data voltage information DVb) provided by the memory 420 to the comparator 430 may correspond to the next pixel row adjacent to the pixel row corresponding to the data voltage information (e.g., the first data voltage information DVa) provided by the memory 420 concurrently (e.g., simultaneously or at the same time) to the data driver 300.

[0152] As described above, when the first data voltage information DVa corresponds to the grayscale (e.g., gray level) of the first pixel row, and the second data voltage information DVb corresponds to the grayscale (e.g., gray level) of the second pixel row adjacent to the first pixel row (e.g., the next pixel row of the first pixel row), the time point at which the first data voltage information DVa is supplied to the comparator 430 may be earlier than the time point at which the first data voltage information DVa is supplied to the data driver 300. In addition, the memory 420 may supply the second data voltage information DVb to the comparator 430 at the time point at which the first data voltage information DVa is supplied to the data driver 300.

[0153] The comparator 430 may generate the data offset information OS according to (e.g., based on) the difference between the first data voltage information DVa and the second data voltage information DVb. As described above, the data offset information OS may be information obtained by comparing the first data voltage information DVa and the second data voltage information DVb. The process of generating the data offset information OS of the comparator 430 will be referred to in detail. Figure 9 The comparator 430 is described in more detail.

[0154] Figure 9 The diagram is included in Figure 8 Diagram of the comparator in the timing controller.

[0155] refer to Figure 9 , the comparator 430 may include a first data averaging unit 4301 and a second data averaging unit 4302 (for example, a first data average calculator and a second data average calculator), a first adder 4303 and a second adder 4304 and an offset provider 4305 .

[0156] The first data voltage information DVa may be input to the first data averaging unit 4301 , and the second data voltage information DVb may be input to the second data averaging unit 4302 .

[0157] The first data averaging unit 4301 may divide the input first data voltage information DVa into p first data voltage blocks (e.g., first blocks) DVa[1] to DVa[p] (where p is a natural number greater than or equal to 1). The first data voltage blocks DVa[1] to DVa[p] may have the same or substantially the same size as each other, but the present disclosure is not limited thereto.

[0158] For example, the first data voltage block (e.g., the first first data voltage block) DVa[1] placed first may include (e.g., may be) a block containing the grayscale value of each pixel in the k pixels of the first pixel row connected to the first data line to the kth data line (where k is a natural number greater than or equal to one), the next first data voltage block (e.g., the second first data voltage block) DVa[2] placed adjacent to the first data voltage block DVa[1] placed first may include (e.g., may be) a block containing the grayscale value of each pixel in the k pixels of the first pixel row connected to the (k+1)th data line to the 2kth data line, and so on.

[0159] In an embodiment, the first data voltage information DVa may be divided into a range of 3 to 64 blocks, for example, the first data voltage information DVa may be divided into 7 or more blocks, but the present disclosure is not limited thereto.

[0160] The first data averaging unit 4301 may calculate an average value of the data voltage information included in each of the first data voltage blocks DVa[1] to DVa[p]. For example, the first data averaging unit 4301 may calculate an average value of the data voltage information of each of the first data voltage blocks DVa[1] to DVa[p] to calculate first average data voltage information AVa[1] to AVa[p] (e.g., first average grayscale information).

[0161] The first data averaging unit 4301 may provide the calculated first average data voltage information AVa[1] to AVa[p] to the first adder 4303 .

[0162] The first adder 4303 may calculate first added data voltage information AVa_S (eg, first added grayscale information) by adding the provided first average data voltage information AVa[1] to AVa[p], and may transmit the first added data voltage information AVa_S to the offset provider 4305 .

[0163] The second data averaging unit 4302 may divide the input second data voltage information DVb into the same number of blocks as the number of blocks of the first data voltage information DVa, and the second data voltage information DVb may have the same or substantially the same size as the first data voltage information DVa. In other words, the second data voltage information DVb may be divided into p second data voltage blocks (e.g., second blocks) DVb[1] to DVb[p].

[0164] The second data averaging unit 4302 may calculate an average value of the data voltage information included in each of the second data voltage blocks DVb[1] to DVb[p]. For example, the second data averaging unit 4302 may calculate an average value of the data voltage information of each of the second data voltage blocks DVb[1] to DVb[p] to calculate second average data voltage information AVb[1] to AVb[p] (e.g., second average grayscale information).

[0165] The second data averaging unit 4302 may provide the calculated second average data voltage information AVb[1] to AVb[p] to the second adder 4304 .

[0166] The second adder 4304 can calculate second added data voltage information AVb_S (e.g., second added grayscale information) by adding the provided second average data voltage information AVb[1] to AVb[p], and can transmit the second added data voltage information AVb_S to the offset provider 4305.

[0167] The offset provider 4305 may generate data offset information OS by comparing the first added data voltage information AVa_S with the second added data voltage information AVb_S. For example, the offset provider 4305 may generate data offset information OS according to (e.g., based on) the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S.

[0168] The offset level of the data offset information OS can be determined based on the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S. For example, as the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S increases, the offset level of the data offset information OS can increase. Similarly, as the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S decreases, the offset level of the data offset information OS can decrease.

[0169] In more detail, the offset provider 4305 may store a first difference value corresponding to the difference between the data voltage for maximum brightness light emission and the data voltage for non-light emission. The first difference value may be a value set during the production process of the display device 11. In addition, the offset provider 4305 may calculate a second difference value corresponding to the difference between the data voltage according to the first added data voltage information AVa_S and the data voltage according to the second added data voltage information AVb_S. The offset provider 4305 may generate the data offset information OS by comparing the previously stored first difference value with the second difference value calculated according to (e.g., based on) the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S.

[0170] In other words, the offset provider 4305 may determine that the variation of the data voltage decreases, and may set the offset level of the data offset information OS to decrease as the difference between the first difference value and the second difference value increases. Alternatively, the offset provider 4305 may determine that the variation of the data voltage increases, and may set the offset level of the data offset information OS to increase as the difference between the first difference value and the second difference value decreases.

[0171] As the variation of the data voltage between adjacent pixel rows increases, the variation of the driving voltage may increase, and therefore, more compensation for the reference voltage may be desired. In other words, the offset provider 4305 can set the offset level to increase so that compensation of the reference voltage can be appropriately performed as the variation of the data voltage between adjacent pixel rows increases.

[0172] The offset level of the data offset information OS can be determined as needed or desired, and can be divided into eight offset levels and represented as three bits of data. However, the offset level of the data offset information OS is not limited thereto, and can be divided into more than eight levels and represented as four or more bits of data.

[0173] Figure 10 The diagram is included in Figure 7 A diagram of a reference voltage generator in a display device.

[0174] refer to Figure 10 , the reference voltage generator 701 may include an initial voltage generator 710 , a reference voltage compensator 721 , and an offset compensator 730 .

[0175] Figure 10 The reference voltage generator 701 is connected to Figure 5 The reference voltage generator 700 may differ in that, Figure 10 The reference voltage generator 701 may further include an offset compensator 730. In other words, Figure 10 The initial voltage generator 710 and the reference voltage compensator 721 can be connected with Figure 5 The initial voltage generator 710 and the reference voltage compensator 721 are the same or substantially the same (or similar) as those of FIG. 1 , and therefore, redundant descriptions of the initial voltage generator 710 and the reference voltage compensator 721 may not be repeated.

[0176] The offset compensator 730 may receive the data offset information OS and may generate offset compensation data OSCD according to (e.g., based on) the data offset information OS. The offset compensation data OSCD may include information corresponding to a compensation value determined according to the data offset information OS. The offset compensator 730 may include a plurality of compensators and may determine the compensation value by each compensator.

[0177] The reference voltage compensator 721 can further receive offset compensation data OSCD from the offset compensator 730, and can generate a first reference voltage VG1' and a second reference voltage VG2' according to (e.g., based on) the first initial reference voltage VIG1 and the second initial reference voltage VIG2, the reference drive voltage VDD_R, the sensing drive voltage VDD_S and the offset compensation data OSCD.

[0178] In the following, reference will be made to Figures 11 to 14 The offset compensator 730 included in the reference voltage generator 701 is described in more detail.

[0179] Figure 11 The diagram is included in Figure 10 Diagram of the offset compensator in the reference voltage generator. Figure 12 The diagram is through Figure 11 FIG. 1 is a diagram of an example of time delay compensation of a first compensator. Figure 13 The diagram is through Figure 11 FIG. 5 is a diagram of an example of slew rate compensation of a second compensator. Figure 14 The diagram is through Figure 11 FIG. 1 is a diagram of an example of gain compensation of the third compensator.

[0180] refer to Figures 11 to 14 The offset compensator 730 may include a plurality of compensators 730a, 730b, and 730c. For example, the plurality of compensators 730a, 730b, and 730c may include a first compensator 730a, a second compensator 730b, and a third compensator 730c. The compensators 730a, 730b, and 730c may determine a degree of compensation (e.g., a compensation amount) based on an offset level of the data offset information OS.

[0181] The first compensator 730a may compensate for a time delay between the first reference voltage VG1' and the second reference voltage VG2'. For example, the first compensator 730a may include (eg, may be) a time delay compensator.

[0182] The first compensator 730a may receive the data offset information OS and generate first compensation data CD1 (e.g., time delay compensation data) corresponding to the data offset information OS. For example, the first compensator 730a may generate the first compensation data CD1 by referring to a lookup table in which time delay compensation values ​​are determined to correspond to the offset levels of the data offset information OS. The time delay compensation level of the first compensation data CD1 may be determined to correspond to the offset level of the data offset information OS.

[0183] For example, Figure 12 As shown in , the control time point (e.g., voltage change time point) of the time delay compensation before the reference voltage VG_REF may be different from the control time point of the time delay compensation after the first compensation reference voltage VG_C1a and the second compensation reference voltage VG_C2a. Here, compared to the compensation before the reference voltage VG_REF, the first compensation reference voltage VG_C1a may be a reference voltage controlled at a later time point. In addition, compared to the compensation before the reference voltage VG_REF, the second compensation reference voltage VG_C2a may be a reference voltage controlled at an earlier time point.

[0184] As the offset level of the data offset information OS decreases, the reference voltage VG_REF may be compensated toward the first compensation reference voltage VG_C1a, and thus, the control time point may be delayed. As the offset level of the data offset information OS increases, the reference voltage VG_REF may be compensated toward the second compensation reference voltage VG_C2a, and thus, the control time point may be earlier. However, the present disclosure is not limited thereto.

[0185] The second compensator 730b may compensate for the slew rates of the first reference voltage VG1' and the second reference voltage VG2'. For example, the second compensator 730b may include (eg, may be) a slew rate compensator.

[0186] The second compensator 730b may receive the data offset information OS and may generate second compensation data CD2 (e.g., slew rate compensation data) corresponding to the data offset information OS. For example, the second compensator 730b may generate the second compensation data CD2 by referring to a lookup table in which slew rate compensation values ​​are determined to correspond to the offset levels of the data offset information OS. The slew rate compensation level of the second compensation data CD2 may be determined to correspond to the offset level of the data offset information OS.

[0187] For example, Figure 13 As shown in FIG, the slew rate (or rising slew rate) of the slew rate compensation before the reference voltage VG_REF may be different from the slew rate of the slew rate compensation after the first compensation reference voltage VG_C1b and the second compensation reference voltage VG_C2b. Here, the first compensation reference voltage VG_C1b may be a reference voltage having a slew rate less than the slew rate of the compensation before the reference voltage VG_REF. In addition, the second compensation reference voltage VG_C2b may be a reference voltage having a slew rate greater than the slew rate of the compensation before the reference voltage VG_REF.

[0188] As the offset level of the data offset information OS decreases, the reference voltage VG_REF may be compensated toward the first compensation reference voltage VG_C1b having a low slew rate. As the offset level of the data offset information OS increases, the reference voltage VG_REF may be compensated toward the second compensation reference voltage VG_C2b having a high slew rate. However, the present disclosure is not limited thereto.

[0189] The third compensator 730c may compensate for gains of the first reference voltage VG1' and the second reference voltage VG2'. For example, the third compensator 730c may include (eg, may be) a gain compensator.

[0190] The third compensator 730c may receive the data offset information OS and generate third compensation data CD3 (e.g., gain compensation data) corresponding to the data offset information OS. For example, the third compensator 730c may generate the third compensation data CD3 by referring to a lookup table in which gain compensation values ​​are determined to correspond to the offset levels of the data offset information OS. The gain compensation level of the third compensation data CD3 may be determined to correspond to the offset level of the data offset information OS.

[0191] For example, Figure 14 As shown in , the gain of the gain compensation before the reference voltage VG_REF may be different from the gain of the gain compensation after the first compensation reference voltage VG_C1c and the second compensation reference voltage VG_C2c. Here, the first compensation reference voltage VG_C1c may be a reference voltage having a gain smaller than the gain of the compensation before the reference voltage VG_REF. In addition, the second compensation reference voltage VG_C2c may be a reference voltage having a gain greater than the gain of the compensation before the reference voltage VG_REF.

[0192] As the offset level of the data offset information OS decreases, the reference voltage VG_REF may be compensated toward the first compensation reference voltage VG_C1c having a small gain. As the offset level of the data offset information OS increases, the reference voltage VG_REF may be compensated toward the second compensation reference voltage VG_C2c having a large gain. However, the present disclosure is not limited thereto.

[0193] As described above, the compensators 730a, 730b, and 730c may generate the first to third compensation data CD1, CD2, and CD3 using the offset level of the lookup table corresponding to the data offset information OS. However, the method of generating the first to third compensation data CD1, CD2, and CD3 is not limited thereto, and the first to third compensation data CD1, CD2, and CD3 may be generated by including a separate operating device.

[0194] The first to third compensation data CD1 , CD2 , and CD3 output from the compensators 730 a , 730 b , and 730 c may be output as offset compensation data OSCD.

[0195] As described above, the first driving voltage VDD applied to each pixel PX in the pixel PX may vary (for example, may vary greatly) according to the difference in data voltages between adjacent pixel rows. Therefore, the display device 11 according to the present embodiment may generate the difference between the data voltages of adjacent pixel rows as data offset information OS, and may generate a first reference voltage VG1' and a second reference voltage VG2' by further reflecting the data offset information OS. Based on the compensation of the first reference voltage VG1' and the second reference voltage VG2', the data signal (for example, the data voltage) provided to each pixel PX in the pixel PX may also be compensated. Therefore, even if the first driving voltage VDD provided to each pixel PX may vary (for example, may change or deviate), the data signal flowing through Figure 2A The amount of driving current of the light emitting element LD can still be maintained or substantially maintained as expected or desired, and therefore, the display quality of the display device 11 can be further improved.

[0196] Hereinafter, another embodiment of the display device will be described. In the following description of one or more embodiments, the configuration and / or elements that are the same or substantially the same as those of one or more previously described embodiments may be referred to by the same reference numerals, and therefore, redundant descriptions of the configuration and / or elements may be simplified or may not be repeated, and the differences in the configuration and / or elements may be mainly described.

[0197] Figures 15 to 17 One or more embodiments of Figures 7 to 14 One or more embodiments may differ in that the reference voltage generator may further receive distance offset information and may generate the first reference voltage and the second reference voltage according to (eg, based on) the distance offset information.

[0198] Figure 15 is a diagram illustrating a display device according to another embodiment. Figure 16 The diagram is included in Figure 15 A diagram of a reference voltage generator in a display device. Figure 17 The diagram is included in Figure 16 Diagram of the offset compensator in the reference voltage generator.

[0199] refer to Figures 15 to 17 , the timing controller 402 of the display device 12 may further provide distance offset information OSD to the reference voltage generator 702. The distance offset information OSD may include (e.g., may be) information corresponding to (e.g., set according to) the distance between each of the pixels of the display unit 100 and the data driver 300.

[0200] In more detail, the display unit 100 may be divided into a plurality of regions DT1 to DT8 , and each of the regions DT1 to DT8 may be a region extending in the first direction DR1 and arranged in the second direction DR2 . Figure 15 The display unit 100 is illustrated as including eight regions DT1 to DT8 , but the present disclosure is not limited thereto. The first to eighth regions DT1 to DT8 may be sequentially arranged along the second direction DR2 according to distances from the data driver 300 .

[0201] The distance offset information OSD may be determined according to the distances between the regions DT1 to DT8 of the display unit 100 and the data driver 300. The distance offset information OSD of the first region DT1, which is closest to the data driver 300, may have the lowest offset level, and the distance offset information OSD of the eighth region DT8, which is farthest from the data driver 300, may have the highest offset level. The distance offset information OSD of the second to seventh regions DT2 to DT7 may be determined as a value between the offset level of the first region DT1 and the offset level of the eighth region DT8.

[0202] Variation (e.g., change or deviation) of the data signals transmitted through the data lines D1 to Dm may increase with increasing distance from the data driver 300. For example, a time delay and / or a voltage drop may occur in the data signals due to line resistance of the data lines D1 to Dm and / or capacitance generated between the lines.

[0203] Therefore, the timing controller 402 may set the distance offset information OSD and may provide the distance offset information OSD to the reference voltage generator 702 .

[0204] The reference voltage generator 702 may generate a first reference voltage VG1″ and a second reference voltage VG2″ according to (eg, based on) the provided distance offset information OSD. In more detail, the reference voltage generator 702 may include an offset compensator 732, and the offset compensator 732 may include a fourth compensator 730d.

[0205] The fourth compensator 730d may receive the distance offset information OSD and generate fourth compensation data CD4 (e.g., distance compensation data) corresponding to the distance offset information OSD. For example, the fourth compensator 730d may generate the fourth compensation data CD4 by referring to a lookup table in which a distance compensation value is determined based on an offset level of the distance offset information OSD. The fourth compensation data CD4 may include at least one of time delay compensation data for a reference voltage, slew rate compensation data, and gain compensation data. The compensation level of the fourth compensation data CD4 may be determined corresponding to the offset level of the distance offset information OSD (e.g., the distance from the data driver 300).

[0206] When the data offset information OS for different pixel rows is the same or substantially the same, the time delay, slew rate, and / or gain compensated for according to the distance offset information OSD determined based on the distance from the data driver 300 may be different. For example, when the data offset information OS for different pixel rows is the same or substantially the same, the control time point of the pixel row with a higher distance offset level may be earlier. In addition, the slew rate of the reference voltage may be adjusted to be greater, and the gain may be adjusted to be greater, for the pixel row with a higher distance offset level.

[0207] The reference voltage compensator 722 can receive offset compensation data OSCDd which further includes fourth compensation data CD4 according to the distance offset information OSD, and the reference voltage compensator 722 can generate a first reference voltage VG1″ and a second reference voltage VG2″ according to (for example, based on) the first initial reference voltage VIG1 and the second initial reference voltage VIG2, the reference drive voltage VDD_R, the sensing drive voltage VDD_S and the offset compensation data OSCDd.

[0208] The gamma voltage generator 600 may generate grayscale voltages V0″ to V255″ according to (e.g., based on) a first reference voltage VG1″ and a second reference voltage VG2″. The data driver 300 may generate data signals according to (e.g., based on) the grayscale voltages V0″ to V255″ and may provide the data signals to the data lines D1 to Dm in pixel row units (e.g., in pixel row units).

[0209] As described above, for example, due to line resistance and / or capacitance between lines, a time delay and / or voltage drop may occur in the data signal as the distance from the data driver 300 increases. Therefore, the display device 12 according to this embodiment can further set distance offset information OSD according to the distance from the data driver 300, and can provide the distance offset information OSD to the reference voltage generator 702. Therefore, the first reference voltage VG1″ and the second reference voltage VG2″ can be compensated more accurately, and the display quality of the display device 12 can be further improved.

[0210] Figure 18 and Figure 19 is a flowchart illustrating a method of driving a display device according to one or more embodiments.

[0211] refer to Figures 1 to 19 , the method of driving the display device according to one or more embodiments may generate a sensing driving voltage VDD_S by measuring a first driving voltage VDD supplied to the display unit 100 including a plurality of pixels PX ( S100 ).

[0212] As described above, the first driving voltage VDD generated by the power supply 500 and supplied to the display unit 100 may be delayed due to the resistance of the line for transmitting the first driving voltage VDD to each of the pixels PX and / or the capacitance between other lines, and thus a voltage drop may occur. In other words, the driving voltage supplied to (e.g., substantially supplied to) each of the pixels PX may be the sensing driving voltage VDD_S and may be different from the first driving voltage VDD generated by the power supply 500.

[0213] therefore, Figure 18 The driving method of FIG. 5 may generate the sensing driving voltage VDD_S by measuring a driving voltage supplied to each of the pixels PX.

[0214] Afterwards, Figure 18 The driving method may generate data offset information OS by comparing data voltage information DVa and DVb of adjacent pixel rows ( S200 ).

[0215] As reference Figure 8 Described, Figure 18 The driving method may compare data voltage information DVa and DVb of adjacent pixel rows through the comparator 430 of the timing controller 401 and may generate data offset information OS according to (eg, based on) the data voltage information DVa and DVb.

[0216] refer to Figure 19 In some embodiments, as shown in FIG. Figure 9 As described, operation S200 of generating data offset information OS may include dividing first data voltage information DVa applied to a first pixel row into a plurality of first data voltage blocks DVa[1] to DVa[p], and dividing second data voltage information DVb applied to a second pixel row adjacent to the first pixel row into a plurality of second data voltage blocks DVb[1] to DVb[p] (S210). First average data voltage information AVa[1] to AVa[p] may be calculated for each of the first data voltage blocks DVa[1] to DVa[p], and second average data voltage information AVb[1] to AVb[p] may be calculated for each of the second data voltage blocks DVb[1] to DVb[p] (S220). The first added data voltage information AVa_S may be calculated by adding the first average data voltage information AVa[1] to AVa[p], and the second added data voltage information AVb_S may be calculated by adding the second average data voltage information AVb[1] to AVb[p] (S230). In addition, data offset information OS may be generated according to (e.g., based on) the first added data voltage information AVa_S and the second added data voltage information AVb_S (S240).

[0217] The offset level of the data offset information OS can be determined based on the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S. As the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S increases, the offset level of the data offset information OS can increase, and as the difference between the first added data voltage information AVa_S and the second added data voltage information AVb_S decreases, the offset level of the data offset information OS can decrease. In other words, the offset level of the data offset information OS can be determined based on the difference between the data voltage information DVa and DVb of adjacent pixel rows.

[0218] Reference again Figure 18 , Figure 18 The driving method may generate a first reference voltage VG1 and a second reference voltage VG2 according to (e.g., based on) a sensing driving voltage VDD_S, a reference driving voltage VDD_R, and data offset information OS (S300). A plurality of grayscale voltages V0 to V255 may be generated by dividing the first reference voltage VG1 and the second reference voltage VG2 (S400).

[0219] As described above, the offset level of the data offset information OS can be determined according to the difference between the data voltage information DVa and DVb of the adjacent pixel rows. Figures 11 to 14 As described, the time delay, slew rate, and / or gain of the first reference voltage VG1 and the second reference voltage VG2 may be controlled (eg, compensated) according to the offset level of the data offset information OS.

[0220] For example, as the offset level of the data offset information OS increases, the reference voltage can be adjusted so that the control time point (or voltage control time point) is earlier. In addition, as the offset level increases, the slew rate and gain of the reference voltage can be adjusted to be increased.

[0221] As described above, Figure 18 The driving method can reflect the difference between the reference driving voltage VDD_R and the sensing driving voltage VDD_S when generating the first reference voltage VG1 and the second reference voltage VG2. Figure 18 The driving method may control the first reference voltage VG1 and the second reference voltage VG2 according to (eg, based on) data offset information OS reflecting a difference in data voltages applied to adjacent pixel rows, so Figure 18 The driving method may effectively compensate for a variation (eg, change or deviation) of the first driving voltage VDD through the first reference voltage VG1 and the second reference voltage VG2 , and may improve the display quality of the display device.

[0222] The electronic device or electrical device and / or any other related device or component according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM or a flash drive. In addition, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the present disclosure.

[0223] Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the example embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of features or aspects in each embodiment should typically be considered to be other similar features or aspects that can be used in other embodiments. Therefore, it is to be understood that the above is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed herein, and that various modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: a display unit including a plurality of pixels configured to display an image according to a driving voltage; a data driver configured to provide data signals to the plurality of pixels; a gamma voltage generator configured to provide a plurality of grayscale voltages to the data driver; a timing controller configured to compare data voltage information of adjacent pixel rows to generate data offset information, and provide the data offset information to the reference voltage generator; as well as the reference voltage generator being configured to provide a first reference voltage and a second reference voltage to the gamma voltage generator, wherein the gamma voltage generator is configured to generate the plurality of gray voltages by dividing the first reference voltage and the second reference voltage, and The reference voltage generator is configured to generate a sensing driving voltage by measuring the driving voltage from the display unit, and generate the first and second reference voltages by using the sensing driving voltage, a reference driving voltage, and the data offset information.

2. The display device according to claim 1, wherein The timing controller includes: an image processor configured to convert the first image data into second image data; a memory configured to receive the second image data from the image processor and store the second image data; and a comparator configured to receive first data voltage information of a first pixel row of the second image data and second data voltage information of a second pixel row of the second image data adjacent to the first pixel row from the memory, and output the data offset information according to a difference between the first data voltage information and the second data voltage information.

3. The display device according to claim 2, wherein A time point at which the memory provides the first data voltage information to the comparator is earlier than a time point at which the memory provides the first data voltage information to the data driver, and wherein the memory is configured to provide the second data voltage information of the second pixel row to the comparator at a time point when the memory provides the first data voltage information of the first pixel row to the data driver, and The second pixel row is a next pixel row adjacent to the first pixel row. The display device according to claim 1 , wherein: The reference voltage generator is configured to control at least one of a time delay, a slew rate, and a gain of the first reference voltage and the second reference voltage according to an offset level of the data offset information, and The shift level of the data shift information increases as a difference in the data voltage information of the adjacent pixel rows increases, and decreases as the difference in the data voltage information of the adjacent pixel rows decreases.

5. The display device according to claim 4, wherein The reference voltage generator is configured to control the voltage change time point of the first reference voltage and the second reference voltage to be earlier, control the conversion rate of the first reference voltage and the second reference voltage to increase, or control the gain of the first reference voltage and the second reference voltage to increase as the offset level increases. The display device according to claim 1 , wherein: The timing controller is further configured to: generating distance offset information according to a separation distance between the plurality of pixels and the data driver; and providing the distance offset information to the reference voltage generator, and The reference voltage generator is configured to control the first reference voltage and the second reference voltage according to the data offset information, the distance offset information, the sensing driving voltage, and the reference driving voltage, and wherein the reference voltage generator is configured to control at least one of a time delay, a conversion rate, and a gain of the first reference voltage and the second reference voltage according to an offset level of the distance offset information, and The offset level of the distance offset information increases as the separation distance increases, and decreases as the separation distance decreases.

7. A method for driving a display device, the method comprising: generating a sensing driving voltage by measuring a driving voltage supplied to a display unit including a plurality of pixels; Generate data offset information by comparing data voltage information of adjacent pixel rows; generating a first reference voltage and a second reference voltage according to the sensing driving voltage, the reference driving voltage and the data offset information; and A plurality of gray voltages are generated by dividing the first reference voltage and the second reference voltage.

8. The method according to claim 7, wherein: Generating the first reference voltage and the second reference voltage includes: According to the offset level of the data offset information, at least one of a time delay, a conversion rate, and a gain of the first reference voltage and the second reference voltage is controlled, and The offset level increases as a difference in the data voltage information of the adjacent pixel rows increases, and decreases as the difference in the data voltage information of the adjacent pixel rows decreases.

9. The method according to claim 7, wherein: Generating data offset information includes: dividing the first data voltage information of the first pixel row into a plurality of first data voltage blocks; dividing second data voltage information of a second pixel row adjacent to the first pixel row into a plurality of second data voltage blocks; calculating first average data voltage information of each first data voltage block of the plurality of first data voltage blocks; calculating second average data voltage information of each second data voltage block in the plurality of second data voltage blocks; calculating first added data voltage information by adding the first average data voltage information; calculating second added data voltage information by adding the second average data voltage information; and The data offset information is generated according to the first added data voltage information and the second added data voltage information.

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