Methods, related apparatuses, and systems for reliably forming microelectronic devices with conductive contacts targeting silicide regions.

Abstract

This application relates to a method, and related apparatus and system, for reliably forming a microelectronic device having conductive contacts targeting silicide regions. The microelectronic device having at least one conductive contact structure adjacent to a silicide region is formed using a method that avoids unintentional contact expansion and contact reduction. A first metal nitride liner is formed in the contact opening, and the exposed surface of the polysilicon structure is subsequently treated (e.g., cleaned and dried) to prepare for the formation of the silicide region. During the pretreatment (e.g., cleaning and drying), adjacent dielectric material is protected by the metal nitride liner, thereby preventing expansion of the contact opening. After the silicide region is formed, a second metal nitride liner is formed on the silicide region before forming a conductive material to fill the contact opening and before forming a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application Serial No. 16 / 654,865, entitled “Methods for Reliably Forming Microelectronic Devices with Conductive Contacts to Silicide Regions, and Related Devices and Systems,” filed on October 16, 2019. Technical Field

[0003] Embodiments of this disclosure relate to the field of microelectronic device design and manufacturing. More specifically, embodiments of this disclosure relate to methods of forming devices having contacts, and to related devices, semiconductor devices, and electronic systems. Background Technology

[0004] Semiconductor device designers typically aim to increase the integration or density of features within a semiconductor device by reducing the size of individual features and the spacing between adjacent features. Furthermore, semiconductor device designers often seek architectures that are not only compact but also offer performance advantages and simplified design.

[0005] An example of a semiconductor device is a memory device. Memory devices are typically housed as internal integrated circuits in computers or other electronic devices. Many types of memory exist, including, but not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistive variable memory. Non-limiting examples of resistive variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

[0006] A typical memory cell in a memory device includes an access device (e.g., a transistor) and a memory storage structure (e.g., a capacitor) electrically coupled to the access device via conductive contacts. The access device typically includes a channel region between a pair of source / drain regions and a gate electrode configured to electrically connect the source / drain regions to each other through the channel region. The access device can include planar access devices or vertical access devices. Planar access devices can be distinguished from vertical access devices based on the current direction between their source and drain regions. The current between the source and drain regions of a vertical access device is substantially orthogonal (e.g., perpendicular) to the main (e.g., primary) surface of its underlying substrate or base structure, while the current between the source and drain regions of a planar access device is primarily parallel to the main surface of its underlying substrate or base structure.

[0007] The structure and fabrication methods of conventional memory cells used in memory devices may have less than desirable electrical properties. For example, conductive contacts included in a conventional memory cell may employ cobalt disilicide (CoSi2) to reduce contact resistance, and metal nitride (e.g., TiN) liners may be used to promote adhesion of conductive structures (e.g., conductive plugs) to CoSi2. To form these materials, contact openings may be formed to expose the surface of a polycrystalline silicon structure. Cleaning and drying are performed to remove impurities or other debris from the surface of the polycrystalline silicon. Cobalt is then deposited on the cleaned and dried exposed polycrystalline silicon surface, and heat treatment is performed to form CoSi2 on the polycrystalline silicon surface by cobalt and polycrystalline silicon. The remaining cobalt (e.g., cobalt not converted to CoSi2) is then removed (e.g., by etching or other “residue removal” actions). A metal nitride (e.g., TiN) liner is then formed on the CoSi2 and along the sidewalls in the contact openings. The conductive structure (e.g., conductive plug) is then formed.

[0008] The aforementioned cleaning, drying, and residue removal processes enable the formation of silicide materials with sufficient purity to provide adequate electrical connectivity between the conductive contact structure to be formed and the polycrystalline silicon structure (e.g., which may contain the source / drain regions of a microelectronic device such as a memory device). However, these processes, identical to those in conventional manufacturing methods, can lead to contact widening (e.g., due to unintentional widening of contact openings during cleaning, drying, and cobalt removal processes), resulting in an increased risk of short circuits and current leakage. Conventional methods for preventing such problems (e.g., including a protective dielectric structure (e.g., SiN) around the contact openings) are prone to causing other problems, such as contact reduction (e.g., reduced contact width, reduced silicide region size, or both), leading to increased contact resistance and degraded device performance.

[0009] For example, such as Figure 1AAs shown, ideally, forming the conductive contact structure 102 (e.g., a conductive unit contact structure) using conventional methods can aim to form a conductive contact structure 102 with a sufficient width WC (and therefore sufficient electronic connectivity) at the interface 104 between the silicide region 106 (e.g., a cobalt silicide region) and one or more metal nitride liners (e.g., a first metal nitride liner 108 and a second metal nitride liner 110). Moreover, ideally, the silicide region 106 extends entirely along the upper surface of the polysilicon structure 112. However, the use of conventional methods can lead to unintentional contact expansion, such as... Figure 1B Reduced exposure, whether intentional or unintentional, such as Figure 1C As shown.

[0010] Further information Figure 1B Contact widening can be achieved, for example, by cleaning and drying the contact openings during conventional manufacturing processes to prepare the surface of the polycrystalline silicon structure 112, thereby forming cobalt thereon, or, for example, by removing unconverted cobalt material after forming the cobalt silicide region 106. The cleaning, drying, and cobalt removal actions may unintentionally remove all or part of adjacent dielectric material (such as dielectric liner 114 (e.g., SiN liner), dielectric structure 116 (e.g., another SiN structure), and another dielectric structure 118 (e.g., SiO2 structure)), thereby widening the contact openings during manufacturing. The resulting Figure 1B The unintentionally widened conductive contact structure 102 may pose a risk of short circuit and current leakage with adjacent conductive areas (e.g., bit line structure 120).

[0011] Further information Figure 1C If, for example, sufficient dielectric liner 114 is not removed during cleaning, drying, and cobalt removal operations (especially since controlling the amount of material removed from dielectric liner 114 during these operations is challenging), routine work to combat contact expansion by providing a thicker dielectric liner 114 adjacent to the contact opening may result in unintentional contact reduction. Using a thicker dielectric liner 114 also limits the amount of cobalt that can be formed on the polysilicon structure 112, and therefore also limits the size of the silicide region 106. With the reduced silicide region 106, the interface 104 is reduced, thereby providing fewer physical and electrical connections between the silicide region 106 and, for example, the first metal nitride liner 108. Therefore, relative to… Figure 1A In the ideal scenario, the effective resistance of the conductive structure will increase.

[0012] Figures 1A to 1CThis paper demonstrates the challenges of conventional manufacturing methods and structures for conductive contact structures 102 in the form of conductive memory cell contacts. Conventional manufacturing methods also present the aforementioned challenges of contact expansion and contact reduction compared to other types of conductive contact structures, including peripheral contact structures. Figures 2A to 2C As shown.

[0013] like Figure 2A As shown, the ideal fabrication of the conductive contact structure 202 (e.g., a peripheral contact structure) will form the conductive contact structure 202 such that the interface 204 having the silicide region 206 has the width required to form sufficient electrical contacts. The interface connection material can be at least one metal nitride liner (e.g., a first metal nitride liner 208 that also includes a second metal nitride liner 210) and silicide (e.g., cobalt silicide) formed in the silicide region 206 in a portion of the surface of the polycrystalline silicon structure 212 (e.g., a substrate). Ideally, a dielectric liner (e.g., Figure 2C The dielectric liner 214), while the adjacent dielectric materials (e.g., the dielectric materials of dielectric structure 216 and another dielectric structure 218) remain intact after the contact openings occupied by the first metal nitride liner 208, the second metal nitride liner 210, and the conductive contact structure 202 are formed. However, as described above... Figure 1B and Figure 1C Similar to the discussion, the fact that conventional manufacturing methods are used may lead to... Figure 2B The contact expansion shown or as Figure 2C The resulting reduction in contact is significant. In other words, cleaning, drying, and residual cobalt removal actions during conventional manufacturing processes can lead to contact opening expansion because dielectric material (e.g., the dielectric material of dielectric structure 216 and other dielectric structures 218) is unintentionally removed, particularly from unprotected dielectric linings (e.g., Figure 2C In the case of dielectric liner 214, as such contacts expand, the risk of short circuits and current leakage between conductive contact structure 202 and other nearby conductive structures (e.g., gate 220) increases. Alternatively, using, as in Figure 2C The protective dielectric liner 214, etc., may result in smaller silicide regions 206 (e.g., with...). Figure 2A or Figure 2B Compared to the silicide region) and the conductive contact structure 202 with a smaller width (e.g., with...), Figure 2A and Figure 2B Compared to the contact structure, the contact is reduced (e.g., if such dielectric liner is completely or insufficiently removed during cleaning, drying, or other operations). Therefore, the reduced contact causes higher resistance in the conductive contact structure 202, thereby impairing the performance of the conductive contact structure 202.

[0014] Therefore, reliably forming conductive contact structures (e.g., memory cell contact structures and peripheral contact structures) adjacent to silicide regions remains a challenge. Summary of the Invention

[0015] A method for forming a microelectronic device is disclosed. The method includes forming an opening through at least one dielectric material to expose the surface of a polysilicon structure. A first metal nitride liner is formed in the opening. After forming the first metal nitride liner, the surface of the polysilicon structure is cleaned and dried. A metal silicide region is formed on the surface of the polysilicon structure. A second metal nitride liner is formed on the first metal nitride liner and the metal silicide region. The remaining portion of the opening covering the second metal nitride liner is filled with a conductive material to form a conductive contact structure.

[0016] A microelectronic device is also disclosed. The microelectronic device includes at least one conductive contact structure on a metal silicide material. A first metal nitride liner is located on the vertical sidewall of the at least one conductive contact structure. A second metal nitride liner is located between the conductive contact structure and the metal silicide material.

[0017] Furthermore, a method for forming a microelectronic device is disclosed. The method includes forming a contact opening through at least one dielectric material to expose a surface portion of a polysilicon structure. A first metal nitride liner is formed in the contact opening without cleaning and drying the surface portion of the polysilicon structure. A portion of the first metal nitride liner is removed to re-expose the surface portion of the polysilicon structure. The surface portion of the polysilicon structure is cleaned and dried, and a silicide region is formed on the surface portion of the polysilicon structure. A second metal nitride liner is formed on the silicide region. A conductive contact structure is formed on the second metal nitride liner.

[0018] Furthermore, a microelectronic device is disclosed. The microelectronic device includes a conductive contact structure laterally adjacent to an electrically insulating conductive region. A silicide region is located below the conductive contact structure. A single metal nitride liner is directly located between the silicide region and the conductive contact structure.

[0019] Furthermore, an electronic system is disclosed. The electronic system includes at least one memory device, the at least one memory device including at least one digit line and at least one word line operatively communicating with at least one memory cell. The at least one memory cell includes at least one conductive contact structure within a metal nitride liner. The metal nitride liner includes a first metal nitride liner and a second metal nitride liner. The at least one memory cell also includes a metal silicide material on a polysilicon structure. The second metal nitride liner is directly disposed between the metal silicide material and the at least one conductive contact structure. The electronic system also includes at least one electronic signal processor, at least one input device, and at least one output device. The at least one electronic signal processor is operatively connected to the at least one memory device. The at least one input device is operatively communicating with the at least one electronic signal processor. The at least one output device is operatively communicating with the at least one input device. Attached Figure Description

[0020] Figures 1A to 1C This is a schematic cross-sectional elevation view of a hypothetical microelectronic device structure, in which:

[0021] Figure 1A A hypothetical microelectronic device structure with a unit contact structure formed by an idealized conventional method is presented;

[0022] Figure 1B A hypothetical microelectronic device structure with a unit contact structure is demonstrated, which exhibits unintentional contact expansion due to challenges of conventional manufacturing methods; and

[0023] Figure 1C A hypothetical microelectronic device structure with a unit contact structure is shown, which exhibits unintentional contact reduction due to challenges of conventional manufacturing methods.

[0024] Figures 2A to 2C This is a schematic cross-sectional elevation view of a hypothetical microelectronic device structure, in which:

[0025] Figure 2A A hypothetical microelectronic device structure with an external contact structure formed by an idealized conventional method is presented;

[0026] Figure 2B A hypothetical microelectronic device structure with peripheral contact structures is demonstrated, which exhibit unintentional contact expansion due to challenges of conventional manufacturing methods; and

[0027] Figure 2C A hypothetical microelectronic device structure with peripheral contact structures is shown, which exhibit unintentional contact reduction due to challenges of conventional manufacturing methods.

[0028] Figures 3 to 10 Manufacturing according to embodiments of this disclosure Figure 10 The diagram shows cross-sectional elevation views of the microelectronic device structure with unit contact structure during various fabrication stages.

[0029] Figures 11 to 18 Manufacturing according to embodiments of this disclosure Figure 18 The diagram shows cross-sectional elevation views of the microelectronic device structure with peripheral contact structure during various fabrication stages.

[0030] Figure 19 This is a functional block diagram of a memory device according to embodiments of the present disclosure.

[0031] Figure 20 This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0032] According to embodiments of this disclosure, structures (e.g., microelectronic device structures), devices (e.g., microelectronic devices, such as memory devices), and systems (e.g., electronic systems) include one or more conductive contact structures, each of which results in the formation of a silicide region within a polysilicon structure. Prior to cleaning and drying operations, the conductive contact structure is laterally lined with a first metal nitride liner formed in a contact opening. The conductive contact structure is also laterally and underside lined with a second metal nitride liner. During formation, the first metal nitride liner protects adjacent dielectric material in which the contact opening is formed, thereby preventing the dielectric material from being removed to prevent unintentional widening of the contact opening. The use of the first metal nitride liner also avoids the need for conventional thick dielectric liners (e.g., ...) within the contact opening. Figure 1C Dielectric liner 114 Figure 2C The dielectric liner 214 is required; therefore, the risk of unintentional contact reduction is also avoided. The method described herein enables precise control of the lateral dimensions (e.g., width, diameter) of the conductive contact structure, for example on the order of nanometers, even in the case of high aspect ratio contact openings, and control over the use of cleaning, drying, and etching processing actions.

[0033] As used herein, the term "opening" means a volume extending through at least one structure or at least one material, leaving a gap within said at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between said structures or materials. Unless otherwise stated, an "opening" is not necessarily devoid of material. That is, an "opening" is not necessarily an empty space. An "opening" formed in or between a structure or material may include one or more structures or one or more materials other than the structure or material in which or between the opening is formed. Furthermore, one or more structures or one or more materials "exposed" within an opening are not necessarily in contact with the atmosphere or a non-solid environment. One or more structures or one or more materials "exposed" within an opening may be adjacent to or in contact with other one or more structures or one or more materials disposed within the opening.

[0034] As used herein, the term "substrate" means and includes a base material or other structure forming a component such as a component within a memory cell. A substrate can be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, one or more structures, or one or more regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate containing semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") or silicon-on-glass ("SOG") substrates, epitaxial silicon layers on a base semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si... 1-x Ge x , where x is, for example, a mole fraction between 0.2 and 0.8, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when "substrate" is referred to in the following description, the material, structure, or junction may have been formed in the substrate semiconductor structure or base using previous process stages.

[0035] As used herein, the terms "horizontal" or "lateral" mean and include the orientation of the referenced material or structure parallel to the substrate on the main surface. The width and length of individual materials or structures can be defined as dimensions in the horizontal plane.

[0036] As used herein, the terms "vertical" or "longitudinal" mean and include the orientation perpendicular to the main surface of the referenced material or structure on the substrate. The height of an individual material or structure can be defined as a dimension in a vertical plane.

[0037] As used herein, the term “thickness” or “thinness” means and includes a dimension in a straight line perpendicular to the nearest surface of an adjacent material or structure having a different composition or being distinct from materials or structures whose thickness, thinness, or height is discussed.

[0038] As used herein, the term "between" is a spatial relative term used to describe the relative placement of a material, structure, or substructure with respect to at least two other materials, structures, or substructures. The term "between" can encompass both a material, structure, or substructure placed in direct proximity to other materials, structures, or substructures and a material, structure, or substructure placed in indirect proximity to other materials, structures, or substructures.

[0039] As used herein, the term "proximity" is a spatially relative term used to describe the placement of one material, structure, or substructure in the vicinity of another material, structure, or substructure. The term "proximity" includes placement as indirect proximity, direct proximity, and interior.

[0040] As used herein, the term "neighboring," when referring to a material or structure, means and refers to the next closest material or structure to the identified component or feature. Materials or structures of other components or features besides the identified component or feature may be situated between the identified component or feature and its "neighboring" material or structure. For example, a structure of material X "neighboring" a structure of material Y is, for example, the first material X structure that is the second closest to a specific structure of material Y among a plurality of material X structures. "Neighboring" materials or structures may be directly or indirectly adjacent to the structure or material of the identified component or feature.

[0041] As used herein, the terms “about” or “approximately” when used with respect to a particular parameter include the value and, as would be understood by one of ordinary skill in the art, a degree of difference from the value within an acceptable tolerance for the particular parameter. For example, “about” or “approximately” with respect to a value may include other values ​​in the range of 90.0% to 110.0%, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0042] As used herein, when referring to a parameter, property, or condition, the term "substantially" means and includes a parameter, property, or condition that is equal to or differs from a given value to a degree such that a person skilled in the art would understand that such a given value would be acceptablely satisfied, such as within acceptable manufacturing tolerances. For example, a parameter, property, or condition may be "substantially" a given value if the value is satisfied at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0043] As used herein, referring to an element as being “on” or “above” another element means and includes the element being directly on top of the other element, adjacent to the other element (e.g., laterally adjacent, vertically adjacent), below the other element, or in direct contact with the other element. It also includes the element being indirectly on top of the other element, indirectly adjacent to the other element (e.g., laterally adjacent, vertically adjacent), indirectly below the other element, or indirectly near the other element, wherein other elements are present in between. Conversely, when an element is referred to as being “directly on” or “directly adjacent to” another element, no intermediate elements are present.

[0044] As used herein, for ease of description, other spatially relative terms such as “below,” “lower,” “bottom,” “above,” “upper,” and “top” may be used to describe the relationship of one element or feature as shown in the accompanying drawings to one or more other elements or features. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material in addition to those depicted in the accompanying drawings. For example, if the material in the accompanying drawings were inverted, an element described as being “below,” “under,” or “bottom” of other elements or features would be oriented as being “above” or “top” of said other elements or features. Thus, the term “below” can encompass both above-orientation and below-orientation, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (rotated ninety degrees, inverted, etc.) and therefore spatially relative descriptive terms are used accordingly herein.

[0045] As used herein, any formula (e.g., a compound formula) containing one or more of “x,” “y,” and “z” represents a material comprising the average ratio of “x” atoms of one element, “y” atoms of another element, and / or “z” atoms of another element (if any). Because the formula represents relative atomic ratios rather than strict chemical structures, the material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and / or “z” (if any) may be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and comprises a compound having an elemental composition that cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions.

[0046] As used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of stated features, structures, stages, operations, elements, materials, components, and / or groups, but do not exclude the presence or addition of one or more other features, structures, stages, operations, elements, materials, components, and / or groups thereof.

[0047] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context explicitly indicates otherwise.

[0049] As used herein, the terms “configured” and “configuration” mean and refer to the size, shape, material composition, orientation, and arrangement of the referenced material, structure, assembly, or device in order to facilitate the reference operation of the referenced material, structure, assembly, or device in a predetermined manner.

[0050] The illustrations presented herein are not intended to be actual views of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but are merely idealized representations used to describe embodiments of this disclosure.

[0051] This document describes embodiments with reference to cross-sectional illustrations as schematic diagrams. Therefore, variations in shape as shown in the illustrations should be expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes or structures shown, but may include shape deviations, for example, resulting from manufacturing techniques. For instance, a structure shown or described as box-shaped may have coarse and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the materials, features, and structures shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of materials, features, or structures, and do not limit the scope of the claims of this invention.

[0052] The following description provides specific details, such as material types and processing conditions, to provide a comprehensive description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, those skilled in the art will understand that embodiments of the apparatus and methods can be practiced without these specific details. In fact, embodiments of the apparatus and methods can be practiced in conjunction with conventional semiconductor manufacturing techniques used in the industry.

[0053] The manufacturing processes described herein do not form a complete process flow for processing equipment (e.g., apparatus, system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, this document only describes the methods and structures necessary for understanding embodiments of the inventive equipment (e.g., apparatus, system) and methods.

[0054] Unless the context otherwise requires, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Those skilled in the art can select the technique for depositing or growing the material depending on the specific material to be formed.

[0055] Unless the context otherwise indicates, the material described herein can be removed by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, grinding planarization, or other known methods.

[0056] Referring now to the accompanying drawings, where similar reference numerals refer to similar components throughout. The drawings are not necessarily drawn to scale.

[0057] According to the method of this disclosure, a device having a conductive contact structure is formed without the risk of contact expansion or contact reduction. It will be apparent to those skilled in the art from the description provided below that the method described herein can be used to manufacture various devices (e.g., microelectronic devices). In other words, the method of this disclosure can be used when it is necessary to form a device having a conductive contact structure (such as a conductive contact structure adjacent to a silicide region formed by a method including cleaning, drying, or residue removal operations).

[0058] Figures 3 to 10 This is a simplified cross-sectional view illustrating an embodiment of a method for forming a device (e.g., a microelectronic device, such as a semiconductor device, a memory device, or a DRAM device) with conductive unit contact structures.

[0059] refer to Figure 3 Contact openings 302 are formed (e.g., etched) using at least one dielectric material to expose the surface of the polysilicon structure 304. For example, Figure 3 The contact opening 302 is formed by a dielectric liner 306 (e.g., SiN) and adjacent additional dielectric materials, such as dielectric structure 308 (e.g., SiN), another dielectric structure 310 (e.g., SiO2), and another dielectric structure 312 (e.g., SiN). Dielectric structure 308, other dielectric structures 310, and other dielectric structures 312 can be disposed between the polysilicon structure 304 and the bit line structure 314, which has already been formed by methods known in the art, and therefore will not be described in detail herein.

[0060] refer to Figure 4 Exposure to contact opening 302 before it has been cleaned, dried or otherwise treated Figure 3 In the case of a surface exposed in the contact opening 302, a first metal nitride liner 402 is formed at least along the surface exposed in the contact opening 302, thereby forming a first liner contact opening 404. The thickness of the first metal nitride liner 402 can be in the range of about 1.5 nm to about 5 nm. The first metal nitride liner 402 can be formed directly on the surface exposed in the contact opening 302. Figure 3 The contact opening 302 exposes the dielectric liner 306 and the surface of the polysilicon structure 304. In other words, the first metal nitride liner 402 is formed on at least one untreated surface of the polysilicon structure 304. As used herein, the term "untreated surface" means and includes a surface that, once exposed by a completed material removal action (e.g., etching), is not subsequently exposed to material removal actions such as cleaning (e.g., an action configured to remove impurities from the surface), drying (e.g., an action configured to remove moisture), and etching.

[0061] The first metal nitride liner 402 is formed of a metal nitride material (e.g., titanium nitride (TiN)) that is resistant to isotropic etching and can be used as a barrier material for the conductive material of the conductive contact structure to be formed.

[0062] The first metal nitride liner 402 can be formed, for example, by depositing (e.g., conformal deposition via CVD, ALD) a metal nitride (e.g., TiN) and then removing (e.g., via CMP) the material of the first metal nitride liner 402 outside the boundary of the first liner contact opening 404.

[0063] Remove a portion (commonly referred to as a "perforation") of the first metal nitride liner 402 adjacent to the bottom of the first liner contact opening 404 to form such Figure 5 The opening 502 shown has a first metal nitride sidewall liner 504 along its side. The surface portion 506 of the polysilicon structure 304 is exposed at the bottom of the opening 502.

[0064] Remove the bottom portion of the first metal nitride liner 402. Figure 4 The formation of the first metal nitride sidewall liner 504 can be accomplished by conventional processes, such as conventional etching processes (e.g., conventional dry etching processes) that are not described in detail herein.

[0065] A first metal nitride sidewall liner 504 is disposed between an opening 502 and a dielectric material adjacent to the opening 502, the dielectric material comprising a dielectric liner 306, dielectric structures 308, and other dielectric structures 310. Each of these dielectric materials may cover the opening 502. Thus, the first metal nitride sidewall liner 504 is configured to cover and protect the dielectric material comprising the directly adjacent dielectric liner 306 during subsequent manufacturing operations.

[0066] After forming a first metal nitride sidewall liner 504 along the sidewall of the opening 502, the exposed surface portion 506 of the polycrystalline silicon structure 304 can be cleaned and dried to prepare a surface portion 506 of metal (e.g., cobalt (Co)) that will eventually be contained in the silicide region.

[0067] Cleaning may include performing isotropic etching, such as a vapor etching pretreatment before subsequent metal (e.g., cobalt) sputtering. For example, cleaning may include using dilute hydrofluoric acid (DHF).

[0068] Drying may include... Figure 5 The structure is exposed to heat. In some embodiments, the drying process may not use a chlorine-based etchant; therefore, the metal nitride (e.g., TiN) of the first metal nitride sidewall liner 504 may not be degraded or removed during drying.

[0069] Because the first metal nitride sidewall liner 504 is present on the dielectric liner 306 and other dielectric materials adjacent to the opening 502 (e.g., dielectric structure 308, other dielectric structures 310), the dielectric material (including the dielectric liner 306) is not exposed to the cleaning and drying processes and is therefore not threatened by the unintentional removal of part or all of the dielectric material. Therefore, the opening 502 does not expand during cleaning or drying. Instead, the opening (e.g., ...) is formed in the contact opening. Figure 3 Performing conventional cleaning and drying methods after contact opening 302 carries the risk of unintentionally widening the contact opening by removing some or all of the adjacent dielectric material, for example, as described above. Figure 1B The subject of discussion.

[0070] Furthermore, since the first metal nitride sidewall liner 504 is present on the dielectric liner 306 and other dielectric materials, the dielectric liner 306 does not need to have a large thickness to compensate for material loss during, for example, cleaning and drying, prior to these processes. For example, in some embodiments, the dielectric liner 306 is formed during... Figure 3 The contact opening 302 can have a thickness of approximately 2 nm. With this relatively low thickness of the dielectric liner 306, the opening 502 (and subsequent conductive contact structure) can be wider than the opening (and subsequent conductive contact structure) when using a thicker dielectric liner (e.g., as discussed above). Figure 1C As shown, this allows the conductive contact structure to be formed with a lower resistance than it would otherwise have, and thus has improved performance.

[0071] Furthermore, since the thickness of the dielectric liner 306 remains the same or substantially the same before and after, for example, cleaning and drying, the thickness of the dielectric liner 306 can be more precisely tailored and / or controlled to form a conductive contact structure with a more precisely tailored and / or controlled width, taking into account the width of the opening 502. For example, if the width of the opening 502 is relatively narrow, the thickness of the dielectric liner 306 can be tailored to be relatively thin, for example, before cleaning and drying, so that a conductive contact structure with a desired sufficient width can subsequently be formed within the relatively narrow opening. On the other hand, if the width of the opening 502 is relatively wide, the thickness of the dielectric liner 306 can be tailored to be relatively thick, for example, before cleaning and drying, so that a conductive contact structure with a desired sufficient width can subsequently be formed within the relatively wide opening. Therefore, compared to conventional manufacturing processes, the protection of the dielectric liner 306 by the first metal nitride sidewall liner 504 during, for example, cleaning and drying, allows for more precise tailoring and / or control of the formation of the conductive contact structure.

[0072] After cleaning and drying, metal 602 (ultimately contained in a metal silicide) is formed (e.g., by sputtering) on ​​at least the surface portion 506 of the polysilicon structure 304 at the substrate of opening 502. Metal 602 may also be formed on the upper surface of intermediate structures, such as on the upper surfaces of dielectric liner 306, dielectric structure 308, and other dielectric structures 310. The vertical surfaces of the first metal nitride sidewall liner 504 may be substantially free of metal 602.

[0073] As a non-limiting example, metal 602 may include one or more of cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), platinum (Pt), ruthenium (Ru), and nickel (Ni).

[0074] The metal 602 along the surface portion 506 of the polysilicon structure 304 is exposed to, for example, rapid thermal processing (RTP) so that the metal 602 reacts with the polysilicon structure 304 at the surface portion 506 to form a metal silicide, such as Figure 7 As shown. Therefore, a silicide region 702 is formed at the bottom of the opening 502 to at least partially (e.g., substantially) cover the polysilicon structure 304. The silicide region 702 can be formed to exhibit any desired height (e.g., vertical thickness), and the silicide region 702 can span at least the width of the opening 502 (e.g., the entire width). In some embodiments, the silicide region 702 can span the entire width of the polysilicon structure 304. For example, the silicide region 702 can extend across the entire width of the opening 502 and, for example, below the first metal nitride sidewall liner 504 and below the dielectric liner 306. The vertical surface of the first metal nitride sidewall liner 504 may substantially lack the metal silicide of the silicide region 702.

[0075] Depending on the composition of metal 602, the metal silicide of silicide region 702 may include one or more of the following or be formed by one or more of the following: cobalt silicide (CoSi) x Titanium silicide (TiSi) x ), Tungsten silicide (WSi) x ), tantalum silicide (TaSi) x ), molybdenum silicide (MoSi) x Platinum silicide (PtSi) x Ruthenium silicide (RuSi) x ) and nickel silicide (NiSi) x ).

[0076] The portion of metal silicide in metal 602 that has not been converted into silicide region 702 (hereinafter referred to as the "residual portion" of metal 602) is then removed from, for example, the upper surface of a structure, including removal from the upper surfaces of the first metal nitride sidewall liner 504, dielectric liner 306, dielectric structure 308, and other dielectric structures 310, such as... Figure 8 As shown.

[0077] Residual portion of metal 602 ( Figure 6 It can be removed, for example, by etching (e.g., wet stripping) followed by a cleaning action (e.g., with DHF).

[0078] Because the first metal nitride sidewall liner 504 is in place during this residue removal process, it protects adjacent dielectric materials (e.g., dielectric liner 306, dielectric structure 308, and other dielectric structures 310) from removal; therefore, as per the above regarding Figure 1B The hypothetical embodiments discussed are different, thus avoiding unintentional contact expansion once again.

[0079] refer to Figure 9 Then, a second metal nitride liner 902 is formed (e.g., conformally formed) on all exposed surfaces, including the first metal nitride sidewall liner 504 and the silicide region 702. Thus, the second metal nitride liner opening 904 is completely defined by the second metal nitride liner 902.

[0080] Because when forming the first metal nitride sidewall liner 504, the first metal nitride liner 402 ( Figure 4 A portion of the ) is removed earlier, so the second metal nitride liner 902 is formed to be in direct contact with the silicide region 702.

[0081] The second metal nitride liner 902 can be formed by CVD of, for example, a metal (e.g., Ti) along with nitriding, to conformally form the metal nitride material as the second metal nitride liner 902. The second metal nitride liner 902 adjacent to the silicide region 702 can also eliminate oxygen. That is, prior to the formation of the second metal nitride liner 902, native oxygen may have already formed on the surface of the silicide region 702 exposed in the opening 502. Figure 5In some embodiments, a cleaning process may be performed to remove native oxygen before forming the second metal nitride liner 902. Even so, residual oxygen may still be present, and in such cases, the metal forming the second metal nitride liner 902 on a surface containing residual oxygen can eliminate (e.g., absorb) the residual oxygen. Therefore, a thin metal oxide having the aforementioned second metal nitride liner 902 may be formed along the upper surface of the silicide region 702. The presence of the metal oxide can prevent the nitriding of the metal silicide of the silicide region 702 during the nitriding of the metal of the second metal nitride liner 902 (for forming its metal nitride material). In such embodiments, however, a small amount of metal oxide between the metal silicide (the metal silicide of the silicide region 702) and the metal nitride (the metal nitride of the second metal nitride liner 902) can exhibit lower resistance compared to a structure comprising a broad insulating liner (e.g., an oxide film) on such silicide regions 702.

[0082] refer to Figure 10 Then, a conductive material 1002 is formed to fill the space. Figure 9 The second metal nitride liner opening 904 forms a microelectronic device structure 1000 having a conductive contact structure 1004. Although not shown, in subsequent processes, the microelectronic device structure 1000 may undergo, for example, planarization or other material removal operations to electrically isolate the conductive contact structure 1004 from adjacent conductive contact structures that may have been simultaneously formed by the conductive material 1002 (e.g., another structure of the conductive contact structure 1004).

[0083] The conductive material 1002 may be formed of or contain at least one conductive material, such as one or more of metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. As a non-limiting example, the conductive material 10002 may be formed of or contain one or more of the following: tungsten (W), tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Cobalt (Co), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x Titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN)x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z ) and conductive doped silicon. In some embodiments, the conductive material 1002 is formed of tungsten (W) and contains tungsten (W).

[0084] In embodiments where the conductive material 1002 is formed of tungsten (W), the presence of the first metal nitride sidewall liner 504 and the second metal nitride liner 902 also protects adjacent dielectric materials (e.g., dielectric liner 306, etc.) from damage during the use of film-forming gases such as tungsten hexafluoride (WF6).

[0085] The second metal nitride liner 902 located between the conductive material 1002 and the silicide region 702 (e.g., directly between the two) can act as a barrier material, thereby preventing atoms of the conductive material 1002 from traversing the silicide region 702.

[0086] Due to the earlier removal of the first metal nitride liner 402 ( Figure 4 The lower portion of the material forms a first metal nitride sidewall liner 504, thus there is only one metal nitride liner between the conductive material 1002 and the silicide region 702, namely the second metal nitride liner 902. Conversely, the above regarding... Figures 1A to 1C The described hypothetical embodiment includes a plurality of metal nitride liners (e.g., a first metal nitride liner 108 and a second metal nitride liner 110) between the silicide region 106 and the conductive contact structure 102. Therefore, the conductive material 1002 and the silicide region 702 can be compared according to... Figures 1A to 1C The hypothetical embodiments are closer to each other, which allows for greater electrical connectivity between the conductive material 1002 and the silicide region 702. Only one metal nitride liner (e.g., a second metal nitride liner 902) is permitted between the conductive material 1002 and the silicide region 702, at least because the metal nitride liner can also act as a barrier material.

[0087] Accordingly, a method for forming a microelectronic device is disclosed. The method includes forming an opening through at least one dielectric material to expose the surface of a polysilicon structure. A first metal nitride liner is formed in the opening. After forming the first metal nitride liner, the surface of the polysilicon structure is cleaned and dried. A metal silicide region is formed on the surface of the polysilicon structure. A second metal nitride liner is formed on the first metal nitride liner and the metal silicide region. The remaining portion of the opening covering the second metal nitride liner is filled with a conductive material to form a conductive contact structure.

[0088] Furthermore, a microelectronic device is disclosed, comprising at least one conductive contact structure on a metal silicide material. A first metal nitride liner is located on the vertical sidewall of the at least one conductive contact structure. A second metal nitride liner is located between the conductive contact structure and the metal silicide material.

[0089] The method disclosed herein can also be used to form other conductive contact structures, such as peripheral contact structures, such as... Figures 11 to 18 As shown.

[0090] refer to Figure 11 A contact opening 1102 is formed (e.g., etched) using at least one dielectric material, such as a dielectric filling structure 1104 (e.g., formed or containing SiO2), an upper dielectric structure 1106 (e.g., formed or containing SiN), another dielectric structure 1108 (e.g., formed or containing SiO2), and another dielectric structure 1110 (e.g., formed or containing SiN), to expose the surface of the polysilicon structure 1112. The contact opening 1102 can be formed on either side of the already formed structure including a conductive region, such as the gate 1114. The dielectric filling structure 1104, the other dielectric structure 1108, and the other dielectric structure 1110 can be located between the contact opening 1102 and the gate 1114.

[0091] In the case where the surface exposed to the contact opening 1102 has not yet been treated (e.g., cleaned, dried), a first metal nitride liner 1204 is formed at least on the surface defining the contact opening 1102 (e.g., in accordance with the above regarding the formation of Figure 4 The first metal nitride liner 402 is formed in the same manner as the first metal nitride liner 402, thereby forming the first liner contact opening 1202. The first metal nitride liner 1204 is in direct physical contact with the polysilicon structure 1112, the dielectric filling structure 1104, the upper dielectric structure 1106, the other dielectric structures 1108, and the additional dielectric structure 1110.

[0092] Remove a portion of the first metal nitride liner 1204 from each of the first liner contact openings 1202 (e.g., in accordance with the above regarding the formation). Figure 5 The first metal nitride sidewall liner 504 is formed in the same way as the first metal nitride sidewall liner 504. Figure 13 The openings 1302 shown have a first metal nitride sidewall liner 1304 along the side of each of the openings 1302. Thus, the surface portion 1306 of the polysilicon structure 1112 is exposed within each of the openings 1302.

[0093] With the first metal nitride sidewall liner 1304 in place, adjacent dielectric materials (e.g., adjacent dielectric materials of dielectric fill structure 1104, upper dielectric structure 1106, other dielectric structures 1108, and additional dielectric structures 1110) are covered and not exposed in the opening 1302. Cleaning and drying are performed (e.g., in accordance with the above-mentioned...) Figure 5 (In the same manner as described above), during this period, the first metal nitride sidewall liner 1304 prevents adjacent dielectric material from being removed, and thus prevents, as described above, from being removed. Figure 2B The same unintentional contact expansion discussed.

[0094] With regard to the above discussion Figure 2C The hypothetical implementation is different, including Figure 13 The method may not include an additional dielectric liner (e.g., a SiN liner) between the first metal nitride sidewall liner 1304 and the dielectric filling structure 1104. Therefore, as described above regarding... Figure 2C The discussion avoided the risk of reduced contact.

[0095] After cleaning and drying, as Figure 14 The examples shown, for instance, are related to the above regarding Figure 6 Metal 602 for metal silicides is formed in the same manner as described.

[0096] The metal 602 in contact with the polycrystalline silicon structure 1112 is, for example, in accordance with the above-mentioned Figure 7 The same method described is used to convert the material into metal silicide, thereby forming a silicide region 1502 in each of the openings 1302, as... Figure 15 As shown. The silicide region 1502 may have at least the width of each of the openings 1302 (e.g., the entire width). The metal silicide of the silicide region 1502 may also extend below the first metal nitride sidewall liner 1304.

[0097] Then, in relation to the above about Figure 8 The remaining portion of metal 602 on the upper surface of, for example, the upper dielectric structure 1106 and the first metal nitride sidewall liner 1304 is removed in the same manner as described above. Figure 2B Unlike the hypothetical embodiment described, during the residue removal operation, with the first metal nitride sidewall liner 1304 in place, adjacent dielectric materials (e.g., dielectric fill structure 1104, upper dielectric structure 1106, other dielectric structures 1108, and additional dielectric structures 1110) are protected from removal, thereby again avoiding unintentional contact expansion.

[0098] exist Figure 16The opening 1302 of the structure and optionally other exposed surfaces are formed as follows Figure 17 The second metal nitride liner 1702 is shown. The second metal nitride liner 1702 can, for example, be configured with the above-mentioned... Figure 9 The second metal nitride liner 902 is formed in the same manner as described above. The second metal nitride liner 1702 is in direct contact with the silicide region 1502, and the second metal nitride liner opening 1704 is completely defined by the second metal nitride liner 1702.

[0099] refer to Figure 18 Then, a conductive material 1002 is formed to fill the space. Figure 17 Each of the second metal nitride liner openings 1704 and, for example, with the above regarding Figure 10 The conductive contact structure 1802 (e.g., a peripheral contact structure) is formed in the same manner as described. Although not shown, subsequent processing may include planarization to electrically isolate each of the conductive contact structures 1802 from one another.

[0100] The second metal nitride liner 1702 located between the silicide region 1502 and the conductive material 1002 of the conductive contact structure 1802 (e.g., directly between the two) can act as a barrier material, thereby preventing atoms of the conductive material 1002 from traversing the silicide region 1502.

[0101] Figure 18 The microelectronic device structure 1800 includes only one metal nitride liner (e.g., a second metal nitride liner 1702) disposed between the silicide region 1502 and the conductive contact structure 1802.

[0102] Accordingly, a method for forming a microelectronic device is disclosed. The method includes forming a contact opening through at least one dielectric material to expose a surface portion of a polysilicon structure. A first metal nitride liner is formed in the contact opening without cleaning and drying the surface portion of the polysilicon structure. A portion of the first metal nitride liner is removed to re-expose the surface portion of the polysilicon structure. The surface portion of the polysilicon structure is cleaned and dried, and a silicide region is formed on the surface portion of the polysilicon structure. A second metal nitride liner is formed on the silicide region, and a conductive contact structure is formed on the second metal nitride liner.

[0103] A microelectronic device is also disclosed, comprising a conductive contact structure laterally adjacent to an electrically insulating conductive region. A silicide region is located below the conductive contact structure. A single metal nitride liner is located directly between the silicide region and the conductive contact structure.

[0104] Figure 19 A functional block diagram of a microelectronic device in the form of a memory device 1900 (e.g., a DRAM device) according to embodiments of the present disclosure is shown. The memory device 1900 may include, for example, devices previously described herein (e.g., Figure 10 Microelectronic device structure 1000, Figure 18 An embodiment of one of the microelectronic device structures (1800). For example... Figure 19 As shown, the memory device 1900 may include a memory cell 1902, a bit line 1904, a word line 1906, a row decoder 1908, a column decoder 1910, a memory controller 1912, a read device 1914, and an input / output device 1916.

[0105] The memory cell 1902 of the memory device 1900 is programmable to at least two different logic states (e.g., logic 0 and logic 1). The devices previously described herein (e.g., Figure 10 Microelectronic device structure 1000, Figure 18 A portion of the microelectronic device structure 1800 can form a portion of the memory cell 1902 of the memory device 1900. Each of the memory cells 1902 can individually contain a memory node structure and a transistor. The memory node structure stores charges representing programmable logic states of the memory cell 1902 (e.g., a charged capacitor can represent a first logic state, such as logic 1; and an uncharged capacitor can represent a second logic state, such as logic 0). When a minimum threshold voltage is applied to the semiconductor channel of the transistor, the transistor allows access to the capacitor to operate on the memory node structure (e.g., read, write, rewrite).

[0106] Digital line 1904 is connected to the memory node structure of memory cell 1902 via a transistor in memory cell 1902. Word line 1906 extends perpendicularly to digital line 1904 and is connected to the gate of the transistor in memory cell 1902 (e.g., Figure 18 (Gate 1114). Memory cell 1902 can be operated by activating the appropriate digit line 1904 and word line 1906. Activating one of the digit lines 1904 or one of the word lines 1906 may involve applying a voltage potential to one of the digit lines 1904 or one of the word lines 1906. Each column of memory cell 1902 can be individually connected to one of the digit lines 1904, and each row of memory cell 1902 can be individually connected to one of the word lines 1906. Individual memory cells 1902 can be addressed and accessed via the intersections (e.g., intersection points) of the digit lines 1904 and word lines 1906.

[0107] The memory controller 1912 can control the operation of the memory cell 1902 through various components, including a row decoder 1908, a column decoder 1910, and a read device 1914. The memory controller 1912 can generate row address signals directed to the row decoder 1908 to activate predetermined word lines 1906 (e.g., by applying a voltage potential thereto), and can generate column address signals directed to the column decoder 1910 to activate predetermined bit lines 1904 (e.g., by applying a voltage potential thereto). The memory controller 1912 can also generate and control various voltage potentials employed during the operation of the memory device 1900. Typically, the amplitude, shape, and / or duration of the applied voltage can be adjusted (e.g., changed), and these amplitudes, shapes, and / or durations can be different for various operations of the memory device 1900.

[0108] During the use and operation of the memory device 1900, one of the memory cells 1902 can be read (e.g., read out) by the readout device 1914 after being accessed. The readout device 1914 can compare a signal (e.g., voltage) of an appropriate bit line in the bit lines 1904 with a reference signal to determine the logic state of one of the memory cells 1902. For example, if the voltage of one of the bit lines 1904 is higher than the reference voltage, the readout device 1914 can determine that the stored logic state of the memory cell 1902 is logic 1, and vice versa. The readout device 1914 may include transistors and amplifiers to detect and amplify differences in signals (commonly referred to in the art as "latch"). The detected logic state of the memory cell in the memory cell 1902 can be output to the input / output device 1916 via the column decoder 1910. Alternatively, a memory cell in memory cell 1902 can be configured (e.g., written to) by activating an appropriate word line of word line 1906 and an appropriate digital line of digital line 1904 in a similar manner. One of the memory cells 1902 can be configured (e.g., a logic value can be stored in one of the memory cells 1902) by controlling one of the digital lines 1904 while activating word line 1906. The column decoder 1910 can accept data from input / output device 1916 to write to memory cell 1902. Furthermore, the memory cells in memory cell 1902 can be refreshed (e.g., charged) by reading each of the memory cells in memory cell 1902. A read operation places the contents of the memory cell in memory cell 1902 onto an appropriate digital line of digital line 1904, which is then pulled up to full level by read device 1914 (e.g., fully charged or fully discharged). When one of the word lines 1906 associated with the memory cell in memory cell 1902 is deactivated, all memory cells 1902 in the row associated with one of the word lines 1906 are restored to full charge or full discharge.

[0109] The device according to embodiments of this disclosure (e.g., Figure 10 Microelectronic device structure 1000, Figure 18 Microelectronic device structure 1800) and microelectronic devices (e.g., Figure 19 The memory device 1900 is used in embodiments of the electronic system disclosed herein. For example, Figure 20This is a block diagram of an illustrative electronic system 2000 according to embodiments of the present disclosure. The electronic system 2000 may include one or more of the following: for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, for example, or Tablet computers, e-book readers, and navigation devices. Electronic system 2000 includes at least one memory device 2002. Memory device 2002 may include, for example, microelectronic devices incorporated herein by reference (e.g.,...). Figure 19 Devices in the memory device 1900 (e.g., the microelectronic device structure 1000 of FIG1 and / or) Figure 18 The electronic system 2000 may further include at least one electronic signal processor device 2004 (generally referred to as a “microprocessor”). The electronic signal processor device 2004 may optionally include devices incorporated into a semiconductor device (e.g., memory device 1900) previously described herein. Figure 10 Microelectronic device structure 1000 and / or Figure 18 This is an embodiment of a microelectronic device architecture 1800, such an arrangement is generally referred to as a "System-on-a-Chip" (SoC). The electronic system 2000 may further include one or more input devices 2006 for inputting information to the electronic system 2000 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 2000 may further include one or more output devices 2008 for outputting information to the user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 2006 and output device 2008 may include a single touchscreen device, which can be used both to input information to the electronic system 2000 and to output visual information to the user. The input device 2006 and output device 2008 may be in electrical communication with one or more of the memory device 2002 and the electronic signal processor device 2004.

[0110] Accordingly, an electronic system is disclosed, comprising at least one memory device, at least one electronic signal processor, at least one input device, and at least one output device. The at least one memory device includes at least one digit line and at least one word line operatively communicating with at least one memory cell. The at least one memory cell includes at least one conductive contact structure within a metal nitride liner. The metal nitride liner includes a first metal nitride liner and a second metal nitride liner. The at least one memory cell also includes a metal silicide material on a polysilicon structure. The second metal nitride liner is directly disposed between the metal silicide material and the at least one conductive contact structure. The at least one electronic signal processor is operatively connected to the at least one memory device. The at least one input device is operatively communicating with the at least one electronic signal processor. The at least one output device is operatively communicating with the at least one input device.

[0111] Compared with conventional methods, conventional equipment, conventional devices and conventional electronic systems, the methods, equipment (e.g., structures), devices (e.g., microelectronic devices, such as memory devices, such as DRAM devices) and electronic systems of this disclosure can promote one or more of the following improvements: performance, efficiency, reliability and durability.

[0112] Non-limiting example embodiments may include the following, either individually or in combination:

[0113] Example 1: A method of forming a microelectronic device, the method comprising: forming an opening through at least one dielectric material to expose a surface of a polysilicon structure; forming a first metal nitride liner in the opening; cleaning and drying the surface of the polysilicon structure after forming the first metal nitride liner; forming a metal silicide region on the surface of the polysilicon structure; forming a second metal nitride liner on the first metal nitride liner and on the metal silicide region; and filling the remaining portion of the opening covering the second metal nitride liner with a conductive material to form a conductive contact structure.

[0114] Example 2: The method according to Example 1, wherein no cleaning or drying is performed between forming the opening and forming the first metal nitride liner.

[0115] Example 3: The method according to any one of Examples 1 and 2, wherein forming the first metal nitride liner includes forming a metal nitride material on the vertical sidewall of the at least one dielectric material.

[0116] Example 4: According to the method of Example 3, the metal nitride material formed on the vertical sidewall of the at least one dielectric material comprises: forming the metal nitride material on the vertical sidewall of the at least one dielectric material and on the surface of the polysilicon structure; and removing a portion of the metal nitride material adjacent to the surface of the polysilicon structure to re-expose the surface of the polysilicon structure within the opening.

[0117] Example 5: The method according to any one of Examples 1 to 4, wherein forming the second metal nitride liner includes forming a metal nitride material by chemical vapor deposition and nitriding.

[0118] Example 6: The method according to any one of Examples 1 to 5, wherein during cleaning and drying of the surface of the polycrystalline silicon structure, the first metal nitride liner is disposed between the opening and the at least one dielectric material.

[0119] Example 7: The method according to any one of Examples 1 to 6, wherein the width of the opening remains substantially constant during cleaning and drying of the surface of the polycrystalline silicon structure.

[0120] Example 8: The method according to any one of Examples 1 to 7, wherein forming the metal silicide region comprises: sputtering metal onto the surface of the polysilicon structure; and converting the metal into a metal silicide to form the metal silicide region on the surface of the polysilicon structure.

[0121] Example 9: The method according to Example 8 further includes removing residual portions of the metal without widening the opening after converting the metal into the metal silicide.

[0122] Example 10: A microelectronic device comprising: at least one conductive contact structure on a metal silicide material; a first metal nitride liner on a vertical sidewall of the at least one conductive contact structure; and a second metal nitride liner between the conductive contact structure and the metal silicide material.

[0123] Example 11: The microelectronic device according to Example 10 further includes at least one dielectric material adjacent to the first metal nitride liner.

[0124] Example 12: A microelectronic device according to any one of Examples 10 and 11, wherein the first metal nitride liner does not extend beneath the at least one conductive contact structure.

[0125] Example 13: The microelectronic device according to any one of Examples 10 to 12, wherein: the metal silicide material comprises cobalt silicide; the first metal nitride liner and the second metal nitride liner comprise titanium nitride; and the conductive contact structure comprises tungsten.

[0126] Example 14: A microelectronic device according to any one of Examples 10 to 13, wherein the second metal nitride liner extends from and between the conductive contact structure and the metal silicide region.

[0127] Example 15: A microelectronic device according to any one of Examples 10 to 14, wherein the microelectronic device includes a dynamic random access memory device.

[0128] Example 16: A method of forming a microelectronic device, the method comprising: forming a contact opening through at least one dielectric material to expose a surface portion of a polysilicon structure; forming a first metal nitride liner in the contact opening without cleaning and drying the surface portion of the polysilicon structure; removing a portion of the first metal nitride liner to re-expose the surface portion of the polysilicon structure; cleaning and drying the surface portion of the polysilicon structure; forming a silicide region on the surface portion of the polysilicon structure; forming a second metal nitride liner on the silicide region; and forming a conductive contact structure on the second metal nitride liner.

[0129] Example 17: According to the method of Example 16, wherein: forming the first metal nitride liner includes forming the first metal nitride liner comprising titanium nitride; and forming the second metal nitride liner includes forming the second metal nitride liner comprising additional titanium nitride.

[0130] Example 18: The method according to any one of Examples 16 and 17 further includes forming the at least one dielectric material comprising at least one silicon dioxide region and at least one other silicon nitride region.

[0131] Example 19: The method according to any one of Examples 16 to 18, wherein forming the silicide region on the surface portion of the polysilicon structure includes forming the silicide region spanning the entire width of the surface portion of the polysilicon structure.

[0132] Example 20: The method according to any one of Examples 16 to 19, wherein forming the silicide region on the surface portion of the polycrystalline silicon structure includes forming the silicide region extending beneath the first metal nitride liner.

[0133] Example 21: A microelectronic device comprising: a conductive contact structure laterally adjacent to an electrically insulating conductive region; a silicide region beneath the conductive contact structure; and a single metal nitride liner directly located between the silicide region and the conductive contact structure.

[0134] Example 22: The microelectronic device according to Example 21 further includes an additional metal nitride liner that laterally surrounds the conductive contact structure.

[0135] Example 23: The microelectronic device according to Example 22, wherein the silicide region extends beneath the additional metal nitride liner.

[0136] Example 24: An electronic system comprising: at least one memory device including at least one digital line and at least one word line operatively communicating with at least one memory cell, the at least one memory cell including: at least one conductive contact structure within a metal nitride liner, the metal nitride liner including a first metal nitride liner and a second metal nitride liner; and a metal silicide material on a polysilicon structure, the second metal nitride liner being directly disposed between the metal silicide material and the at least one conductive contact structure; at least one electronic signal processor operatively connected to the at least one memory device; at least one input device operatively communicating with the at least one electronic signal processor; and at least one output device operatively communicating with the at least one input device.

[0137] Example 25: The electronic system according to Example 24, wherein the at least one memory device includes at least one DRAM device.

[0138] While this disclosure is susceptible to various modifications and alternatives, specific embodiments have been illustrated by way of example in the accompanying drawings and described in detail herein. However, this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of this disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A method for forming a microelectronic device, the method comprising: An opening is formed through at least one dielectric material to expose the surface of the polycrystalline silicon structure; A first metal nitride liner is formed in the opening; After forming the first metal nitride liner, the surface of the polycrystalline silicon structure is cleaned and dried; A metal silicide region is formed on the surface of the polycrystalline silicon structure; A second metal nitride liner is formed on the first metal nitride liner and on the metal silicide region; as well as The remaining portion of the opening covering the second metal nitride liner is filled with a conductive material to form a conductive contact structure, wherein the first metal nitride liner does not extend below the conductive contact structure.

2. The method of claim 1, wherein no cleaning or drying is performed between forming the opening and forming the first metal nitride liner.

3. The method according to any one of claims 1 and 2, wherein forming the first metal nitride liner comprises forming a metal nitride material on the vertical sidewall of the at least one dielectric material.

4. The method of claim 3, wherein forming the metal nitride material on the vertical sidewall of the at least one dielectric material comprises: The metal nitride material is formed on the vertical sidewall of the at least one dielectric material and on the surface of the polycrystalline silicon structure; as well as A portion of the metal nitride material adjacent to the surface of the polycrystalline silicon structure is removed to re-expose the surface of the polycrystalline silicon structure within the opening.

5. The method according to any one of claims 1 and 2, wherein forming the second metal nitride liner comprises forming the metal nitride material by chemical vapor deposition and nitriding.

6. The method according to any one of claims 1 and 2, wherein during cleaning and drying of the surface of the polycrystalline silicon structure, the first metal nitride liner is disposed between the opening and the at least one dielectric material.

7. The method according to any one of claims 1 and 2, wherein the width of the opening remains substantially constant during cleaning and drying of the surface of the polycrystalline silicon structure.

8. The method according to any one of claims 1 and 2, wherein forming the metal silicide region comprises: Metal is sputtered onto the surface of the polycrystalline silicon structure; as well as The metal is converted into a metal silicide to form the metal silicide region on the surface of the polycrystalline silicon structure.

9. The method of claim 8, further comprising: After the metal is converted into the metal silicide, any remaining portion of the metal is removed without widening the opening.

10. A microelectronic device comprising: At least one conductive contact structure on a metal silicide material, the at least one conductive contact structure extending through at least one dielectric material; A first metal nitride liner on the vertical sidewall of the at least one conductive contact structure, wherein the metal silicide material extends below the first metal nitride liner, the first metal nitride liner is directly adjacent to the at least one dielectric material, and the first metal nitride liner does not extend below the at least one conductive contact structure. as well as A second metal nitride liner is located between the at least one conductive contact structure and the metal silicide material.

11. The microelectronic device according to claim 10, wherein: The metal silicide material includes cobalt silicide; The first metal nitride liner and the second metal nitride liner comprise titanium nitride; and The at least one conductive contact structure includes tungsten.

12. The microelectronic device of claim 10, wherein the second metal nitride liner extends from and between the at least one conductive contact structure and the metal silicide material.

13. The microelectronic device of claim 10, wherein the microelectronic device includes a dynamic random access memory device.

14. The microelectronic device of claim 10, wherein the upper longitudinal end of the first metal nitride liner is directly laterally located between the second metal nitride liner and the at least one dielectric material.

15. The microelectronic device of claim 10, wherein the lower longitudinal end of the first metal nitride liner is directly laterally located between the second metal nitride liner and the at least one dielectric material.

16. The microelectronic device of claim 10, wherein the at least one dielectric material is in direct contact with the metal silicide material.

17. A method of forming a microelectronic device, the method comprising: Forming contact openings through at least one dielectric material to expose surface portions of the polycrystalline silicon structure; A first metal nitride liner is formed in the contact opening without cleaning or drying the surface portion of the polycrystalline silicon structure; A portion of the first metal nitride liner is removed to re-expose the surface portion of the polycrystalline silicon structure; Clean and dry the surface portion of the polycrystalline silicon structure; A silicide region is formed on the surface portion of the polycrystalline silicon structure; A second metal nitride liner is formed on the silicide region; as well as A conductive contact structure is formed on the second metal nitride liner, wherein the first metal nitride liner does not extend below the conductive contact structure.

18. The method of claim 17, wherein: Forming the first metal nitride liner includes forming the first metal nitride liner comprising titanium nitride; and Forming the second metal nitride liner includes forming a second metal nitride liner comprising additional titanium nitride.

19. The method according to any one of claims 17 and 18, further comprising: The at least one dielectric material comprising at least one silicon dioxide region and at least one other silicon nitride region is formed.

20. The method of any one of claims 17 and 18, wherein forming the silicide region on the surface portion of the polysilicon structure comprises forming the silicide region spanning the entire width of the surface portion of the polysilicon structure.

21. The method of any one of claims 17 and 18, wherein forming the silicide region on the surface portion of the polycrystalline silicon structure comprises forming the silicide region extending beneath the first metal nitride liner.

22. A microelectronic device comprising: A conductive contact structure laterally adjacent to an electrically insulating conductive region, the conductive contact structure extending through at least one dielectric material; The silicide region beneath the conductive contact structure; A single metal nitride liner directly located between the silicide region and the conductive contact structure; and An additional metal nitride liner laterally surrounds and is laterally adjacent to the single metal nitride liner, the additional metal nitride liner being in direct contact with the at least one dielectric material, and the additional metal nitride liner not extending beneath the conductive contact structure. The silicide region extends beneath the additional metal nitride liner.

23. An electronic system comprising: At least one memory device, the at least one memory device including at least one bit line and at least one word line operatively communicatively with at least one memory cell, the at least one memory cell comprising: At least one conductive contact structure within a metal nitride liner, the metal nitride liner comprising a first metal nitride liner and a second metal nitride liner; and A metal silicide material on a polycrystalline silicon structure, wherein the second metal nitride liner is directly disposed between the metal silicide material and the at least one conductive contact structure. The first metal nitride liner does not extend beneath the at least one conductive contact structure; At least one electronic signal processor, said at least one electronic signal processor being operatively connected to said at least one memory device; At least one input device, the at least one input device being operatively communicative with the at least one electronic signal processor; and At least one output device, the at least one output device being operatively communicative with the at least one input device.

24. The electronic system of claim 23, wherein the at least one memory device comprises at least one DRAM device.

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