semiconductor packages

Abstract

A semiconductor package is provided. The semiconductor package includes: a semiconductor chip; a redistribution structure located below the semiconductor chip; a first insulating layer located below the redistribution structure; a pad located below the first insulating layer and in contact with the redistribution structure; and a bump located below the pad, wherein a maximum horizontal length of an upper portion of the pad is greater than a maximum horizontal length of a lower portion of the pad.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0127858, filed on October 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a redistribution structure. Background Art

[0003] As electronic devices with smaller size and higher performance are required, it is beneficial to reduce the size of semiconductor chips in electronic devices. In order to reduce the size of semiconductor chips, a redistribution structure (RDS) can be used instead of a conventional printed circuit board (PCB) to connect the semiconductor chips to the outside of the semiconductor package. Summary of the Invention

[0004] The inventive concept is directed to providing a semiconductor package having a lower failure rate and improved stability and a method of manufacturing the same.

[0005] According to one aspect of the inventive concept, a semiconductor package includes: a semiconductor chip; a redistribution structure located below the semiconductor chip; a first insulating layer located below the redistribution structure; a pad located below the first insulating layer, the pad contacting the redistribution structure; and a bump located below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

[0006] According to another aspect of the inventive concept, a semiconductor package includes: a bump; a pad located on the bump; a first insulating layer spaced apart from a lower portion of the pad and in contact with a side surface and an upper surface of an upper portion of the pad; a first conductive pattern including a first line portion and a first via portion, the first line portion being located on the first insulating layer, the first via portion protruding downward from the first line portion to contact the pad; a second insulating layer located on the first insulating layer and the first conductive pattern; a second conductive pattern including a second line portion and a second via portion, the second line portion being located on the second insulating layer, the second via portion protruding downward from the second line portion to contact the first line portion of the first conductive pattern; and a semiconductor chip electrically connected to the second conductive pattern, wherein a horizontal maximum length of the upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

[0007] According to another aspect of the inventive concept, a semiconductor package includes: a package substrate; a first bump located below the package substrate; a second bump located on the package substrate; an interposer located on the second bump; and a first semiconductor chip located on the interposer, wherein the interposer includes: a pad located on the second bump; a first insulating layer located on the pad; and a redistribution structure located on the first insulating layer, the redistribution structure being connected between the pad and the first semiconductor chip, the upper portion of the pad being located in a first opening in the first insulating layer, and the horizontal maximum length of the upper portion of the pad being greater than the horizontal maximum length of the lower portion of the pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0010] Figure 2A and Figure 2B are a cross-sectional view and a bottom view, respectively, of a pad included in a semiconductor package according to an embodiment of the inventive concept;

[0011] Figure 3A and Figure 3B are a cross-sectional view and a bottom view, respectively, of a conductive pattern included in a redistribution structure included in a semiconductor package according to an embodiment of the inventive concept;

[0012] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0013] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0014] Figure 6 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept; and

[0015] Figures 7A to 7Y is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0016] In this specification, ordinal expressions (e.g., first, second, third, etc.) are used for convenience to distinguish elements with the same name from each other and should not be interpreted as representing an absolute order. Thus, for example, a component referred to as a fourth insulating layer in a specific embodiment may be referred to as a second insulating layer in a claim. Furthermore, for example, a component referred to as a second insulating layer in a first set of claims may be referred to as a third insulating layer in a second set of claims. Furthermore, for example, a component referred to as a fourth insulating layer in a paragraph describing the structure of a semiconductor package according to the inventive concept with reference to the accompanying drawings may be referred to as a first insulating layer in a description of a method for manufacturing a semiconductor package according to the inventive concept with reference to other drawings.

[0017] For ease of description, spatial relative terms such as "below," "below," "below," "above," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figure. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, an element described as "below," "below," or "below" other elements or features will then be positioned as "above" the other elements or features. Therefore, the example terms "below" and "below" may encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or located at other orientations), and the spatial relative descriptors used herein interpreted accordingly.

[0018] In this specification, when the term "approximately" or "substantially" is used in conjunction with a numerical value, it means that the relevant numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it means that the accuracy of the geometric shape is not required, but the degree of freedom of the shape is within the disclosed range. In addition, regardless of whether a numerical value or shape is modified as "approximately" or "substantially", it will be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0019] Figure 1 is a cross-sectional view of a semiconductor package 100 according to an embodiment of the inventive concept. Figure 2A and Figure 2B 1 and 2 are a cross-sectional view and a bottom view, respectively, of a pad 120 included in a semiconductor package 100 according to an embodiment of the inventive concept. Figure 3A and Figure 3B 1 and 2 are respectively a cross-sectional view and a bottom view of a conductive pattern 131 included in a redistribution structure RDS included in a semiconductor package 100 according to an embodiment of the inventive concept.

[0020] Reference Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B The semiconductor package 100 may include a semiconductor chip 150, a redistribution structure RDS located under the semiconductor chip 150, a first insulating layer IL2 located under the redistribution structure RDS, a pad 120 located under the first insulating layer IL2 and in contact with the redistribution structure RDS, and a first bump 180 located under the pad 120.

[0021] The semiconductor chip 150 may include a body 152 and a chip pad 151 located on the lower surface of the body 152. The body 152 may include a substrate. The body 152 may include an active surface ( Figure 1 the lower surface of the main body 152 in the embodiment) and the ineffective surface ( Figure 1 The body 152 may also include an integrated circuit on the active surface.

[0022] The substrate may include a semiconductor material, for example, a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or a combination thereof. The Group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or a combination thereof. The Group III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), gallium indium arsenide (InGaAs), or a combination thereof. The Group II-VI semiconductor material may include, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof.

[0023] The integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. The memory circuit may include, for example, a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a flash memory circuit, an electrically erasable programmable read-only memory (EEPROM) circuit, a phase change random access memory (PRAM) circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (RRAM) circuit, or a combination thereof. The logic circuit may include, for example, a central processing unit (CPU) circuit, a graphics processing unit (GPU) circuit, a controller circuit, an application specific integrated circuit (ASIC) circuit, an application processor (AP) circuit, or a combination thereof.

[0024] The chip pad 151 of the semiconductor chip 150 can be used to electrically connect the semiconductor chip 150 to another component. The chip pad 151 can include a conductive material such as a metal (e.g., copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti)), a doped semiconductor material, a conductive organic material (e.g., a conductive polymer), a carbon-based material (e.g., carbon nanotubes and graphene), or a combination thereof.

[0025] In some embodiments, the semiconductor chip 150 may further include a passivation layer (not shown) covering the lower surface of the body 152 and exposing at least a portion of the chip pad 151. The passivation layer may physically and / or chemically protect the integrated circuit on the active surface of the body 152. For example, the passivation layer may include: an inorganic insulating material such as silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or a combination thereof; an organic insulating material such as an insulating polymer; or a combination of an inorganic insulating material and an organic insulating material.

[0026] The redistribution structure RDS may be electrically connected to the semiconductor chip 150. In some embodiments, the planar area of ​​the redistribution structure RDS (e.g., the area of ​​a cross section of the redistribution structure RDS perpendicular to the Z axis) may be larger than the planar area of ​​the semiconductor chip 150. For example, the semiconductor package 100 may be a fan-out wafer-level package. However, in another embodiment, Figure 1 Unlike the embodiment shown in FIG, the planar area of ​​the redistribution structure RDS may be the same as the planar area of ​​the semiconductor chip 150. For example, the semiconductor package 100 may be a fan-in wafer level package.

[0027] The redistribution structure RDS may include a plurality of insulating layers (e.g., a second insulating layer 141 and a third insulating layer 142) and a plurality of conductive patterns (e.g., a first conductive pattern 131, a second conductive pattern 132, and a third conductive pattern 133). For example, the redistribution structure RDS may include a second insulating layer 141, a third insulating layer 142 located on the second insulating layer 141, a first conductive pattern 131 located below the second insulating layer 141, a second conductive pattern 132 located between the second insulating layer 141 and the third insulating layer 142, and a third conductive pattern 133 located on the third insulating layer 142. Although Figure 1 It is shown that the redistribution structure RDS includes two insulating layers 141 and 142 and three conductive patterns 131 to 133 , but the number of insulating layers and conductive patterns included in the redistribution structure RDS may be less or more.

[0028] The first to third conductive patterns 131 to 133 of the redistribution structure RDS can electrically connect the pad 120 below the redistribution structure RDS to the chip pad 151 of the semiconductor chip 150. For example, the first conductive pattern 131 can contact the pad 120. The second insulating layer 141 can be located on the first conductive pattern 131 and include a second opening 141OP exposing a portion of the first conductive pattern 131. The second conductive pattern 132 can be provided on the second insulating layer 141 and can contact the first conductive pattern 131 via the second opening 141OP of the second insulating layer 141. The third insulating layer 142 can be located on the second conductive pattern 132 and include a third opening 142OP exposing a portion of the second conductive pattern 132. The third conductive pattern 133 can be located on the third insulating layer 142 and contact the second conductive pattern 132 via the third opening 142OP of the third insulating layer 142. The chip pad 151 of the semiconductor chip 150 can be connected to the third conductive pattern 133.

[0029] The first conductive pattern 131 may include a first line portion 131L and a first via portion 131V, the first via portion 131V protruding downward (along the -Z axis direction) from the first line portion 131L to contact the pad 120. In some embodiments, a thickness H5 of the first line portion 131L of the first conductive pattern 131 may be in a range from about 3 μm to about 5 μm. In some embodiments, a thickness H4 of the first via portion 131V of the first conductive pattern 131 may be in a range from about 3 μm to about 10 μm. In some embodiments, the first line portion 131L of the first conductive pattern 131 may have a square shape, and the first via portion 131V of the first conductive pattern 131 may have a cylindrical shape, but in another embodiment, the first line portion 131L and the first via portion 131V of the first conductive pattern 131 may have different shapes. For example, the first via portion 131V of the first conductive pattern 131 may have a square pillar shape, and the first line portion 131L of the first conductive pattern 131 may have a shape in which a plurality of polygons (eg, quadrilaterals) are connected to each other in a plan view.

[0030] Similarly, the second conductive pattern 132 may include a second line portion and a second via portion, the second line portion being located on the second insulating layer 141, the second via portion protruding downward (along the −Z-axis direction) from the second line portion and extending through the second opening 141OP of the second insulating layer 141 to contact the first line portion 131L of the first conductive pattern 131. Similarly, the third conductive pattern 133 may include a third line portion and a third via portion, the third line portion being located on the third insulating layer 142, the third via portion protruding downward (along the −Z-axis direction) from the third line portion and extending through the third opening 142OP of the third insulating layer 142 to contact the second line portion of the second conductive pattern 132.

[0031] In some embodiments, the first conductive pattern 131 may include a first barrier layer 131a, a first seed layer 131b, and a first filling layer 131c sequentially stacked on the first insulating layer IL2. Figure 1 Unlike the illustration in FIG, the boundary between the first barrier layer 131a and the first seed layer 131b and the boundary between the first seed layer 131b and the first filling layer 131c may be unclear in outline and / or not well defined. Similarly, the second conductive pattern 132 may include a second barrier layer 132a, a second seed layer 132b, and a second filling layer 132c sequentially stacked on the second insulating layer 141. Similarly, Figure 1 Unlike the illustration in FIG, the boundary between the second barrier layer 132a and the second seed layer 132b and the boundary between the second seed layer 132b and the second filling layer 132c may be unclear and / or not well defined in outline. Similarly, the third conductive pattern 133 may include a third barrier layer 133a, a third seed layer 133b, and a third filling layer 133c sequentially stacked on the third insulating layer 142. Similarly, Figure 1 Unlike the illustration in FIG. 1 , the boundary between the third barrier layer 133 a and the third seed layer 133 b and the boundary between the third seed layer 133 b and the third fill layer 133 c may be unclear and / or not well defined in outline.

[0032] For example, the second insulating layer 141 and the third insulating layer 142 of the redistribution structure RDS may include an inorganic insulating material such as silicon oxide, silicon nitride, PSG, BPSG, FSG, or a combination thereof; an organic insulating material such as an insulating polymer; or a combination of an inorganic insulating material and an organic insulating material. In some embodiments, the second insulating layer 141 and the third insulating layer 142 may be formed of a photosensitive dielectric (PID) material. When the second insulating layer 141 and the third insulating layer 142 are formed of the PID material, the second opening 141OP and the third opening 142OP can be easily formed in the second insulating layer 141 and the third insulating layer 142.

[0033] The first filling layers 131c to the third filling layers 133c of the first conductive patterns 131 to the third conductive patterns 133 of the redistribution structure RDS may include a conductive material, for example, a metal (e.g., copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti)), a doped semiconductor material, a conductive organic material (e.g., a conductive polymer), a carbon-based material (e.g., carbon nanotubes and graphene), or a combination thereof. The first seed layers 131b to the third seed layers 133b of the first conductive patterns 131 to the third conductive patterns 133 of the redistribution structure RDS may include the same material as the first filling layers 131c, the second filling layers 132c, and the third filling layers 133c. The first barrier layers 131a to the third barrier layers 133a of the first conductive patterns 131 to the third conductive patterns 133 of the redistribution structure RDS may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

[0034] In some embodiments, the semiconductor package 100 may further include a second bump 160 located between the chip pad 151 of the semiconductor chip 150 and the third conductive pattern 133 of the redistribution structure RDS. The second bump 160 may contact the chip pad 151 of the semiconductor chip 150 and the third conductive pattern 133 of the redistribution structure RDS, and may electrically connect the semiconductor chip 150 and the redistribution structure RDS. For example, the second bump 160 may include a metal such as tin (Sn), lead (Pb), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), antimony (Sb), or a combination thereof. In some embodiments, the second bump 160 may be formed by a solder ball. In some embodiments, the semiconductor package 100 may further include an underfill or chip adhesive layer (not shown) located between the semiconductor chip 150 and the redistribution structure RDS and surrounding the second bump 160.

[0035] The first insulating layer IL2 may be located below the second insulating layer 141 of the redistribution structure RDS. The first insulating layer IL2 may include a first opening OP2 exposing a portion of the pad 120. The first conductive pattern 131 of the redistribution structure RDS may include a first line portion 131L located on the first insulating layer IL2 and a first via portion 131V. The first line portion 131L is located on the first insulating layer IL2. The first via portion 131V protrudes downward (along the -Z axis direction) from the first line portion 131L and extends through the first opening OP2 of the first insulating layer IL2 to contact the pad 120. For example, the first insulating layer IL2 may include an inorganic insulating material such as silicon oxide, silicon nitride, PSG, BPSG, FSG, or a combination thereof; an organic insulating material such as an insulating polymer; or a combination of an inorganic insulating material and an organic insulating material. In some embodiments, the first insulating layer IL2 may be formed of a PID material.

[0036] The pad 120 may be an under-bump metallurgy (UBM). The pad 120 may include an upper portion (hereinafter referred to as an "upper portion") 120U in contact with the first conductive pattern 131 of the redistribution structure RDS and a lower portion (hereinafter referred to as a "lower portion") 120L in contact with the first bump 180. The horizontal maximum length D2 of the upper portion 120U of the pad 120 may be greater than the horizontal maximum length D1 of the lower portion 120L of the pad 120. In some embodiments, the horizontal maximum length D2 of the upper portion 120U of the pad 120 may be in a range from about 50 μm to about 300 μm. In some embodiments, the total thickness H3 of the pad 120 may be in a range from about 6 μm to about 20 μm, for example, between about 6 μm and about 13 μm. In some embodiments, the thickness H1 of the lower portion 120L of the pad 120 may be in a range from about 3 μm to about 10 μm. In some embodiments, the thickness H2 of the upper portion 120U of the pad 120 may be in a range from about 3 μm to about 10 μm.

[0037] In some embodiments, each of the upper portion 120U and the lower portion 120L of the pad 120 may have a cylindrical shape. In this case, the horizontal maximum length D1 and the horizontal maximum length D2 may correspond to the diameters of the lower portion 120L and the upper portion 120U, respectively. However, in another embodiment, the upper portion 120U and the lower portion 120L of the pad 120 may have another shape, such as a square pillar or an oval. In these cases, the horizontal maximum length D1 and the horizontal maximum length D2 may correspond to the long axis defined by the maximum distance between points on the edges of the lower portion 120L and the upper portion 120U, respectively. In some embodiments, the upper portion 120U and the lower portion 120L of the pad 120 may have the same central axis AX. That is, the center of the upper portion 120U and the center of the lower portion 120L of the pad 120 may be aligned with each other in the vertical direction (Z-axis direction).

[0038] In some embodiments, the pad 120 may include a barrier layer 120a in contact with the first bump 180, a filling layer 120c in contact with the first via portion 131V of the first conductive pattern 131 of the redistribution structure RDS, and a seed layer 120b located between the barrier layer 120a and the filling layer 120c. However, the boundary between the barrier layer 120a and the seed layer 120b and the boundary between the seed layer 120b and the filling layer 120c may be unclear and / or not well defined. For example, the filling layer 120c of the pad 120 may include a metal such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), or a combination thereof. The seed layer 120b of the pad 120 may include the same material as the filling layer 120c. The barrier layer 120a of the pad 120 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

[0039] The first insulating layer IL2 may be spaced apart from the lower portion 120L of the pad 120 and may be in contact with the side surfaces and the upper surface of the upper portion 120U of the pad 120. For example, the first insulating layer IL2 may cover the side surfaces and the upper surface of the upper portion 120U of the pad 120. In some embodiments, the lower surface of the first insulating layer IL2 and the lower surface of the upper portion 120U of the pad 120 may be coplanar.

[0040] In some embodiments, the semiconductor package 100 may further include a fourth insulating layer IL1 located below the first insulating layer IL2. The fourth insulating layer IL1 may include a fourth opening OP1. The upper portion 120U of the pad 120 may be located on the fourth insulating layer IL1, and the lower portion 120L of the pad 120 may be located in the fourth opening OP1 of the fourth insulating layer IL1. The lower surface of the fourth insulating layer IL1 and the lower surface of the lower portion 120L of the pad 120 may be coplanar, and the upper surface of the fourth insulating layer IL1 and the lower surface of the upper portion 120U of the pad 120 may be coplanar. In some embodiments, the fourth insulating layer IL1 may be in contact with the lower surface of the upper portion 120U of the pad 120 and the side surface of the lower portion 120L of the pad 120, and may be separated from the lower surface of the lower portion 120L of the pad 120 and the side and upper surfaces of the upper portion 120U of the pad 120 (e.g., not in contact with the lower surface of the lower portion 120L of the pad 120 and the side and upper surfaces of the upper portion 120U of the pad 120). For example, the fourth insulating layer IL1 may include an inorganic insulating material such as silicon oxide, silicon nitride, PSG, BPSG, FSG, or a combination thereof; an organic insulating material such as an insulating polymer; or a combination of an inorganic insulating material and an organic insulating material. In some embodiments, the fourth insulating layer IL1 may be formed of a PID material.

[0041] The first bump 180 may contact the lower surface of the lower portion 120L of the pad 120. In some embodiments, the first bump 180 may be spaced apart from the side surface of the lower portion 120L of the pad 120 and the lower surface of the upper portion 120U of the pad 120. In some embodiments, for example, the first bump 180 may include a metal such as tin (Sn), lead (Pb), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), antimony (Sb), or a combination thereof. The first bump 180 may be formed, for example, of a solder ball.

[0042] In some embodiments, the semiconductor package 100 may further include a protective insulating layer 110 located below the fourth insulating layer IL1. The protective insulating layer 110 may include an opening 110OP, and the first bump 180 may be located in the opening 110OP of the protective insulating layer 110. The protective insulating layer 110 may physically protect the interface between the first bump 180 and the pad 120, thereby improving the reliability of the semiconductor package 100. In some embodiments, for example, the protective insulating layer 110 may include an inorganic insulating material such as silicon oxide, silicon nitride, PSG, BPSG, FSG, or a combination thereof; an organic insulating material such as an insulating polymer; or a combination of an inorganic insulating material and an organic insulating material.

[0043] In some embodiments, the semiconductor package 100 may further include a molding member 170 located over the redistribution structure RDS and the semiconductor chip 150. The molding member 170 may physically and / or chemically protect the semiconductor chip 150 and the redistribution structure RDS. The molding member 170 may include a polymer material, such as a resin. For example, the molding member 170 may include a thermosetting resin, a thermoplastic resin, a UV curable resin, or a combination thereof. For example, the molding member 170 may include an epoxy resin, a silicone resin, or a combination thereof. For example, the molding member 170 may include an epoxy molding compound (EMC).

[0044] Figure 4 is a cross-sectional view of a semiconductor package 100 a according to an embodiment of the inventive concept.

[0045] Will Figure 1 and Figure 4 Compare with each other, Figure 1 The semiconductor package 100 is different, Figure 4 The semiconductor package 100a may not include the protective insulating layer 110. Therefore, the lower surface of the fourth insulating layer IL1 may be exposed to the outside of the semiconductor package 100a.

[0046] Figure 5 is a cross-sectional view of a semiconductor package 100 b according to an embodiment of the inventive concept.

[0047] Will Figure 1and Figure 5 Compare with each other, Figure 5 In the semiconductor package 100b, Figure 1 Unlike the semiconductor package 100 of FIG. 1 , the fourth insulating layer IL1 may be spaced apart from the side surface of the lower portion of the pad 120. In some embodiments, the fourth insulating layer IL1 may also be spaced apart from the lower surface of the upper portion of the pad 120. The first bump 180 may contact the lower surface and the side surface of the lower portion of the pad 120. When the first bump 180 also contacts the side surface of the lower portion of the pad 120, the contact area between the first bump 180 and the pad 120 may increase, thereby improving the reliability of the semiconductor package 100b. In some embodiments, the first bump 180 may also contact the lower surface of the upper portion of the pad 120. When the first bump 180 also contacts the lower surface of the upper portion of the pad 120, the contact area between the first bump 180 and the pad 120 may increase, thereby improving the reliability of the semiconductor package 100b.

[0048] Figure 6 is a cross-sectional view of a semiconductor package 200 according to an embodiment of the inventive concept.

[0049] Reference Figure 6 The semiconductor package 200 may include a package substrate 210, a third bump 290 located under the package substrate 210, a first bump 180 located on the package substrate 210, an interposer 220 located on the first bump 180, and a semiconductor chip 150 (hereinafter, the first semiconductor chip 150) located on the interposer 220.

[0050] The package substrate 210 may include a body 212, a lower pad 211 located on the lower surface of the body 212, an upper pad 214 located on the upper surface of the body 212, and a conductive pattern 213 connecting the lower pad 211 and the upper pad 214. In some embodiments, the package substrate 210 may include a printed circuit board. The body 212 of the package substrate 210 may include a phenolic resin, an epoxy resin, a polyimide resin, or a combination thereof. For example, the body 212 of the package substrate 210 may include flame retardant 4 (FR4), a tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), polyamide staple fiber mat (thermount), cyanate ester, polyimide, or liquid crystal polymer. For example, the lower pad 211, the upper pad 214 and the conductive pattern 213 of the package substrate 210 may include conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti)), doped semiconductor materials, conductive organic materials (e.g., conductive polymers), carbon-based materials (e.g., carbon nanotubes and graphene), or combinations thereof.

[0051] The third bump 290 may contact the lower pad 211 of the package substrate 210. The third bump 290 may be used to connect the semiconductor package 200 to the outside. For example, the third bump 290 may include a metal such as tin (Sn), lead (Pb), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), antimony (Sb), or a combination thereof. The third bump 290 may be formed, for example, by a solder ball.

[0052] The first bump 180 may contact the upper pad 214 of the package substrate 210 and the pad 120 of the interposer 220. The first bump 180 is described in detail above with reference to Figures 1 to 5 As described above. In some embodiments, the semiconductor package 200 may further include an underfill 230 filled between the interposer 220 and the package substrate 210 and surrounding the first bump 180. The underfill 230 may be an insulating material and may include, for example, a polymer material (such as a thermosetting resin, a thermoplastic resin, a UV curable resin, or a combination thereof; an epoxy resin, a silicone resin, or a combination thereof; an epoxy molding compound (EMC); or a combination thereof).

[0053] The interposer 220 may include a pad 120 located on the first bump 180, a first insulating layer IL2 located on the pad 120, and a redistribution structure RDS located on the first insulating layer IL2. In some embodiments, the interposer 220 may further include a fourth insulating layer IL1 located below the first insulating layer IL2. In some embodiments, the interposer 220 may further include a protective insulating layer 110 located below the fourth insulating layer IL1. The pad 120, the first insulating layer IL2, the redistribution structure RDS, the fourth insulating layer IL1, and the protective insulating layer 110 are described in detail above with reference to Figures 1 to 5 Just as described.

[0054] The first semiconductor chip 150 on the interposer 220 can be electrically connected to the redistribution structure RDS of the interposer 220. In some embodiments, the semiconductor package 200 may further include a second bump 160, which contacts the third conductive pattern 133 of the redistribution structure RDS of the interposer 220 and the chip pad 151 of the first semiconductor chip 150, and the second bump 160 connects the first semiconductor chip 150 and the interposer 220. The detailed description of the first semiconductor chip 150 and the second bump 160 is as described above with reference to Figure 1 Just as described.

[0055] In some embodiments, the semiconductor package 200 may further include at least one second semiconductor chip positioned on the interposer 220. For example, the semiconductor package 200 may include a plurality of second semiconductor chips 250a to 250e stacked on the interposer 220. In some embodiments, each of the second semiconductor chips 250a to 250e may include a body 252, an upper pad 254 positioned on an upper surface of the body 252, a lower pad 251 positioned on a lower surface of the body 252, and a via 253 connected between the upper pad 254 and the lower pad 251 and passing through the body 252. In some embodiments, the uppermost second semiconductor chip 250e may not include the upper pad 254 and the via 253.

[0056] The body 252 of each of the second semiconductor chips 250a to 250e may include a substrate. The body 252 may include an active surface ( Figure 6 The lower surface of the main body 252 in the embodiment) and the ineffective surface opposite to the effective surface ( Figure 6 The main body 252 may also include an integrated circuit located on the active surface. The substrate may include a semiconductor material. The integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. Each of the second semiconductor chips 250a to 250e may include an integrated circuit that is the same as and / or different from the integrated circuits of the other second semiconductor chips 250a to 250e. For example, the bottommost second semiconductor chip 250a may include a logic circuit, and the other second semiconductor chips 250b to 250d may each include a memory circuit. For example, the lower pad 251, the upper pad 254, and the via 253 of each of the second semiconductor chips 250a to 250e may include a conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti)), a doped semiconductor material, a conductive organic material (e.g., a conductive polymer), a carbon-based material (e.g., carbon nanotubes and graphene), or a combination thereof.

[0057] In some embodiments, the semiconductor package 200 may further include fourth bumps 260 located between adjacent second semiconductor chips (e.g., between the second semiconductor chip 250a and the second semiconductor chip 250b, between the second semiconductor chip 250b and the second semiconductor chip 250c, between the second semiconductor chip 250c and the second semiconductor chip 250d, and between the second semiconductor chip 250d and the second semiconductor chip 250e) and between the lowermost second semiconductor chip (e.g., the second semiconductor chip 250a) and the interposer 220. Each of some of the fourth bumps 260 may contact the lower pad 251 of the upper second semiconductor chip (e.g., the second semiconductor chip 250c) and the upper pad 254 of the lower second semiconductor chip (e.g., the second semiconductor chip 250b) of two adjacent second semiconductor chips (e.g., the second semiconductor chips 250b and 250c). The other fourth bumps 260 may contact the lower pad 251 of the lowermost second semiconductor chip 250a and the third conductive pattern 133 of the redistribution structure RDS of the interposer 220. The plurality of semiconductor chips 250a to 250e may be electrically connected to the third conductive pattern 133 of the redistribution structure RDS of the interposer 220 via the upper pad 254, the via 253, the lower pad 251, and the fourth bumps 260. For example, the fourth bumps 260 may include a metal such as tin (Sn), lead (Pb), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), antimony (Sb), or a combination thereof. The fourth bumps 260 may be formed, for example, of a solder ball.

[0058] In some embodiments, the semiconductor package 200 may further include a chip bonding layer and / or an underfill, the chip bonding layer and / or the underfill being located between adjacent second semiconductor chips (e.g., between the second semiconductor chip 250a and the second semiconductor chip 250b, between the second semiconductor chip 250b and the second semiconductor chip 250c, between the second semiconductor chip 250c and the second semiconductor chip 250d, and between the second semiconductor chip 250d and the second semiconductor chip 250e) and between the lowermost second semiconductor chip (e.g., the second semiconductor chip 250a) and the interposer 220, and the chip bonding layer and / or the underfill surrounding the fourth bumps 260. In some embodiments, the semiconductor package 200 may further include a molding member 170 covering the interposer 220, the first semiconductor chip 150, and the plurality of second semiconductor chips 250a to 250e.

[0059] Figures 7A to 7Y is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0060] Reference Figure 7AA protective insulating layer 110 may be formed on the carrier 101, and a first insulating layer IL1 may be formed on the protective insulating layer 110. In some embodiments, the carrier 101 may include glass. The protective insulating layer 110 and the first insulating layer IL1 may be formed by, for example, spin coating or slide coating.

[0061] Reference Figure 7B , a first opening OP1 may be formed in the first insulating layer IL1 to expose the protective insulating layer 110, thereby forming the first insulating layer IL1. When the first insulating layer IL1 includes a PID material, the first opening OP1 may be formed in the first insulating layer IL1 by selectively exposing and developing the first insulating layer IL1.

[0062] Reference Figure 7C A barrier layer 120a and a seed layer 120b may be formed on the first insulating layer IL1. The barrier layer 120a and the seed layer 120b may be conformally formed on the protective insulating layer 110, the side surfaces of the first opening OP1 of the first insulating layer IL1, and the upper surface of the first insulating layer IL1. For example, the barrier layer 120a and the seed layer 120b may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0063] Reference Figure 7D , a first photoresist layer PR1 may be formed on the seed layer 120b. The first photoresist layer PR1 may be formed by, for example, spin coating or slide coating. Next, an opening OP1P may be formed in the first photoresist layer PR1 to expose the seed layer 120b. For example, the opening OP1P may be formed in the first photoresist layer PR1 by selectively exposing and developing the first photoresist layer PR1.

[0064] Reference Figure 7E A filling layer 120c may be formed on the seed layer 120b to fill the opening OP1P of the first photoresist layer PR1. The filling layer 120c may be formed by, for example, electroplating.

[0065] Reference Figure 7E and Figure 7F , the first photoresist layer PR1 can be removed. The first photoresist layer PR1 can be removed by, for example, ashing (e.g., plasma ashing), dry etching, and / or wet etching. Next, the seed layer 120b and the barrier layer 120a can be etched using the filling layer 120c as an etching mask, thereby forming the barrier layer 120a and the seed layer 120b. Thus, the pad 120 can be obtained.

[0066] Reference Figure 7G, a second insulating layer IL2 may be formed on the first insulating layer IL1 and the pad 120. The second insulating layer IL2 may be formed by, for example, spin coating or slide coating. Since the lower portion of the pad 120 is formed in the first opening OP1 of the first insulating layer IL1 and only the upper portion of the pad 120 protrudes from the upper surface of the first insulating layer IL1, the undulations of the upper surface of the second insulating layer IL2 may not be affected by the thickness of the lower portion of the pad 120 but only by the thickness of the upper portion of the pad 120. Therefore, even when the pad 120 is formed thick to improve the reliability of the semiconductor package, the undulations of the upper surface of the second insulating layer IL2 may not be significant, and the upper surface of the second insulating layer IL2 may not be significantly degraded, and the second insulating layer IL2 may have a relatively flat upper surface.

[0067] Reference Figure 7H , a second opening OP2 may be formed in the second insulating layer IL2 to expose the pad 120, thereby forming the first insulating layer IL2. When the second insulating layer IL2 includes a PID material, the second opening OP2 may be formed in the second insulating layer IL2 by selectively exposing and developing the second insulating layer IL2. Because the upper surface of the second insulating layer IL2 can be formed to be relatively flat, the possibility of the second opening OP2 not being formed at a desired position and size due to a reduction in the depth of focus (DOF) margin that may be caused by undulations in the upper surface of the second insulating layer IL2 can be reduced.

[0068] Reference Figure 7I A first barrier layer 131a and a first seed layer 131b may be formed on the second insulating layer IL2. The first barrier layer 131a and the first seed layer 131b may be conformally formed on the pad 120, the side surfaces of the second opening OP2 of the second insulating layer IL2, and the upper surface of the second insulating layer IL2. For example, the first barrier layer 131a and the first seed layer 131b may be formed by chemical vapor deposition or physical vapor deposition.

[0069] Reference Figure 7J , a second photoresist layer PR2 can be formed on the first seed layer 131b. The second photoresist layer PR2 can be formed by, for example, spin coating or slide coating. Then, an opening OP2P can be formed in the second photoresist layer PR2 to expose the first seed layer 131b. For example, the opening OP2P can be formed in the second photoresist layer PR2 by selectively exposing and developing the second photoresist layer PR2. Because the upper surface of the second insulating layer IL2 is formed to be relatively flat, the upper surface of the second photoresist layer PR2 can also be formed to be relatively flat. Therefore, the possibility of the following situation can be reduced: the exposure process is affected by the undulations of the upper surface of the second photoresist layer PR2, and therefore the opening OP2P is not formed at the desired position and is not formed in the desired size.

[0070] Reference Figure 7K A first filling layer 131c may be formed on the first seed layer 131b to fill the opening OP2P of the second photoresist layer PR2. The first filling layer 131c may be formed by, for example, electroplating.

[0071] Reference Figure 7K and Figure 7L , the second photoresist layer PR2 may be removed. The second photoresist layer PR2 may be removed by, for example, ashing (eg, plasma ashing), dry etching, and / or wet etching.

[0072] Reference Figure 7M The first seed layer 131b and the first barrier layer 131a may be etched using the first filling layer 131c as an etching mask, thereby forming the first seed layer 131b and the first barrier layer 131a. As a result, the first conductive pattern 131 may be obtained.

[0073] Reference Figure 7N , a third insulating layer 141 may be formed on the second insulating layer IL2 and the first conductive pattern 131. The third insulating layer 141 may be formed by, for example, spin coating or slide coating.

[0074] Reference Figure 7O , third openings 141OP may be formed in the third insulating layer 141 to expose the first conductive pattern 131, thereby forming the third insulating layer 141. When the third insulating layer 141 includes a PID material, the third openings 141OP may be formed in the third insulating layer 141 by selectively exposing and developing the third insulating layer 141.

[0075] Reference Figure 7P , a second barrier layer 132a and a second seed layer 132b may be formed on the third insulating layer 141. The second barrier layer 132a and the second seed layer 132b may be conformally formed on the side surfaces of the first conductive pattern 131, the third opening 141OP of the third insulating layer 141, and the upper surface of the third insulating layer 141. For example, the second barrier layer 132a and the second seed layer 132b may be formed by chemical vapor deposition or physical vapor deposition.

[0076] Reference Figure 7Q , a third photoresist layer PR3 may be formed on the second seed layer 132b. The third photoresist layer PR3 may be formed by, for example, spin coating or slide coating. Next, an opening OP3P may be formed in the third photoresist layer PR3 to expose the second seed layer 132b. For example, the opening OP3P may be formed in the third photoresist layer PR3 by selectively exposing and developing the third photoresist layer PR3.

[0077] Reference Figure 7R A second filling layer 132c may be formed on the second seed layer 132b to fill the opening OP3P of the third photoresist layer PR3. The second filling layer 132c may be formed by, for example, electroplating.

[0078] Reference Figure 7R and Figure 7S , the third photoresist layer PR3 may be removed. The third photoresist layer PR3 may be removed by, for example, ashing (eg, plasma ashing), dry etching, and / or wet etching.

[0079] Reference Figure 7T The second seed layer 132b and the second barrier layer 132a may be etched using the second filling layer 132c as an etching mask, thereby forming the second seed layer 132b and the second barrier layer 132a. As a result, the second conductive pattern 132 may be obtained.

[0080] Reference Figure 7U , and above Figures 7N to 7T Similar to the described operation, a fourth insulating layer 142 may be formed on the third insulating layer 141 and the second conductive pattern 132, a fourth opening 142OP may be formed in the fourth insulating layer 142, and a third conductive pattern 133 may be formed on the fourth insulating layer 142. As a result, a redistribution structure RDS including the third insulating layer 141, the fourth insulating layer 142, and the first to third conductive patterns 131 to 133 may be obtained. Subsequently, a plurality of semiconductor chips 150 may be attached to the redistribution structure RDS via a plurality of second bumps 160. For example, the second bumps 160 may be reflowed to bond the plurality of semiconductor chips 150 to the redistribution structure RDS.

[0081] Reference Figure 7V , a molding member 170 may be formed on the redistribution structure RDS and the plurality of semiconductor chips 150 .

[0082] Reference Figure 7V and Figure 7W , the carrier 101 may be separated from the protective insulating layer 110, and the mold 170 may be attached to the support 102. For example, the mold 170 may be attached to the support 102, and the carrier 101 may be separated from the protective insulating layer 110 by causing a reaction of the protective insulating layer 110, for example, by applying laser and / or heat. The protective insulating layer 110 may be used to separate the carrier 101 and thus may be a release layer.

[0083] Reference Figure 7X , an opening 110OP may be formed in the protective insulating layer 110 to expose the pad 120 , thereby forming the protective insulating layer 110 .

[0084] Reference Figure 7Y , a first bump 180 may be formed on the pad 120. For example, the first bump 180 may be formed by placing a solder ball on the pad 120 and reflowing the solder ball. Then, the protective insulating layer 110, the first insulating layer IL1, the second insulating layer IL2, the redistribution structure RDS, and the molding 170 may be cut in a vertical direction to separate the semiconductor chips 150 from each other, and the support member 102 may be separated from the molding 170. Thus, a Figure 1 The semiconductor package 100 shown in FIG. can be manufactured by removing the protective insulating layer 110 after or during the removal of the carrier 101 from the protective insulating layer 110. Figure 4 The semiconductor package 100a shown in FIG. Figure 7X The operations shown in Figure 7Y The first opening OP1 of the first insulating layer IL1 is enlarged by etching a portion of the first insulating layer IL1 between the operations shown in FIG. Figure 5 The semiconductor package 100b is shown in FIG.

[0085] According to a method of manufacturing a semiconductor package according to an embodiment of the inventive concept, a first insulating layer IL1 may be formed to have a first opening OP1, a pad 120 may be formed to have a lower portion located in the first opening OP1 of the first insulating layer IL1 and an upper portion located on the first insulating layer IL1, a second insulating layer IL2 may be formed to cover the upper portion of the pad 120 and the first insulating layer IL1, a redistribution structure RDS may be formed on the second insulating layer IL2, a semiconductor chip 150 may be attached to the redistribution structure RDS, and a first bump 180 may be attached to the pad 120. Because the lower portion of the pad 120 is located in the first opening OP1 of the first insulating layer IL1, the undulations of the upper surface of the second insulating layer IL2 are affected only by the thickness of the upper portion of the pad 120, and thus the undulations of the upper surface of the second insulating layer IL2 may be reduced compared to when the undulations of the upper surface of the second insulating layer IL2 are affected by the total thickness of the pad 120. Therefore, even when the pad 120 is formed to have a large total thickness H3 (see Figure 2A ), the undulations on the upper surface of the second insulating layer IL2 may not be significantly degraded. Therefore, it is possible to prevent a defective redistribution structure RDS from being manufactured on the second insulating layer IL2 due to a reduction in a depth of focus (DOF) margin in an exposure process caused by the undulations on the upper surface of the second insulating layer IL2, and to prevent an increase in the rate of manufacturing defective semiconductor packages.

[0086] When the total thickness H3 of the pad 120 is increased (see Figure 2A), although a brittle intermetallic compound is formed between the pad 120 and the first bump 180, the proportion of the portion of the pad 120 where the intermetallic compound is formed is reduced, thereby improving the reliability of the semiconductor package. Therefore, according to the above manufacturing method, a semiconductor package with high reliability can be manufactured without significantly increasing the rate of manufacturing defective semiconductor packages.

[0087] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: semiconductor chips; a redistribution structure located beneath the semiconductor chip; a first insulating layer located below the redistribution structure; a pad having an upper portion and a lower portion, the lower portion being located below the first insulating layer, the pad being in contact with the redistribution structure, the upper portion having a horizontal maximum length greater than a horizontal maximum length of the lower portion; a second insulating layer positioned below the first insulating layer, wherein a lower surface of the second insulating layer and a lower surface of the lower portion of the pad are coplanar; and The bump contacts the lower surface of the lower portion of the pad.

2. The semiconductor package according to claim 1, wherein The first insulating layer contacts an upper surface and side surfaces of an upper portion of the pad.

3. The semiconductor package according to claim 1, wherein The lower surface of the first insulating layer is coplanar with the lower surface of the upper portion of the pad.

4. The semiconductor package according to claim 1, wherein The second insulating layer contacts a lower surface of the upper portion of the pad and a side surface of the lower portion of the pad.

5. The semiconductor package according to claim 1, wherein The second insulating layer is spaced apart from a side surface of a lower portion of the pad.

6. The semiconductor package according to claim 1, further comprising: The protective insulating layer is located below the second insulating layer.

7. The semiconductor package according to claim 1, wherein The planar area of ​​the redistribution structure is larger than the planar area of ​​the semiconductor chip.

8. The semiconductor package according to claim 1, wherein The upper portion of the pad and the lower portion of the pad share a common central axis.

9. A semiconductor package, comprising: bumps; a pad positioned on the projection, the pad having a lower portion and an upper portion, the upper portion having a horizontal maximum length greater than a horizontal maximum length of the lower portion; a first insulating layer spaced apart from the lower portion of the pad and in contact with the side surface and the upper surface of the upper portion of the pad; a first conductive pattern located on the first insulating layer, the first conductive pattern comprising a first line portion and a first via portion protruding downward from the first line portion, the first via portion being in contact with the pad; a second insulating layer, located on the first insulating layer and the first conductive pattern; a second conductive pattern located on the second insulating layer, the second conductive pattern comprising a second line portion and a second via portion protruding downward from the second line portion, the second via portion being in contact with the first line portion of the first conductive pattern; a semiconductor chip electrically connected to the second conductive pattern; and A third insulating layer is located below the first insulating layer. wherein the lower surface of the lower portion of the pad is coplanar with the lower surface of the third insulating layer, and The bump contacts the lower surface of the lower portion of the pad.

10. The semiconductor package according to claim 9, wherein The bump contacts a lower surface of the lower portion of the pad and is spaced apart from a side surface of the lower portion of the pad.

11. The semiconductor package according to claim 9, wherein The third insulating layer is spaced apart from a side surface of a lower portion of the pad.

12. The semiconductor package according to claim 11, wherein The bumps are in contact with the lower surface and side surfaces of the lower portion of the pad.

13. The semiconductor package according to claim 12, wherein The bump contacts the lower surface of the upper portion of the pad.

14. The semiconductor package according to claim 9, wherein Pad includes: a barrier layer, contacting the bump; as well as The filling layer contacts the first via portion of the first conductive pattern.

15. A semiconductor package, comprising: packaging substrate; A first bump is located below the package substrate; A second bump is located on the package substrate; an interposer located on the second bump, the interposer including a pad located on the second bump; A first semiconductor chip is located on the interposer, a first insulating layer located on the pad; and a redistribution structure located on the first insulating layer, the redistribution structure connecting the pad and the first semiconductor chip, an upper portion of the pad located in the first opening in the first insulating layer, and the upper portion of the pad having a horizontal maximum length greater than a horizontal maximum length of a lower portion of the pad, The interposer further includes a second insulating layer located below the first insulating layer. The lower surface of the lower portion of the pad is coplanar with the lower surface of the second insulating layer, and The second bump contacts the lower surface of the lower portion of the pad.

16. The semiconductor package according to claim 15, further comprising: The second semiconductor chip is located on the interposer.

17. The semiconductor package according to claim 15, wherein A lower portion of the pad is located in the second opening in the second insulating layer.

18. The semiconductor package according to claim 17, wherein The interposer further includes a protective insulating layer located below the second insulating layer, and The second bump is located in the opening in the protective insulating layer.

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