Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a storage region and a logic region, wherein the storage region has a first conductive layer, wherein the logic region has a second conductive layer, and wherein the substrate exposes the top surface of the first conductive layer and the top surface of the second conductive layer; forming a first electrode layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction on the surface of the first conductive layer; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer; forming a third conductive layer in the first dielectric layer, wherein the bottom of the third conductive layer contacts the top surface of the second electrode layer. The method can save process steps and improve process compatibility.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] MRAM (Magnetic Random Access Memory) is a non-volatile magnetic random access memory. It has the high-speed read and write capabilities of static random access memory (SRAM), the high integration of dynamic random access memory (DRAM) and much lower power consumption than DRAM. Compared with flash memory (Flash), its performance will not degrade with the increase of usage time. Due to the above characteristics of MRAM, it is called universal memory and is considered to be able to replace SRAM, DRAM, EEPROM and Flash.

[0003] Unlike traditional random access memory chip manufacturing technology, the data in MRAM is not stored in the form of charge or current, but in a magnetic state, and is sensed by measuring resistance without interfering with the magnetic state. MRAM uses a magnetic tunnel junction (MTJ) structure to store data. Generally speaking, an MRAM unit consists of a transistor (1T) and a magnetic tunnel junction to form a storage unit. The magnetic tunnel junction structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. The current flows vertically from one electromagnetic layer through the insulating layer or "through" another electromagnetic layer. One of the electromagnetic layers is a fixed magnetic layer, which fixes the electrode in a specific direction through a strong fixed field. The other electromagnetic layer is a freely rotatable magnetic layer that keeps the electrode on one side.

[0004] However, the process steps of forming the magnetic random access memory in the prior art are complicated. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to save process steps and improve the compatibility of the process.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: providing a substrate, the substrate including a storage area and a logic area, the storage area having a first conductive layer, the logic area having a second conductive layer, and the substrate exposing the top surface of the first conductive layer and the top surface of the second conductive layer; forming a first electrode layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction on the surface of the first conductive layer; forming a first dielectric layer on the substrate, the first dielectric layer covering the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer; forming a third conductive layer in the first dielectric layer, the bottom of the third conductive layer is in contact with the top surface of the second electrode layer.

[0007] Optionally, the method further includes: before forming the first electrode layer, forming an etching stop layer on the surface of the logic area.

[0008] Optionally, the method for forming the etch stop layer includes: forming a stop material layer on the surface of the substrate; forming a first patterned layer on the surface of the stop material layer on the logic area, and the first patterned layer exposes the surface of the stop material layer on the storage area; using a first etching process, using the first patterned layer as a mask, etching the stop material layer until the substrate surface is exposed to form the etch stop layer.

[0009] Optionally, the etching rate of the first etching process on the stop material layer is greater than the etching rate on the substrate, and the etching rate of the first etching process on the stop material layer is greater than the etching rate on the first conductive layer.

[0010] Optionally, the material of the stop material layer is different from that of the substrate, and the material of the stop material layer is different from that of the first conductive layer; the material of the stop material layer includes: silicon oxide, silicon nitride, silicon carbide, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

[0011] Optionally, the method for forming the first dielectric layer includes: forming a first dielectric material film on the substrate that covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer, and the surface of the second conductive layer, and the top surface of the first dielectric material film is higher than the top surface of the second electrode layer; and flattening the first dielectric material film to form the first dielectric layer.

[0012] Optionally, the method further includes: after forming the first dielectric layer, forming a plug in the first dielectric layer, the bottom of the third conductive layer is in contact with the top surface of the plug, and the plug is located on the surface of the second conductive layer.

[0013] Optionally, the top surface of the first dielectric layer is higher than the top surface of the second electrode layer; the method for forming the plug and the third conductive layer comprises: forming a through hole and a groove in the first dielectric layer, the bottom of the groove exposing the through hole and the top surface of the second electrode layer, and the bottom of the through hole exposing the surface of the second conductive layer; forming a conductive material film in the through hole, in the groove and on the surface of the first dielectric layer; flattening the conductive material film until the surface of the first dielectric layer is exposed, forming the plug in the through hole, and forming the third conductive layer in the groove.

[0014] Optionally, the material of the plug includes: one or more of copper, tungsten, aluminum, titanium and tantalum; the material of the third conductive layer includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

[0015] Optionally, it also includes: after forming the first electrode layer, the magnetic tunnel junction and the second electrode layer, and before forming the first dielectric layer, forming a protective layer on the substrate surface, the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, and the side wall surface and top surface of the second electrode layer.

[0016] Optionally, the protective layer and the dielectric layer are made of different materials; the material of the protective layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0017] Optionally, the material of the first electrode layer includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0018] Optionally, the thickness of the first electrode layer is in the range of 50 angstroms to 300 angstroms.

[0019] Optionally, the material of the second electrode layer includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0020] Optionally, the thickness of the second electrode layer is in the range of 50 angstroms to 300 angstroms.

[0021] Optionally, the method for forming the first electrode layer, the magnetic tunnel junction and the second electrode layer includes: forming a first electrode film, a magnetic tunnel film located on the surface of the first electrode film, and a second electrode film located on the surface of the magnetic tunnel film on the substrate; forming a second patterned layer on the surface of the second electrode film, and the second patterned layer covers a portion of the surface of the second electrode film on the first conductive layer, and the second patterned layer exposes the surface of the second electrode film on the logic area; using the second patterned layer as a mask, etching the second electrode film, the magnetic tunnel film and the first electrode film until the surface of the substrate is exposed, and forming the first electrode layer, the magnetic tunnel junction located on the surface of the first electrode layer, and the second electrode layer located on the surface of the magnetic tunnel junction on the first conductive layer.

[0022] Optionally, a second etching process is adopted to etch the second electrode film, the magnetic tunnel film and the first electrode film using the second patterned layer as a mask; the second etching process also includes: after exposing the substrate surface, continuing to perform over-etching using the second patterned layer as a mask.

[0023] Optionally, the magnetic tunnel junction includes: a lower electromagnetic layer located on the surface of the first electrode layer, an insulating layer located on the surface of the lower electromagnetic layer, and an upper electromagnetic layer located on the surface of the insulating layer.

[0024] Optionally, the base includes: a substrate and a second dielectric layer located on the surface of the substrate, the first conductive layer and the second conductive layer are located in the second dielectric layer; and logic devices are provided in the substrate and the second dielectric layer of the logic region.

[0025] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by any of the above methods, including: a substrate, the substrate including a storage area and a logic area, the storage area having a first conductive layer, the logic area having a second conductive layer, and the substrate exposing the top surface of the first conductive layer and the top surface of the second conductive layer; a first electrode layer located on the first conductive layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction; a first dielectric layer located on the substrate, the first dielectric layer covering the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer; a third conductive layer located in the first dielectric layer, the bottom of the third conductive layer is in contact with the top surface of the second electrode layer.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first electrode layer is formed on the surface of the first conductive layer, and the bottom of the formed third conductive layer is in contact with the top surface of the second electrode layer, so that the first electrode layer, the magnetic tunnel junction and the second electrode layer are in contact with the first conductive layer and the third conductive layer through the upper and lower surfaces respectively, thereby achieving electrical connection, so that the formed semiconductor structure can have a storage function.

[0028] Furthermore, a first electrode layer, a magnetic tunnel junction, and a second electrode layer are formed by a patterning process; after the first electrode layer, the magnetic tunnel junction, and the second electrode layer are formed, a plug and a third conductive layer are formed, and the plug is electrically connected to the second conductive layer of the logic area. The first electrode layer, the magnetic tunnel junction, and the second electrode layer are formed by a single exposure and development process and a single etching process, and the plug is used to electrically connect the logic device, so that the formed semiconductor structure can have a storage function. It can be seen that the method can be well compatible with the existing logic process and has fewer process steps.

[0029] Furthermore, before forming the first electrode film, an etching stop layer is formed on the surface of the logic region, and the etching stop layer exposes the surface of the storage region. Therefore, in the process of etching the first electrode film, the magnetic tunnel film and the second electrode film on the storage region using the second patterned layer as a mask to form the first electrode layer, the magnetic tunnel layer and the second electrode layer, no etching damage is caused to the substrate surface and the second conductive layer surface of the logic region, thereby reducing the impact on the logic region, which is conducive to improving the performance of the formed semiconductor structure.

[0030] Furthermore, the plug and the third conductive layer may be formed by depositing a conductive material film in the through hole and the groove through a one-time deposition process; after planarizing the conductive material film, a plug is formed in the through hole, and a third conductive layer is formed in the groove. The process steps for forming the plug and the third conductive layer are relatively few, which is conducive to improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 6 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0032] Figures 7 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the conventional process steps for forming a semiconductor structure are complicated.

[0034] The following is a detailed description of the reasons why the process steps for forming a semiconductor structure are complicated with reference to the accompanying drawings. Figures 1 to 6 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0035] Please refer to Figure 1 , providing a substrate 100, the substrate 100 includes a storage area A and a logic area B, the storage area A has a first conductive layer 101, the logic area B has a second conductive layer 102, and the substrate 100 exposes the top surface of the first conductive layer 101 and the top surface of the second conductive layer 102.

[0036] Please refer to Figure 2 A first dielectric layer 110 is formed on the surface of the substrate 100 , and a first plug 111 is provided in the first dielectric layer 110 .

[0037] Please refer to Figure 3 A second dielectric layer 120 is formed on the surface of the first plug 111 and the surface of the first dielectric layer 110, and the second dielectric layer 120 has a first electrode layer 121, a magnetic tunnel junction 122 located on the surface of the first electrode layer 121, and a second electrode layer 123 located on the surface of the magnetic tunnel junction 122, and the bottom of the first electrode layer 121 is in contact with the first plug 111.

[0038] Please refer to Figure 4 A third dielectric layer 130 is formed on the surface of the second electrode layer 123 and the surface of the second dielectric layer 120 . The third dielectric layer 130 has a second plug 131 , and the bottom of the second plug 131 is in contact with the surface of the second electrode layer 123 .

[0039] Please refer to Figure 5 A third plug 132 is formed in the first dielectric layer 110 , the second dielectric layer 120 and the third dielectric layer 130 , and the bottom of the third plug 132 is in contact with the surface of the second conductive layer 102 .

[0040] Please refer to Figure 6 A fourth dielectric layer 140 is formed on the surface of the second plug 131 , the surface of the third plug 132 and the surface of the third dielectric layer 130 . The fourth dielectric layer 140 has a third conductive layer 141 , and the bottom of the third conductive layer 141 is in contact with the top surface of the second plug 131 and the top surface of the third plug 132 .

[0041] In the above method, a first electrode layer 121, a magnetic tunnel junction 122 located on the surface of the first electrode layer 121, and a second electrode layer 123 located on the surface of the magnetic tunnel junction 122 are formed on the surface of the first plug 111 on the storage area A; a second plug 131 is formed in the third dielectric layer 130, and the second plug 131 is electrically connected to the second electrode layer 123. The first electrode layer 121, the magnetic tunnel junction 122, and the second electrode layer 123 are used together as a storage device, and the storage device is electrically connected to other devices through the first plug 111 and the second plug 131. At the same time, the substrate 100 of the logic area B has a logic device (not shown in the figure), such as a gate structure, a source, and a drain. Therefore, the semiconductor structure formed by the method has a storage function.

[0042] However, in order to form the first electrode layer 121, the magnetic tunnel junction 122 and the second electrode layer 123 on the storage area A, it is necessary to form a first opening (not shown in the figure) in the first dielectric layer 110 before forming the first electrode layer 121, the magnetic tunnel junction 122 and the second electrode layer 123, and form a first plug 111 in the first opening; after forming the first electrode layer 121, the magnetic tunnel junction 122 and the second electrode layer 123, form a second opening (not shown in the figure) in the third dielectric layer 130, and form a second plug 131 in the second opening; after forming the second plug 131, form a third opening (not shown in the figure) in the first dielectric layer 110, the second dielectric layer 120 and the third dielectric layer 130, and form a third plug 132 in the third opening. Multiple exposure and development processes and deposition processes are required to form the first plug 111, the second plug 131 and the third plug 132 respectively. It can be seen that the process steps of the method are complicated and are not conducive to improving production efficiency.

[0043] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a first electrode layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction on the surface of the first conductive layer; forming a dielectric layer on the substrate, the dielectric layer covering the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer, and the top surface of the second electrode layer; forming a third conductive layer in the dielectric layer, the bottom of the third conductive layer is in contact with the top surface of the second electrode layer. The method can save process steps and improve process compatibility.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 7 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0046] Please refer to Figure 7 , providing a substrate 200, the substrate 200 includes a storage area A and a logic area B, the storage area A has a first conductive layer 201, the logic area B has a second conductive layer 202, and the substrate 200 exposes the top surface of the first conductive layer 201 and the top surface of the second conductive layer 202.

[0047] In this embodiment, the base 200 includes: a substrate 203 and a second dielectric layer 204 located on the surface of the substrate 203, and the first conductive layer 201 and the second conductive layer 202 are located in the second dielectric layer 204; the substrate 203 and the second dielectric layer 204 of the logic area B have logic devices (not shown in the figure).

[0048] The material of the substrate 203 is a semiconductor material. In this embodiment, the material of the substrate 203 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0049] The material of the second dielectric layer 204 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0050] In this embodiment, the material of the second dielectric layer 204 is silicon oxide.

[0051] Next, an etch stop layer is formed on the surface of the logic area. For the specific process of forming the etch stop layer, please refer to Figures 8 to 10 .

[0052] Please refer to Figure 8 , a stop material layer 210 is formed on the surface of the substrate 200 .

[0053] The stop material layer 210 is used to provide material for subsequently forming an etch stop layer.

[0054] The process of forming the stop material layer 210 includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0055] In this embodiment, the process of forming the stop material layer 210 is a chemical vapor deposition process.

[0056] The material of the stop material layer 210 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0057] Please refer to Fig. 9 , a first patterned layer 220 is formed on the surface of the stop material layer 210 on the logic area B, and the first patterned layer 220 exposes the surface of the stop material layer 210 on the storage area A.

[0058] The first patterned layer 220 is used as a mask for forming an etch stop layer by the subsequent etch stop material layer 210 .

[0059] Since the first patterned layer 220 exposes the surface of the stop material layer 210 on the storage area A, the subsequent etching process can remove the stop material layer 210 on the storage area A, thereby forming an etching stop layer only on the logic area B to meet the process requirements.

[0060] Please refer to Fig.10 , using a first etching process, using the first patterned layer 220 as a mask, etching the stop material layer 210 until the surface of the substrate 200 is exposed, thereby forming the etching stop layer 211 .

[0061] The etching stop layer 211 is used to protect the surface of the logic region B and reduce the impact on the logic region B during the subsequent etching process to form the first electrode layer, the magnetic tunnel junction and the second electrode layer.

[0062] The material of the stop material layer 210 is different from that of the substrate 200 , and the material of the stop material layer 210 is different from that of the first conductive layer 201 .

[0063] Since the material of the stop material layer 210 is different from that of the substrate 200, and the material of the stop material layer 210 is different from that of the first conductive layer 201, it is beneficial to adopt a suitable etching process to etch the stop material layer 210 until the surface of the substrate 200 and the surface of the first conductive layer 201 are exposed, thereby forming an etching stop layer 211. In this process, the etching loss caused to the substrate 200 and the first conductive layer 201 is reduced, which is beneficial to improving the performance of the formed semiconductor structure.

[0064] The etching rate of the first etching process on the stop material layer 210 is greater than the etching rate on the substrate 200 . The etching rate of the first etching process on the stop material layer 210 is greater than the etching rate on the first conductive layer 201 .

[0065] In this embodiment, specifically, the etching rate of the first etching process on the stop layer 210 is greater than the etching rate on the second dielectric layer 204 located on the surface of the substrate 203 .

[0066] In this embodiment, the material of the stop material layer 210 is silicon nitride, so the material of the formed etch stop layer 211 is silicon nitride.

[0067] In other embodiments, the etch stop layer may not be formed.

[0068] In this embodiment, after forming the etching stop layer 211 , the method further includes: removing the first patterned layer 220 .

[0069] After the etching stop layer is formed, a first electrode layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction are formed on the surface of the first conductive layer. For details on the process of forming the first electrode layer, the magnetic tunnel junction, and the second electrode layer, please refer to Figures 11 to 13 .

[0070] Please refer to Fig.11 A first electrode film 221 , a magnetic tunnel film 222 located on a surface of the first electrode film 221 , and a second electrode film 223 located on a surface of the magnetic tunnel film 222 are formed on the substrate 200 .

[0071] In this embodiment, the first electrode film 221 also covers the sidewall surface and the top surface of the etch stop layer 211 .

[0072] The first electrode film 221 provides material for subsequently forming a first electrode layer, the magnetic tunnel film 222 provides material for subsequently forming a magnetic tunnel junction, and the second electrode film 223 provides material for subsequently forming a second electrode layer.

[0073] The material of the first electrode film 221 includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0074] In this embodiment, the first electrode film 221 is a stacked structure, and the materials of the first electrode film 221 are titanium nitride and tungsten. In other embodiments, the first electrode film is a stacked structure formed of other materials. In other embodiments, the first electrode film can also be a single-layer structure.

[0075] The material of the second electrode film 223 includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0076] In this embodiment, the second electrode film 223 is a stacked structure, and the material of the second electrode film 223 is titanium nitride and tungsten. In other embodiments, the second electrode film is a stacked structure formed of other materials. In other embodiments, the second electrode film can also be a single-layer structure.

[0077] The magnetic tunnel film 222 includes: a lower electromagnetic film (not shown in the figure) located on the surface of the first electrode film 221; an insulating film (not shown in the figure) located on the surface of the lower electromagnetic film; and an upper electromagnetic film (not shown in the figure) located on the surface of the insulating film.

[0078] The lower electromagnetic film is used to subsequently form a lower electromagnetic layer, the insulating film is used to subsequently form an insulating layer, and the upper electromagnetic film is used to subsequently form an upper electromagnetic layer.

[0079] Please refer to Fig.12A second patterned layer 230 is formed on the surface of the second electrode film 223 , and the second patterned layer 230 covers a portion of the surface of the second electrode film 223 on the first conductive layer 201 , and the second patterned layer 230 exposes the surface of the second electrode film 223 on the logic area B.

[0080] The second patterned layer 230 is used as a mask for etching the second electrode film 223 , the magnetic tunnel film 222 , and the first electrode film 221 .

[0081] Since the second patterned layer 230 exposes the second electrode film 223 on the logic area B, a first electrode layer, a magnetic tunnel structure located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction are subsequently formed on the surface of the storage area A, that is, a device with storage function is formed on the surface of the storage area A.

[0082] Since the surface of the logic area B has an etch stop layer 211, and the etch stop layer 211 exposes the surface of the storage area A, the first electrode film 221, the magnetic tunnel film 222 and the second electrode film 223 on the storage area A are etched using the second patterned layer 230 as a mask to form the first electrode layer 241, the magnetic tunnel layer 242 and the second electrode layer 243. In this process, no etching damage will be caused to the surface of the substrate 200 and the surface of the second conductive layer 202 of the logic area B, thereby reducing the impact on the logic area B and facilitating improving the performance of the formed semiconductor structure.

[0083] Please refer to Fig.13 , using the second patterned layer 230 as a mask, the second electrode film 223, the magnetic tunnel film 222 and the first electrode film 221 are etched until the surface of the substrate 200 is exposed, and the first electrode layer 241, the magnetic tunnel junction 242 located on the surface of the first electrode layer 241, and the second electrode layer 243 located on the surface of the magnetic tunnel junction 242 are formed on the first conductive layer 201.

[0084] It should be noted that the first electrode layer 241 , the magnetic tunnel junction 242 located on the surface of the first electrode layer 241 , and the second electrode layer 243 located on the surface of the magnetic tunnel junction are used together as a storage device.

[0085] In this embodiment, a second etching process is adopted to etch the second electrode film 223 , the magnetic tunnel film 222 and the first electrode film 221 using the second patterned layer 230 as a mask.

[0086] The second etching process is adopted to form the first electrode layer 241 , the magnetic tunnel junction 242 and the second electrode layer 243 through a patterning process, that is, through one exposure and development process and one etching process, the process steps are relatively small.

[0087] In this embodiment, the second etching process further includes: after exposing the surface of the substrate 200 , continuing to perform over etching using the second patterned layer 230 as a mask.

[0088] Through the over-etching process, it is possible to ensure that the first electrode layers 241 formed on adjacent first conductive layers 201 are fully isolated, thereby avoiding electrical crosstalk between adjacent storage devices, so that the formed semiconductor structure has better performance.

[0089] In this embodiment, after forming the first electrode layer 241 , the magnetic tunnel junction 242 and the second electrode layer 243 , the process further includes: removing the second patterned layer 230 .

[0090] The first electrode layer 241 is formed by the first electrode film 221 . Accordingly, the material of the first electrode layer 241 includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0091] In this embodiment, the first electrode layer 241 is a stacked structure formed by titanium nitride and tungsten.

[0092] The thickness of the first electrode layer 241 ranges from 50 angstroms to 300 angstroms. The thicker first electrode layer 241 is conducive to meeting process requirements.

[0093] The material of the second electrode layer 243 includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0094] The thickness of the second electrode layer 243 ranges from 50 angstroms to 300 angstroms. The thicker second electrode layer 243 is conducive to meeting process requirements.

[0095] The magnetic tunnel junction 242 includes: a lower electromagnetic layer (not shown in the figure) located on the surface of the first electrode layer 241, an insulating layer (not shown in the figure) located on the surface of the lower electromagnetic layer, and an upper electromagnetic layer (not shown in the figure) located on the surface of the insulating layer.

[0096] The material of the upper electromagnetic film includes: one or a combination of iron, cobalt, nickel, cobalt iron boron, cobalt iron, nickel iron or lanthanum strontium manganese oxide. In this embodiment, the material of the upper electromagnetic film is the same as the material of the lower electromagnetic film, which is cobalt iron boron. In other embodiments, the material of the upper electromagnetic film is different from the material of the lower electromagnetic film.

[0097] The material of the insulating film includes: one or a combination of magnesium oxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium dioxide and zirconium dioxide. In this embodiment, the material of the insulating film is magnesium oxide.

[0098] The common height of the first electrode layer 241 , the magnetic tunnel junction 242 , and the second electrode layer 243 is consistent with the height of a plug to be formed subsequently, thereby satisfying the compatibility of the storage area A and the logic area B.

[0099] Please refer to Fig.14 After forming the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243, a protective layer 250 is formed on the surface of the substrate 200, the side wall surface of the first electrode layer 241, the side wall surface of the magnetic tunnel junction 242, and the side wall surface and top surface of the second electrode layer 243.

[0100] The function of the protective layer 250 is, on the one hand, to protect the surface of the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 to reduce the impact of subsequent processes; on the other hand, to improve the stability of the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 on different first conductive layers 201 as a whole.

[0101] In this embodiment, the protection layer 250 is also located on the surface of the etch stop layer 211 .

[0102] The protective layer 250 and the first dielectric layer formed subsequently are made of different materials.

[0103] The material of the protection layer 250 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0104] In this embodiment, the material of the protection layer 250 is silicon oxynitride.

[0105] In other embodiments, the protective layer may not be formed.

[0106] Please refer to Fig.15 After forming the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243, a first dielectric layer 260 is formed on the substrate 200, and the first dielectric layer 260 covers the side wall surface of the first electrode layer 241, the side wall surface of the magnetic tunnel junction 242, the side wall surface and the top surface of the second electrode layer 243.

[0107] The method for forming the first dielectric layer 260 includes: forming a first dielectric material film (not shown in the figure) on the substrate 200, covering the side wall surface of the first electrode layer 241, the side wall surface of the magnetic tunnel junction 242, the side wall surface and the top surface of the second electrode layer 242, and the top surface of the first dielectric material film is higher than the top surface of the second electrode layer 243; and flattening the first dielectric material film to form the first dielectric layer 260.

[0108] In this embodiment, the first dielectric layer 260 is located on the surface of the protection layer 250 .

[0109] The material of the first dielectric material film includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride or silicon oxynitride.

[0110] The first dielectric layer 260 is formed of a first dielectric material film. Accordingly, the material of the first dielectric layer 260 includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride. In this embodiment, the material of the first dielectric layer is silicon oxide.

[0111] In this embodiment, the top surface of the first dielectric layer 260 formed after planarization is higher than the top surface of the second electrode layer 242 .

[0112] In other embodiments, the first dielectric material film may not be planarized, that is, the first dielectric material film directly serves as the first dielectric layer.

[0113] After the first dielectric layer 260 is formed, a third conductive layer is formed in the first dielectric layer 260 , and the bottom of the third conductive layer is in contact with the top surface of the second electrode layer 243 .

[0114] In this embodiment, after forming the first dielectric layer 260 , the method further includes: forming a plug in the first dielectric layer 260 , the bottom of the third conductive layer is in contact with the top surface of the plug, and the plug is located on the surface of the second conductive layer 202 .

[0115] In this embodiment, the third conductive layer and the plug are formed simultaneously. For details on the process of forming the third conductive layer and the plug, please refer to Figure 16 to Figure 17 .

[0116] Please refer to Fig.16 A through hole 261 and a groove 262 are formed in the first dielectric layer 260 , and the bottom of the groove 262 exposes the through hole 261 and the top surface of the second electrode layer 243 , and the bottom of the through hole 261 exposes the surface of the second conductive layer 202 .

[0117] The bottom of the through hole 261 exposes the surface of the second conductive layer 202 , so that after the conductive material is subsequently filled to form a plug, the device in the logic area B can be electrically connected to the peripheral circuit.

[0118] The bottom of the groove 262 exposes the surface of the second electrode layer 243 , so that after the conductive material is subsequently filled to form the third conductive layer, the device in the storage area A can be electrically connected to the peripheral circuit.

[0119] In this embodiment, the groove 262 and the through hole 261 are connected, so that the third conductive layer formed subsequently can electrically connect the devices in the storage area A and the devices in the logic area B at the same time.

[0120] In other embodiments, the groove 262 and the through hole 261 are not connected.

[0121] Please refer to Fig.17 , forming a conductive material film (not shown in the figure) in the through hole 261, in the groove 262 and on the surface of the first dielectric layer 260; planarizing the conductive material film until the surface of the first dielectric layer 260 is exposed, forming the plug 271 in the through hole 261, and forming the third conductive layer 272 in the groove 262.

[0122] The material of the plug 271 includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

[0123] The material of the third conductive layer 272 includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

[0124] In this embodiment, the plug 271 and the third conductive layer 272 are formed by planarizing the conductive material film, so that the plug 271 and the third conductive layer 272 are made of the same material.

[0125] In this embodiment, the material of the conductive material film is tungsten, so the material of the plug 271 and the third conductive layer 272 is tungsten.

[0126] Since the first electrode layer 241 is formed on the surface of the first conductive layer 201, and at the same time, the bottom surface of the third conductive layer 272 is in contact with the top surface of the second electrode layer 243, the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 are in contact with the first conductive layer 201 and the third conductive layer 272 through the upper and lower surfaces respectively, thereby achieving electrical connection, so that the formed semiconductor structure can have a storage function.

[0127] The first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 are formed by a patterning process; after the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 are formed, a plug 271 and a third conductive layer 272 are formed, and the plug 271 is electrically connected to the second conductive layer 202 of the logic area B. The first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 are formed by a single exposure and development process and a single etching process, and the plug 271 is used to electrically connect the logic device, so that the formed semiconductor structure can have a storage function. It can be seen that the method can be well compatible with the existing logic process and has fewer process steps.

[0128] The plug 271 and the third conductive layer 272 are formed by depositing a conductive material film in the through hole 261 and the groove 262 through a one-time deposition process; after the conductive material film is planarized, the plug 271 is formed in the through hole 261, and the third conductive layer 272 is formed in the groove 262, so that the process steps for forming the plug 271 and the third conductive layer 272 are relatively few, which is conducive to improving production efficiency.

[0129] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Fig.17 , comprising: a substrate 200, wherein the substrate 200 comprises a storage area A and a logic area B, wherein the storage area A has a first conductive layer 201, wherein the logic area B has a second conductive layer 202, and wherein the substrate 200 exposes the top surface of the first conductive layer 201 and the top surface of the second conductive layer 202; a first electrode layer 241 located on the first conductive layer 201, a magnetic tunnel junction 242 located on the surface of the first electrode layer 241, and a second electrode layer 243 located on the surface of the magnetic tunnel junction 242; a first dielectric layer 260 located on the substrate 200, wherein the first dielectric layer 260 covers the side wall surface of the first electrode layer 241, the side wall surface of the magnetic tunnel junction 242, and the side wall and top surface of the second electrode layer 243; and a third conductive layer 272 located in the first dielectric layer 260, wherein the bottom of the third conductive layer 272 contacts the top surface of the second electrode layer 242.

[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a logic area, the storage area having a first conductive layer, the logic area having a second conductive layer, and the substrate exposing a top surface of the first conductive layer and a top surface of the second conductive layer; Forming a first electrode layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction on the surface of the first conductive layer, and exposing the substrate surface; After the surface of the substrate is exposed, the substrate is continuously over-etched, and after the over-etching, a protective layer is formed on the side walls and top surfaces of the first electrode layer, the magnetic tunnel junction, and the second electrode layer; Forming a first dielectric layer on the surface of the protective layer, wherein the first dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface; forming a third conductive layer in the first dielectric layer, wherein the bottom of the third conductive layer contacts the top surface of the second electrode layer; The protection layer is in contact with the first electrode layer, the magnetic tunnel junction, and the side walls and top surface of the second electrode layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the first electrode layer, an etching stop layer is formed on the surface of the logic area.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the etch stop layer includes: forming a stop material layer on the surface of the substrate; forming a first patterned layer on the surface of the stop material layer on the logic area, and the first patterned layer exposes the surface of the stop material layer on the storage area; using a first etching process, using the first patterned layer as a mask, etching the stop material layer until the substrate surface is exposed to form the etch stop layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The etching rate of the first etching process on the stop material layer is greater than the etching rate on the substrate, and the etching rate of the first etching process on the stop material layer is greater than the etching rate on the first conductive layer.

5. The method for forming a semiconductor structure according to claim 3, wherein: The material of the stop material layer is different from that of the substrate, and the material of the stop material layer is different from that of the first conductive layer; The material of the stop material layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first dielectric layer includes: forming a first dielectric material film covering the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer, and the surface of the second conductive layer on the substrate, and the top surface of the first dielectric material film is higher than the top surface of the second electrode layer; and flattening the first dielectric material film to form the first dielectric layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first dielectric layer, a plug is formed in the first dielectric layer, the bottom of the third conductive layer is in contact with the top surface of the plug, and the plug is located on the surface of the second conductive layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The top surface of the first dielectric layer is higher than the top surface of the second electrode layer; The method for forming the plug and the third conductive layer comprises: forming a through hole and a groove in the first dielectric layer, wherein the bottom of the groove exposes the through hole and the top surface of the second electrode layer, and the bottom of the through hole exposes the surface of the second conductive layer; forming a conductive material film in the through hole, in the groove and on the surface of the first dielectric layer; flattening the conductive material film until the surface of the first dielectric layer is exposed, forming the plug in the through hole, and forming the third conductive layer in the groove.

9. The method for forming a semiconductor structure according to claim 7, wherein: The material of the plug includes: one or more of copper, tungsten, aluminum, titanium and tantalum; the material of the third conductive layer includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

10. The method for forming a semiconductor structure according to claim 1, wherein: The protective layer and the dielectric layer are made of different materials; the material of the protective layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first electrode layer includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

12. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first electrode layer ranges from 50 angstroms to 300 angstroms.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second electrode layer includes: one or a combination of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

14. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second electrode layer ranges from 50 angstroms to 300 angstroms.

15. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first electrode layer, the magnetic tunnel junction and the second electrode layer includes: forming a first electrode film, a magnetic tunnel film located on the surface of the first electrode film, and a second electrode film located on the surface of the magnetic tunnel film on the substrate; forming a second patterned layer on the surface of the second electrode film, and the second patterned layer covers the surface of the second electrode film on a portion of the first conductive layer, and the second patterned layer exposes the surface of the second electrode film on the logic area; using the second patterned layer as a mask, etching the second electrode film, the magnetic tunnel film and the first electrode film until the substrate surface is exposed, and forming the first electrode layer, the magnetic tunnel junction located on the surface of the first electrode layer, and the second electrode layer located on the surface of the magnetic tunnel junction on the first conductive layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: Using a second etching process, using the second patterned layer as a mask, to etch the second electrode film, the magnetic tunnel film and the first electrode film; The second etching process further includes: after exposing the substrate surface, continuing to perform over-etching using the second patterned layer as a mask.

17. The method for forming a semiconductor structure according to claim 1, wherein: The magnetic tunnel junction includes: a lower electromagnetic layer located on the surface of the first electrode layer, an insulating layer located on the surface of the lower electromagnetic layer, and an upper electromagnetic layer located on the surface of the insulating layer.

18. The method for forming a semiconductor structure according to claim 1, wherein: The base comprises: a substrate and a second dielectric layer located on the surface of the substrate, the first conductive layer and the second conductive layer are located in the second dielectric layer; and logic devices are provided in the substrate and the second dielectric layer of the logic region.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18, characterized in that: include: A substrate, the substrate comprising a storage area and a logic area, the storage area having a first conductive layer, the logic area having a second conductive layer, and the substrate exposing a top surface of the first conductive layer and a top surface of the second conductive layer; A first electrode layer located on the first conductive layer, a magnetic tunnel junction located on a surface of the first electrode layer, and a second electrode layer located on a surface of the magnetic tunnel junction; A first dielectric layer located on the substrate, the first dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface of the second electrode layer; A third conductive layer located in the first dielectric layer, wherein the bottom of the third conductive layer contacts the top surface of the second electrode layer; The protection layer is in contact with the first electrode layer, the magnetic tunnel junction, and the side walls and top surface of the second electrode layer.

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