Integrated chip and method for manufacturing the same

Abstract

An integrated chip including a magnetoresistive random access memory (MRAM) unit above a substrate. A dielectric structure overlies the substrate. The magnetoresistive random access memory unit is disposed within the dielectric structure. The magnetoresistive random access memory unit includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive line overlies the top electrode. A sidewall spacer structure extends continuously along the sidewalls of the magnetic tunnel junction and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer. The first sidewall spacer layer and the second sidewall spacer layer include a first material, and the protective sidewall spacer layer includes a second material different from the first material.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated chip and a manufacturing method thereof, and more particularly to an integrated chip having a sidewall spacer structure for a memory cell and a manufacturing method thereof. Background Art

[0002] Many modern electronic devices contain electronic memory. Electronic memory can be volatile memory or non-volatile memory. Non-volatile memory is able to retain its stored data without power, while volatile memory loses its stored data when power is off. For the next generation of non-volatile electronic memory, magnetoresistive random-access memory (MRAM) is a promising candidate because it has advantages over current electronic memory. Compared with current non-volatile memory (such as flash memory), MRAM is generally faster and has better durability. Compared with current volatile memory (such as dynamic random-access memory (DRAM) and static random-access memory (SRAM)), MRAM generally has similar performance and density, but has lower power consumption. Summary of the invention

[0003] In some embodiments, an integrated chip includes a dielectric structure overlying a substrate, a magnetoresistive random access memory unit disposed in the dielectric structure, a conductive line overlying the top electrode and disposed in the dielectric structure, and a sidewall spacer structure extending continuously along the side walls of the magnetic tunnel junction and the top electrode, wherein the magnetoresistive random access memory unit includes a magnetic tunnel junction sandwiched between a bottom electrode and a top electrode, and the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer include a first material, and the protective sidewall spacer layer includes a second material different from the first material.

[0004] In some embodiments, an integrated chip includes a substrate, a bottom electrode overlying the substrate, a magnetic tunnel junction overlying the bottom electrode, a top electrode overlying the magnetic tunnel junction, a top electrode through hole overlying the top electrode, a first sidewall spacer layer arranged along the outer sidewall of the magnetic tunnel junction and the outer sidewall of the top electrode, a second sidewall spacer layer arranged along the outer sidewall of the top electrode, and a protective sidewall spacer layer disposed between the first sidewall spacer layer and the second sidewall spacer layer, wherein the minimum width of the top electrode through hole is greater than the maximum width of the magnetic tunnel junction, the first sidewall spacer layer includes a first material, the second sidewall spacer layer includes the first material, and the protective sidewall spacer layer includes a second material different from the first material, wherein an upper surface of the protective sidewall spacer layer is vertically located above the top surface of the magnetic tunnel junction, wherein the protective sidewall spacer layer is separated from the outer sidewall of the magnetic tunnel junction by the first sidewall spacer layer, and the protective sidewall spacer layer directly contacts the outer sidewall of the top electrode.

[0005] In some embodiments, a method for forming an integrated chip includes forming a memory cell stack above a substrate, wherein the memory cell stack includes a top electrode overlying a magnetic tunnel junction; forming a sidewall spacer structure around the memory cell stack, wherein the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer; forming an interlayer dielectric structure above the sidewall spacer structure; performing a first etching process on the interlayer dielectric structure and the second sidewall spacer layer to define an opening above the top electrode, wherein the first etching process exposes an upper surface and sidewalls of the protective sidewall spacer layer, wherein the second sidewall spacer layer and the interlayer dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etching process; and filling the opening with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A cross-sectional view of some embodiments of an integrated chip having a magnetoresistive random-access memory (MRAM) cell including a top electrode via overlying a protective sidewall spacer layer is shown.

[0008] Figure 1B Shows the tangent line A-A' Figure 1A Top views of some alternative embodiments of integrated chips.

[0009] Figures 2 to 4 Show Figure 1A Cross-sectional views of some alternative embodiments of integrated chips.

[0010] Figure 5 Cross-sectional views of some embodiments of an integrated chip having an embedded memory region with MRAM cells laterally adjacent to a logic region are shown.

[0011] Figure 6 Cross-sectional views of some embodiments of an integrated chip having an MRAM cell disposed within an interconnect structure and overlying a semiconductor substrate are shown.

[0012] Figures 7 to 10C Show Figure 1A Various cross-sectional views of some alternative embodiments of an integrated chip.

[0013] Figures 11 to 17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20 , Fig.21A , Fig.21B as well as Fig. 22 Various views of some embodiments of a first method of forming an integrated chip having an MRAM cell including a top electrode via overlying a protective sidewall spacer layer are shown.

[0014] Fig.23 A flow chart illustrating some embodiments of a first method for forming an integrated chip having an MRAM cell including a top electrode via overlying a protective sidewall spacer layer.

[0015] Figure 24 to Figure 33 Various views of some embodiments of a second method of forming an integrated chip having an MRAM cell including a protective sidewall spacer layer are shown.

[0016] Fig.34 A flow chart illustrating some embodiments of a second method for forming an integrated chip having an MRAM cell including a protective sidewall spacer layer.

[0017] Fig.35 and Fig.36 Cross-sectional views showing some alternative embodiments of the second method.

[0018] Figure 37 to Figure 39Cross-sectional views showing some additional alternative embodiments of the second method.

[0019] Description of Figure Numbers

[0020] 100, 200, 300, 400, 500, 600, 700, 800, 900a, 900b, 1000a, 1000b, 1000c: integrated chip;

[0021] 102: substrate;

[0022] 104: Inner connection dielectric structure;

[0023] 106: lower inner connecting wire;

[0024] 108: bottom electrode through hole;

[0025] 110: bottom electrode;

[0026] 112: sidewall spacer structure;

[0027] 114: a first sidewall spacer layer;

[0028] 114a: inner sidewall spacer layer;

[0029] 114b: outer side wall spacer layer;

[0030] 116: Protecting sidewall spacer layer;

[0031] 116l: flange;

[0032] 116ls: transverse section;

[0033] 118: a second sidewall spacer layer;

[0034] 120: Magnetic tunnel junction (MTJ);

[0035] 122: top electrode;

[0036] 122ls, 126ls: lower surface;

[0037] 122us, 505us: upper surface;

[0038] 124: Magnetoresistive random access memory (MRAM) cell;

[0039] 124a: a first MRAM cell;

[0040] 124b: second MRAM cell;

[0041] 126: top electrode through hole;

[0042] 128: upper inner connecting wire;

[0043] 202, 207: interlayer dielectric layer;

[0044] 204, 206: dielectric layer;

[0045] 208: diffusion barrier;

[0046] 210: lower metal layer;

[0047] 212: first bottom electrode layer;

[0048] 214: second bottom electrode layer;

[0049] 216: seed layer;

[0050] 218: first fixed layer;

[0051] 220: second fixed layer;

[0052] 222: tunnel barrier;

[0053] 224: free layer;

[0054] 226: top cover layer;

[0055] 230: first protrusion;

[0056] 232: second protrusion;

[0057] 234: third protrusion;

[0058] 302: first substantially straight line;

[0059] 304: second substantially straight line;

[0060] 402: Conductor;

[0061] 404: conductive lining;

[0062] 502: embedded storage area;

[0063] 503: a first outer sidewall spacer layer;

[0064] 504: logical area;

[0065] 505: a second outer sidewall spacer layer;

[0066] 506: dielectric protection layer;

[0067] 508: third ILD layer;

[0068] 516, 622: conductive vias;

[0069] 518, 624: conductive wire;

[0070] 602: internal connection structure;

[0071] 606: shallow trench isolation (STI) region;

[0072] 608: Transistor;

[0073] 610: transistor gate;

[0074] 612: transistor dielectric layer;

[0075] 614: Transistor sidewall spacer structure;

[0076] 618: source / drain region;

[0077] 620: ILD layer;

[0078] 626: etching stop layer;

[0079] 630: Rewiring vias;

[0080] 632: Rewiring wire;

[0081] 634: bonding pad structure;

[0082] 636, 638: passivation layer;

[0083] 1002: a first dielectric protection layer;

[0084] 1004: a second dielectric protection layer;

[0085] 1006: upper ILD layer;

[0086] 1007: Upper ILD structure;

[0087] 1008: dielectric filling layer;

[0088] 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800a, 1800b, 1900, 2000, 2100a, 2100b, 2200: views;

[0089] 1101: bottom electrode stack;

[0090] 1103: storage unit stacking;

[0091] 1104: top electrode layer;

[0092] 1106: top electrode cap layer;

[0093] 1402: substantially straight line;

[0094] 1602: upper dielectric layer;

[0095] 2002: First upper dielectric layer;

[0096] 2004: Second upper dielectric layer;

[0097] 2006, 3502: masking layer;

[0098] 2008: first conductive feature opening;

[0099] 2010: second conductive feature opening;

[0100] 2300: First method;

[0101] 2302, 2304, 2306, 2308, 2310, 2312, 2314, 2316, 2318, 2320, 3402, 3404, 3406, 3408, 3410, 3412, 3414, 3416, 3418, 3420: action;

[0102] 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, 3500, 3600, 3700, 3800, 3900: cross-section;

[0103] 3400: Second method;

[0104] A-A': tangent line;

[0105] B-B', C-C': lines;

[0106] d1, d2: distance;

[0107] dlat: lateral distance;

[0108] hin: initial height;

[0109] h1: height;

[0110] Tfs, Tsp, Tte: thickness;

[0111] W1: minimum width;

[0112] Wmtj, Wte, Wteva: width. DETAILED DESCRIPTION

[0113] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0114] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0115] In addition, for ease of description, "first", "second", "third", etc. may be used herein to distinguish different elements in a figure or a series of figures. "First", "second", "third", etc. are not intended to describe corresponding elements. Thus, the "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to the "first dielectric layer" described in conjunction with another figure.

[0116] A magnetoresistive random-access memory (MRAM) device includes a magnetic tunnel junction (MTJ) vertically arranged in a back-end-of-the-line (BEOL) metal stack between a bottom electrode and a top electrode. The MTJ includes a pinned layer and a free layer vertically separated by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while the magnetic orientation of the free layer can be switched between a parallel configuration and an anti-parallel configuration relative to the magnetic orientation of the pinned layer. The parallel configuration provides a low resistance state that digitally stores data as a first data state (e.g., a logical "0"). The anti-parallel configuration provides a high resistance state that digitally stores data as a second data state (e.g., a logical "1").

[0117] The top electrode of the MRAM device is usually connected to the overlying interconnect wire by means of a top electrode via. The top electrode via can be formed by etching the top electrode via opening into the inter-level dielectric (ILD) layer above the top electrode and then filling the top electrode via opening with a conductive material. Etching needs to last for a period of time longer than the period of time required to reach the top electrode to ensure that the dielectric material is completely removed from the upper surface of the top electrode. However, this will lead to over-etching. The residual dielectric material reduces the electrical coupling between the top electrode via and the top electrode. In addition, the etching may have a higher selectivity to the surrounding dielectric material (e.g., the dielectric material of the sidewall spacer structure) compared to the top electrode. Due to this change in etching selectivity, when the bottom surface of the top electrode via is larger than the top electrode and / or there is a misalignment between the top electrode via and the top electrode, the over-etching may extend along the common sidewall defined by the top electrode and / or MTJ. In addition, the over-etching may reach the tunnel barrier layer of the MTJ and / or the bottom electrode located below the MTJ. If the over-etching reaches the tunnel barrier layer and / or the bottom electrode, the top electrode via may electrically short the fixed and free layers of the MTJ together, thereby causing the MRAM device to fail.

[0118] In addition, the top electrode via opening can be etched according to the patterned masking layer, so that the size of the top electrode via is generally defined by the features of the photolithography system. It is understood that if the top electrode via is too large, the top electrode via opening can extend across the side of the top electrode and / or across the side of the MTJ. Since the size of the top electrode via is relatively small, the top electrode via is usually produced as a feature with the highest precision on the photomask (e.g., the minimum feature size of the photomask). However, for this reason, the top electrode via is limited by the critical dimension (CD) tolerance (e.g., the maximum allowable deviation of the size from the target of the feature). As the size of the MRAM cell continues to decrease, the CD tolerance of the bottom surface of the top electrode via will also increase, making it increasingly difficult for the top electrode via to land on the underlying top electrode. Increasing the difficulty of landing the top electrode via on the top electrode can lead to over-etching, which can cause device failure and yield reduction. For example, during the formation of the top electrode via opening, over-etching can expose the tunnel barrier layer and / or fixed magnetic layer of the MTJ. After landing the top electrode via on the top electrode, the top electrode via may directly contact the fixed magnetic layer, thereby shorting the free layer to the fixed layer and rendering the MRAM device inoperable.

[0119] In some embodiments, the present disclosure relates to an integrated chip having a magnetoresistive random access memory (MRAM) cell and further to a method for forming the integrated chip, the MRAM cell including a protective sidewall spacer layer that laterally surrounds a magnetic tunnel junction (MTJ) and a top electrode. For example, the integrated chip may include an MRAM device surrounded by an interconnect dielectric structure disposed above a substrate. The MRAM device includes an MTJ between a bottom electrode and a top electrode. The sidewall spacer structure laterally surrounds the MTJ and the top electrode. The sidewall spacer structure includes a protective sidewall spacer layer, the protective sidewall spacer layer including a protective material (e.g., a metal oxide and / or a metal nitride), and the sidewall spacer structure is disposed between the MTJ and the interconnect dielectric structure. A top electrode via couples the top electrode to an overlying interconnect wire. During the manufacture of the MRAM device, an etching process is performed to create a top electrode via opening in the interconnect dielectric structure above the top electrode. The protective sidewall spacer layer has a lower etching rate than the top electrode and / or the interconnect dielectric structure, so that the sidewall of the MTJ is not exposed after the etching process. Therefore, the protective sidewall spacer layer prevents over-etching of the MTJ during the etching process for defining the top electrode via opening, thereby preventing damage to the MTJ.

[0120] Figure 1A A cross-sectional view of some embodiments of an integrated chip 100 having a magnetoresistive random access memory (MRAM) cell 124 with a top electrode via 126 overlying a protective sidewall spacer layer 116 is shown.

[0121] The integrated chip 100 includes an MRAM cell 124 disposed within an interconnect dielectric structure 104 above a substrate 102. The MRAM cell 124 includes a magnetic tunnel junction (MTJ) 120 disposed between a top electrode 122 and a bottom electrode 110. In some embodiments, the MTJ 120 includes a fixed layer, a free layer, and a tunnel barrier layer disposed between the free layer and the fixed layer. The MRAM cell 124 is configured to store a data state based on a resistance value of the MRAM cell 124. For example, the MRAM cell 124 will store any of the following data states: storing a first data state (e.g., logic "0") when the MRAM cell 124 has a low resistance state or storing a second data state (e.g., logic "1") when the MRAM cell 124 has a high resistance state. During operation, the MTJ 120 can change between a low resistance state and a high resistance state via a tunnel magnetoresistance (TMR) effect. A bottom electrode via 108 is disposed below the MRAM cell 124. The bottom electrode via 108 is configured to electrically couple the MRAM cell 124 to the lower interconnect conductor 106 disposed within the interconnect dielectric structure 104. The top electrode via 126 overlies the top electrode 122, and the upper interconnect conductor 128 overlies the top electrode via 126.

[0122] The sidewall spacer structure 112 is disposed between the MTJ 120 and the interconnect dielectric structure 104. The sidewall spacer structure 112 includes a first sidewall spacer layer 114, a second sidewall spacer layer 118, and a protective sidewall spacer layer 116 disposed between the first sidewall spacer layer 114 and the second sidewall spacer layer 118. The first sidewall spacer layer 114 and the second sidewall spacer layer 118 may be or include, for example, silicon nitride, silicon carbide, etc. The protective sidewall spacer layer 116 may be or include, for example, a metal oxide (e.g., aluminum oxide), a metal nitride (e.g., aluminum nitride), etc. The protective sidewall spacer layer 116 directly contacts the sidewall of the top electrode 122 and extends continuously along the sidewall of the top electrode 122 and the sidewall of the MTJ 120 to the upper surface of the bottom electrode 110. The lower surface 126ls of the top electrode through hole 126 continuously extends along the upper surface of the protection sidewall spacer layer 116 and the upper surface 122us of the top electrode 122. The upper surface of the protection sidewall spacer layer 116 is vertically disposed above the lower surface 122ls of the top electrode 122.

[0123] In some embodiments, the lower surface 1261s of the top electrode via 126 has a width Wteva that is larger than the width Wte of the upper surface 122us of the top electrode 122. In addition, in some embodiments, the MTJ 120 has a width Wmtj that is smaller than the width Wteva but larger than the width Wte. In some embodiments, the width Wte of the top electrode 122 and / or the width Wmtj of the MTJ 120 is smaller than the minimum feature size of a photomask used to form the top electrode via 126 in a lithography system (e.g., a lithography system using 193 nanometer illumination). In these embodiments, the material and / or layout of the protective sidewall spacer layer 116 allows the top electrode via 126 to land more easily on the top electrode 122 rather than on the MTJ 120 during the manufacture of the MRAM cell 124, thereby preventing over-etching, which may damage the MRAM cell 124. Furthermore, in some embodiments, during fabrication of the integrated chip 100, the protective sidewall spacer layer 116 acts as an etch stop for the etching process used to form the opening where the top electrode via 126 is located. This in turn prevents over-etching from reaching the MTJ 120 and shorting the fixed and free layers of the MTJ 120 together.

[0124] Figure 1B Shown along Figure 1A A top view of an alternative embodiment of the integrated chip 100 is shown along line AA′ of the cross-sectional view.

[0125] like Figure 1B As shown in the top view of , the upper surface 122us and the lower surface 122ls of the top electrode 122 have circular shapes, respectively. In some embodiments, the upper surface 122us and / or the lower surface 122ls of the top electrode 122 may have any shape, such as a rectangular shape, a square shape, a rectangular shape with rounded corners (e.g., due to an etching process), or an elliptical shape, for example, when viewed from above. In addition, the width Wte of the upper surface 122us of the top electrode 122 is smaller than the width of the lower surface 122ls, wherein the upper surface 122us is laterally spaced between the perimeters of the lower surface 122ls. The upper surface and the lower surface 126ls of the top electrode through hole 126 have circular shapes, respectively. In some embodiments, the upper surface and / or the lower surface 126ls of the top electrode through hole 126 may have any shape, such as a rectangular shape, a square shape, a rectangular shape with rounded corners (e.g., due to an etching process), or an elliptical shape, for example, when viewed from above. Furthermore, the width Wteva of the lower surface 1261s of the top electrode via 126 is smaller than the width of the upper surface, wherein the lower surface 1261s is laterally spaced between the perimeters of the upper surface of the top electrode via 126. In some embodiments, each width of the aforementioned surfaces (e.g., width Wte, width Wteva, etc.) may correspond to a diameter of the surface.

[0126] Figure 2 Show according to Figure 1A 2 is a cross-sectional view of an integrated chip 200 of some alternative embodiments of the integrated chip 100 .

[0127] The integrated chip 200 includes an interconnect dielectric structure 104 above a substrate 102. The interconnect dielectric structure 104 includes a plurality of interlayer dielectric (ILD) layers 202, an interlayer dielectric layer 207 and / or a plurality of dielectric layers 204, a dielectric layer 206. In some embodiments, the plurality of ILD layers 202, the ILD layer 207 may include one or more of silicon dioxide, carbon doped oxide (SiCOH), fluorosilicate glass, etc. In some embodiments, the first dielectric layer 204 may include hydrogen and nitrogen doped carbide (HNDC), silicon carbide, etc. and / or may have a thickness of about 250 angstroms or some other suitable thickness. In some embodiments, the second dielectric layer 206 may be configured as an etch stop layer and / or may include silicon-rich oxide, silicon nitride, etc. and / or may have a thickness of about 270 angstroms or some other suitable thickness. The lower interconnect wire 106 is disposed in the first ILD layer 202 and is electrically coupled to the bottom electrode via 108. The bottom electrode via 108 includes a lower metal layer 210 and a diffusion barrier layer 208 .

[0128] The bottom electrode 110 is disposed in the second ILD layer 207 and overlies the bottom electrode through hole 108. The bottom electrode 110 includes a first bottom electrode layer 212 located below the second bottom electrode layer 214. In some embodiments, the first bottom electrode layer 212 can be or include, for example, tantalum, tantalum nitride, etc. and / or can have a thickness of about 100 angstroms or some other suitable thickness. In some embodiments, the second bottom electrode layer 214 can be or include, for example, titanium, titanium nitride, etc. and / or can have a thickness of about 100 angstroms or some other suitable thickness. In some embodiments, the first bottom electrode layer 212 can be or include, for example, a protrusion extending into the upper surface of the lower metal layer 210.

[0129] In some embodiments, the MTJ 120 may be or include, for example, a plurality of memory layers and / or may have a thickness of about 280 angstroms or some other suitable thickness. For example, the MTJ 120 may include a seed layer 216, a first fixed layer 218, a second fixed layer 220, a tunnel barrier layer 222, a free layer 224, and a cap layer 226. In some embodiments, the seed layer 216 may be or include one or more of nickel-chromium, cobalt-iron-boron, magnesium, tantalum, ruthenium, tantalum nitride, etc. and / or may have a thickness of about 20 angstroms or some other suitable thickness. In some embodiments, the first fixed layer 218 and / or the second fixed layer 220 may be or include one or more of iron, cobalt, nickel, iron-cobalt, nickel-cobalt, cobalt-iron-boron, iron-boron, iron-platinum, iron-palladium, etc., respectively. In some embodiments, the first fixed layer 218 or the second fixed layer 220 is omitted so that the MTJ 120 includes a single fixed layer. In addition, in some embodiments, the first fixed layer 218 and the second fixed layer 220 act as a single fixed layer of the MTJ 120. In some embodiments, the tunnel barrier layer 222 may be or include one or more of magnesium oxide (MgO), aluminum oxide (e.g., Al2O3), nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide, etc. In some embodiments, the free layer 224 may be or include one or more of iron, cobalt, nickel, iron cobalt, nickel cobalt, cobalt iron boron, iron boron, iron platinum, iron palladium, etc. In some embodiments, the cap layer 226 may be or include one or more of ruthenium, magnesium oxide, etc. and / or may have a thickness of about 30 angstroms or some other suitable thickness.

[0130] In some embodiments, the first fixed layer 218 and the second fixed layer 220 may each have a fixed or "pinned" magnetic orientation pointing in the same direction. The free layer 224 may have a variable or "free" magnetic orientation that can be switched between two or more different magnetic polarities representing different data states (e.g., different binary states). In some embodiments, if the magnetization directions of the first fixed layer 218 and the second fixed layer 220 and the free layer 224 are oriented in parallel, then charge carriers (e.g., electrons) will be likely to tunnel through the tunnel barrier layer 222, so that the MTJ 120 is in a low resistance state. Conversely, in some embodiments, if the first fixed layer 218 and the second fixed layer 220 and the free layer 224 are oriented in anti-parallel, then charge carriers (e.g., electrons) will be unlikely to tunnel through the tunnel barrier layer 222, so that the MTJ 120 is in a high resistance state. Under normal operation, the MTJ 120 can switch between a low resistance state and a high resistance state based on a bias applied between the top electrode via 126 and the bottom electrode via 108 .

[0131] The top electrode 122 overlies the MTJ 120. The top electrode 122 may be or include one or more of tungsten, titanium nitride, tantalum nitride, etc. and / or may have a thickness of about 350 angstroms or some other suitable thickness. The sidewall spacer structure 112 may continuously surround the opposite sidewalls of the top electrode 122 and the opposite sidewalls of the MTJ 120. In some embodiments, the opposite sidewalls of the MTJ 120 and / or the opposite sidewalls of the top electrode 122 are defined according to a cross-sectional view. For example, if the MRAM cell 124 is circular / elliptical when viewed from above, the opposite sidewalls of the MTJ 120 are a single continuous sidewall when viewed from above, and therefore, the opposite "sidewalls" of the MTJ 120 refer to the properties of such a single continuous sidewall when depicted in a cross-sectional view. Furthermore, if the MRAM cell 124 and / or the top electrode via 126 are circular or elliptical when viewed from above, any length or width associated with a cross-sectional view of a layer including the MRAM cell 124 and / or the top electrode via 126 corresponds to a diameter of the circle or a length defined between two vertices on the major axis of the ellipse, respectively.

[0132] The sidewall spacer structure 112 includes a first sidewall spacer layer 114, a second sidewall spacer layer 118, and a protective sidewall spacer layer 116 disposed between the first sidewall spacer layer 114 and the second sidewall spacer layer 118. The first sidewall spacer layer 114 includes an inner sidewall spacer layer 114a and an outer sidewall spacer layer 114b. The inner sidewall spacer layer 114a may extend continuously along the outer sidewall of the top electrode 122 to the outer sidewall of the MTJ 120. The inner sidewall spacer layer 114a and the outer sidewall spacer layer 114b may be or include silicon nitride, silicon carbide, etc.

[0133] The upper interconnect wire 128 and the top electrode via 126 are disposed in the second ILD layer 207 and overlying the top electrode 122. In some embodiments, the upper interconnect wire 128 and / or the top electrode via 126 may be or include copper, aluminum, a combination of the foregoing, etc. The top electrode via 126 includes a first protrusion 230, a second protrusion 232, and a third protrusion 234. In some embodiments, the first protrusion 230 and the third protrusion 234 are defined according to a cross-sectional view so that when viewed from above, the first protrusion 230 and the third protrusion 234 are a single continuous protrusion. The first protrusion 230 and the third protrusion 234 may each have a triangular shape and may extend through the second sidewall spacer layer 118 to contact the outer sidewall of the protective sidewall spacer layer 116. The second protrusion 232 may have a semicircular shape and may extend into the top electrode 122. In some embodiments, the bottom point of the first protrusion 230 may be vertically offset from the bottom point of the third protrusion 234 by a distance d1. In some embodiments, the height difference between the bottom points of the first protrusion 230 and the third protrusion 234 may be attributed to different etching rates among the second sidewall spacer layer 118, the second ILD layer 207, the top electrode 122, and the protective sidewall spacer layer 116 in the etching process used to manufacture the top electrode via 126. However, the top electrode via 126 directly contacts the protective sidewall spacer layer 116 and is laterally and / or vertically offset from the MTJ 120. Therefore, the material (e.g., aluminum nitride, aluminum oxide, etc.), etching rate, and / or shape of the protective sidewall spacer layer 116 allow the top electrode via 126 to land more easily on the top electrode 122 during the manufacture of the MRAM cell 124 while preventing over-etching from damaging the MRAM cell 124.

[0134] Figure 3 Show according to Figure 1A FIG. 1 is a cross-sectional view of an integrated chip 300 according to some alternative embodiments of the integrated chip 100 .

[0135] In some embodiments, the lowest point of the top electrode via 126 extends a distance d2 below the upper surface of the tunnel barrier layer 222. In some embodiments, the distance d2 is non-zero. The top electrode via 126 is laterally offset from the tunnel barrier layer 222 by the amount of the protective sidewall spacer layer 116. The MTJ 120 is laterally spaced between the opposite sidewalls of the protective sidewall spacer layer 116. In some embodiments, the top electrode via 126 extends continuously along a first sidewall of the opposite sidewalls of the protective sidewall spacer layer 116 and is laterally offset from a second sidewall of the opposite sidewalls of the protective sidewall spacer layer 116. In addition, the center of the top electrode 122 and the center of the MTJ 120 are respectively aligned with the first substantially straight line 302. The center of the top electrode via 126 and / or the center of the upper interconnect wire 128 are aligned with the second substantially straight line 304. The second substantially straight line 304 is laterally offset from the first substantially straight line 302 by a non-zero distance in a direction away from the MRAM cell 124. In some embodiments, the offset between the first substantially straight line 302 and the second substantially straight line 304 may be attributed to the misalignment of the photomask above the MTJ 120 (e.g., used in a lithography system) during the manufacture of the MRAM cell 124. Such misalignment may occur due to limitations of the tools used in the lithography system, and the misalignment may increase as the width Wmtj of the MTJ 120 decreases. In some embodiments, the width Wmtj is less than 75 nanometers. In these embodiments, the protective sidewall spacer layer 116 may prevent over-etching of the dielectric layer (e.g., the first sidewall spacer layer 114 and / or the tunnel barrier layer 222) around and / or within the MTJ 120. Therefore, the MTJ 120 is not exposed during the over-etching process, and the top electrode via 126 is laterally offset from the layer of the MTJ 120 by a non-zero distance. Therefore, the protective sidewall spacer layer 116 helps to scale down the size of the MRAM cell 124. In some embodiments, the maximum width of the tunnel barrier layer 222 is less than the minimum width of the top electrode via 126. In these embodiments, the maximum width of the tunnel barrier layer 222 may be approximately 75 nanometers or less or within a range of approximately 70 nanometers to 80 nanometers.

[0136] Figure 4 Show according to Figure 1A 4 is a cross-sectional view of an integrated chip 400 of some alternative embodiments of the integrated chip 100 .

[0137] like Figure 4, the top electrode via 126 and the upper interconnect wire 128 are continuous conductive structures. The top electrode via 126 and the upper interconnect wire 128 are composed of a conductor 402 surrounded by a conductive liner 404. In some embodiments, the conductor 402 can be or include, for example, aluminum, copper, alloys of the foregoing, etc. In other embodiments, the conductive liner 404 can be or include, for example, tungsten, titanium, etc. The conductor 402 can be a continuous conductive structure extending to a point below the top electrode 122, and the conductive liner 404 can extend continuously along the opposite sidewalls and lower surface of the conductor 402. In some other embodiments, the lower interconnect wire 106 may include the conductor 402 and the conductive liner 404.

[0138] Figure 5 A cross-sectional view of some embodiments of an integrated chip 500 including an embedded memory region 502 having an MRAM cell 124 laterally adjacent to a logic region 504 is shown.

[0139] like Figure 5 As shown in the cross-sectional view of , the dielectric protection layer 506 overlies the second ILD layer 207 in the embedded storage area 502. The dielectric protection layer 506 can be or include, for example, hydrogen and nitrogen doped carbide (HNDC), silicon carbide, etc. and / or can have a thickness of about 300 angstroms or some other suitable thickness. The third ILD layer 508 overlies the dielectric protection layer 506. The third ILD layer 508 can be or include, for example, an extremely low-k dielectric material or another suitable dielectric material. The first outer sidewall spacer layer 503 overlies and surrounds the sidewall spacer structure 112, and the second outer sidewall spacer layer 505 overlies the first outer sidewall spacer layer 503. The first outer sidewall spacer layer 503 can be or include, for example, silicon oxycarbide, silicon carbide, etc. and / or can have a thickness of about 150 angstroms or some other suitable thickness. The second outer sidewall spacer layer 505 may be or include, for example, silicon oxynitride, silicon nitride, etc. and / or may have a thickness of about 200 angstroms or some other suitable thickness.

[0140] In the logic region 504, the lower interconnect wire 106 is disposed in the first ILD layer 202. The first dielectric layer 204 and the second dielectric layer 206 overlie the lower interconnect wire 106. In addition, the third ILD layer 508 overlies the second dielectric layer 206. A conductive via 516 overlies the lower interconnect wire 106, and a conductive line 518 overlies the conductive via 516. In some embodiments, the conductive via 516 and the conductive line 518 may be or include, for example, copper, aluminum, aluminum copper, etc. In other embodiments, the conductive via 516 and the conductive line 518 may be a single continuous conductive structure. In some embodiments, the lower interconnect wire 106 disposed in the logic region 504 is electrically coupled to one or more semiconductor devices (e.g., transistors) disposed above and / or within the substrate 102. The one or more semiconductor devices may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0141] Figure 6 A cross-sectional view of some embodiments of an integrated chip 600 having an MRAM cell 124 disposed within an interconnect structure 602 and overlying a substrate 102 is shown.

[0142] like Figure 6 As shown in FIG. 1 , an interconnect structure 602 overlies a substrate 102. The substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. One or more shallow trench isolation (STI) regions 606 are disposed in the substrate 102, and transistors 608 are separated between the STI regions 606. The STI regions 606 may be or include trenches filled with oxide in the substrate 102.

[0143] The transistors 608 extend parallel to each other and include transistor gates 610, transistor dielectric layers 612, transistor sidewall spacer structures 614, and source / drain regions 618. The transistor gates 610 are disposed over corresponding transistor dielectric layers 612 and lined by corresponding transistor sidewall spacer structures 614. The source / drain regions 618 are embedded in the surface of the substrate 102 between the transistor gates 610 and the STI regions 606. The transistor gates 610 may be or include, for example, doped polysilicon or a metal such as titanium nitride or tantalum nitride, etc. The transistor dielectric layers 612 may be or include, for example, an oxide such as silicon dioxide, another suitable dielectric, etc. The transistor sidewall spacer structures 614 may be or include, for example, silicon nitride, silicon carbide, etc. The source / drain regions 618 correspond to, for example, doped regions of the substrate 102.

[0144] The interconnect structure 602 overlies the transistor 608. The interconnect structure 602 includes a plurality of ILD layers 620, a plurality of etch stop layers 626, a plurality of conductive lines 624, a plurality of conductive vias 622, redistribution wires 632, redistribution vias 630, a passivation layer 636, a passivation layer 638, and a bonding pad structure 634. A pair of MRAM cells 124 are disposed within the ILD layer 620 and stacked between the layers of conductive lines 624. The MRAM cells 124 are shown in FIG. Figure 1A and Figure 2 Conductive line 624 and conductive via 622 may be or include, for example, aluminum, copper, aluminum copper, etc. Conductive via 622 and conductive line 624 are configured to electrically couple MRAM cell 124 to transistor 608. Conductive via 622 located directly above MRAM cell 124 may be configured as Figure 1A The top electrode via 126 of the MRAM cell 124 is configured to electrically couple the MRAM cell 124 to an overlying bonding pad structure 634. The bonding pad structure 634 can be configured to electrically couple the integrated chip 600 to another integrated chip (not shown).

[0145] Figure 7 Show according to Figure 1A 100, wherein the top electrode via 126 directly contacts the ledge 1161 of the protective sidewall spacer layer 116. In some embodiments, the ledge 1161 of the protective sidewall spacer layer 116 continuously surrounds the top electrode 122 and is vertically disposed below the upper surface 122us of the top electrode 122.

[0146] Figure 8 Show according to Figure 1A 100, wherein the upper surface of the second sidewall spacer layer 118 includes a plurality of protrusions. In addition, the thickness Tfs of the first sidewall spacer layer 114 as measured from the sidewall of the MTJ 120 is in the range of about 100 angstroms to 130 angstroms.

[0147] Fig. 9A Show according to Figure 1A 9 is a cross-sectional view of an integrated chip 900 a according to some alternative embodiments of the integrated chip 100 , wherein an upper surface 122 us of the top electrode 122 is disposed below a top surface of the protective sidewall spacer layer 116 .

[0148] Fig. 9B Show according to Figure 1A 1 is a cross-sectional view of an integrated chip 900b of some alternative embodiments of the integrated chip 100, wherein the first MRAM cell 124a and the second MRAM cell 124b are disposed in the second ILD layer 207 and are laterally adjacent to each other. The first MRAM cell 124a and the second MRAM cell 124b may be configured as follows: Figure 1A The MRAM cell 124 shown and described in FIG.

[0149] In some embodiments, the thickness Tsp of the sidewall spacer structure 112 of the first MRAM cell 124a and the second MRAM cell 124b as measured from the outer sidewall of the MTJ 120 is less than about 400 angstroms. The thickness Tsp of the sidewall spacer structure 112 may be the maximum thickness of the sidewall spacer structure 112. In some embodiments, if the thickness Tsp is greater than 400 angstroms, the lateral distance dlat between the first MRAM cell 124a and the second MRAM cell 124b is reduced, and thus the process for forming the second ILD layer 207 around the first MRAM cell 124a and the second MRAM cell 124b may be adversely affected. For example, because the lateral distance dlat is reduced, the second ILD layer 207 may be unevenly deposited between and / or over the first MRAM cell 124a and the second MRAM cell 124b (e.g., due to manufacturing tool limitations), thereby creating gaps and / or voids in the second ILD layer 207. This may, to some extent, cause the conductive structures and / or layers to be electrically shorted together (e.g., due to delamination of adjacent layers and / or structures), thereby causing device failure. In other embodiments, if the thickness Tsp is substantially less than 400 angstroms (e.g., the thickness Tsp is less than 50 angstroms), the sidewall spacer structure 112 may not properly protect the sidewalls of the MTJ 120 and / or the sidewalls of the top electrode 122 during device fabrication.

[0150] Fig. 10A Show according to Figure 1A1 is a cross-sectional view of an integrated chip 1000a of some alternative embodiments of the integrated chip 100 of FIG. 1 , wherein the first dielectric protection layer 1002 overlies the second ILD layer 207 in the embedded storage area 502. The second dielectric protection layer 1004 overlies the first dielectric protection layer 1002. In addition, the upper ILD layer 1006 extends continuously from above the second dielectric protection layer 1004 in the embedded storage area 502 to above the second dielectric layer 206 in the logic area 504. In some embodiments, the first dielectric protection layer 1002 can be or include, for example, silicon nitride, silicon carbide, etc. In other embodiments, the second dielectric protection layer 1004 can be or include, for example, silicon oxycarbide or another suitable dielectric material. In still other embodiments, the upper ILD layer 1006 can be or include, for example, a low-k dielectric material, silicon oxycarbide, or another suitable dielectric material.

[0151] Fig. 10B Show according to Figure 1A 100b of some alternative embodiments of the integrated chip 100 of the present invention, wherein the upper ILD structure 1007 extends continuously from the MRAM cell 124 to above the lower interconnect wire 106 disposed in the logic region 504. In some embodiments, the upper ILD structure 1007 can be or include, for example, a low-k dielectric material, silicon oxycarbide, or another suitable dielectric material. In other embodiments, the upper interconnect wire 128 directly contacts the top electrode 122.

[0152] Fig. 10C Show according to Figure 1A 1000c of some alternative embodiments of the integrated chip 100 of the present invention, wherein the dielectric filling layer 1008 is disposed around the first MRAM cell 124a and the second MRAM cell 124b. In addition, the upper ILD structure 1007 is disposed above the first MRAM cell 124a and the second MRAM cell 124b. In some embodiments, the upper interconnect wire 128 is disposed above each of the first MRAM cell 124a and the second MRAM cell 124b and directly contacts the top electrode 122. In some embodiments, the dielectric filling layer 1008 may be or include, for example, tetra-ethyl-ortho-silicate (TEOS) (e.g., plasma-enhanced TEOS, low-particle TEOS, etc.), an oxide (e.g., silicon oxide, silicon dioxide, etc.), a nitride, etc. In other embodiments, the upper ILD structure 1007 may be or include, for example, a low-k dielectric material, silicon oxycarbide, or another suitable dielectric material.

[0153] Figures 11 to 17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20 , Fig.21A , Fig.21B as well as Fig. 22 Various views 1100 to 1700, 1800a, 1800b, 1900, 2000, 2100a, 2100b, and 2200 of some embodiments of a first method of forming an integrated chip having an MRAM cell including a top electrode via overlying a protective sidewall spacer layer. Although the method is described with reference to FIG. Figures 11 to 17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20 , Fig.21A , Fig.21B as well as Fig. 22 1100 to 1700, 1800a, 1800b, 1900, 2000, 2100a, 2100b, and 2200 are shown in FIG. 1100 , but it should be understood that Figures 11 to 17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20 , Fig.21A , Fig.21B as well as Fig. 22 The structure shown in FIG. 1 is not limited to the first method, but can be independently independent of the method. Figures 11 to 17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20 , Fig.21A , Fig.21B as well as Fig. 22 Described as a series of actions, it should be understood that these actions are not limited to the order of the actions and can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0154] like Fig.11As shown in the cross-sectional view 1100 of FIG. 1 , a first interlayer dielectric (ILD) layer 202 is formed over a substrate (not shown). A lower interconnect wire 106 is formed in the embedded memory region 502 and the logic region 504. In some embodiments, the lower interconnect wire 106 may be or include, for example, copper, aluminum, tungsten, a combination thereof, or the like. A first dielectric layer 204 is formed over the first ILD layer 202, and a second dielectric layer 206 is formed over the first dielectric layer 204. In some embodiments, the first dielectric layer 204 may be or include, for example, hydrogen and nitrogen doped carbide (HNDC), silicon carbide, etc., and / or may be formed to a thickness of about 250 angstroms. In some embodiments, the second dielectric layer 206 may be or include, for example, silicon-rich oxide, silicon nitride, etc., and / or may be formed to a thickness of about 270 angstroms. The first dielectric layer 204 and / or the second dielectric layer 206 may be formed by performing a deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or another suitable deposition process, respectively. After deposition, the first dielectric layer 204 and / or the second dielectric layer 206 are selectively patterned to define bottom electrode via openings extending through the first dielectric layer 204 and / or the second dielectric layer 206 to the underlying lower interconnect wire 106 in the embedded memory region 502.

[0155] In some embodiments, the bottom electrode via 108 is formed within the bottom electrode via opening and contacts the lower interconnect wire 106. In some embodiments, the bottom electrode via 108 may be formed by forming a diffusion barrier layer 208 within the bottom electrode via opening. The diffusion barrier layer 208 may be configured to prevent diffusion between adjacent layers. In some embodiments, the diffusion barrier layer 208 may be configured as a conductive liner and / or may include a colloidal layer configured to increase adhesion between adjacent layers. A lower metal layer 210 is formed above the diffusion barrier layer 208 within the bottom electrode via opening. The diffusion barrier layer 208 and / or the lower metal layer 210 may be deposited, for example, by CVD, PVD, sputtering, electroless plating, or another suitable growth or deposition process. A planarization process (e.g., a chemical mechanical planarization (CMP) process) may then be performed. In some embodiments, the lower metal layer 210 may be or include, for example, tantalum, titanium, or the like. The diffusion barrier layer 208 may be or include, for example, titanium nitride, tantalum nitride, or the like.

[0156] Also in Fig.11, a bottom electrode stack 1101 is formed over the second dielectric layer 206 and the bottom electrode via 108. The bottom electrode 1101 may include a first bottom electrode layer 212 located below the second bottom electrode layer 214. In some embodiments, the first bottom electrode layer 212 and / or the second bottom electrode layer 214 may be formed by, for example, CVD, PVD, sputtering, or another suitable deposition or growth process, respectively. After forming the bottom electrode stack 1101, a memory cell stack 1103 is formed over the bottom electrode stack 1101. The memory cell stack 1103 includes a seed layer 216, a first fixed layer 218, a second fixed layer 220, a tunnel barrier layer 222, a free layer 224, and a cap layer 226. The layers of the memory cell stack 1103 may be formed by, for example, CVD, PVD, sputtering, electroless plating, or another suitable deposition or growth process, respectively. After forming the memory cell stack 1103, a top electrode layer 1104 is formed above the memory cell stack 1103, and a top electrode capping layer 1106 is formed above the top electrode layer 1104. In some embodiments, the top electrode layer 1104 and / or the top electrode capping layer 1106 may be formed by, for example, CVD, PVD, sputtering, electroless plating, or another suitable deposition or growth process, respectively.

[0157] like Fig.12 1200, a patterning process is performed to define a magnetic tunnel junction (MTJ) 120 and a top electrode 122. In some embodiments, the patterning process includes: 1) forming a masking layer (not shown) above the top electrode cap layer 1106; 2) exposing an unmasked area of ​​a layer below the masking layer to one or more etchants, thereby defining the MTJ 120 and the top electrode 122; and 3) performing a removal process to remove the masking layer. In some embodiments, the second bottom electrode layer 214 can be used as an etch stop layer during the aforementioned patterning process. In some embodiments, the top electrode 122 is formed to a thickness Tte of about 350 angstroms or some other suitable thickness.

[0158] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the inner sidewall spacer layer 114a is formed above and around the top electrode 122 and the MTJ 120. Subsequently, the outer sidewall spacer layer 114b is formed above the inner sidewall spacer layer 114a. In some embodiments, the inner sidewall spacer layer 114a and / or the outer sidewall spacer layer 114b may be or include silicon nitride, silicon oxynitride, etc. The inner sidewall spacer layer 114a and / or the outer sidewall spacer layer 114b may be formed by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. In other embodiments, the inner sidewall spacer layer 114a and the outer sidewall spacer layer 114b each have a top surface disposed above the top surface of the top electrode 122.

[0159] like Fig.14 As shown in the cross-sectional view 1400, the inner sidewall spacer layer and the outer sidewall spacer layer ( Fig.13 The inner sidewall spacer layer 114a and the outer sidewall spacer layer 114b are patterned to define the first sidewall spacer layer 114. Fig.14 The upper portion of the inner sidewall spacer layer 114a is shown by a dotted line in FIG. 1 , and it is understood that the upper portion of the inner sidewall spacer layer 114a is removed during the patterning process. In some embodiments, the patterning process may completely remove the outer sidewall spacer layer ( Fig.13 In other embodiments, the patterning process may retain at least a portion of the outer sidewall spacer layer ( Fig.13 The outer sidewall spacer layer 114b), see for example Figures 2 to 5 In some embodiments, the patterning process may include performing a blanket etching process, a wet etching process, a dry etching process, a combination of the foregoing, or another suitable etching process.

[0160] The first sidewall spacer layer 114 is configured to protect the outer sidewalls of the MTJ 120 and is formed to have a height h1 as measured from the top surface of the second bottom electrode layer 214. In some embodiments, the substantially straight line 1402 is disposed at the midpoint of the top electrode 122. For example, in some embodiments, if the thickness Tte of the top electrode 122 is approximately 350 angstroms, the substantially straight line 1402 is disposed at a point of the top electrode 122 that is approximately 175 angstroms above the bottom surface of the top electrode 122. The patterning of the inner sidewall spacer layer 114a and the outer sidewall spacer layer 114b is performed in such a manner that the top surface of the first sidewall spacer layer 114 is disposed at or below the midpoint of the top electrode 122. In these embodiments, the top surface of the first sidewall spacer layer 114 is located above the top surface of the MTJ 120.

[0161] In addition, if Fig.14 As shown in FIG, the inner sidewall spacer layer and the outer sidewall spacer layer ( Fig.13The patterning process performed on the first sidewall spacer layer 114a, the outer sidewall spacer layer 114b) is configured to reduce the initial height hin of the inner sidewall spacer layer 114a to a height h1 (i.e., over-etch the inner sidewall spacer layer 114a). For example, the ratio of the height h1 to the initial height hin (e.g., h1:hin) is approximately 1:1.8, 1:2, 1:2.4, or in the range of approximately 1:1.8 to 2.4. In some embodiments, if the ratio of the height h1 to the initial height hin is less than 1:1.8, the top surface of the first sidewall spacer layer 114 may be disposed above the midpoint of the top electrode 122 (e.g., the top surface of the first sidewall spacer layer 114 is vertically located above the substantially straight line 1402). This may cause damage to adjacent layers during subsequent process steps (e.g. Fig.18A The patterning process may over-etch the vertical segments of the protective sidewall spacer 116 contacting the top electrode 122 and remove the vertical segments), thereby reducing the process yield of the MTJ 120. In other embodiments, if the ratio of the height h1 to the initial height hin is greater than 1:2.4, the top surface of the first sidewall spacer layer 114 may be disposed below the top surface of the MTJ 120, which may hinder the ability of the first sidewall spacer layer 114 to protect the outer sidewalls of the MTJ 120.

[0162] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , the protective sidewall spacer layer 116 is formed above the top electrode 122, the MTJ 120, and the first sidewall spacer layer 114. In some embodiments, the protective sidewall spacer layer 116 may be or include, for example, a metal oxide (e.g., aluminum oxide (e.g., AlO x , where x is a positive integer)) and / or may be formed to a thickness in the range of about 30 angstroms to 50 angstroms. In other embodiments, the protective sidewall spacer layer 116 may be or include, for example, a metal nitride (e.g., aluminum nitride) and / or may be formed to a thickness in the range of about 40 angstroms to 100 angstroms. However, other thicknesses and / or materials are also suitable for the protective sidewall spacer layer 116. The protective sidewall spacer layer 116 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process. In addition, because the top surface of the first sidewall spacer layer 114 has a height h1 (e.g., Fig.14 ), so the lateral section 116ls of the protective sidewall spacer layer 116 is disposed above the top surface of the MTJ 120. This can improve the structural integrity of the protective sidewall spacer layer 116. Fig.14 In this way, a protective sidewall spacer layer 116 can be formed to prevent subsequent processing steps (e.g., see Fig.18A). In some embodiments, the protective sidewall spacer layer 116 is configured as an etch stop layer. In these embodiments, in forming the overlying top electrode via ( Fig. 22 The etching process (eg, Fig.21A During one or more etching processes of the protective sidewall spacer layer 116, the etching process has a low selectivity to the protective sidewall spacer layer 116 relative to the adjacent dielectric material (eg, the first sidewall spacer layer 116).

[0163] like Fig.16 As shown in cross-sectional view 1600 of , a second sidewall spacer layer 118 is formed over the protective sidewall spacer layer 116, and an upper dielectric layer 1602 may be formed over the second sidewall spacer layer 118. In some embodiments, the upper dielectric layer 1602 may be configured to protect the underlying layer during subsequent processing steps (e.g., during an etching process). In some embodiments, the second sidewall spacer layer 118 may be or include, for example, silicon nitride or some other suitable material and / or may be formed to a thickness of about 260 angstroms or some other suitable thickness. In some embodiments, the second sidewall spacer layer 118 is or includes the same material as the first sidewall spacer layer 114. The upper dielectric layer 1602 may be or include, for example, an oxide (e.g., silicon dioxide), another suitable oxide, or some other suitable material and / or may be formed to a thickness of about 150 angstroms or some other suitable thickness. In some embodiments, the second sidewall spacer layer 118 and / or the upper dielectric layer 1602 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process, respectively.

[0164] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , the second sidewall spacer layer 118 and the upper dielectric layer ( Fig.16 The upper dielectric layer 1602 of the protective sidewall spacer layer 116 is patterned to expose the upper surface of the protective sidewall spacer layer 116. In some embodiments, the patterning process includes, for example, performing wet etching, dry etching, blanket etching, or another suitable etching process. In some embodiments, Fig.17 During the patterning process of the protective sidewall spacer layer 116, the protective sidewall spacer layer 116 is configured as an etch stop layer. In these embodiments, relative to the second sidewall spacer layer 118 and the upper dielectric layer ( Fig.16 The upper dielectric layer 1602 of the top electrode is formed by the patterning process, and the patterning process has a low selectivity to the protective sidewall spacer layer 116, so that the protective sidewall spacer layer 116 remains above the top electrode cap layer 1106 after the patterning process.

[0165] like Fig.18A The cross-sectional view 1800a and Fig.18B As shown in the top view 1800b, Fig.17A patterning process is performed on the structure of the MRAM cell 124 , thereby defining the sidewall spacer structure 112 and the bottom electrode 110 . Fig.18B Shown along line BB' Fig.18A A top view 1800b of an alternative embodiment of the cross-sectional view 1800a is shown.

[0166] The bottom electrode 110 includes a first bottom electrode layer 212 and a second bottom electrode layer 214. The sidewall spacer structure 112 includes a first sidewall spacer layer 114 and a second sidewall spacer layer 118 and a protective sidewall spacer layer 116. The patterning process defines and exposes the upper surface of the top electrode 122, and the top electrode cap layer ( Fig.17 In some embodiments, the upper surface of the top electrode 122 is rounded due to over-etching during the patterning process. The patterning process removes a portion of the protective sidewall spacer layer 116 above the upper surface of the top electrode 122 and removes another portion of the protective sidewall spacer layer 116 contacting the second bottom electrode layer 214.

[0167] In some embodiments, the patterning process may include performing a dry etching process until the upper surface of the second dielectric layer 206 is reached. In some embodiments, the dry etching process may include using one or more etchants, such as a chlorine-based etchant. For example, the chlorine-based etchant may be or include, for example, boron chloride (e.g., BCl3), chlorine gas (Cl2), a combination of the foregoing, and the like. In some embodiments, the dry etching process may selectively etch the top electrode 122, the top electrode cap layer ( Fig.17 The protective sidewall spacer layer 116 can be selectively etched at a second etch rate, wherein the second etch rate is less than the first etch rate. For example, the first etch rate may be at least 5 times greater than the second etch rate. Therefore, the etching process used to form the bottom electrode 110 and / or the MRAM cell 124 has a low selectivity to the protective sidewall spacer layer 116 relative to adjacent layers (e.g., the first sidewall spacer layer 114 and / or the second sidewall spacer layer 118, the top electrode 114, and / or the first bottom electrode layer 212 and / or the second bottom electrode layer 214). This helps to form the MRAM cell 124 and the bottom electrode 110 to some extent while preventing damage to the protective sidewall spacer layer 116. Therefore, the protective sidewall spacer layer 116 can be selectively etched at a second etch rate, wherein the second etch rate is less than the first etch rate. For example, the first etch rate may be at least 5 times greater than the second etch rate. Therefore, relative to adjacent layers (e.g., the first sidewall spacer layer 114 and / or the second sidewall spacer layer 118, the top electrode 114, and / or the first bottom electrode layer 212 and / or the second bottom electrode layer 214). FIG. 21A to FIG. 21B ) to protect the MTJ 120 and / or the top electrode 122 during.

[0168] In some embodiments, FIG. 18A to FIG. 18BDuring the patterning process of , the second sidewall spacer layer 118 can be etched, for example, at a rate of about 430 angstroms per minute (Å / min), and the protective sidewall spacer layer 116 can be etched at a rate of about 80 Å / min or less. Therefore, in some embodiments, the etching rate of the protective sidewall spacer layer 116 is at least 5 times less than the etching rate of the second sidewall spacer layer 118 (and / or the first sidewall spacer layer 114). This is in part because the protective sidewall spacer layer 116 includes a first material (e.g., aluminum oxide) and the first sidewall spacer layer and / or the second sidewall spacer layer each include a second material different from the first material (e.g., silicon nitride). In some embodiments, if it is not as Fig.14 The first sidewall spacer layer 114 is defined as described in FIG. 18A to FIG. 18B The lateral section 1161s of the protective sidewall spacer layer 116 is damaged and / or removed during the patterning process of Fig.17 The patterning process performed on the top electrode 122 may over-etch and remove a portion of the top electrode 122 and / or the protective sidewall spacer layer 116 below the substantially straight line 1402. In these embodiments, the lateral segment 1161s of the protective sidewall spacer layer 116 may be removed. This may be removed in a subsequent processing step (e.g., in FIG. 21A to FIG. 21B During the process of MTJ 120 being damaged. Fig.18B As shown in the top view 1800 b , the protective sidewall spacer layer 116 continuously surrounds the top electrode 122 .

[0169] like Fig.19 As shown in cross-sectional view 1900 of , a first outer sidewall spacer layer 503 and a second outer sidewall spacer layer 505 are formed over the MRAM cell 124. In some embodiments, the first outer sidewall spacer layer 503 may be or include, for example, silicon oxycarbide and / or may be formed to a thickness of about 150 angstroms. In some embodiments, the second outer sidewall spacer layer 505 may be or include, for example, silicon oxynitride and / or may be formed to a thickness of about 200 angstroms. A second ILD layer 207 is formed over the first outer sidewall spacer layer 503 and the second outer sidewall spacer layer 505. The second ILD layer 207 may be or include, for example, an oxide (e.g., silicon dioxide) or another suitable dielectric material. A dielectric cap layer 506 is formed over the second ILD layer 207. In some embodiments, the dielectric cap layer 506 may be or include, for example, hydrogen and nitrogen doped carbide (HNDC) or another suitable dielectric material and / or may be formed to a thickness of about 300 angstroms. In some embodiments, the first outer sidewall spacer layer 503 and / or the second outer sidewall spacer layer 505 , the second ILD layer 207 , and / or the dielectric cap layer 506 may be deposited, for example, by CVD, PVD, ALD, or another suitable growth or deposition process, respectively.

[0170] like Fig. 20 As shown in the cross-sectional view 2000 of , the first outer sidewall spacer layer 503 and / or the second outer sidewall spacer layer 505, the second ILD layer 207 and / or the dielectric protection layer 506 are patterned in the logic area 504. Therefore, the aforementioned layers and / or structures are removed from the logic area 504. The patterning process may include: 1) forming a masking layer (not shown) above the embedded storage area 502; 2) exposing the logic area 504 to one or more etchants; and 3) removing the masking layer. In addition, the third ILD layer 508 is formed above the embedded storage area 502 and the logic area 504. The first upper dielectric layer 2002 is formed above the third ILD layer 508, the second upper dielectric layer 2004 is formed above the first upper dielectric layer 2002, and the masking layer 2006 is formed above the second upper dielectric layer 2004. Masking layer 2006 includes sidewalls defining first conductive feature opening 2008 overlying MRAM cell 124 and second conductive feature opening 2010 overlying lower interconnect wire 106 in logic region 504. In some embodiments, masking layer 2006 is patterned to form first conductive feature opening 2008 and second conductive feature opening 2010.

[0171] In some embodiments, the first upper dielectric layer 2002 may be or include, for example, an extremely low-k dielectric material or another suitable dielectric material. The second upper dielectric layer 2004 may be or include, for example, a low-k dielectric material, a nitrogen free anti-reflection layer (NFARL), etc. The masking layer 2006 may be or include, for example, titanium nitride or another suitable material and / or may be formed to a thickness in the range of about 300 angstroms to 400 angstroms.

[0172] like Fig.21A The cross-sectional view 2100a and Fig.21B As shown in the top view 2100b, according to the masking layer 2006 Fig. 20 A patterning process is performed on the structure, thereby enlarging the first conductive feature opening 2008 and the second conductive feature opening 2010. Fig.21B Shown along line CC' Fig.21A A top view 2100b of an alternative embodiment of the cross-sectional view 2100a is shown.

[0173] In some embodiments, the patterning process includes performing one or more etching processes and exposing the unmasked area of ​​the layer below the masking layer 2006 to one or more etchants. The one or more etching processes may include performing a first dry etching process in the first upper dielectric layer 2002 and the second upper dielectric layer 2004, the third ILD layer 508, the dielectric protection layer 506, and the second ILD layer 207 until reaching the upper surface 505us of the second outer sidewall spacer layer 505. In these embodiments, the second outer sidewall spacer layer 505 may not be etched by the first dry etching process. The one or more etching processes further include performing a second dry etching process (e.g., a liner removal process (LMR)) to remove at least a portion of the first outer sidewall spacer layer 503 and the second outer sidewall spacer layer 505 and / or the second sidewall spacer layer 118. In some embodiments, the second dry etching process may utilize one or more etchants, such as carbon fluoride (e.g., C4F8), argon (Ar), oxygen (O2), a combination of the foregoing, and the like. In some embodiments, the second dry etching process may etch the first outer sidewall spacer layer 503 and the second outer sidewall spacer layer 505 and / or the second sidewall spacer layer 118 at a rate at least 5 times faster than etching the protective sidewall spacer layer 116. One or more etching processes may further include performing a wet etching process. In some embodiments, the second etching process and / or the wet etching process may remove at least a portion of the top electrode 122, so that the top electrode 122 may have a curved and / or concave upper surface 122us. In some embodiments, the patterning process may include performing a dual damascene process.

[0174] In some embodiments, the etching process or processes are continued for a time longer than required to ensure that the dielectric material is removed from the top electrode 122, thereby ensuring that the subsequently formed top electrode vias ( Fig. 22 The top electrode through hole 126 of the first conductive feature opening 2008 makes good and / or stable electrical contact (e.g., ohmic contact) with the top electrode 122. This makes the minimum width W1 of the first conductive feature opening 2008 greater than the width Wmtj of the MTJ 120 to some extent. However, because the protective sidewall spacer layer 116 has a lower etching rate than the adjacent layers and / or structures (e.g., the first outer sidewall spacer layer 503 and / or the second outer sidewall spacer layer 505, the second sidewall spacer layer 118, the second ILD layer 207 and / or the top electrode 122) (as described above and / or as described in FIG. 18A to FIG. 18B), so the protective sidewall spacer layer 116 continues to surround and / or directly contact the outer sidewalls of the top electrode 122 after the patterning process. This ensures that the protective sidewall spacer layer 116 remains and continues to protect the sidewalls of the top electrode 122 and the MTJ 120 during the over-etching period, thereby preventing the top electrode 122 and the MTJ 120 from being etched during the patterning process and during subsequent processing steps (e.g. Fig. 22 During the formation of the top electrode through hole 126), the MTJ 120 is damaged.

[0175] like FIG. 21A to FIG. 21B As shown in FIG. 2 , the minimum width W1 of the first conductive feature opening 2008 is greater than the width Wmtj of the MTJ 120. In some embodiments, the width Wmtj of the MTJ 120 is the maximum width of the MTJ 120. Because the top electrode 122 is formed with the MTJ 120 (see FIG. 2 ), the width Wmtj of the MTJ 120 is greater than the width Wmtj of the MTJ 120. Fig.12 ), the maximum width of the top electrode 122 is less than the width Wmtj. Therefore, the width W1 is greater than the maximum width of the top electrode 122.

[0176] like Fig. 22 As shown in the cross-sectional view 2200 of FIG. 1 , the top electrode via 126 and the upper interconnect conductor 128 are formed above the MRAM cell 124, and the conductive via 516 and the conductive line 518 are formed above the lower interconnect conductor 106 in the logic region 504. In some embodiments, the process for forming the top electrode via 126, the upper interconnect conductor 128, and the conductive via 516 and the conductive line 518 includes: 1) depositing a conductive material (e.g., copper, aluminum, titanium nitride, tungsten, a combination of the foregoing, etc.) in the first conductive feature opening 2008 and the second conductive feature opening 2010 (e.g., by CVD, PVD, electroless plating, sputtering, etc.); 2) performing a planarization process (e.g., CMP) in the conductive material until the upper surface of the third ILD layer 508 is reached. In some embodiments, the planarization process removes the masking layer ( Fig.21A The masking layer 2006) and the first upper dielectric layer and the second upper dielectric layer ( Fig.21A In some embodiments, depositing the conductive material may include forming a conductive liner (eg, titanium nitride, tungsten, etc.) and then forming a conductive body (eg, aluminum, copper, aluminum copper, etc.) over the conductive liner.

[0177] Fig.23 A flow chart illustrating some embodiments of a first method 2300 of forming an integrated chip having an MRAM cell including a top electrode via overlying a protective sidewall spacer layer.

[0178] Although the first method 2300 is shown and described as a series of actions or events in this article, it should be understood that the order shown in these actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described in this article, some actions may occur in different orders and / or at the same time with other actions or events. In addition, not all of the actions shown may be needed to implement one or more aspects or embodiments described in this article. In addition, one or more of the actions described in this article can be performed with one or more separate actions and / or stages.

[0179] At act 2302, one or more interconnect layers are formed over a substrate. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 2302 .

[0180] At act 2304, a memory cell stack and a top electrode layer are formed over the one or more lower interconnect layers. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 2304 .

[0181] At act 2306, the memory cell stack and the top electrode layer are patterned to define a top electrode over the magnetic tunnel junction (MTJ). Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 2306 .

[0182] At act 2308, a first sidewall spacer layer is formed around the outer sidewalls of the top electrode and the outer sidewalls of the MTJ. Fig.13 and Fig.14 Cross-sectional view 1300 and cross-sectional view 1400 are shown corresponding to some embodiments of act 2308 .

[0183] At act 2310, a protective sidewall spacer layer is formed over the top electrode and the first sidewall spacer layer. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 2310 .

[0184] At act 2312, a second sidewall spacer layer is formed over the protective sidewall spacer layer. Fig.16 and Fig.17 Cross-sectional view 1600 and cross-sectional view 1700 are shown corresponding to some embodiments of act 2312 .

[0185] At act 2314, the protective sidewall spacer layer and the second sidewall spacer layer are patterned to expose a top surface of the top electrode. Fig.18A A cross-sectional view 1800a corresponding to some embodiments of act 2314 is shown.

[0186] At act 2316, an upper interlayer dielectric (ILD) structure is formed over the MTJ. Fig.19 and Fig. 20 Cross-sectional view 1900 and cross-sectional view 2000 are shown corresponding to some embodiments of act 2316 .

[0187] At act 2318, the upper ILD structure and the second sidewall spacer layer are patterned to define a top electrode via opening above the top electrode. The patterning exposes an upper surface and sidewalls of the protective sidewall spacer layer. Fig.21A A cross-sectional view 2100a corresponding to some embodiments of act 2318 is shown.

[0188] At act 2320, a top electrode via is formed in the top electrode via opening. A minimum width of the top electrode via is greater than a maximum width of the MTJ. Fig. 22 Cross-sectional view 2200 is shown corresponding to some embodiments of act 2320 .

[0189] Figure 24 to Figure 33 Cross-sectional views 2400 to 3300 illustrate some embodiments of a second method of forming an integrated chip having an MRAM cell including a protective sidewall spacer layer. Although referring to the method description Figure 24 to Figure 33 Various views 2400 to 3300 are shown, but it should be understood that Figure 24 to Figure 33 The illustrated structure is not limited to the second method but can actually be independent of said method. Figure 24 to Figure 33 Described as a series of actions, it should be understood that these actions are not limited to the order of the actions and can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0190] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 1 , the top electrode 122 is formed above the MTJ 120, and the first sidewall spacer layer 114 is formed around the top electrode 122 and the MTJ 120. In some embodiments, for example, Figure 11 to Figure 14 The top electrode 122, the MTJ 120 and the first sidewall spacer layer 114 are formed by the processing steps shown and described in FIG. In these embodiments, the top electrode cap layer ( Fig.14 top electrode cap layer 1106).

[0191] like Fig.252500, the first bottom electrode layer 212 and the second bottom electrode layer 214 are patterned to define the bottom electrode 110 and the MRAM cell 124. In some embodiments, the patterning process may include: forming a masking layer (not shown) over the top electrode 122 and the MTJ 120; exposing unmasked areas of the first bottom electrode layer 212 and the second bottom electrode layer 214 to one or more etchants to define the bottom electrode 110; and performing a removal process to remove the masking layer.

[0192] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 26 , the protective sidewall spacer layer 116 is formed above the top electrode 122, the MTJ 120, and the first sidewall spacer layer 114. In some embodiments, the protective sidewall spacer layer 116 may be or include, for example, a metal oxide, such as aluminum oxide (e.g., AlO x , where x is a positive integer) and / or may be formed to a thickness in the range of about 30 angstroms to 100 angstroms. In other embodiments, the protective sidewall spacer layer 116 may be or include, for example, a metal nitride (e.g., aluminum nitride) and / or may be formed to a thickness in the range of about 30 angstroms to 100 angstroms. However, other thicknesses and / or materials are also suitable for the protective sidewall spacer layer 116. The protective sidewall spacer layer 116 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process.

[0193] like Fig. 27 As shown in the cross-sectional view 2700 of , the second sidewall spacer layer 118 is formed on the protective sidewall spacer layer 116. The second ILD layer 207 is formed on the second sidewall spacer layer 118, and the first dielectric protection layer 1002 is formed on the second ILD layer 207. In some embodiments, the second sidewall spacer layer 118, the second ILD layer 207 and / or the first dielectric protection layer 1002 are deposited separately, for example, by CVD, PVD, ALD or another suitable deposition process.

[0194] like Fig.28 As shown in the cross-sectional view 2800, Fig. 27 A planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed on the structure. In addition, after the planarization process is performed, a second dielectric protection layer 1004 is formed over the first dielectric protection layer 1002 and the second ILD layer 207. In some embodiments, the second dielectric protection layer 1004 can be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process.

[0195] like Fig.29 As shown in the cross-sectional view 2900 of Fig.28The structure of the present invention is subjected to a patterning process to remove the layer of the second dielectric layer 206 overlying the logic region 504. In these embodiments, the protective sidewall spacer layer 116 is completely removed from the logic region 504, so that the second dielectric layer 206 can be over-etched by the patterning process. In addition, in some embodiments, the patterning process may include: forming a masking layer (not shown) above the MRAM cell 124; exposing the unmasked area of ​​the logic region 504 to one or more etchants, thereby exposing the upper surface of the second dielectric layer 206 in the logic region 504; and performing a removal process to remove the masking layer.

[0196] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 300 , an upper ILD layer 1006 is formed over the embedded memory region 502 and the logic region 504. In some embodiments, the upper ILD layer 1006 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process. In some embodiments, the upper ILD layer 1006 may be or include, for example, a low-k dielectric material, silicon oxycarbide, another suitable dielectric material, or the like.

[0197] like Fig.31 As shown in the cross-sectional view 3100, Fig.30 The structure of the MRAM cell 124 is patterned to define a first conductive feature opening 2008 in the embedded memory region 502 and a second conductive feature opening 2010 in the logic region 504. In some embodiments, the patterning process includes: forming a masking layer (not shown) over the upper ILD layer 1006; exposing an unmasked area of ​​a layer below the masking layer to one or more etchants to define the first conductive feature opening 2008 and the second conductive feature opening 2010; and removing the masking layer. In some embodiments, the masking layer (not shown) includes sidewalls defining the first conductive feature opening 2008 overlying the MRAM cell 124 and sidewalls defining the second conductive feature opening 2010 overlying the lower interconnect wire 106 in the logic region 504.

[0198] In some embodiments, Fig.31The patterning process may include: performing one or more dry etching processes until the upper surface and / or sidewalls of the protective sidewall spacer layer 116 are exposed. In some embodiments, the one or more dry etching processes may selectively etch the upper ILD layer 1006, the first dielectric protection layer 1002 and the second dielectric protection layer 1004, the second sidewall spacer layer 118 and / or the second ILD layer 207 at a first etching rate, and may selectively etch the protective sidewall spacer layer 116 at a second etching rate, wherein the second etching rate is less than the first etching rate. For example, the first etching rate may be at least 5 times greater than the second etching rate. This in turn prevents damage to the MRAM cell 124 during the patterning process and / or mitigates damage to the MRAM cell during the patterning process.

[0199] like Fig.32 As shown in the cross-sectional view 3200 of , the protective sidewall spacer layer 116 is patterned to expose the top electrode 122 and / or the first sidewall spacer layer 114. In some embodiments, the patterning process may include performing a wet etching process. In some embodiments, the wet etching may selectively etch the upper ILD layer 1006, the first dielectric protection layer 1002 and the second dielectric protection layer 1004, the second ILD layer 207, the second sidewall spacer layer 118 and / or the top electrode 122 at a third etching rate, and may selectively etch the protective sidewall spacer layer 116 at a fourth etching rate, wherein the fourth etching rate is greater than the third etching rate. In other embodiments, the patterning process may include only wet etching, and the wet etching includes one or more etchants. For example, in some embodiments, the fourth etching rate may be, for example, about 10 times, 20 times, 30 times, or 40 times greater than the third etching rate. Thus, in some embodiments, an upper surface and / or sidewalls of the top electrode 122 may be exposed without damaging adjacent dielectric structures / layers and / or without exposing layers disposed within the MTJ 120 .

[0200] In some embodiments, Fig.32 During the patterning process, the upper ILD layer 1006, the first dielectric protection layer 1002 and the second dielectric protection layer 1004, the second ILD layer 207, the second sidewall spacer layer 118 and / or the top electrode 122 may be etched at a rate of about 1 angstrom per minute (angstrom / min), respectively, and the protective sidewall spacer layer 116 may be etched at a rate of about 40 angstroms / min. Therefore, the upper surface and / or sidewall of the top electrode 122 may be exposed without damaging adjacent layers and / or structures.

[0201] like Fig.33As shown in the cross-sectional view 3300 of FIG. 1 , the top electrode via 126 and the upper interconnect wire 128 are formed above the MRAM cell 124, and the conductive via 516 and the conductive wire 518 are formed above the lower interconnect wire 106 in the logic region 504. In some embodiments, the process for forming the top electrode via 126, the upper interconnect wire 128, and the conductive via 516 and the conductive wire 518 includes: forming a first conductive feature opening and a second conductive feature opening ( Fig.32 In some embodiments, a conductive material (e.g., copper, aluminum, titanium nitride, tungsten, a combination of the foregoing, etc.) is deposited in the first conductive feature opening 2008 and the second conductive feature opening 2010 (e.g., by CVD, PVD, electroless plating, sputtering, etc.); and a planarization process (e.g., CMP) is performed in the conductive material and the upper ILD layer 1006. In some embodiments, depositing the conductive material may include forming a conductive liner (e.g., titanium nitride, tungsten, etc.) and then forming a conductor (e.g., aluminum, copper, aluminum copper, etc.) over the conductive liner.

[0202] Figure 24 to Figure 33 The second method shown in represents some embodiments of forming the MRAM cell 124 and the protective sidewall spacer layer 116 that laterally surrounds the MRAM cell 124. In some embodiments, the first conductive feature opening and the second conductive feature opening ( Fig.32 By maintaining the protective sidewall spacer layer 116 around and over the top electrode 122 and the MTJ 120 before the first conductive feature opening 2008 and the second conductive feature opening 2010 are formed, damage to the top electrode 122 and / or the MTJ 120 can be eliminated or reduced. For example, the protective sidewall spacer layer 116 is formed before the top electrode 122 and / or the MTJ 120 are formed. Fig.31 The MTJ 120 and / or the top electrode 122 are prevented from being damaged during the patterning process of the MTJ 120 and / or the top electrode 122, and furthermore, the wet etching process (e.g., Fig.32 ) to remove the protective sidewall spacer layer 116. This in turn can increase the performance of the MRAM cell 124. In some embodiments, if the protective sidewall spacer layer 116 is not Fig.31 If the top electrode 122 extends along the upper surface of the top electrode 122 before the patterning process, the top electrode 122 may be damaged during the aforementioned patterning process. This may result in poor electrical connection when forming a conductive structure in the first conductive feature opening 2008, thereby reducing the performance of the MRAM cell 124.

[0203] Fig.34 A flow chart illustrating some embodiments of a second method 3400 of forming an integrated chip having an MRAM cell including a top electrode via overlying a protective sidewall spacer layer.

[0204] Although second method 3400 is shown and described as a series of actions or events in this article, it should be understood that the order shown of these actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described in this article, some actions can occur in different orders and / or at the same time with other actions or events. In addition, not all of the actions shown may be needed to implement one or more aspects or embodiments described in this article. In addition, one or more of the actions described in this article can be performed with one or more separate actions and / or stages.

[0205] At act 3402, one or more interconnect layers are formed over a substrate. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 3402 .

[0206] At act 3404, a memory cell stack and a top electrode layer are formed over one or more lower interconnect layers. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 3404 .

[0207] At act 3406, the memory cell stack and the top electrode layer are patterned to define a top electrode over the magnetic tunnel junction (MTJ). Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 3406 .

[0208] At act 3408, a first sidewall spacer layer is formed around the outer sidewalls of the top electrode and the outer sidewalls of the MTJ. Fig.13 and Fig.14 Cross-sectional view 1300 and cross-sectional view 1400 are shown corresponding to some embodiments of act 3408 .

[0209] At act 3410, a protective sidewall spacer layer is formed over the top electrode and the first sidewall spacer layer. Fig.26 Cross-sectional view 2600 is shown corresponding to some embodiments of act 3410 .

[0210] At act 3412, a second sidewall spacer layer is formed over the protective sidewall spacer layer, and an upper dielectric interconnect structure is formed over the protective sidewall spacer layer. Figures 27 to 30 Cross-sectional views 2700 through 3000 are shown corresponding to some embodiments of act 3412 .

[0211] At act 3414 , the second sidewall spacer layer and the upper dielectric interconnect structure are patterned to define an opening above the top electrode and to expose an upper surface of the protective sidewall spacer layer. Fig.31 Cross-sectional view 3100 is shown corresponding to some embodiments of act 3414.

[0212] At act 3416, the protective sidewall spacer layer is patterned to expose the top electrode and enlarge the opening. Fig.32 Cross-sectional view 3200 is shown corresponding to some embodiments of act 3416.

[0213] At activity 3418, a top electrode via is formed in the opening. Fig.33 Cross-sectional view 3300 is shown corresponding to some embodiments of act 3418.

[0214] Figure 35 to Figure 36 Shows alternative Figure 27 to Figure 31 The cross-sectional diagrams 3500 to 3600 of some embodiments of the actions performed at the actions, such that Figure 24 to Figure 33 The second method can alternatively be from Fig.26 Continue to Fig.35 ,from Fig.35 Continue to Fig.36 , then from Fig.36 Continue to Figure 32 to Figure 33 (jump over Figure 27 to Figure 31 ). Fig.35 As shown in the cross-sectional view 3500 of FIG. 35, a masking layer 3502 is formed over the protective sidewall spacer layer 116 disposed in the embedded memory region 502. Subsequently, the protective sidewall spacer layer 116 is patterned according to the masking layer 3502 to remove the protective sidewall spacer layer 116 from the logic region 504. Fig.36 As shown in the cross-sectional view 3600 of FIG. 36 , the upper ILD structure 1007 is formed above the embedded memory region 502 and the logic region. In some embodiments, the upper ILD structure 1007 can be or include, for example, silicon oxycarbide, a low-k dielectric material, or another suitable dielectric material. In other embodiments, the upper ILD structure 1007 is patterned to define a first conductive feature opening 2008 in the embedded memory region 502 and a second conductive feature opening 2010 in the logic region 504.

[0215] In some embodiments, Fig.36 The patterning process may include: performing one or more dry etching processes until the upper surface and / or sidewalls of the protective sidewall spacer layer 116 are exposed. In some embodiments, the one or more dry etching processes may selectively etch the upper ILD structure 1007 at a first etching rate, and may selectively etch the protective sidewall spacer layer 116 at a second etching rate, wherein the second etching rate is less than the first etching rate. For example, the first etching rate may be at least 5 times greater than the second etching rate. This in turn prevents damage to the MRAM cell 124 during the patterning process and / or mitigates damage to the MRAM cell during the patterning process. In other embodiments, the conductive line may (during the execution of Fig.32After the action at 2008) is formed in the first conductive feature opening 2008, so that the conductive line directly contacts the top electrode 122 (for example, see Fig. 10B ).

[0216] Figure 37 to Figure 39 Shows alternative Figure 27 to Figure 31 The cross-sectional diagrams 3700 to 3900 of some alternative embodiments of the actions performed at the actions at Figure 24 to Figure 33 The second method can alternatively be from Fig.26 Continue to Fig.37 ,from Fig.37 Continue to Figure 38 to Figure 39 , then from Fig.39 Continue to Figure 32 to Figure 33 (jump over Figure 27 to Figure 31 ). Fig.37 As shown in the cross-sectional view 3700 of FIG. 1 , the dielectric filling layer 1008 is formed above the MRAM cell 124. In some embodiments, the dielectric filling layer 1008 may be or include, for example, tetraethyl orthosilicate (TEOS) (e.g., plasma enhanced TEOS, low particle TEOS, etc.), oxide (e.g., silicon oxide, silicon dioxide, etc.), nitride, etc. Fig.38 As shown in the cross-sectional view 3800 of , the dielectric filling layer 1008 and the protective sidewall spacer layer 116 are patterned so that the dielectric filling layer 1008 and the protective sidewall spacer layer 116 can be removed from the logic area 504. In some embodiments, Fig.38 The patterning process may include an etch-back process. Fig.39 As shown in the cross-sectional view 3900 of FIG. 39 , the upper ILD structure 1007 is formed above the embedded memory region 502 and the logic region. In some embodiments, the upper ILD structure 1007 can be or include, for example, silicon oxycarbide, a low-k dielectric material, or another suitable dielectric material. In other embodiments, the upper ILD structure 1007 is patterned to define a first conductive feature opening 2008 in the embedded memory region 502 and a second conductive feature opening 2010 in the logic region 504. In still other embodiments, the conductive lines can be (in the implementation Fig.32 After the action at 2008) is formed in the first conductive feature opening 2008, so that the conductive line directly contacts the top electrode 122 (for example, see Fig. 10C ).

[0217] In some embodiments, Fig.39The patterning process may include: performing one or more dry etching processes until the upper surface and / or sidewalls of the protective sidewall spacer layer 116 are exposed. In some embodiments, the one or more dry etching processes may selectively etch the upper ILD structure 1007 at a first etching rate, and may selectively etch the protective sidewall spacer layer 116 at a second etching rate, wherein the second etching rate is less than the first etching rate. For example, the first etching rate may be at least 5 times greater than the second etching rate. This in turn prevents damage to the MRAM cell 124 during the patterning process and / or mitigates damage to the MRAM cell during the patterning process.

[0218] Therefore, in some embodiments, the present disclosure is directed to a protective sidewall spacer layer that continuously surrounds the outer sidewall of the top electrode and the outer sidewall of the MTJ. The top electrode via directly contacts the top electrode and the protective sidewall spacer layer.

[0219] In some embodiments, an integrated chip includes: a dielectric structure overlying a substrate, a magnetoresistive random access memory (MRAM) cell disposed in the dielectric structure, a conductive line overlying a top electrode and disposed in the dielectric structure, and a sidewall spacer structure extending continuously along sidewalls of the MTJ and the top electrode, wherein the MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode, and the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer include a first material, and the protective sidewall spacer layer includes a second material different from the first material.

[0220] In some embodiments, the integrated chip further includes a top electrode via disposed between the conductive line and the top electrode, wherein the lower surface of the top electrode via includes one or more segments disposed below the upper surface of the top electrode, wherein the top electrode via contacts the upper surface of the protective sidewall spacer layer. In some embodiments, the width of the lower surface of the top electrode via is greater than the width of the upper surface of the top electrode. In some embodiments, the width of the lower surface of the top electrode via is greater than the maximum width of the magnetic tunnel junction. In some embodiments, the protective sidewall spacer layer includes curved opposite sidewalls, wherein the lower surface of the top electrode via is conformal to the curved opposite sidewalls of the protective sidewall spacer layer and the lower surface of the top electrode via directly contacts the curved opposite sidewalls of the protective sidewall spacer layer. In some embodiments, the magnetic tunnel junction includes a tunnel barrier layer disposed between a free layer and a fixed layer, wherein the lower surface of the top electrode via extends below the top surface of the tunnel barrier layer. In some embodiments, the top electrode via comprises a semicircular protrusion laterally adjacent to the triangular protrusion, wherein the upper surface of the top electrode directly contacts the semicircular protrusion, and the protective sidewall spacer layer directly contacts the triangular protrusion. In some embodiments, the conductive line directly contacts the upper surface and sidewall of the top electrode, wherein the lower surface of the conductive line is disposed below the upper surface of the magnetic tunnel junction. In some embodiments, the protective sidewall spacer layer continuously extends from the lower surface of the conductive line to the sidewall of the bottom electrode.

[0221] In some embodiments, an integrated chip includes: a substrate, a bottom electrode overlying the substrate, a magnetic tunnel junction (MTJ) overlying the bottom electrode, a top electrode overlying the MTJ, a top electrode through-hole overlying the top electrode, a first sidewall spacer layer arranged along the outer sidewall of the MTJ and the outer sidewall of the top electrode, a second sidewall spacer layer arranged along the outer sidewall of the top electrode, and a protective sidewall spacer layer arranged between the first sidewall spacer layer and the second sidewall spacer layer, wherein a minimum width of the top electrode through-hole is greater than a maximum width of the MTJ, the first sidewall spacer layer includes a first material, the second sidewall spacer layer includes a first material, the protective sidewall spacer layer includes a second material different from the first material, wherein an upper surface of the protective sidewall spacer layer is vertically located above a top surface of the MTJ, wherein the protective sidewall spacer layer is separated from the outer sidewall of the MTJ by the first sidewall spacer layer, and the protective sidewall spacer layer directly contacts the outer sidewall of the top electrode.

[0222] In some embodiments, the first material is silicon nitride or silicon carbide, and the second material is aluminum oxide or aluminum nitride. In some embodiments, the top electrode and the magnetic tunnel junction are laterally spaced between opposite side walls of the top electrode through hole, respectively. In some embodiments, the upper surface of the protective sidewall spacer layer is disposed between opposite side walls of the protective sidewall spacer layer, wherein the top electrode through hole continuously extends from a first side wall of the opposite side wall to a second side wall of the opposite side wall, wherein the top electrode through hole directly contacts the opposite side wall and the upper surface of the protective sidewall spacer layer. In some embodiments, the maximum width of the top electrode is less than the minimum width of the top electrode through hole, wherein the maximum width of the bottom electrode is greater than the maximum width of the top electrode through hole. In some embodiments, the integrated chip further comprises an inner connection wire overlying the top electrode through hole, wherein the top electrode through hole is laterally spaced between the side walls of the inner connection wire, wherein the inner connection wire and the top electrode through hole are continuous conductive structures. In some embodiments, the continuous conductive structure comprises a conductive liner disposed along the perimeter of a conductor, wherein the conductive liner comprises tungsten, and the conductor comprises aluminum or copper.

[0223] In some embodiments, a method for forming an integrated chip includes: forming a memory cell stack above a substrate, wherein the memory cell stack includes a top electrode overlying a magnetic tunnel junction (MTJ); forming a sidewall spacer structure around the memory cell stack, wherein the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer; forming an upper interlayer dielectric (ILD) structure above the sidewall spacer structure; performing a first etching process on the ILD structure and the second sidewall spacer layer to define an opening above the top electrode, wherein the first etching process exposes an upper surface and sidewalls of the protective sidewall spacer layer, wherein during the first etching process, the second sidewall spacer layer and the ILD structure are etched at a higher rate than the protective sidewall spacer layer; and filling the opening with a conductive material.

[0224] In some embodiments, during the first etching process, the interlayer dielectric structure and the second sidewall spacer layer are etched at a first rate and the protective sidewall spacer layer is etched at a second rate, wherein the first rate is 5 times faster or greater than 5 times faster than the second rate. In some embodiments, the method of forming an integrated chip further includes performing a second etching process on the protective sidewall spacer layer to expose the top electrode, wherein during the second etching process, the interlayer dielectric structure is etched at a third rate and the protective sidewall spacer is etched at a fourth rate, wherein the fourth rate is 10 times faster or greater than 10 times faster than the third rate, the second etching process includes wet etching, and the first etching process includes dry etching. In some embodiments, forming the sidewall spacer structure includes: depositing the protective sidewall spacer layer over the first sidewall spacer layer and the top electrode; and performing a second etching process on the protective sidewall spacer layer to expose the top surface of the top electrode, wherein the second etching process includes performing dry etching with a chlorine-based etchant.

[0225] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, comprising: a dielectric structure overlying the substrate; a magnetoresistive random access memory cell disposed within the dielectric structure, wherein the magnetoresistive random access memory cell comprises a magnetic tunnel junction sandwiched between a bottom electrode and a top electrode; a conductive line overlying the top electrode and disposed within the dielectric structure; a top electrode via disposed between the conductive line and the top electrode, wherein a lower surface of the top electrode via includes one or more segments disposed below an upper surface of the top electrode; as well as A sidewall spacer structure extends continuously along the sidewalls of the magnetic tunnel junction and the top electrode, wherein the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer include a first material, and the protective sidewall spacer layer includes a second material different from the first material. 2 . The integrated chip according to claim 1 , wherein the top electrode via contacts an upper surface of the protective sidewall spacer layer. 3 . The integrated chip according to claim 2 , wherein a width of the lower surface of the top electrode via is greater than a width of the upper surface of the top electrode. 4 . The integrated chip according to claim 3 , wherein the width of the lower surface of the top electrode via is greater than a maximum width of the magnetic tunnel junction.

5. The integrated chip according to claim 2, wherein the protective sidewall spacer layer includes curved relative sidewalls, wherein the lower surface of the top electrode through hole is conformal to the curved relative sidewalls of the protective sidewall spacer layer and the lower surface of the top electrode through hole directly contacts the curved relative sidewalls of the protective sidewall spacer layer.

6. An integrated chip according to claim 2, wherein the magnetic tunnel junction includes a tunnel barrier layer arranged between a free layer and a fixed layer, wherein the first sidewall spacer layer continuously extends along the relative side walls of the tunnel barrier layer, the relative side walls of the free layer, and the relative side walls of the fixed layer to the inner surface of the protective sidewall spacer layer.

7. The integrated chip according to claim 2, wherein the top electrode through hole comprises a semicircular protrusion laterally adjacent to the triangular protrusion, wherein the upper surface of the top electrode directly contacts the semicircular protrusion, and the protective sidewall spacer layer directly contacts the triangular protrusion. 8 . The integrated chip according to claim 2 , wherein the protective sidewall spacer layer continuously extends from the one or more sections of the top electrode via to a top surface of the bottom electrode.

9. An integrated chip comprising: substrate; a bottom electrode, overlying the substrate; a magnetic tunnel junction overlying the bottom electrode; a top electrode, overlying the magnetic tunnel junction; a top electrode through hole, overlying the top electrode, wherein a minimum width of the top electrode through hole is greater than a maximum width of the magnetic tunnel junction; a first sidewall spacer layer disposed along an outer sidewall of the magnetic tunnel junction and an outer sidewall of the top electrode, wherein the first sidewall spacer layer comprises a first material; a second sidewall spacer layer disposed along the outer sidewall of the top electrode, wherein the second sidewall spacer layer comprises the first material; as well as A protective sidewall spacer layer is disposed between the first sidewall spacer layer and the second sidewall spacer layer, wherein the protective sidewall spacer layer includes a second material different from the first material, wherein an upper surface of the protective sidewall spacer layer is vertically located above a top surface of the magnetic tunnel junction, wherein the protective sidewall spacer layer is separated from the outer sidewall of the magnetic tunnel junction by the first sidewall spacer layer, and the protective sidewall spacer layer directly contacts the outer sidewall of the top electrode. 10 . The integrated chip according to claim 9 , wherein the first material is silicon nitride or silicon carbide, and the second material is aluminum oxide or aluminum nitride.

11. The integrated chip of claim 9, wherein the top electrode and the magnetic tunnel junction are laterally spaced apart between opposite sidewalls of the top electrode via, respectively.

12. An integrated chip according to claim 9, wherein the upper surface of the protective sidewall spacer layer is arranged between the opposite side walls of the protective sidewall spacer layer, wherein the top electrode through hole continuously extends from the first side wall of the opposite sidewall to the second side wall of the opposite sidewall, wherein the top electrode through hole directly contacts the opposite sidewall and the upper surface of the protective sidewall spacer layer.

13. The integrated chip according to claim 9, wherein a maximum width of the top electrode is smaller than the minimum width of the top electrode through-hole, wherein a maximum width of the bottom electrode is larger than a maximum width of the top electrode through-hole.

14. The integrated chip according to claim 9, further comprising: An inner connection wire overlies the top electrode through hole, wherein the top electrode through hole is laterally spaced between side walls of the inner connection wire, wherein the inner connection wire and the top electrode through hole are a continuous conductive structure. 15 . The integrated chip according to claim 14 , wherein the continuous conductive structure comprises a conductive liner disposed along a perimeter of an electrical conductor, wherein the conductive liner comprises tungsten, and the electrical conductor comprises aluminum or copper.

16. A method for forming an integrated chip, comprising: forming a memory cell stack above the substrate, wherein the memory cell stack includes a top electrode overlying the magnetic tunnel junction; forming a sidewall spacer structure around the memory cell stack, wherein the sidewall spacer structure comprises a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer; forming an interlayer dielectric structure over the sidewall spacer structure; performing a first etching process on the interlayer dielectric structure and the second sidewall spacer layer to define an opening above the top electrode, wherein the first etching process exposes an upper surface and a sidewall of the protective sidewall spacer layer, wherein the second sidewall spacer layer and the interlayer dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etching process; as well as The opening is filled with a conductive material to form a top electrode via, wherein a lower surface of the top electrode via includes one or more segments disposed below an upper surface of the top electrode.

17. The method for forming an integrated chip according to claim 16, wherein during the first etching process, the interlayer dielectric structure and the second sidewall spacer layer are etched at a first rate and the protective sidewall spacer layer is etched at a second rate, wherein the first rate is 5 times or more faster than the second rate.

18. The method for forming an integrated chip according to claim 17, further comprising: performing a second etching process on the protective sidewall spacer layer to expose the top electrode, wherein during the second etching process, the interlayer dielectric structure is etched at a third rate, and the protective sidewall spacer is etched at a fourth rate, wherein the fourth rate is 10 times or more faster than the third rate; and The second etching process includes wet etching, and the first etching process includes dry etching.

19. The method for forming an integrated chip according to claim 16, wherein forming the sidewall spacer structure comprises: depositing the protective sidewall spacer layer over the first sidewall spacer layer and the top electrode; as well as A second etching process is performed on the protective sidewall spacer layer to expose a top surface of the top electrode, wherein the second etching process includes performing dry etching with a chlorine-based etchant.

20. An integrated chip, comprising: substrate; a magnetoresistive random access memory cell disposed above the substrate, wherein the magnetoresistive random access memory cell includes a magnetic tunnel junction sandwiched between a bottom electrode and a top electrode; a top electrode through hole, overlying the top electrode; A first sidewall spacer layer continuously extends along the sidewalls of the magnetic tunnel junction and the sidewalls of the top electrode; a second sidewall spacer layer laterally surrounding the first sidewall spacer layer, wherein a top surface of the second sidewall spacer layer is disposed below a top surface of the first sidewall spacer layer; as well as A protective sidewall spacer layer is arranged between the first sidewall spacer layer and the second sidewall spacer layer, wherein the protective sidewall spacer layer includes a first lateral segment, a curved vertical segment and a second lateral segment located below the first lateral segment, wherein the curved vertical segment continuously extends from the first lateral segment to the second lateral segment, the first lateral segment contacts the side wall of the top electrode and is spaced between the lower surface of the top electrode through hole and the top surface of the first sidewall spacer layer.

21. The integrated chip according to claim 20, wherein a top surface of the first lateral section is aligned with an upper edge of the top electrode. 22 . The integrated chip according to claim 20 , wherein the top electrode via continuously extends from an inner sidewall of the second sidewall spacer layer along an outer surface of the curved vertical segment to a top surface of the first lateral segment.

23. The integrated chip according to claim 20, wherein an outermost wall of the protective sidewall spacer layer and an outermost wall of the bottom electrode are aligned.

24. The integrated chip according to claim 20, wherein the second lateral section continuously extends along and directly contacts a top surface of the bottom electrode.

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