Flyback power converter and method and driver for operating a flyback power converter

Abstract

The present invention is entitled "Flyback Power Converter and Method and Driver for Operating a Flyback Power Converter". The present invention discloses a flyback power converter and a method and driver for operating the flyback power converter. At least some exemplary embodiments are methods, which include: sensing that the power converter has entered a charging mode of a transformer arranged for flyback operation based on a rate of change of voltage on the drain of a synchronous rectifier field effect transistor (SR FET); in response to the sensing, changing a parameter within a SR driver from an initial state to a modified state, the SR driver being coupled to the SR FET; turning on the SR FET during a discharge mode of the transformer; sensing that the discharge mode of the converter has ended based on a voltage at the drain of the SR FET; and returning the parameter to an initial state in response to sensing that the discharge mode has ended.

Description

Technical Field

[0001] The present patent application relates to the technical field of power converters, and in particular to a flyback power converter. Background Art

[0002] An active clamp flyback (ACF) power converter uses a resonant or quasi-resonant primary circuit that operates during continuous conduction mode (CCM) to not only transfer the energy associated with the leakage inductance to the secondary side, but also strives to achieve zero volt switching (ZVS) of the main field effect transistor (FET) on the primary side. ACF power converters can achieve high efficiency at high loads, but the ACF operation may be curtailed during low loads when the power converter transitions to discontinuous conduction mode (DCM). The transition between DCM operation and ACF operation may cause problems for the driver of the secondary-side synchronous rectifier. That is, the driver for the secondary-side synchronous rectifier may have difficulty distinguishing between the transformer entering charging mode on the one hand and the ACF circuit becoming active on the other hand. Summary of the invention

[0003] One exemplary embodiment is a method of operating a power converter, the method comprising: sensing that the power converter has entered a charging mode of a transformer arranged for flyback operation based on a rate of change of voltage on a drain of a synchronous rectifier field effect transistor (SR FET); in response to the sensing, changing a parameter within a SR driver from an initial state to a modified state, the SR driver being coupled to the SR FET; turning on the SR FET during a discharge mode of the transformer; sensing that the discharge mode of the power converter has ended based on a voltage at the drain of the SR FET; and returning the parameter to the initial state in response to sensing that the discharge mode has ended.

[0004] In an exemplary method, changing the parameter may further include increasing the minimum on-time of the SR FET during the discharge mode, and returning the parameter to the initial state may further include decreasing the minimum on-time of the SR FET. Increasing the minimum on-time of the SR FET may further include increasing based on the resistance of a resistor external to the SR driver and coupled to the SR driver. Returning the parameter to the initial state may further include returning the minimum on-time to a predetermined value. Sensing that the power converter has entered the charge mode may further include sensing that the rate of change of voltage is positive and above a first predetermined value.

[0005] In an exemplary method, changing the parameter may further include activating a standby signal; turning on the SR FET during the discharge mode of the transformer may further include turning on the SR FET only when the standby signal is activated; and returning the parameter to the initial state may further include deactivating the standby signal. Activating the standby signal may further include: activating the standby signal when the voltage change rate is positive and the voltage change rate is higher than a first predetermined value. Deactivating the standby signal also includes: deactivating the standby signal when the voltage on the drain rises above a second predetermined value. Turning on the SR FET during the discharge mode may further include: monitoring the voltage on the drain of the SR FET during the time period when the standby signal is activated; and turning on the SR FET when the voltage on the drain indicates that the body diode of the SR FET is turned on.

[0006] Another exemplary embodiment is a driver for a secondary-side synchronous rectifier, the driver comprising: a drain sense terminal and a gate terminal; and a controller. The controller may be configured to: sense a voltage change rate indicating that a power converter has entered a charging mode of a transformer arranged for flyback operation based on a voltage change rate on the drain sense terminal; in response to entering the charging mode, change a parameter within the driver from an initial state to a modified state; during a discharge mode of the transformer, enable the gate terminal; based on a voltage at the drain sense terminal, sense that the discharge mode has ended; and then, in response to sensing that the discharge mode has ended, return the parameter to the initial state.

[0007] In an exemplary driver, the controller may be configured to increase the minimum on-time during the discharge mode when the controller changes the parameter; and the controller may be configured to decrease the minimum on-time when the controller returns the parameter to an initial state. The exemplary driver may also include: an on-time terminal, and the controller may be configured to increase the minimum on-time based on the resistance sensed through the on-time terminal when the controller increases the minimum on-time. The controller may be configured to return the minimum on-time to a predetermined value when the controller returns the parameter to an initial state. The controller may be configured to sense that the voltage change rate is positive and above a first predetermined value when the controller senses that the power converter has entered a charging mode.

[0008] In an exemplary drive, the controller may be further configured to assert the standby signal when the controller changes the parameter; the controller may be further configured to assert the gate terminal only when the standby signal is asserted when the controller asserts the gate terminal during the discharge mode of the transformer; and the controller may be further configured to deactivate the standby signal when the controller returns the parameter to an initial state. The controller may be further configured to assert the standby signal when the voltage change rate is positive and the voltage change rate is higher than a first predetermined value when the controller asserts the standby signal. In an exemplary drive, the controller may be further configured to deactivate the standby signal when the voltage change rate is positive and the voltage on the drain sense terminal rises above a second predetermined value when the controller deactivates the standby signal. The controller may be further configured to maintain the gate terminal in an asserted state at least for a predetermined on-time when the controller deactivates the standby signal; and then deactivate the standby signal and deactivate the gate terminal when the voltage change rate is positive and the voltage on the drain sense terminal rises above a second predetermined value when the controller deactivates the standby signal.

[0009] In an exemplary driver, the controller may be further configured to: during the time period when the arm signal is inactive, when the rate of change of the voltage on the drain sense terminal indicates that the clamp FET on the primary side is turned on, inhibit the arm signal from being active. The controller is further configured to monitor the voltage on the drain sense terminal when the controller is inhibiting; and keep the arm signal inactive when the rate of change of the voltage is negative and below a first predetermined threshold.

[0010] In an exemplary driver, the controller may be further configured to monitor the voltage on the drain sense terminal during a time period in which the standby signal is asserted when the controller asserts the gate terminal; and assert the gate terminal when the voltage on the drain sense terminal indicates that the body diode of the synchronous rectifier field effect transistor is conducting.

[0011] Another exemplary embodiment is a power converter, which includes: a primary side; and a secondary side. The primary side may include: a primary winding of a transformer, the primary winding having a first lead and a second lead, the first lead coupled to an input voltage, the second lead defining a switch node; a primary field effect transistor (FET), the primary field effect transistor coupled between the switch node and a ground terminal on the primary side; and a clamp FET coupled between the switch node and a clamp capacitor. The second side may include: a secondary winding of a transformer, the secondary winding of the transformer being arranged for flyback operation; a secondary rectifier FET (SR FET), the secondary rectifier FET defining a drain, a source, and a gate, the drain coupled to the secondary winding; and a driver for the SR FET, the driver defining a gate terminal coupled to the gate and a drain sense terminal coupled to the drain. The driver is configured to: sense a rate of change of voltage based on a rate of change of voltage on a drain of the SR FET indicating that the power converter has entered a charging mode of the transformer; change a parameter within the driver from an initial state to a modified state in response to entering the charging mode; turn on the SR FET during a discharge mode of the transformer; sense that the discharge mode has ended based on a voltage at the drain of the SR FET; and then, in response to sensing that the discharge mode has ended, return the parameter to the initial state.

[0012] In an exemplary power converter: the driver may be configured to increase the minimum on-time of the SR FET during a discharge mode when the driver changes a parameter; and the driver may be configured to reduce the minimum on-time of the SR FET when the driver returns the parameter to an initial state. The exemplary power converter may also include: an on-time terminal; and a resistor having a lead coupled to the on-time terminal. The driver may be configured to increase based on the resistance of the resistor when the driver increases the minimum on-time of the SRFET. The driver may be configured to return the minimum on-time to a predetermined value when the driver returns the parameter to an initial state. The driver may be configured to sense that the voltage change rate is positive and above a first predetermined value when the driver senses that the power converter has entered a charging mode.

[0013] In an exemplary power converter: the driver may also be configured to assert a standby signal within the driver when the driver changes a parameter; the driver may also be configured to, when the driver turns on the SR FET during the discharge mode, turn on the SR FET only when the standby signal is asserted; and the driver may also be configured to deactivate the standby signal when the driver returns the parameter to an initial state. The driver may also be configured to assert the standby signal when the voltage change rate is positive and the voltage change rate is higher than a first predetermined value when the driver asserts the standby signal. The driver may also be configured to deactivate the standby signal when the voltage change rate is positive and the voltage on the drain of the SR FET rises above a second predetermined value when the driver deactivates the standby signal. The driver may also be configured to keep the SR FET in the on state at least for a predetermined on time when the standby signal is deactivated; and then, deactivate the standby signal and make the SR FET non-conductive when the voltage change rate is positive and the voltage on the drain of the SR FET rises above a second predetermined value. The driver may also be configured to inhibit the arming signal from being asserted when the rate of change of voltage on the drain of the SR FET indicates that the clamping FET on the primary side is conducting during the time period when the arming signal is inactive. The driver may also be configured to monitor the voltage on the drain of the SR FET when the driver is inhibiting; and maintain the arming signal in an inactive state when the rate of change of voltage is negative and below a first predetermined threshold. The driver may also be configured to monitor the voltage on the drain of the SR FET during the time period when the arming signal is asserted when the driver is turning on the SR FET; and turn on the SR FET when the voltage on the drain of the SR FET indicates that the body diode of the synchronous rectifier field effect transistor is conducting. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To describe in detail the exemplary embodiments, reference will now be made to the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram illustrating an active clamp flyback power converter according to at least some embodiments;

[0016] Figure 2 illustrates a timing diagram according to at least some embodiments;

[0017] Figure 3 shows a block diagram of a secondary driver according to at least some embodiments; and

[0018] Figure 4 Methods according to at least some embodiments are shown.

[0019] definition

[0020] Various terms are used to refer to specific system components. Different companies may refer to a component by different names - this document is not intended to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "include" and "comprising" are used in an open-ended manner, and therefore, these terms should be interpreted to mean "including, but not limited to...". In addition, the terms "couple" or "coupled" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0021] With respect to an electrical device (whether stand-alone or as part of an integrated circuit), the terms "input" and "output" refer to electrical connections to the electrical device and should not be construed as requiring verbs to operate. For example, a differential amplifier (such as an operational amplifier) ​​may have a first differential input and a second differential input, and these "inputs" define electrical connections to the operational amplifier and should not be construed as requiring signal inputs to the operational amplifier.

[0022] “Controller” shall mean, alone or in combination, a single circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a processor with control software, or a field programmable gate array (FPGA) configured to read inputs and drive outputs in response to the inputs. DETAILED DESCRIPTION

[0023] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure, including the claims. In addition, it should be understood by those skilled in the art that the following description has a wide range of applications, and the discussion of any embodiment is only intended to be an example of that embodiment, and is not intended to indicate that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0024] Various embodiments are directed to systems and methods for an active clamp flyback power converter. More specifically, exemplary embodiments are directed to a driver for a secondary side synchronous rectifier that is capable of distinguishing between a primary field effect transistor (FET) on the primary side becoming conductive on the one hand and a clamp FET on the primary side becoming conductive on the other hand. More specifically, exemplary embodiments distinguish between the primary FET becoming conductive and the clamp FET becoming conductive based on a rate of change of voltage on the secondary side. The present specification first turns to an exemplary active clamp flyback power converter and its operation to guide the reader.

[0025] Figure 1Schematic diagram of an active clamp flyback power converter according to at least some embodiments is shown. Specifically, power converter 100 includes a primary circuit or primary side 102 electrically coupled to a secondary circuit or secondary side 104 through a transformer 106. Primary side 102 defines a voltage coupled to a direct current (DC) input voltage V IN 108. In an exemplary system, the node 108 is also directly coupled to a first lead of a primary winding 110 of the transformer 106. A second lead of the primary winding 110 is coupled to a switch node 112. The switch node 112 (and therefore the second lead of the primary winding 110) is coupled to a primary FET 114. The drain of the primary FET 114 is coupled to the switch node 112, and the source of the primary FET 114 is coupled to a common terminal or ground terminal on the primary side 102 through a sense resistor 116. The switch node 112 is also coupled to the source of a clamp FET 118. The drain of the clamp FET 118 is coupled to a first lead of a clamp capacitor 120, and a second lead of the clamp capacitor 120 is coupled to the node 108. In an exemplary system, the primary FET 114 and the clamp FET 118 are N-channel metal oxide semiconductor (MOS) FETs. However, in other exemplary cases, the primary FET 114 and the clamp FET 118 may be P-channel MOSFETs, or any other suitable devices that operate as electrically controlled switches, including FETs known as "super junction" (SJFETs), and higher performance gallium nitride (GaN) FETs.

[0026] In the exemplary system, the primary side 102 includes a primary side driver 130. The primary side driver 130 is coupled to: the gate of the primary FET 114; the gate of the clamp FET 118; and a sense node 132, which is defined between the primary FET 114 and the sense resistor 116. There may be additional connections to the primary side driver 130 (e.g., ground on the primary side, to the input voltage V IN connections and voltage feedback connections), but the additional connections are not shown to avoid overly complicating the drawing.

[0027] The exemplary secondary side 104 includes a secondary winding 122 of the transformer 106. A first lead of the secondary winding 122 is coupled to an output node 124 of the secondary side 104 and is therefore coupled to an output voltage V OUTThe second lead of the secondary winding 122 is coupled to a synchronous rectifier in the form of an exemplary form of a FET, hereinafter referred to as SR FET 126. Specifically, the second lead of the secondary winding 122 is coupled to the drain of the SR FET 126, and the source of the SR FET 126 is coupled to a common terminal on the secondary side 104. The exemplary secondary side 104 also includes a capacitor 128 coupled between the output node 124 and a common terminal of the secondary side 104, which need not be the same as the ground terminal of the primary side 102 due to the isolation aspect of the transformer 106.

[0028] In addition, in the exemplary system, the secondary side 104 includes a synchronous rectifier driver 134 (hereinafter referred to as SR driver 134). The SR driver 134 is coupled to the gate of the SR FET 126 and is also coupled to the drain of the SR FET 126. As discussed in more detail below, by monitoring the voltage on the drain of the SR FET 126, the SR driver 134 controls when the SR FET 126 is conducting and non-conducting. The exemplary system also includes a resistor 140 coupled to the SR driver 134. As will be discussed in more detail below, the resistance of the resistor 140 can be set to or can be proportional to the minimum conduction time of the SR FET 126. The description now turns to the various operating states or modes of the power converter 100.

[0029] In the exemplary system, transferring energy from the primary side 102 to the secondary side 104 is conceptually a two-step process. Specifically, the power converter 100 first enters a charging mode, where energy is stored in the field of the transformer 106. More specifically, the exemplary power converter 100 enters the charging mode by turning on the primary FET 114 by the primary side driver 130. When the primary FET 114 is turned on, the current flows from the input voltage V IN114, and through the sense resistor 116, and then to the ground on the primary side 102. The current flowing through the primary winding 110 generates a voltage across the secondary winding 122. However, the transformer 106 is arranged for flyback operation, and during the charging mode, the voltage across the secondary winding 122 is higher (according to the point specified in the figure) on the connection or lead coupled to the drain of the SR FET 126 than on the connection or lead coupled to the output node 124. During the charging mode, the SR FET 126 is not conducting, the body diode 136 of the SR FET 126 is reverse biased, and therefore no current flows in the secondary winding 122; instead, during this charging mode, energy is stored in the field of the transformer 106. When the current flowing through primary winding 110 reaches a peak current setting (as determined by primary side driver 130 sensing the voltage at sense node 132 ), primary side driver 130 renders primary FET 114 non-conductive, thereby ending the charge mode and beginning the discharge mode.

[0030] The second step of transferring energy is the discharge mode. Once the primary FET 114 is rendered non-conductive, the voltage on the secondary winding 122 reverses polarity and current flows through the secondary winding 122 to the output node 124 (e.g., charging the capacitor 128, supplying a load (not specifically shown), or both). The period of time during which the current flows through the secondary winding is referred to as the discharge mode. That is, during the discharge mode, the energy stored during the previous charging mode (when no current flows in the secondary winding 122) is provided at the secondary winding 122 from the transformer 106 in the form of voltage and current. More specifically, the collapse field associated with the transformer 106 provides voltage and current to the secondary winding 122 during the discharge mode. In some cases, the SR driver 134 can sense the rate of change of the voltage on the drain of the SR FET 126 and predictively begin the process of driving the SR FET 126 to the conductive state. That is, when the rate of change of the voltage on the drain of the SR FET 126 decreases, this can indicate an impending discharge mode. In other cases, the SR driver 134 may sense a threshold voltage on the drain of the SR FET 126 and, based on the threshold, turn on the SR FET 126. Initially, the current flowing through the secondary winding 122 may flow through the body diode 136 of the SR FET 126, and shortly thereafter, the SR driver 134 fully turns on the SR FET 126, causing current to flow through the SR FET 126. After the discharge mode ends, a new charge mode begins, and this cycle continues, in which each charge mode and associated discharge mode used transfers energy across the transformer 106 and reaches the output voltage V OUT .

[0031] The exemplary power converter 100 can operate in various conduction modes of the transformer 106. More specifically, the exemplary power converter 100 can operate in a continuous conduction mode (CCM) or a discontinuous conduction mode (DCM). First consider the continuous conduction mode that can be used during high loads. In the continuous conduction mode, current always flows through the primary winding 110 or the secondary winding 122. For example, in the continuous conduction mode, each discharge mode of the transformer 106 ends before the field associated with the transformer 106 completely collapses. More specifically, in the continuous conduction mode, the primary side driver 130 turns on the primary FET 114, thereby starting the next charging mode before the current flowing in the secondary winding 122 reaches zero in the discharge mode. Even though current may still flow in the secondary winding 122 at the moment when the primary FET 114 begins to turn on, the voltage on the secondary winding 122 reverses once the current begins to flow in the primary winding 110. When the SR driver 134 senses the voltage change (eg, by monitoring the voltage on the drain of the SR FET 126 ), the SR driver 134 renders the SR FET 126 non-conductive.

[0032] Still reference Figure 1 , the active clamp flyback aspect of the exemplary power converter 100 is utilized during the continuous conduction mode. Specifically, during the discharge mode of the continuous conduction mode, the clamp FET 118 is turned on to provide a path for current flow associated with the leakage inductance of the primary winding 110 (the leakage inductance is not specifically shown). That is, when current flows in the secondary winding 122 during the discharge mode, the current may also initially flow through the clamp FET 118 to the clamp capacitor 120. However, the clamp capacitor 120 and the parasitic capacitance associated with the primary FET 114 (the parasitic capacitance is not specifically shown) form a tank circuit with leakage inductance. Although the resonant current initially flows through the clamp FET 118 to the clamp capacitor 120, the resonant current flow associated with the clamp circuit eventually reverses direction. The exemplary power converter 100 uses the resonant current, and in particular the current from the clamp capacitor 120 , to dissipate or release the parasitic capacitance associated with the primary FET 114 to achieve zero volt switching (ZVS) operation during the continuous conduction mode.

[0033] Now consider the discontinuous conduction mode that can be used during light or low loads. In the discontinuous conduction mode, the current flow in the secondary winding 122 reaches zero and remains at zero for a period of time before the next charging mode begins. Therefore, unlike the continuous conduction mode, in the discontinuous conduction mode, there are time periods when no current flows in the primary winding 110 or the secondary winding 122 (not considering parasitic oscillations). More specifically, in the discontinuous conduction mode, the current in the secondary winding 122 reaches zero, and in response, the SR driver 134 renders the SR FET 126 non-conductive. However, due to the reactive components on both the primary side 102 and the secondary side 104, various parasitic oscillations occur. For example, after the current in the secondary winding 122 reaches zero (i.e., the field associated with the transformer 106 has completely collapsed), the voltage at the switch node 112 on the primary side 102 begins to oscillate. Similar oscillations occur at the drain of the SR FET 126.

[0034] In the discontinuous conduction mode, the next charging mode can be started at any time after the current in the secondary winding 122 reaches zero. In an exemplary embodiment, the next charging mode is started at the "valley" of the voltage oscillation at the switch node 112. That is, the primary side driver 130 can monitor the voltage at the switch node 112 in any suitable form, such as through a dedicated connection to the switch node 112 (not specifically shown), or by monitoring the voltage on the gate of the primary FET 114 caused by the oscillation. When the voltage reaches or approaches a low voltage "valley" as part of the oscillation, the primary side driver 130 can turn the primary FET 114 on again, thereby starting the next charging mode. Turning on the primary FET 114 in the valley of the voltage oscillation reduces the voltage across the primary FET 114, which reduces the switching losses associated with the primary FET 114. In addition, switching in the valley can also be considered as ZVS operation. Therefore, in the discontinuous conduction mode, the clamp FET 118 and the clamp capacitor 120 are not required to achieve ZVS operation of the primary FET 114. Therefore, in the discontinuous conduction mode, the primary side driver 130 keeps the clamp FET 118 in a non-conducting state.

[0035] When transitioning from a high load state or condition (and operating in continuous conduction mode) to a light load state or condition (and thus changing to discontinuous conduction mode), the primary side driver 130 may stop using the active clamp flyback component at the start of discontinuous conduction mode. However, due to the body diode 138 associated with the clamp FET 118, the clamp capacitor 120 may accumulate voltage over time. For example, during the discharge mode, the voltage at the switch node 112 is the input voltage V IN The output voltage V reflected across the transformer 106 OUTThe reflected voltage of the form of 1 / 2 is the sum of the reflected voltages of the form of 1 / 2 (where the magnitude of the reflected voltage is based on the turns ratio of the transformer 106). Due to the rectifying action of the body diode 138 even when the clamping FET 118 is not used, the voltage on the clamping FET 118 eventually matches the highest voltage on the switch node 112. The problem can be exacerbated by parasitic oscillations at the switch node 112, which can even have a magnitude higher than the input voltage V IN The voltage accumulated on the clamp capacitor 120 during the discontinuous conduction mode is not a problem until the power converter 100 transitions from a light load condition (still in the discontinuous conduction mode) to a high load condition (restarting the continuous conduction mode). The exemplary primary side driver 130 addresses the problem of the voltage accumulated on the clamp capacitor 120 during the discontinuous conduction mode by activating the clamp FET 118 during the discontinuous conduction mode, although the activation lasts for a reduced period of time as the power converter 100 transitions back to the continuous conduction mode.

[0036] Figure 2 A timing diagram is shown according to at least some embodiments. That is, Figure 2 A series of waveforms are shown as multiple scattered points and with corresponding time axes when the exemplary power converter 100 transitions from discontinuous conduction mode to continuous conduction mode (although these graphs do not show operation in the continuous conduction mode). Figure 2 The time ranges shown for performing the conversions are not necessarily drawn to scale. Figure 2 The curve 200 of FIG. 200 shows the gate signal applied to the primary FET 114. The exemplary gate signal is shown as being active high, but this should not be construed as limiting. In the exemplary time range shown, the duration of the charging mode (i.e., the duty cycle of the gate signal in the curve 200) increases over time, thereby showing that the energy storage in the field of the transformer 106 increases over time.

[0037] Figure 2 Curve 202 of shows the gate signal applied to the clamp FET 118. The exemplary gate signal is shown as being asserted high, but this should not be construed as limiting. In the exemplary time range shown, the gate signal initially applied to the clamp FET 118 remains inactive (e.g., between time t0 and t8). However, beginning with the period associated with the start of the charge mode at time t5 and the following discharge mode (between time t6 and time t7), the gate signal to the clamp FET 118 is asserted for a short period of time (at time t8) in the dead zone between the end of the discharge mode and the start of the next charge mode. The assertion of the gate signal to the clamp FET 118 turns the clamp FET 118 on to begin the process of depleting the accumulated charge on the clamp FET 118 in preparation for the next continuous conduction mode. Thus, during the period associated with the start of the charge mode at time t5 and the following discharge mode (between time t6 and time t7), the gate signal to the clamp FET 118 is asserted for a short period of time (at time t8) in the dead zone between the end of the discharge mode and the start of the next charge mode. Figure 2 In the illustrated time range, the duration of activation of the clamp FET 118 increases as the duty cycle of the gate signal (curve 200) applied to the primary FET 114 increases. When the exemplary power converter 100 reaches the continuous conduction mode, the clamp FET 118 may always be turned on when the primary FET 114 is not conducting, except for the dead time between the conduction states of the clamp FET 118 and the primary FET 114, to ensure that there is no cross conduction of the clamp capacitor 120 to the ground terminal on the primary side 102.

[0038] Figure 2 The curve 204 of FIG. 1 shows the voltage at the drain of the SR FET 126. For example, considering the time range between time t1 and t2, the voltage at the drain of the SR FET 126 is shown as follows: Figure 2 The second charging mode is shown in the timing diagram of . During the exemplary charging mode, the voltage at the drain of the SR FET 126 (remember, the SR FET 126 is non-conducting during the charging mode) is the voltage transmitted across the transformer 106. Because the transformer 106 is arranged for flyback operation, the voltage on the drain is higher than the voltage on the source of the SR FET 126, so the body diode 136 is reverse biased and no current flows. Once the primary FET 114 is rendered non-conductive (at time t2), the discharge mode begins. The exemplary discharge mode begins at time t2 and ends at time t3. During the exemplary discharge mode, the SR driver 134 turns on the SR FET 126, so the voltage at the drain is low or zero as shown. It should be remembered that Figure 2 The various time ranges are relative to the discontinuous conduction mode, and at time t3, the current of the secondary winding 122 reaches zero, thereby ending the discharge mode. Therefore, the exemplary SR driver 134 makes the SR FET 126 non-conductive, and as shown at 210, the voltage at the drain of the SR FET 126 oscillates in the dead band between time t3 and t4. The oscillation is based on the interaction of various reactive elements on both sides of the transformer (e.g., capacitor 128, and leakage and magnetizing inductance of the primary winding 110). The process starts a new next charging mode from time t4.

[0039] In the first few time frames, the primary side driver 130 inhibits activating the active clamp and, therefore, inhibits the clamp FET 118 from turning on. However, in the exemplary time frame starting at time t8, the primary side driver 130 turns on the clamp FET 118 in each cycle in the dead band between the end of the discharge mode and the beginning of the next charge mode. For example, as shown by curve 202, in the dead band between time t7 and time t9, the exemplary primary side driver 130 turns on the clamp FET 118 at time t8. Activating the active clamp circuit during the dead band causes a voltage drop at the drain of the SR FET 126, as shown by voltage drop 212. In each time frame starting at time t8, each time the clamp FET 118 is turned on, there is a corresponding voltage drop on the drain of the SR FET 126. Each voltage drop is Figure 2 It is exemplarily marked as 212.

[0040] The inventors of the present specification have discovered that it is difficult for the SR driver of the related art to distinguish the voltage drop (voltage drop 212) associated with turning on the clamp FET 118 during the dead time from the voltage drop that signals the start of the discharge mode. When the SR driver of the related art incorrectly senses the voltage drop 212 as starting the discharge mode, the SR driver of the related art may turn on the SR FET at an inappropriate time (e.g., during the charging mode). The SR driver of the related art may attempt to solve this problem using various minimum off times associated with the SR FET, but it is difficult to establish a minimum off time for a power converter that switches back and forth between a continuous conduction mode and a discontinuous conduction mode. For example, if a minimum off time sufficient to suppress erroneous sensing during light load conditions is used during a high load condition operating in the continuous conduction mode, the power converter may be rendered inoperable.

[0041] To at least partially address the above problems, various exemplary embodiments sense that the power converter has entered the charging mode based on the rate of change of the voltage on the drain of the SR FET 126. When the charging mode is sensed, the exemplary SR driver 134 changes the parameters within the SR driver from an initial state to a modified state. The change in the parameter state reduces the problems caused by activating the clamp FET 118 during the dead zone of the discontinuous conduction mode, and in some cases can completely eliminate these problems. In an exemplary embodiment, the state of changing the parameter is to standby the SR driver 134 based on the rate of change of the voltage on the drain of the SR FET 126, wherein the rate of change indicates that the power converter 100 has entered the charging mode. When the SR driver 134 is on standby, the SR driver 134 is therefore placed in or converted to the standby mode. During the standby mode, and only during the standby mode, the SR driver 134 can turn on the SR FET 126. Releasing the SR driver 134 from standby can occur at the end of each discharge mode. When the SR driver 134 is de-armed, the SR driver 134 is thus placed in or transitioned to the de-armed mode. During the de-armed mode (i.e., during the dead time), the SR driver 134 cannot turn on the SR FET 126 regardless of the voltage sensed on the drain of the SR FET 126. In this way, during the time period when the clamp FET 118 may be turned on during the dead time between the end of the discharge mode and the beginning of the next charge mode, the SR driver 134 is not armed, thereby avoiding the possibility that the SR driver 134 may inadvertently turn on the SR FET 126 based on the voltage drop 212.

[0042] See again Figure 2 . Curve 206 illustrates an exemplary arming signal that illustrates the time period during which the exemplary SR driver 134 is arming relative to each exemplary charging mode, discharging mode, and dead zone. Curve 206 illustrates an arming signal for purposes of explanation, but depending on the implementation, such an arming signal need not be created specifically for this purpose. For example, arming may be one or more first states of a state machine within the SR driver 134, and de-arming may be one or more second states of a state machine implemented within the SR driver 134. Thus, the arming signal may be a bit or a series of bits that identify the state of the state machine. Figure 2 The curve 208 of FIG. 1 shows the gate signal applied to the SRFET 126 during the various time ranges shown in the figure. For example, considering again the time range between time t1 and t2, the gate signal t1 is represented as Figure 2206 . According to an exemplary embodiment, the SR driver 134 is armed (e.g., an arm signal is asserted) based on the power converter 100 entering the charging mode. More specifically, as shown by curve 206, the exemplary SR driver 134 monitors the voltage on the drain of the SR FET 126, and based on the rate of change of the voltage on the drain of the SR FET 126, the SR driver 134 is placed or transitioned to the standby mode accordingly. The exemplary SR driver 134 makes the determination to be armed based on the rate of change of the voltage at the drain of the SR FET 126 (e.g., the slope or first derivative of the voltage as a function of time (dV / dt)) being positive and the rate of change being above a predetermined threshold. That is, a very sharp transition in the voltage on the drain of the SR FET 126 (e.g., a voltage spike 214) indicates the start of the charging mode, and the voltage spike 214 can be distinguished from other voltage swings based on the rate of change of the voltage, the magnitude of the rate of change of the voltage, and / or the polarity or sign of the rate of change. For example, voltage spike 214 has a positive slope, where the magnitude of the slope is higher than any other voltage transition sensed on the drain of SR FET 126. The rate of change of voltage associated with this voltage spike 214 is not a resonant effect; rather, the rate of change of voltage is a reaction of transformer 106 to the direction and rate of change of current flowing through primary winding 110 when primary FET 114 becomes conductive, and therefore, the rate of change of voltage is higher than the resonant current flowing in the system and is distinguishable for that cause.

[0043] Referring now to time t1 to t3. As shown by curve 206, during the exemplary time period t1 to t3, the exemplary SR driver 134 is in a standby state. During the standby mode, the SR driver 134 turns on the SR FET 126 during the discharge mode of the transformer. Specifically, in the exemplary embodiment, the SR driver 134 again monitors the voltage on the drain of the SR FET 126. When the voltage on the drain of the SR FET 126 drops to zero or near zero (e.g., drops to the forward voltage drop of the body diode 136), as shown at time t2, the SR driver 134 enables the gate of the SR FET 126. The exemplary SR driver 134 continues to monitor the voltage on the drain of the SR FET 126, and when the voltage rises at time t3, indicating the end of the discharge mode, the gate of the SR FET 126 is disabled. More specifically, the example SR driver 134 is placed or transitioned to the de-armed mode (eg, deactivates the arm signal) when the rate of change of voltage at the drain of the SR FET 126 is positive and / or the voltage on the drain rises above a predetermined value.

[0044] In the dead band between times t3 and t4, the SR driver 134 again monitors the voltage on the drain of the SR FET 126. When the rate of change of voltage is positive and above a predetermined value (at time t4), the exemplary SR driver 134 again arms. Therefore, voltage events in the dead band between times t3 and t4 cannot cause the SR driver 134 to turn on the SR FET 126. However, in the exemplary dead band between times t3 and t4, the clamp FET 118 is not conducting, so there is no significant voltage drop.

[0045] Now consider the time range in which the clamp FET 118 is turned on in the dead zone between the end of the discharge mode and the beginning of the charge mode, such as the time range between time t7 and t9. As previously described, at time t5, the SR driver 134 is armed based on the voltage rate of change being positive and above a predetermined threshold (e.g., the voltage spike 214 at time t5). During the exemplary armed mode, the SR driver 134 again monitors the voltage on the drain of the SR FET 126. When the voltage on the drain of the SR FET 126 drops to zero or near zero at time t6, the SR driver 134 enables the gate of the SR FET 126, and the SR FET 126 becomes conductive. The exemplary SR driver 134 continues to monitor the voltage on the drain of the SR FET 126, and when the voltage rises at time t7, indicating the end of the discharge mode, the gate of the SR FET 126 is disabled, and the exemplary SR driver 134 is placed in or transitioned to the de-armed mode.

[0046] However, the dead zone between time t7 and time t9 has a voltage drop 212 due to the primary side driver 130, turning on the clamp FET 118. However, when the rate of change of the voltage on the drain indicates that the clamp FET 118 on the primary side is turned on (again, the voltage drop 212 at time t8), the exemplary SR driver 134 is deactivated (e.g., the arming signal is deactivated), thereby inhibiting the SR FET 126 from turning on. That is, in the exemplary embodiment, the SR driver 134 monitors the voltage on the drain of the SR FET 126 and remains in the de-arming mode when the rate of change of the voltage is negative and below the first predetermined threshold.

[0047] although Figure 2 Although not specifically shown in the figure, each time a transition is made from a charging mode to a discharging mode, and each time a transition is made from a discharging mode (or dead zone) to a charging mode, a transient voltage such as that caused by a reactive component is generated. Figure 2The voltage at the drain of the SR FET 126 is shown to drop to a steady value near zero during the discharge mode, but the reactive components (particularly those on the primary side 102) induce transient voltages at the drain of the SR FET 126 during the discharge mode. To avoid prematurely rendering the SR FET 126 non-conductive during the discharge mode, exemplary embodiments of the SR driver 134 implement a minimum on-time or minimum conduction time for the SR FET 126 in each discharge mode. In these exemplary embodiments, then, once the SR FET 126 is rendered conductive, the SR FET 126 remains conductive for at least a predetermined on-time, and then the SR FET 126 is rendered non-conductive (and the SR driver 134 is de-armed) when the rate of change of voltage at the drain of the SR FET 126 is positive and the voltage on the drain rises above a second predetermined value.

[0048] Alternatively or optionally, the SR driver 134 is armed based on the rate of change of voltage on the drain of the SR FET 126, and when the rate of change of voltage indicates that the power converter 100 has entered the charging mode, the SR driver 134 may also change the parameter in the form of changing the minimum on time or minimum conduction time of the SR FET 126. Returning the parameter to the initial state after sensing that the discharge mode has ended may include reducing the minimum on time of the SR FET 126.

[0049] See again Figure 2 For example, again considering the time range between time t1 and t2, we can express Figure 21. The second charging mode shown in the timing diagram of . According to an exemplary embodiment, the SR driver 134 is armed based on the power converter 100 entering the charging mode. In addition to being armed at time t1, the exemplary SR driver 134 can also increase the minimum on-time of the SR FET 126. It should be understood that the SR FET 126 is not turned on at time t1; instead, at time t1, in the example, a parameter that controls or sets the minimum on-time is changed within the SR driver 134. Now refer to time t1 to t3. During time t1 to t3, the SR driver 134 turns on the SR FET 126 during the discharge mode of the transformer. Specifically, in an exemplary embodiment, the SR driver 134 again monitors the voltage on the drain of the SR FET 126. When the voltage on the drain of the SR FET 126 drops to zero or near zero (e.g., drops to the forward voltage drop of the body diode 136), as shown at time t2, the SR driver 134 enables the gate of the SR FET 126. The exemplary SR driver 134 keeps the SR FET 126 on for at least the minimum on time, regardless of the voltage sensed at the drain of the SR FET 126. After the minimum on time expires, the SR driver 134 then monitors the voltage at the drain of the SR FET 126 until the voltage rises at time t3, indicating the end of the discharge mode, deactivating the gate of the SR FET 126. Thereafter, the exemplary SR driver 134 reduces the minimum on time of the SR FET. In the exemplary dead time between times t3 and t4, the clamp FET 118 is not conducting, so there is no significant voltage drop.

[0050] Now consider the time range in which the clamp FET 118 is turned on in the dead zone between the end of the discharge mode and the start of the charge mode, such as the time range between time t7 and t9. As previously described, at time t5, the SR driver 134 may be armed based on the voltage rate of change being positive and above a predetermined threshold (e.g., the voltage spike 214 at time t5), and the SR driver 134 increases the minimum on-time. The SR driver 134 again monitors the voltage on the drain of the SR FET 126. When the voltage on the drain of the SR FET 126 drops to zero or near zero at time t6, the SR driver 134 enables the gate of the SR FET 126, and the SR FET 126 becomes conductive. The exemplary SR driver 134 keeps the SR FET 126 on for at least the minimum on-time, regardless of the voltage sensed at the drain of the SR FET 126. After the minimum on-time expires, the example SR driver 134 continues to monitor the voltage on the drain of the SR FET 126 and when the voltage rises at time t7, indicating the end of the discharge mode, the gate of the SR FET 126 is disabled and the example SR driver 134 decreases the minimum on-time parameter.

[0051] However, the dead zone between time t7 and time t9 has a voltage drop 212 due to the primary side driver 130, turning on the clamp FET 118. However, in some exemplary cases, the SR driver 134 fails and thus inhibits the SR FET 126 from turning on. In other exemplary cases where the SR driver 134 does not implement an arm and de-arm strategy, the shortened minimum on time ensures that even if the SR FET 126 is turned on based on the voltage induced in the secondary side based on the clamp FET 118 becoming conductive, the shorter minimum on time does not force the SR FET 126 to turn on during the discharge mode.

[0052] In some exemplary embodiments, increasing the minimum on-time parameter may include reading or sensing a resistor 140 ( Figure 1). In other cases, increasing the minimum on-time parameter may include reading or sensing any external component (e.g., an external capacitor) having a parameter that can be sensed by the SR driver 134. In other cases, the increased minimum on-time parameter may be communicated to a controller within the SR driver 134 as part of a setup operation (e.g., serially communicated into the controller during setup). Similarly, decreasing the minimum on-time parameter may include reading or sensing an external component (e.g., a resistor, a capacitor) having a parameter that can be sensed by the SR driver 134. In other cases, the decreased minimum on-time parameter may be preset or hard-coded within the SR driver 134, or may be communicated to a controller within the SR driver 134 as part of a setup operation (e.g., serially communicated into the controller during setup).

[0053] Figure 3 A block diagram of an SR driver according to at least some embodiments is shown. In particular, the SR driver 134 may include one or more electrical devices monolithically formed on a substrate 302 and encapsulated in a package; however, the functionality of the controller 190 may be embodied on multiple substrates that are co-packaged and electrically coupled to each other and to various terminals. The package may take any suitable form, such as a small outline integrated circuit (SOIC) eight-pin package, or a thin small outline package (TSOP) six-pin package. The exemplary SR driver 134 defines a drain sense terminal 304, a gate terminal 306, a reference terminal 308, and an on-time terminal 324. The exemplary terminals are exposed and accessible electrical connections through the package. There will be additional terminals (e.g., power terminals), but these additional terminals are not shown to avoid overly complicating the drawings.

[0054] The exemplary SR driver 134 includes a controller 310 coupled to the drain sense terminal 304, the gate terminal 306, the reference terminal 308, and various other terminals present. The exemplary controller 310 is configured to change parameters within the SR driver 134 based on a rate of change of voltage sensed on the drain sense terminal 304, wherein the rate of change of voltage indicates that the power converter has entered a charging mode of a transformer arranged for flyback operation. The changed parameters may place the driver in a standby mode, may change the minimum on-time, or both. The controller 310 is also configured to enable the gate terminal 306 during the discharge mode of the transformer, and return the parameters to an initial state at the end of the discharge mode (e.g., de-arming the driver, reducing the minimum on-time, or both).

[0055] More specifically, the exemplary controller 310 can be conceptually divided into a control logic component 312, a slope detector 314 (shown as a "dV / dt detector" in the figure), a minimum on-time logic component 316, and a drive circuit 318, but this is not physically necessary. The exemplary control logic component 312 receives various signals and controls various parameters of the SR driver 134. The control logic component 312 also drives the gate signal to the gate terminal 306 through the drive circuit 318. Specifically, the exemplary slope detector 314 monitors the voltage on the drain sense terminal 304 and provides information about the rate of change of the voltage and possible other information (e.g., magnitude) to the control logic component 312. The control logic component 312 then changes the parameters (e.g., parameters 332). In some cases, the parameters 332 arm the SR driver 134 based on the rate of change of the voltage sensed by the slope detector 314. That is, arming occurs when the rate of change of the voltage indicates that the power converter has entered a charging mode of a transformer arranged for flyback operation. More specifically, arming occurs when the rate of change of the voltage sensed on the drain sense terminal 304 is positive and above a first predetermined value.

[0056] In other cases, parameter 332 may be a minimum on-time parameter. Control logic 312 may increase the minimum on-time in response to sensing that the power converter has entered a charging mode. In an exemplary embodiment, controller 310 increases the minimum on-time based on the resistance of resistor 140 sensed through on-time terminal 324. In other cases, controller 310 may both arm the driver and increase the minimum on-time parameter.

[0057] During the arming mode, the slope detector 314 continues to monitor the drain sense terminal 304 and provides relevant information to the control logic 312. When the voltage on the drain sense terminal 304 indicates that the discharge mode is about to begin or has begun, the control logic 312 asserts the gate terminal 306. The exemplary controller 310 keeps the gate terminal 306 asserted for at least the (increased) minimum on-time, regardless of the voltage sensed at the drain sense terminal 304. At the end of the discharge mode, the exemplary control logic 312 disables the gate terminal 306 and de-arms the SR driver 134. Specifically, when the rate of change of voltage sensed at the drain sense terminal 304 (as sensed by the exemplary slope detector 314) is positive and the voltage on the drain sense terminal rises above a second predetermined value, the exemplary control logic 312 disables the gate terminal 306 and de-arms the SR driver 134. In addition, at the end of the discharge mode, the exemplary controller 310 reduces the minimum on-time parameter.

[0058] During the de-armed mode, the exemplary control logic component 312 inhibits arming when the rate of change of voltage on the drain sense terminal 304 (as sensed by the slope detector 314) indicates that the clamp FET on the primary side is conducting. That is, the exemplary control logic component 312 monitors the voltage on the drain sense terminal 304 (monitored by the slope detector 314), and when the rate of change of voltage is negative and below a first predetermined threshold, the exemplary control logic component 312 remains in the de-armed mode.

[0059] In some exemplary embodiments, the control logic component 312 works in conjunction with the minimum on-time logic component 316. Specifically, in some exemplary embodiments, the control logic component 312 asserts the gate terminal 306 and simultaneously communicates the assertion (e.g., as indicated by arrow 320). The exemplary control logic component 312 maintains the gate terminal asserted until the minimum on-time determined by the minimum on-time logic component 316 expires. When the minimum on-time has been reached, the reaching may be communicated from the minimum on-time logic component 316 to the control logic component 312, as indicated by arrow 322. After the minimum on-time has been reached, the control logic component 312 may resume monitoring the voltage on the drain sense terminal 304 and then deactivate the gate terminal 306 and de-arm the SR driver 134 when the rate of change of voltage sensed at the drain sense terminal 304 (as sensed by the exemplary slope detector 314) is positive and the voltage on the drain sense terminal rises above a second predetermined value. The control logic component 312 may also work in conjunction with the minimum off-time logic component 326. Specifically, in some exemplary embodiments, the control logic component 312 disables the gate terminal 306 and simultaneously communicates the disablement (e.g., as indicated by arrow 328). The exemplary control logic component 312 maintains the gate terminal disabled, regardless of the voltage on the drain sense terminal 304, until the minimum off time determined by the minimum off time logic component 326 expires. When the minimum off time has been reached, as indicated by arrow 330, the reaching can be communicated from the minimum off time logic component 326 to the control logic component 312. After the minimum off time is reached, as described above, the control logic component 312 can resume monitoring the voltage on the drain sense terminal 304 and arm the control logic component 312 and / or increase the minimum on time.

[0060] Figure 4A method according to at least some embodiments is shown. Specifically, the method starts (box 400) and includes: sensing that a power converter has entered a charging mode of a transformer arranged for flyback operation based on a rate of change of voltage on the drain of a synchronous rectifier field effect transistor (SR FET) (box 402); and then in response to the sensing, changing a parameter within a SR driver from an initial state to a modified state, the SR driver being coupled to the SR FET (box 404); turning on the SR FET during a discharge mode of the transformer (box 406); sensing that the discharge mode of the converter has ended based on a voltage at the drain of the SR FET (box 408); and then in response to sensing that the discharge mode has ended, returning the parameter to an initial state (box 410). Thereafter, the method ends (box 412) to restart in the next charging mode.

[0061] Many electrical connections in the drawings are shown as directly coupled without intervening devices, but are not explicitly described as such in the above description. However, for electrical connections shown in the drawings without intervening devices, this paragraph should serve as an antecedent basis for the claims for referencing any electrical connection as "directly coupled."

[0062] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are interpreted as being intended to include all such variations and modifications.

Claims

1. A method of operating a power converter, the method comprising: sensing that the power converter has entered a charging mode of a transformer arranged for flyback operation based on a rate of change of voltage on a drain of a synchronous rectifier field effect transistor (SR) FET; and then responsive to the sensing, changing a parameter within a SR driver from an initial state to a modified state, the SR driver being coupled to the SR FET; During a discharge mode of the transformer, turning on the SR FET; sensing that the discharge mode of the power converter has ended based on a voltage at the drain of the SR FET; and then In response to sensing that the discharge mode has ended, the parameter is returned to the initial state.

2. The method according to claim 1: wherein changing the parameter further comprises increasing a minimum on-time of the SR FET during a discharge mode; Wherein returning the parameter to the initial state further comprises reducing the minimum on-time of the SR FET.

3. The method according to claim 1: Wherein changing the parameter further comprises making a standby signal effective; wherein turning on the SR FET during the discharge mode of the transformer further comprises turning on the SR FET only when the standby signal is asserted; and The step of returning the parameter to the initial state further comprises disabling the standby signal.

4. The method of claim 3, wherein activating the arming signal further comprises: When the voltage change rate is positive and the voltage change rate is higher than a first predetermined value, the standby signal is enabled.

5. The method of claim 3, wherein turning on the SR FET during the discharge mode further comprises: monitoring a voltage on the drain of the SR FET during a period of time when the standby signal is asserted; as well as When the voltage on the drain indicates that the body diode of the SR FET is conducting, the SR FET is turned on.

6. A driver for a secondary-side synchronous rectifier, the driver comprising: a drain sense terminal and a gate terminal; A controller, the controller being configured to: sensing a rate of change of voltage on the drain sense terminal indicating that the power converter has entered a charging mode of a transformer arranged for flyback operation based on the rate of change of voltage on the drain sense terminal; and then In response to entering the charging mode, changing a parameter within the driver from an initial state to a modified state; enabling the gate terminal during a discharge mode of the transformer; sensing that the discharge mode has ended based on the voltage at the drain sense terminal; and then In response to sensing that the discharge mode has ended, the parameter is returned to the initial state.

7. The driver according to claim 6: wherein the controller is configured to increase a minimum on-time during the discharge mode when the controller changes the parameter; The controller is configured to reduce the minimum on-time when the controller returns the parameter to the initial state.

8. The driver according to claim 6: wherein the controller is further configured to enable a standby signal to take effect when the controller changes the parameter; wherein the controller is further configured to, when the controller asserts the gate terminal during the discharge mode of the transformer, assert the gate terminal only if the arming signal is asserted; and The controller is further configured to disable the standby signal when the controller returns the parameter to the initial state.

9. The driver of claim 8, wherein the controller is further configured to assert the arming signal when the voltage change rate is positive and the voltage change rate is above a first predetermined value when the controller asserts the arming signal.

10. The driver of claim 8, wherein the controller is further configured to, when the controller deactivates the arming signal, deactivate the arming signal when the rate of voltage change is positive and the voltage on the drain sense terminal rises above a second predetermined value.

11. The driver of claim 8, wherein the controller is further configured to inhibit assertion of the arm signal when a rate of change of voltage on the drain sense terminal indicates that a clamp FET on the primary side is conducting during a time period when the arm signal is inactive.

12. The driver of claim 8, wherein the controller is further configured to, when the controller asserts the gate terminal: During a time period when the arming signal is asserted, monitoring a voltage on the drain sense terminal; and The gate terminal is asserted when the voltage on the drain sense terminal indicates that a body diode of a synchronous rectifier field effect transistor is conducting.

13. A power converter, comprising: A primary side, the primary side comprising: a primary winding of a transformer having a first lead coupled to an input voltage and a second lead defining a switching node; a primary field effect transistor FET coupled between the switch node and a ground terminal on the primary side; a clamp FET coupled between the switch node and a clamp capacitor; A secondary side, the secondary side comprising: a secondary winding of the transformer, the secondary winding of the transformer being arranged for flyback operation; a secondary rectifier FET SR FET defining a drain, a source, and a gate, the drain being coupled to the secondary winding; a driver for the SR FET, the driver defining a gate terminal coupled to the gate and a drain sense terminal coupled to the drain; The driver is configured as: sensing a rate of voltage change indicating that the power converter has entered a charging mode of the transformer based on a rate of voltage change on the drain of the SR FET; and then In response to entering the charging mode, changing a parameter within the driver from an initial state to a modified state; During a discharge mode of the transformer, turning on the SR FET; sensing that the discharge mode has ended based on a voltage at the drain of the SR FET; and then returning the parameter to the initial state in response to sensing that the discharge mode has ended.

Images