Microelectronic device assembly, package and related methods

Abstract

The present application relates to microelectronic device assemblies, packages and related methods. A microelectronic device assembly is disclosed, the microelectronic device assembly comprising a substrate having conductors exposed on its surface. Two or more microelectronic devices are stacked on the substrate, and components are connected with conductive materials in preformed holes in dielectric materials in bonding wires aligned with TSVs of the devices and exposed conductors of the substrate. A manufacturing method is also disclosed.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the filing dates of U.S. Provisional Patent Application Serial No. 62 / 916,371, filed on October 17, 2019, entitled “Methods for Fabrication of Microelectronic Device Packages and Related Packages and Systems,” U.S. Provisional Patent Application Serial No. 63 / 037,902, filed on June 11, 2020, entitled “Methods for Fabrication of Microelectronic Device Packages and Related Packages and Systems,” and U.S. Patent Application Serial No. 16 / 939,678, filed on July 27, 2020, entitled “Microelectronic Device Assemblies, Packages and Related Methods.”

[0003] The subject matter of this application relates to U.S. patent application serial number 16 / 939,756, filed on July 27, 2020, entitled “Microelectronic Device Assemblies and Packages and Related Methods and Systems,” U.S. patent application serial number 16 / 939,650, filed on July 27, 2020, entitled “Microelectronic Device Assemblies and Packages Including Multiple Device Stacks and Related Methods,” and U.S. patent application serial number 16 / 939,720, filed on July 27, 2020, entitled “Microelectronic Device Assemblies and Packages Including Surface Mount Components.” Technical Field

[0004] Embodiments disclosed herein relate to the fabrication of microelectronic device packages. More specifically, embodiments disclosed herein relate to the fabrication of microelectronic device assemblies including stacked microelectronic devices that employ conductive materials in preformed holes in dielectric materials between TSVs of the microelectronic devices and to related packages and methods. Background Art

[0005] As the electronics industry moves toward three-dimensional assemblies of stacked microelectronic devices, most commonly in the form of stacked semiconductor dies, which are widely commercialized, the time and cost expended in vertically connecting aligned conductive elements of the stacked dies to conductive elements of the base substrate prior to encapsulating the die stack has become an issue. Conventionally, multiple singulated semiconductor dies including so-called through-substrate vias (TSVs, also called "through-silicon vias") terminating at opposing surfaces of each semiconductor die in the form of posts and pads are stacked together with the posts of their dies aligned with the pads of adjacent dies. Each die stack may be formed on and aligned with the conductive elements of the die locations of an unsingulated base wafer, other bulk semiconductor substrate, or other component. The posts may include a single conductive material such as copper, or a conductive material capped by solder. Although the uppermost semiconductor die in the stack may not be equipped with TSVs, the posts of such semiconductor die are aligned with the pads of the next lower semiconductor die and communicate through the TSVs for signal, power, and ground (e.g., bias) purposes, as are the other semiconductor dies in the stack.

[0006] The use of TSVs presents some issues in terms of manufacturing costs and the resulting package. For example, the manufacture of TSVs conventionally involves forming blind holes in a semiconductor wafer prior to thinning, followed by lining the holes with a dielectric material to electrically isolate the conductive material of the TSV. In a post-wafer finishing process, a conductive post is formed on one side of the TSV (i.e., on the active surface of the wafer), and a conductive pad is formed thereon after the semiconductor wafer is thinned to expose the conductive material. In addition, after singulating the semiconductor die from the semiconductor wafer, the semiconductor die is then stacked together with the posts, TSVs, and pads aligned with each other for subsequent interconnection of adjacent posts and pads by thermocompression bonding according to the current state of the art.

[0007] Thermocompression bonding techniques that apply heat and pressure (i.e., vertical force) to diffusion bond the conductive elements of a semiconductor die to the conductive elements of another semiconductor die or other base substrate have been demonstrated to provide a strong mechanical and electrical connection between components. However, thermocompression bonding is expensive and time consuming when multiple stacked semiconductor dies are to be diffusion bonded, and the implementation of three-dimensional (3D) assemblies of semiconductor dies using smaller conductive elements in the form of copper pillars at reduced pitches on a commercial scale is an increasingly common requirement. For example, stacks of memory dies may be manufactured that include four, eight, twelve, or even sixteen dies as a complete assembly, or stacks of memory dies combined with logic dies as may be implemented in a hybrid memory cube architecture, and such stacks that include device logic dies in the case of a high bandwidth memory (HBM) architecture.

[0008] For example, when multiple semiconductor dies are to be stacked on die sites of a bulk semiconductor substrate (e.g., a wafer), singulated dies of a given layer are placed as the stack is formed, and then the thermocompression groups are bonded one by one to the base wafer or lower layer dies by application of heat and pressure, and this process is repeated die layer by die layer until a desired number of dies (e.g., four dies, eight dies, etc.) are stacked. Even when such stacking and group bonding is performed at the wafer level, it will be appreciated that such an approach is cost and time intensive, requiring multiple actions of stacking and individual group bonding of the dies for each die layer using a pick and place device with a bonding head before proceeding to form the next higher layer. In addition, conventional thermocompression bonding of copper-copper conductive elements is a solid state diffusion bonding process that results in atomic interdiffusion and grain growth between two adjacent metal surfaces at undesirably high temperatures, on the order of about 300° C. even for so-called "low temperature" bonding. Such temperatures associated with thermocompression bonding are desirable to avoid due to thermal budget constraints of the die, as well as thermomechanical stress control and alignment accuracy limitations after bonding.

[0009] In addition to the foregoing, the use of TSVs for vertical conductive paths in a stack of semiconductor die also consumes valuable real estate (i.e., area) on each die. As semiconductor die become smaller and the critical dimensions and pitches of features decrease in size to increase circuit density, the use of TSVs becomes less desirable, especially as the number of semiconductor dies in the stack increases. This is a particular problem for memory devices that incorporate more and more, smaller, and more densely distributed memory cells, although the problem is not limited thereto. Summary of the invention

[0010] Embodiments of the present disclosure include a microelectronic device assembly comprising: a microelectronic device having an active surface facing a substrate; and a preformed hole filled with a conductive material and extending through a dielectric film between an array of bonding pads on the active surface of the microelectronic device and terminal pads on the substrate.

[0011] Embodiments of the present disclosure include a microelectronic device assembly, the microelectronic device assembly comprising: a stack of microelectronic devices on a substrate, each microelectronic device including a TSV extending through its thickness between a bonding pad on an active surface and a terminal pad on a back surface thereof; and a dielectric film inserted between adjacent microelectronic devices of the stack, the dielectric film including preformed holes aligned between the bonding pads and the terminal pads of adjacent microelectronic devices of the stack, the preformed holes being filled with a conductive material that contacts the aligned bonding pads and terminal pads of adjacent microelectronic components.

[0012] An embodiment of the present disclosure includes a method comprising: forming a reconstructed wafer or panel by placing singulated semiconductor die in a spaced relationship with each other and laminating a polymer film over the active surface of the singulated semiconductor die including a bonding pad; forming a through hole through the polymer film to expose the bonding pad on the active surface; filling the through hole with a conductive material; singulating the semiconductor die of the reconstructed panel or wafer through the polymer film; inverting at least one semiconductor die and placing the inverted at least one semiconductor die on a substrate, wherein the through hole filled with the conductive material is aligned with the terminal pad on the substrate; and bonding the polymer film to the substrate, wherein the conductive material is in contact with the terminal pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A1 and 1A2 A flow chart including an embodiment of a method for manufacturing a microelectronic device package according to the present disclosure;

[0014] Figure 1B is a schematic side cross-sectional view of a microelectronic device package according to an embodiment of the present disclosure, and the microelectronic device package can be Figure 1A1 and 1A2 Method of manufacturing;

[0015] Figure 2A is a flow chart of another embodiment of a method for manufacturing a microelectronic device package according to the present disclosure;

[0016] Figure 2B is a schematic partial cross-sectional side view of a microelectronic device package according to an embodiment of the present disclosure, and the microelectronic device package can be Figure 2A Method of manufacturing;

[0017] Figure 3A is a flow chart of an embodiment of a method for manufacturing a microelectronic device package according to the present disclosure;

[0018] Figure 3B is a schematic side cross-sectional view of a microelectronic device package according to an embodiment of the present disclosure, and the microelectronic device package can be Figure 3A Method of manufacturing;

[0019] Figures 4A-4D is a schematic top elevation view of a die stack according to an embodiment of the present disclosure illustrating various embodiments including through-poly vias on one, two, three, or four sides of the die stack;

[0020] Figure 5A and 5B are schematic top elevation views of a die stack according to an embodiment of the present disclosure, showing different arrangements of multiple rows of through-polysilicon vias, and Figure 5C is a schematic side elevation view of an embodiment of the present disclosure including a Faraday cage including surrounding through-silicon vias and a ground structure above a die stack;

[0021] Figures 6A-6D are schematic diagrams of different example configurations of connections between conductive traces and conductive material through-polysilicon vias;

[0022] Figure 7 is a block diagram of an electronic system incorporating one or more semiconductor packages according to an embodiment of the present disclosure;

[0023] Fig. 8A is a flow chart of an embodiment of a method for manufacturing a microelectronic device package including a stack of multiple microelectronic devices according to the present disclosure, and Figure 8B is a schematic side cross-sectional view of a microelectronic device package including a plurality of microelectronic device stacks according to an embodiment of the present disclosure;

[0024] Fig. 9A is a flow chart of an embodiment of a method for manufacturing a microelectronic device for directly attaching a chip to a substrate according to the present disclosure, and Fig. 9B Describes about Fig. 9A The process sequence described;

[0025] Fig. 9C Depicts the die stack used to form the Fig. 9A and 9B Another embodiment of the embodiment of;

[0026] Fig. 10A is a flow chart of an embodiment of a method for manufacturing a microelectronic device assembly incorporating surface mount components according to the present disclosure, and Figures 10B1-10D Different die assemblies incorporating surface mount components are shown;

[0027] Fig.11A is a flow chart of an embodiment of a method for fabricating a microelectronic device assembly incorporating an inductively coupled loop (ICL) for data signal transmission and through polysilicon vias (TPVs) for power and ground biasing according to the present disclosure, and Fig. 11B is a schematic side elevation view of a microelectronic device package according to an embodiment of the present disclosure, wherein the microelectronic device package can be configured according to Fig.11A Method of manufacturing;

[0028] Fig.12 is a side cross-sectional schematic elevation view of a microelectronic device assembly incorporating through-silicon vias (TSVs) and through-polysilicon vias (TPVs) according to an embodiment of the present disclosure;

[0029] Fig.13A is a flow chart of an embodiment of a method for manufacturing a microelectronic device package using a redistribution layer (RDL) of a fan-out package (FOP) configuration according to the present disclosure, and Fig. 13B is a schematic side cross-sectional view of a microelectronic device package using an RDL configured with a FOP according to an embodiment of the present disclosure; and

[0030] Fig.14A is a flow chart of an embodiment of a method for manufacturing a microelectronic device package employing an RDL in a FOP configuration combined with TPV according to the present disclosure, and Fig. 14B is a schematic side cross-sectional view of a microelectronic device package using an RDL in a FOP configuration combined with TPV according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] A microelectronic device package including a plurality of stacked microelectronic devices (eg, semiconductor dies) without TSVs and methods for making such a package and related electronic systems.

[0032] The following description provides specific details, such as size, shape, material composition and orientation, so as to provide a comprehensive description of the embodiments of the present disclosure. However, it will be appreciated by those skilled in the art that the embodiments of the present disclosure may be practiced without adopting these specific details. The embodiments of the present disclosure may be practiced in conjunction with conventional manufacturing techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic package, a structure comprising a microelectronic package, or a system (e.g., an electronic system) comprising a microelectronic package. Only those process actions and materials necessary for understanding the embodiments of the present disclosure are described in detail below. Other actions and materials for forming a complete microelectronic device package, a complete structure comprising a microelectronic package, or a complete system comprising a microelectronic package may be performed by conventional manufacturing processes.

[0033] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions shown, but rather include shape deviations resulting from, for example, manufacturing. For example, a region shown or described as a frame-shape may have rough and / or nonlinear features, and a region shown or described as a circle may include some rough and / or linear features. In addition, the acute angles between the surfaces shown may be rounded, and vice versa. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shape of the region and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale.

[0034] As used herein, the terms "comprising," "including," "containing," "characterized by," and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or methodological actions, and also encompass the more restrictive terms "consisting of" and "consisting essentially of," and grammatical equivalents thereof. As used herein, the term "may," with respect to materials, structures, features, or methodological actions, indicates that these are contemplated for use in implementations of the embodiments of the present disclosure, and such terms are used in preference to the more restrictive term "are," to avoid any suggestion that other compatible materials, structures, features, and methods that may be used in conjunction therewith should or must be excluded.

[0035] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to the major plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in which or on which one or more structures and / or features are formed, and the one or more structures and / or features are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of a substrate is defined by a surface of the substrate having a relatively larger area than other surfaces of the substrate.

[0036] As used herein, for ease of description, spatially relative terms such as "below", "under", "lower", "bottom", "above", "above", "upper", "top", "front", "back", "left", "right", etc. may be used to describe the relationship of one element or feature to another or more elements or features as shown in the accompanying drawings. Unless otherwise stated, spatially relative terms are intended to cover different material orientations in addition to the orientation depicted in the accompanying drawings. For example, if the material in the accompanying drawings is inverted, the elements described as being "above" or "above" or "above" or "top" other elements or features will be oriented as being "below" or "below" or "below" or "bottom" of the other elements or features. Therefore, depending on the context in which the term is used, the term "above" can cover both the above and below orientations, which will be apparent to one of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein are interpreted accordingly.

[0037] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] As used herein, the terms "configured" and "configuration" refer to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device, which size, shape, material composition, orientation, and arrangement facilitate operation of one or more of the structures and devices in a predetermined manner.

[0039] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses to the extent that one of ordinary skill in the art would understand that the given parameter, property, or condition satisfies a certain degree of variance, such as variance within acceptable manufacturing tolerances. For example, depending on a particular parameter, property, or condition being substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 95.0% satisfied, at least 99.0% satisfied, or even at least 99.9% satisfied.

[0040] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a certain degree of difference relative to the numerical value that will be understood by those of ordinary skill in the art as being within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0041] As used herein, the terms "layer" and "film" mean and include a layer, sheet, or coating of a material residing on a structure, which layer or coating may be continuous or discontinuous between portions of the material and may be conformal or non-conformal, unless otherwise specified.

[0042] As used herein, the term "substrate" means and includes a base material or structure on which additional materials are formed or additional structures are positioned, or both. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, one or more layers, one or more structures, or one or more regions formed thereon. The material on the semiconductor substrate may include, but is not limited to, semiconductor materials, insulating materials, conductive materials, and the like. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon on insulator ("SOI") substrates (such as silicon on sapphire ("SOS") substrates and silicon on glass ("SOG") substrates), silicon epitaxial layers on base semiconductors, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped. In some embodiments, the substrate may include an interposer or a circuit board.

[0043] As used herein, the terms "comprising," "including," "containing," "characterized by," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps, and also encompass the more restrictive terms "consisting of," and "consisting essentially of," and their grammatical equivalents.

[0044] As used herein, the term "configuration" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device, which size, shape, material composition, orientation, and arrangement facilitate operation of one or more of the structures and devices in a predetermined manner.

[0045] As used herein, the term "may" with respect to materials, structures, features, or method acts indicates that these are intended for use in implementations of the embodiments of the present disclosure, and such terminology is used in preference to the more restrictive term "is" to avoid any suggestion that other compatible materials, structures, features, and methods that may be used in conjunction therewith should or must be excluded.

[0046] As used herein, the term "wafer" should be broadly interpreted to mean and include conventional semiconductor material wafers as well as other bulk substrates including semiconductor material on another supporting material.

[0047] As used herein, the term "microelectronic device" means and includes singulated semiconductor dies, groups of unsingulated semiconductor dies, dies and groups of dies that include functions other than those that rely on semiconductor materials (e.g., optical devices and MEMS devices). Likewise, as used herein, the term "semiconductor die" may be broadly interpreted to encompass other microelectronic devices.

[0048] As used herein, the terms "fan-out package" and FOP mean and include a microelectronic device package that includes at least one layer of conductive traces carried on a dielectric material such as a film and operably coupled to the bonding pads of an associated semiconductor die and extending (i.e., fanning out) to locations outside the periphery of the die on one or more sides thereof. Similarly, a redistribution layer or RDL of a FOP configuration is a redistribution layer that includes at least one layer of conductive traces carried on a dielectric material such as a film and configured to have inner ends at locations of the bonding pads of the semiconductor to be operably coupled to the conductive traces, which extend (e.g., fan out) to locations outside the periphery of the mounting location of the semiconductor die, leading to locations outside the periphery of the die mounting location on one or more sides thereof.

[0049] As used herein, "memory device" means and includes a microelectronic device that exhibits, but is not limited to, memory functionality.

[0050] Figure 1A1 and 1A2are two portions of a flow chart of an embodiment of a method 100 for manufacturing a microelectronic device package according to the present disclosure. In act 102, active circuitry (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on an active surface of a semiconductor substrate (e.g., a wafer). In act 104, the wafer is probed to determine the location of a known good die (KGD). In act 106, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example, to a thickness of about 5 μm to about 200 μm, and as specific non-limiting examples, to a thickness of approximately about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) into individual KGDs at act 108 using conventional processes (saw blade, laser, stealth (i.e., laser induced street-like defects followed by fracture caused by radial expansion of the carrier film), etc.). In act 110, a reconstructed wafer or panel of KGDs is then (optionally) formed by placing the singulated KGDs by their back sides in a spaced relationship with each other and adhering them to an adhesive film (e.g., a die attach film (DAF) or film on die (FOD) type material). In act 112, a film is laminated over the front side (i.e., active surface) of the spaced KGDs of the reconstructed wafer or panel, or to the active surfaces of the singulated KGD locations thereon, the film being, for example, a wafer or panel level film, such as a non-conductive film (NCF) comprising a silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 114, openings are formed through the film (e.g., by laser ablation) to expose bonding pad locations on the active surface of the KGD, followed by, optionally, a solvent cleaning act to remove any residue from the laser ablation at the bonding pad locations, thereby ensuring a strong electrical connection between the conductive traces that will be formed on the polymer film in act 116. In act 116, a conductive material, such as an Ag or Cu paste, is dispensed to form conductive traces on the polymer film from the bonding pads to predetermined via locations outside the lateral periphery of the KGD. Alternatively, the conductive traces can be applied by inkjet technology. In act 118, the KGDs are singulated laterally through the polymer film outside of the predetermined via locations, and the KGDs are stacked on a substrate, which can be a wafer-level substrate to be singulated into individual substrates and carrying a plurality of KGD stacks in a spaced relationship with each other. In act 120, vias, which may be referred to as through-poly vias (TPVs), may be formed through the films in the KGD stack at the via locations, such as by laser or patterned and anisotropic etching, and extended to conductive pads or traces on an adjacent surface of the substrate.In act 122, the vias are filled with a sintered Ag or Cu paste or other conductive material, for example using an inkjet-type applicator. As another approach, the vias may be filled with Sn solder in a wave soldering process. In act 124, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths extending to conductive pads or traces on the substrate surface adjacent to the KGD stack) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the EMC (if present) and the substrate to form a package. In act 126, the top of the die stack may be covered with the EMC, or it may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM).

[0051] Figure 1B is a schematic side cross-sectional view of a microelectronic device package 150 according to an embodiment of the present disclosure, and the microelectronic device package can be Figure 1A1 and 1A2The microelectronic device package 150 includes a substrate 152 having traces (not shown) carried in a dielectric material and extending from a conductive pad 154 on its upper surface to a conductive element 156 on its opposite lower surface. The conductive element 156 may include, for example, solder balls formed on or applied to an under bump metallization layer (UBM) of the substrate 152. A plurality of semiconductor dies 160A-160D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 152. Each semiconductor die 160A-160D is laminated to a polymer film 162, such as a non-conductive film (NCF), a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film extending beyond at least one lateral periphery of the corresponding die 160A-160D on one or more sides thereof (two sides are shown). Each semiconductor die 160A-160D is attached to a DAF 164 on its back side 166. The DAF may be eliminated if an NCF exhibiting adequate adhesive properties is employed for lamination purposes. Conductive traces 168 extend laterally outward from bonding pad locations (not shown) on active surface 170 of each semiconductor die 160A-160D over upper surface 172 of polymer film 162, at least to locations of vias 174 filled with conductive material 176 extending between semiconductor die 160A-160D and to conductive pads 154 of substrate 152. As shown in dashed lines, semiconductor die 160A-160D may be encapsulated in, for example, an EMC 178 extending around at least the lateral periphery of die stack 180 and abutting the upper surface of substrate 152. As shown, EMC 178 may extend over the uppermost semiconductor die 160D. Alternatively, EMC 178 may have uncovered active surface 170 and conductive traces 168 covered by a thin dielectric layer that may include thermal interface material (TIM) 182 and heat spreader 184 , both shown in dashed lines, for enhancing heat transfer from microelectronic device package 150 .

[0052] Figure 2A200 is a flow chart of an embodiment of a method 200 for manufacturing a microelectronic device package according to the present disclosure. In 202, active circuit systems (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs are manufactured at die locations on an active surface of a semiconductor substrate (e.g., a wafer). In action 204, the wafer is probed to determine the location of a known good die (KGD). In action 206, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness of approximately about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) at action 208 using conventional processes (saw blades, lasers, stealth (i.e., laser-induced street defects followed by fractures caused by radial expansion of the carrier film), etc.). In act 210, a reconstructed wafer or panel of KGDs is then formed by placing and adhering the singulated KGDs by their front sides (i.e., active surfaces) in a spaced relationship with each other on the die mounting locations of a panel or wafer, the panel or wafer being configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more layers of conductive (e.g., copper) traces carried by a dielectric material, the conductive traces extending beyond at least one lateral periphery of the associated die locations. In act 212, a film is laminated over the back side of the KGDs of the reconstructed wafer or panel, the film being, for example, a wafer-level film such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 214, the panel or wafer of the polymer film and FOP configuration is singulated into segments, each segment carrying a separate FOP RDL and KGD. In action 216, the segments are then stacked on a substrate, which may be a wafer-level substrate to be singulated into individual substrates and carrying a plurality of KGD stacks in a spaced relationship with each other. In action 218, openings are formed (e.g., by laser ablation or anisotropic etching) through the polymer film and through the conductive traces of the RDL of the FOP configuration extending to the conductive pads or traces on the adjacent surface of the substrate, which openings may be referred to as TPVs. In action 220, the vias are filled with Ag or Cu paste or other conductive materials, for example, using an inkjet-type applicator. As another example, the vias may be filled with Sn solder in a wave soldering process. In action 222, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the EMC (if present) and the substrate to form a package.In act 224 , the top of the die stack may be covered with an EMC (if present), or may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM).

[0053] Figure 2B is a schematic side cross-sectional view of a microelectronic device package 250 according to an embodiment of the present disclosure, and the microelectronic device package can be Figure 2A The microelectronic device package 250 includes a substrate 252 having traces (not shown) carried in a dielectric material and extending from a conductive pad 254 on its upper surface to a conductive element 256 on its opposite lower surface. The conductive element 256 may include, for example, solder balls formed on or applied to an under bump metallization layer (UBM) of the substrate 252. A plurality of semiconductor dies 260A-260D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 252. Each semiconductor die 260A-260D is laminated to a polymer film 262, such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding die 260A-260D on one or more sides thereof (two sides are shown). A FOP-configured RDL 266 carrying conductive traces 268 is secured to the active surface 270 of each semiconductor die 260A-260D, with the conductive traces 268 extending laterally outward from bonding pad locations (not shown) on the active surface 270 of each semiconductor die 260A-260D through or over the RDL 266, at least to the locations of vias 274 filled with conductive material 276 extending between the semiconductor die 260A-260D and to the conductive pads 254 of the substrate 252. As shown in dashed lines, the semiconductor die 260A-260D are encapsulated in an EMC 278, for example, extending around at least the lateral periphery of the die stack 280 and abutting the upper surface of the substrate 252. As shown, the EMC 278 may extend over the uppermost semiconductor die 260D. Alternatively, EMC 278 may have uncovered active surface 270 and conductive traces 268 covered by a thin dielectric layer that may include thermal interface material (TIM) 282 and heat spreader 284 , both shown as dashed lines, for enhancing heat transfer from microelectronic device package 250 .

[0054] Figure 3A30 is a flow chart of an embodiment of a method 300 for manufacturing a microelectronic device package according to the present disclosure. In action 302, an active circuit system without TSV (e.g., a DDRx DRAM with a master / slave architecture) is manufactured at the die location of the active surface of a corresponding semiconductor substrate (e.g., a wafer) configured for a master architecture and a slave architecture, respectively. In action 304, the master wafer and the slave wafer are each probed to determine the location of a known good die (KGD). In action 306, the master wafer is a post-processing wafer with conductive (e.g., copper) elements in the form of columns configured for direct chip attachment (DCA). In action 308, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example, to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness of approximately about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The master and slave wafers are then singulated (i.e., cut) at act 310 using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fractures caused by radial expansion of the carrier film), etc.). In act 312, a reconstructed wafer or panel of master die KGDs is then formed by placing and adhering the singulated master KGDs by their backsides in a spaced relationship with each other on a panel or wafer comprising a polymer film, such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 314, a reconstructed wafer or panel of slave KGDs is then formed by placing and adhering the singulated slave KGDs by their front sides (i.e., active surfaces) in a spaced relationship with each other on the die mounting locations of a panel or wafer, the panel or wafer being configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more layers of conductive (e.g., copper) traces carried by a dielectric material and extending beyond at least one lateral periphery of the associated die mounting locations. In act 316, a film is laminated over the back side of each of the reconstructed master and slave KGD wafers or panels, the film being, for example, a wafer-level film such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 318, the reconstructed master and slave wafers are singulated into segments between the master KGD locations and between the RDLs of the FOP configuration, respectively, each segment carrying a separate master KGD or slave KGD, wherein a FOP RDL is associated with each slave KGD. In action 320, the master KGD segments are placed in a spaced relationship on a wafer-level substrate, inverted with their conductive pillars in a DCA orientation opposite to the conductive pads or traces of the substrate, and thermocompression bonded. In action 322, the slave KGDs are then stacked on the master KGDs in a spaced relationship.In act 324, openings are formed (e.g., by laser ablation or anisotropic etching) through the polymer film and through the conductive pads or traces extending to the substrate from the conductive traces of the RDL of the FOP configuration of the KGD, which openings may be referred to as TPVs. In act 326, the vias are filled with Ag or Cu paste or other conductive material, for example, using an inkjet-type applicator. As another example, the vias may be filled with Sn solder in a wave soldering process. In act 328, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the EMC (if present) and the substrate to form a package. In act 330, the top of the die stack may be covered with the EMC, or it may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM).

[0055] Figure 3B is a schematic side cross-sectional view of a microelectronic device package 350 according to an embodiment of the present disclosure, and the microelectronic device package can be Figure 3AThe microelectronic device package 350 includes a substrate 352 having traces (not shown) carried in a dielectric material and extending from conductive pads 354a and 354b on its upper surface to conductive elements 356 on its opposite lower surface. The conductive elements 356 may include, for example, solder balls formed on or applied to an under-bump metallization (UBM) layer of the substrate 352. A plurality of semiconductor dies 360A-360D (e.g., dies configured as double data rate (DDRx) DRAMs in a master / slave architecture) are stacked on the upper surface of the substrate 352. Each semiconductor die 360A-360D is laminated on its back side to a polymer film 362, such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film extending beyond the lateral periphery of the corresponding die 360A-360D on one or more sides thereof (two sides are shown). The semiconductor die 360A is inverted in a flip chip orientation over the substrate 352, and the conductive elements in the form of pillars P are connected to the conductive pads 354a in a DCA arrangement by thermocompression (i.e., diffusion) bonding. A FOP-configured RDL 366 carrying conductive traces 368 is secured to the active surface 370 of each semiconductor die 260B-260D, the conductive traces 368 extending laterally outward from the bonding pad locations (not shown) on the active surface 370 of each semiconductor die 360B-360D through or over the RDL 366, at least to the locations of vias 374 filled with conductive material 376 extending between the semiconductor die 360A-360D and to the conductive pads 354b of the substrate 352. As shown, the semiconductor die 360A-360D are encapsulated in, for example, an EMC 378 extending around at least the lateral periphery of the die stack 380 and abutting the upper surface of the substrate 352. As shown, EMC 378 can extend over the uppermost semiconductor die 360D. Alternatively, EMC 378 can leave the uncovered active surface 370 and conductive traces 368 covered by a thin dielectric layer that can include a thermal interface material (TIM) 382 and a heat sink 384, both shown as dashed lines, for enhancing heat transfer from microelectronic device package 350.

[0056] Although the three embodiments shown and described above provide TPVs on opposite sides of the die stack, the embodiments of the present disclosure are not limited thereto. For example, an RDL of a FOP configuration or a conductive trace ( Figure 1A1 , 1A2 The other dielectric films of 1B) may extend beyond the lateral periphery of the die stack DS on the substrate S on one side, two sides, three sides or four sides of the die stack, as shown in FIG. Figures 4A-4D What is shown.

[0057] In addition, although the three embodiments shown and described above provide a single row of TPVs, the embodiments of the present disclosure are not limited thereto. For example, Figure 5A A substrate S with a die stack DS is shown, the substrate having RDL or including conductive traces ( Figure 1A1 , 1A2 and 1B), the RDL or other dielectric film having two rows of aligned TPVs on each of the four sides, and Figure 5B A substrate S with a die stack DS is shown, the substrate having RDL or including conductive traces ( Figure 1A1 , 1A2 and 1B), the RDL or other dielectric film having three rows of staggered TPVs on each of the four sides. Of course, the number of TPVs on one side of the die stack may be different from the number of TPVs on one or more other sides thereof. In addition to moving the signal, power, and ground (e.g., bias) paths to locations outside the semiconductor die of the die stack DS, if one or more semiconductor dies (other than NAND flash memory) of the die stack DS are susceptible to electromagnetic interference (EMI), the outer ring of the ground TPV (TPVg) can provide a ground stitching function for the die stack DS. Similarly, a ground plane or ground grid, trace array, or other ground structure GS extending over the top of the die stack DS and operably coupled to the ground TPVg can provide a complete Faraday cage that protects the die stack DS from EMI and serves as an EMI shield, such as Figure 5C As shown. The ground structure GS may include a conductive (e.g., metal) mesh or a conductive film. In the former case, the size of the mesh and the thickness of the mesh material may be adjusted to isolate desired EMI frequencies. Of course, the ground structure GS is electrically isolated by dielectric material from the conductive traces on top of the die stack DS that are operably coupled to the semiconductor die. Figure 5C In another embodiment of the structure, as shown by the dashed line, the radio frequency antenna RF can be disposed on the dielectric film D and electrically isolated from the ground structure GS by the dielectric film D, and operably coupled to one or more semiconductor dies in the die stack DS. The radio frequency antenna RF can be formed in situ to a configuration and thickness tuned to the expected operating wavelength.

[0058] Furthermore, it is contemplated that each layer of conductive traces extending from the bonding pad locations on the various semiconductor dies may be identical and extend to locations such as Figure 1A1 , 1A2 , 2A and 3A, or can be customized so that some or all of the conductive trace patterns of a given semiconductor die layer can be the same or different from the conductive trace patterns of one or more other semiconductor die layers in the stack. Fig. 6A As shown, the conductive traces T of the third layer SD3 and the fourth layer SD4 of the semiconductor die SD1-SD4 can be operably coupled to the conductor C of the TPV by physical and electrical contact with the sidewalls of the conductor C, while the conductive traces T of the first layer SD1 and the second layer SD2 can be electrically isolated from the TPV by the dielectric material surrounding the conductor C. Therefore, in some examples, a signal generated by the circuit system of one semiconductor die (e.g., SD4) can be routed through the conductor C of the TPV and received by the circuit system of another die (e.g., SD3) and the circuit system of the substrate S. Similarly, a signal can be routed between the circuit system of one semiconductor die (e.g., SD3) and another semiconductor die (e.g., SD1) through the conductor C of one TPV, and routed between the circuit systems of the substrate S through the conductor C of another TPV.

[0059] like Figure 6B As shown, in the case of using multiple rows of TPVs, the conductive traces T may extend from the semiconductor die SD to the conductors C of different rows of TPVs at different layers and be operably coupled to the conductors C. Figure 6B In the case of , the conductive traces T of the first layer SD1 and the third layer SD3 of the semiconductor die SD1-SD4 are operably coupled to the conductors C of the TPVs of the inner row, and the second layer SD2 and the fourth layer SD4 are operably coupled to the conductors C of the TPVs of the outer row. As previously described, the rows of TPVs may be aligned, in which case the conductive traces T may extend from the semiconductor die SD and be routed around the TPVs of the inner row to extend to the TPVs of the outer row, as Figure 6C As shown, in the TPV line Fig.6D In the staggered case shown, the conductive trace T can extend directly from the semiconductor die SD between the TPVs in the inner row to reach the TPVs in the outer row and couple with their conductors C. In the case of a multi-row TPV arrangement, through the selective contact and selective electrical isolation of the trace T with a given conductor C, signals can not only be selectively routed between the circuit systems of the semiconductor dies SD1-SD4 and between the circuit system of any one of the semiconductor dies SD1-SD4 and the circuit system of the substrate S, but the signal can also be routed from a trace T of one semiconductor die up or down along a given conductor C of one TPV to a trace T on another semiconductor die, and returned to the conductor C of a different TPV in a different row through another trace T of another semiconductor die, thereby increasing the potential number of available signal paths.

[0060] Figure 7700 is a block diagram of an illustrative electronic system 700 according to an embodiment of the present disclosure. The electronic system 700 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 700 includes at least one memory device 702. The memory device 702 may include, for example, Figure 1B , 2B 3B or 3B. The electronic system 700 may further include at least one electronic signal processor device 704 (commonly referred to as a "microprocessor"). The electronic signal processor device 704 may optionally include a microprocessor according to Figure 1B , 2B 3B or any of the embodiments of the microelectronic device package previously described herein. Figure 7 702 and the electronic signal processor device 704 are depicted as two (2) separate devices, but in other embodiments, the electronic system 700 includes a single (e.g., only one) memory / processor device having the functionality of the memory device 702 and the electronic signal processor device 704. In such embodiments, the memory / processor device may include a processor according to, for example, Figure 3B The electronic system 700 may further include one or more input devices 706 for inputting information into the electronic system 700 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 700 may further include one or more output devices 708 for outputting information (e.g., visual output or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 706 and the output device 708 may include a single touch screen device, which can be used to input information to the electronic system 700 and to output visual information to the user. The input device 706 and the output device 708 can be in electrical communication with one or more of the memory device 702 and the electronic signal processor device 704.

[0061] In the above embodiments, a specific number of semiconductor dies in a given die stack has been mentioned as an example, but the number of semiconductor dies in the stack is not limited thereto. For example, a stack of DRAM memory dies may include thirty-two dies, while a stack of NAND flash memory dies may include up to 128 or even 256 dies.

[0062] In addition, although specific types of semiconductor dies are mentioned as examples in the above embodiments, there is no limitation on the type or types of dies that can be stacked in a single die stack. In other words, other types of memory dies, such as SRAM, HRAM, MRAM, and FeRAM, etc., can be stacked. In addition, in addition to conventional microprocessors, logic dies including memory controller dies and processors (e.g., graphics processor units (GPUs), audio processors, and ASICs including processor cores and memory blocks) can be stacked in combination with dies that exhibit other functions (such as logic and memory dies). Field programmable gate arrays (FPGAs) are another example of stackable components.

[0063] The customization of each layer of conductive traces obtainable through embodiments of the present disclosure enables bonding pads of different patterns and at different (e.g., center, multiple rows adjacent to the centerline, periphery on one or more sides) locations of semiconductor dies exhibiting different functions to be easily operably coupled to peripherally positioned TPVs to connect to conductive pads and traces on the substrate for communication with higher-level packages through conductive paths extending to conductive elements of the substrate. The implementation of the RDL of the FOP configuration carrying multiple layers of conductive traces adds further flexibility to the ever-expanding number of pin connections of the most advanced semiconductor dies. In addition, instead of conventional organic substrates, a silicon substrate including an active circuit system can be used. For example, embodiments of the present disclosure can be used to implement a wide range of I / O hybrid memory cube architectures using DDR logic in a memory die stack without the need to use expensive TSVs while allowing greater memory density. Similarly, embodiments of the present disclosure can be used to implement a wide range of I / O high-bandwidth memory architectures using device logic in a memory die stack without the need to use expensive TSVs while allowing greater memory density.

[0064] Fig. 8A8 is a flow chart of an embodiment of a method 800 for manufacturing a microelectronic device package including a stack of multiple microelectronic devices according to the present disclosure. In action 802, an active circuit system (e.g., DRAM, NAND, 3D Xpoint (e.g., SXP)) without TSVs is manufactured at the die location on the active surface of a semiconductor substrate (e.g., a wafer). In action 804, the wafer is probed to determine the location of a known good die (KGD). In action 806, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example, to a thickness of about 5 μm to about 200 μm, and as specific non-limiting examples, to a thickness of approximately about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) into individual KGDs at act 808 using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of the carrier film), etc.). In act 810, a reconstructed wafer or panel of KGDs is then (optionally) formed by placing the singulated KGDs in a spaced relationship by their back sides and adhering them to an adhesive film (e.g., a die attach film (DAF) or film-on-die (FOD) type material). In act 812, a polymer film is laminated over the front side (i.e., active surface) of the spaced KGDs of the reconstructed wafer or panel, or laminated onto the adhesive film (if present), wherein the polymer film is, for example, a wafer or panel level film, such as a non-conductive film (NCF) including a silica-filled epoxy resin, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 814, openings are formed through the polymer film (e.g., by laser ablation) to expose bonding pad locations on the active surfaces of the KGDs, followed by, optionally, a solvent cleaning act to remove any residue from the laser ablation at the bonding pad locations, thereby ensuring a robust electrical connection between the conductive traces that will be formed on the polymer film in act 816. In act 816, a conductive material (e.g., Ag or Cu paste) is dispensed to form conductive traces on the polymer film that extend from the bonding pads to predetermined via locations beyond the lateral periphery of the KGDs and, in some embodiments, between adjacent KGDs to be packaged together. Alternatively, the conductive traces may be applied by inkjet technology. In action 818, the KGDs are singulated laterally using a cutting blade through the polymer film and optional adhesive film outside of the predetermined through-hole locations and around groups (e.g., two groups, three groups, four groups, etc.), and multiple groups of KGDs are stacked on a substrate, which can be a wafer-level substrate to be singulated into individual substrates and carrying multiple KGD stacks in a spaced relationship with each other.In action 820, a via, which may be referred to as a through poly via (TPV), may be formed through the film in the KGD stack at the via location, such as by laser or patterned and anisotropic etching, and extended to a conductive pad or trace on an adjacent surface of the substrate. In action 822, the via is filled with a sintered Ag or Cu paste or other conductive material, such as by using an inkjet type applicator. As another approach, the via may be filled with Sn solder in a wave soldering process. In act 824, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths extending to conductive pads or traces on a substrate surface adjacent to the KGD stack) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stacks singulated into groups of KGD stacks may be operably coupled to each other via conductive traces extending between the KGD stacks and through the EMC (if present) and the substrate to form a package. In act 826, the top of the KGD stack may be covered with the EMC, or it may be exposed, for example, for attaching a heat sink with an interposer thermal interface material (TIM).

[0065] Figure 8B is a schematic side cross-sectional view of a microelectronic device package 850 according to an embodiment of the present disclosure, and the microelectronic device package can be Fig. 8AThe microelectronic device package 850 includes a substrate 852 having traces (not shown) carried in a dielectric material and extending from a conductive pad 854 on its upper surface to a conductive element 856 on its opposite lower surface. The substrate 852 may include an organic or inorganic (e.g., silicon) material, the latter allowing smaller features and tighter spacing than the former. The conductive element 856 may include, for example, solder balls formed on or applied to terminal pads on the bottom surface of the substrate 852. A plurality of semiconductor dies 860A1-860D1 and 860A2-860D2 (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory) to be grouped in the package are stacked on the upper surface of the substrate 852. Each of the semiconductor dies 860A1 and 860A2, 860B1 and 860B2, 860C1 and 860C2, and 860D1 and 860D2 is laminated to a polymer film 862, such as a non-conductive film (NCF), b-staged polyimide film, or polytetrafluoroethylene (PTFE) film extending beyond at least one lateral periphery of the respective die 860A1-860D1, 860A2-860D2 on one or more sides thereof (two sides are shown). Each of the semiconductor dies 860A1 and 860A2, 860B1 and 860B2, 860C1 and 860C2, and 860D1 and 860D2 can be attached to a DAF 864 on its back side 866. The DAF can be eliminated if an NCF exhibiting adequate adhesive properties is employed for lamination purposes. Conductive traces 868 in the form of redistribution layers (RDLs) extend laterally outward from bonding pad locations (not shown) on the active surface 870 of each of the semiconductor die 860A1 and 860A2, 860B1 and 860B2, 860C1 and 860C2, and 860D1 and 860D2 over the upper surface 872 of the polymer film 862 and, at least in some cases, between adjacent die of a given layer in different stacks, to at least the location of through-holes 874 filled with conductive material 876 that extend between the semiconductor die 860A1-860D1 and the semiconductor die 860A2 and 860D2 and to the conductive pads 854 of the substrate 852. As shown by dashed lines, semiconductor die 860A1-860D1 and 860A2-860D2 may be encapsulated in an EMC 878 that extends, for example, at least around the lateral peripheries of die stacks 880A and 880B and between the die stacks and abuts an upper surface of substrate 852. As shown, EMC 878 may extend over the uppermost semiconductor die 860D1 and 860D2.Alternatively, the EMC 878 may cause the active surface 870 and conductive traces 868 of the uncovered uppermost semiconductor die of semiconductor die 860D1 and 860D2 to be covered by a thin dielectric layer, which may include a thermal interface material (TIM) and a heat sink for enhancing heat transfer from the microelectronic device package 850. In one embodiment, there may be only one master die (e.g., semiconductor die 860A1) in the package to control all other slave dies (i.e., 860B1-860D1 and 860A2-860D2) in the microelectronic device package 850, such control being achieved by conductive traces extending between the die stack, such as. Figure 8B Depicted and about Fig. 8A As described. Alternatively, for each corresponding associated stack of slave die 860B1-860D1 and 860A2-860D2, there can be a separate main die, such as 860A1 and 860A2, and the communication between the die stacks can be operated by conductive traces 868. Therefore, if necessary, the master / slave die stack can be separated across the package channel. If the package has a height restriction, but a large number of die (e.g., sixteen, thirty-two) are required, both methods can distribute the die across a larger footprint in multiple die stacks, and the first method can allow multiple or even lower die stacks, with the slave die of each die stack linked to a single main die in a stack. In another embodiment, a logic die configured as a memory controller can be used to replace the main die of each semiconductor die stack substrate, or a logic die can be deployed at the bottom of the semiconductor die stack and operably coupled to the memory die in multiple stacks.

[0066] Compared with the current 3D packaging process, through silicon vias (TSVs) are eliminated and post-wafer manufacturing actions to form complex back-end-of-line (BEOL) structures are not required. Fig. 8A and 8B The embodiment can significantly reduce costs. In the assembly process, DRAM, NAND or SXP memory can be easily stacked in layers, each layer including multiple dies. In addition, this embodiment allows the use of different conductive trace patterns for each different die layer and allows separate address pins. In addition, the power and / or ground of each die can be connected together or individually. As described above with respect to Figure 5C As described, EMI shielding in the form of a Faraday cage or grounding area can be incorporated into the redistribution layer (RDL) over and between the top die only or for each die layer.

[0067] One conventional die-to-substrate attachment technology for high-power, high-data-rate, high-I / O-count devices (e.g., memory controllers, ASICs, etc.) is direct chip attach (DCA), which allows for optimal signal and power / ground placement between the die and the package substrate, as well as placing more physical area (conceptually the entire die area) over it to distribute the connections. However, commodity memories are now being pushed into the power / signal space and can benefit from DCA, as discussed above with respect to Figure 3A and 3B As described, however, the cost of processing and manufacturing is a significant barrier. The best solution is to achieve the flexibility of DCA at the expense of bonding wires. Existing options for DCA include chip scale packaging (CSP) and fan-out packaging (FOP) approaches, neither of which offer the benefits of DCA at a low cost. Fig. 9A and 9B In an embodiment, the use of through polysilicon vias (TPVs) as described above may be adapted to perform the functionality of a DCA, but at a lower cost using a die incorporated into an iRDL structure formed in a post wafer fabrication process and including rerouting of bonding pads to traces in an array pattern suitable for DCA-like attachment to a substrate.

[0068] Fig. 9A900 is a flow chart of an embodiment of a method 900 for manufacturing a microelectronic device for direct chip attachment to a substrate according to the present disclosure. In action 902, active circuit systems (e.g., DRAM, NAND, 3D Xpoint (e.g., SXP)) without TSVs are manufactured at die locations on an active surface of a semiconductor substrate (e.g., a wafer), and iRDLs are formed with traces at each die location to reroute bonding pad locations on the active surface of the die into a Cu pad array. In action 904, the wafer is probed to determine the location of a known good die (KGD). In action 906, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example, to a thickness of about 5 μm to about 200 μm, and as specific non-limiting examples, to a thickness of approximately about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) into individual KGDs at act 908 using conventional processes (saw blade, laser, stealth (i.e., laser induced street-like defects followed by fracture caused by radial expansion of the carrier film), etc.). In act 910, a reconstructed wafer or panel of KGDs is then (optionally) formed by placing the singulated KGDs by their back sides in a spaced relationship with each other and adhering them to an adhesive film (e.g., a die attach film (DAF) or film on die (FOD) type material). In act 912, a film is laminated over the front side (i.e., active surface) of the spaced KGDs of the reconstructed wafer or panel over the KGDs and the adhesive film (if present), such as a wafer or panel level film, such as a non-conductive film (NCF) including a silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 914, vias are formed through the polymer film (e.g., by laser ablation) to expose the iRDL pads on the active surface of the KGD, followed by, optionally, a solvent cleaning act to remove any residue from the laser ablation on the iRDL pads. In act 916, a conductive material (e.g., Ag or Cu paste) is dispensed to fill the vias, or filled with another conductive material via inkjet technology. As another approach, the vias can be filled with Sn solder in a wave soldering process. In act 918, a cutting blade is used to singulate the KGD laterally through the polymer film outside of the predetermined via locations of the die footprint and TPV as shown by the dashed lines for connection to other higher dies in the stack to be formed, as described above with respect to Figure 3A and 3BIn act 920, each singulated KGD can be picked up, inverted and placed on a substrate with the conductive material-filled through-holes in the polymer film aligned with the terminal pads on the upper surface of the substrate, followed by heating the assembly to adhere the die to the substrate by curing the polymer film and bonding the conductive material in the through-holes to the terminal pads.

[0069] As described about Fig. 9A The process sequence described Fig. 9B As shown, a semiconductor die 950 carrying an iRDL 952 on an active surface 954 of the semiconductor die 950 has a bonding pad (not shown) rerouted to a (e.g., Cu) iRDL pad 956, this structure having a polymer film, such as NCF, b-stage polyimide film, or PTFE film 958 laminated thereon. A through hole 960 is then formed in the polymer film 958 by laser ablation to expose the iRDL pad 956. Ag, Cu, solder, or other conductive fill material is introduced to fill the through hole 960 and form a conductive contact 962. The semiconductor die 950 is then inverted and placed on a substrate 964, which can be an organic or inorganic (e.g., silicon) substrate, wherein the conductive contacts 962 of the semiconductor die 950 are aligned with the terminal pads 966 of the substrate 964. The assembly is then heated to adhere the semiconductor die 950 to the substrate 964 and the terminal pads 966 via the polymer film 958 and the conductive contacts 962, respectively. For example, a thermocompression bonding tool can be used for die placement accuracy and heating to achieve adhesion of the polymer film. In the case of NCF, the heating temperature will be above the glass transition temperature (T g ). As shown, terminal pads 966 are connected to conductive elements 968 (e.g., solder balls) on opposite sides of substrate 964 by traces and vias including conductive paths 970. Although a single die package is shown, the stacked die assembly can be complete and optionally packaged if desired, as described herein with respect to Figure 3A and 3B Depicted and described, wherein the lowermost main die is connected to the substrate as described.Of course, the described processes and resulting dies may be employed with dies that exhibit any functionality, and are not limited to memory.

[0070] As Fig. 9A and 9B Potential additional embodiments of the embodiments, and as Fig. 9CAs depicted, a die stack DS may be fabricated using a plurality of semiconductor dies 950′ below the topmost semiconductor die 950, the plurality of semiconductor dies being provided with TSVs 972 and then provided with a dielectric (e.g., polymer) film 958 having through-holes 960 aligned with the TSVs 972 and filled with a conductive fill material forming conductive contacts 962. The semiconductor dies 950 and 950′ may then be stacked in a laterally spaced relationship on a base wafer or other substrate 974, and physically and electrically connected by heating to cure the polymer film in the bond wires between the dies and between the bottommost die and the substrate, after which the assembly may be encapsulated with an EMC 976, and solder bumps 978 applied to the base wafer or substrate as shown in dashed lines, after which the complete package may be singulated, as is known in the art. Using this approach, the conventional use of Cu pillars (capped by solder in some cases) and thermocompression bonding of the die stack may be avoided.

[0071] Reference now Figures 10A-10D In further embodiments, the architecture of the die assembly previously described may be further adapted to provide additional advantages in packaging and performance by incorporating surface mount components at various layers of the semiconductor die in the die stack outside of the footprint of the stacked die. Fig. 10A1 is a flow chart of an embodiment of a method 1000 for manufacturing a microelectronic device assembly incorporating surface mount components according to the present disclosure. In action 1002, an active circuit system (e.g., DRAM, NAND, 3DXPoint (e.g., SXP)) without TSVs is manufactured at a die location on an active surface of a semiconductor substrate (e.g., a wafer). In action 1004, the wafer is probed to determine the location of a known good die (KGD). In action 1006, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example to a thickness of about 5 μm to about 200 μm, and as a specific non-limiting example, to a thickness of approximately about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) into individual KGDs at act 1008 using conventional processes (saw blade, laser, stealth (i.e., laser induced street-like defects followed by fracture caused by radial expansion of the carrier film), etc.). In act 1010, a reconstructed wafer or panel of KGDs is then (optionally) formed by placing and adhering the singulated KGDs by their active surfaces in a spaced relationship with each other on an RDL panel or wafer in a fan-out package (FOP) configuration, the panel or wafer having traces extending from the die's bonding pads to an area outside the die's footprint. In act 1012, surface mount components (e.g., capacitors, resistors, inductors) may be placed or pre-formed on an RDL panel or wafer in a FOP configuration, the panel or wafer being adjacent to but outside the semiconductor die's footprint at locations where vias will not be formed. In action 1014, a polymer film is laminated over the back side of the mutually spaced KGDs of the reconstructed wafer or panel, the polymer film being, for example, a wafer or panel level film, such as a non-conductive film (NCF) including a silicon dioxide-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In action 1016, the polymer film carrying the KGDs and the RDL of the FOP configuration is singulated with a dicing blade, and each individual KGD with the RDL is inverted and stacked on a base wafer or other substrate. In action 1018, through-holes (which may be referred to as through-polysilicon vias (TPVs)) may be formed, for example, by laser or patterning and anisotropic etching, through the RDL and polymer film in the KGD stack at the through-hole locations and extended to conductive pads or traces on an adjacent surface of the substrate. In act 1020, a sintered Ag or Cu paste is dispensed, or other conductive materials are employed, to fill the vias, for example, using an inkjet-type applicator, and form through-poly vias (TPVs). As another method, the vias may be filled with Sn solder in a wave soldering process.In act 1022, surface mount components (e.g., capacitors, resistors, inductors) may be placed or preformed and operably coupled to the RDL of the top die of each KGD stack, and coupled to other dies as needed through the conductive material of one or more TPVs. In act 1024, the KGD stack and substrate assembly may optionally be encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths extending to conductive pads or traces on the substrate surface adjacent to the KGD stack) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the EMC (if present) and the substrate to form a package. In act 1026, the top of the die stack may be covered with the EMC, or it may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM) if the surface mount components are mounted inside the die stack rather than on the top die.

[0072] like Figures 10B1-10D As depicted, it is possible to implement Fig. 10A The manufacturing process described is used to form different die assemblies. For example, Fig.10B1 is a side cross-sectional schematic elevation view of a microelectronic device package 1050B according to an embodiment of the present disclosure and Fig.10B2 is a schematic top elevation view thereof, and the microelectronic device package can be based on Fig. 10A . Although shown as a memory device package including a stack of memory dies, the structure is not limited thereto. The microelectronic device package 1050B includes a substrate 1052 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1054 on its upper surface to a conductive element 1056 on its opposite lower surface. The conductive element 1056 may include, for example, a solder ball formed on or applied to a terminal pad of the substrate 1052. A plurality of semiconductor dies 1060A-1060D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1052. Each semiconductor die 1060A-1060D is laminated to a polymer film 1062 on its back side, for example, on one or more sides ( Fig.10B1 Two sides are shown, Fig.10B2A non-conductive film (NCF), b-stage polyimide film, polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding tube core 1060A-1060D on four sides (shown). An RDL 1066 of a FOP configuration carrying conductive traces 1068 is fixed to the active surface 1070 of each semiconductor tube core 1060A-1060D, and the conductive traces 1068 pass through or cross the RDL 1066 and extend laterally outward from the bonding pad location (not shown) on the active surface 1070 of each semiconductor tube core 1060A-1060D, at least to the location of the through hole 1074 filled with conductive material 1076 (i.e., TPV), which extends between the semiconductor tube core 1060A-1060D and extends to the conductive pad 1054 of the substrate 1052. In this embodiment, one or more surface mount components (e.g., capacitors, resistors, inductors) SM (one shown), such as a decoupling capacitor, are mounted to the uppermost RDL 1066 and operably coupled to the uppermost RDL and, optionally, to one or more TPVs. Fig.10B2 As depicted, surface mount components SM may be mounted over one or more TPV locations and connected to conductive traces 1068 of the uppermost RDL. As shown in dashed lines, semiconductor die 1060A-1060D may then be encapsulated in an EMC 1078 extending, for example, around at least the lateral periphery of die stack 1080 and abutting the upper surface of substrate 1052. As shown, EMC 1078 may extend over uppermost semiconductor die 1060D.

[0073] Fig.10C1 is a side cross-sectional schematic elevation view of a microelectronic device package 1050C according to an embodiment of the present disclosure and Fig.10C2 is a schematic top elevation view thereof, and the microelectronic device package can be based on Fig. 10A . Although shown as a memory device package including a stack of memory dies, the structure is not limited thereto. The microelectronic device package 1050C includes a substrate 1052 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1054 on its upper surface to a conductive element 1056 on its opposite lower surface. The conductive element 1056 may include, for example, a solder ball formed on or applied to an under bump metallization layer (UBM) of the substrate 1052. A plurality of semiconductor dies 1060A-1060D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1052. Each semiconductor die 1060A-1060D is laminated to a polymer film 1062 on its back side, for example, on one or more sides ( Fig.10C1 Two sides are shown, Fig.10C2 A non-conductive film (NCF), b-stage polyimide film, polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding tube core 1060A-1060D on four sides (shown). An RDL 1066 of a FOP configuration carrying conductive traces 1068 is fixed to the active surface 1070 of each semiconductor tube core 1060A-1060D, and the conductive traces 1068 pass through or cross the RDL 1066 and extend laterally outward from the bonding pad location (not shown) on the active surface 1070 of each semiconductor tube core 1060A-1060D, at least to the location of the through hole 1074 filled with conductive material 1076 (i.e., TPV), which extends between the semiconductor tube core 1060A-1060D and extends to the conductive pad 1054 of the substrate 1052. In this embodiment, one or more surface mount components (e.g., capacitors, resistors, inductors) SM (two are shown), such as decoupling capacitors, are each mounted to an RDL 1066 external to the assembly and operably coupled to its traces 1068, and optionally to one or more TPVs via RDL traces 1068 extending from the surface mount component SM location to the TPV location. Fig.10C2 As depicted, the internally positioned surface mount components SM may be mounted spaced apart from the TPV locations. As shown in dashed lines, the semiconductor dies 1060A-1060D may then be encapsulated in an EMC 1078 extending, for example, around at least the lateral periphery of the die stack 1080 and abutting the upper surface of the substrate 1052. As shown, the EMC 1078 may extend over the uppermost semiconductor die 260D. Alternatively, the EMC 1078 may have the uppermost uncovered RDL 1066 covered by a thin dielectric layer, which may include a thermal interface material (TIM) and a heat sink for enhancing heat transfer from the microelectronic device package 1050C.

[0074] Fig. 10D is a side cross-sectional schematic elevation view of a microelectronic device package 1050D according to an embodiment of the present disclosure, and the microelectronic device package can be based on Fig. 10A. Although shown as a memory device package including a stack of memory dies and controller dies, it may be configured, for example, as a managed NAND (mNAND) package, but the structure is not limited thereto. The microelectronic device package 1050D includes a substrate 1052 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1054 on its upper surface to a conductive element 1056 on its opposite lower surface. The conductive element 1056 may include, for example, a solder ball formed on or applied to an under bump metallization layer (UBM) of the substrate 1052. A plurality of semiconductor dies 1060A-1060E (e.g., dies configured as NAND flash memory or 3D XPoint (e.g., SXP) memory (dies 1060A and 1060D), low power DRAM (LPDRAM) dies 1060C and 1060D, and a controller die (die 1060E)) are stacked on the upper surface of substrate 1052. However, other numbers and combinations of dies incorporating surface mount components that exhibit different functions may be manufactured. In addition, if a controller die, ASIC, or other relatively high power density device is deployed at the top of the die stack, a thermally conductive material such as a copper plate or other heat sink structure (not shown) may be placed between the topmost die and the relatively lower power density memory die below. This approach is applicable to all embodiments of the present disclosure. Each semiconductor die 1060A-1060E is laminated to a polymer film 1062 on its back side, for example on one or more sides thereof ( Fig. 10DA non-conductive film (NCF), b-stage polyimide film, polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding tube core 1060A-1060D on both sides (shown). An RDL 1066 of a FOP configuration carrying conductive traces 1068 is fixed to the active surface 1070 of each semiconductor tube core 1060A-1060E, and the conductive traces 1068 pass through or cross the RDL 1066 and extend laterally outward from the bonding pad location (not shown) on the active surface 1070 of each semiconductor tube core 1060A-1060E, at least to the location of the through hole 1074 filled with conductive material 1076 (i.e., TPV), which extends between the semiconductor tube core 1060A-1060E and extends to the conductive pad 1054 of the substrate 1052. In this embodiment, one or more surface mount components (e.g., capacitors, resistors, inductors) SM (two are shown), such as decoupling capacitors, are each mounted to the uppermost RDL 1066 (one above, one below) and operably coupled to its traces 1068. Two other surface mount components SM are mounted to the RDL 1066 outside the assembly and operably coupled to its traces 1068, and optionally coupled to one or more TPVs via RDL traces 1068 extending from the surface mount component SM locations to the TPV locations. Fig.10B2 and 10C2 As depicted, the interior positioned surface mount components SM may be mounted spaced apart from the TPV locations, while the top mounted surface mount components may be mounted anywhere above the uppermost RDL. As shown in dashed lines, the semiconductor dies 1060A-1060E may then be encapsulated in an EMC 1078 extending, for example, around at least the lateral periphery of the die stack 1080 and abutting the upper surface of the substrate 1052. As shown, the EMC 1078 may extend above the uppermost semiconductor die 1060E.

[0075] Figures 10A-10DEmbodiments use additional surface area of ​​the RDL of a FOP configuration outside of the footprint of each die to incorporate surface mount components (e.g., capacitors, resistors, inductors) near each die of a stacked die package. The surface mount components do not increase the package height if located inside the die stack on the internal RDL, and the additional vertical spacing between inter-die bonding wires provided by the die thickness can allow the use of larger (i.e., thicker) surface mount components. In addition, the placement of surface mount components can be optimized relative to each die, and placement of decoupling capacitors for stable power delivery close to the die is particularly beneficial due to the reduction in loop inductance and resistance. In contrast, placing substrate mounted decoupling capacitors near the die bonding pads is not possible due to manufacturing design rule checking (DRC) regulations. In addition, removing the surface mount components from the substrate of the package provides more signal routing space on the substrate.

[0076] Now referring to yet another embodiment, Fig.11A and 11B Depicted are a process sequence for fabricating a microelectronic device package employing an inductively coupled loop for data signal transmission and a TPV for power and ground / bias signal transmission, and a side cross-sectional schematic elevation view of the microelectronic device package, respectively, according to an embodiment of the present disclosure.

[0077] Fig.11Ais a flow chart of an embodiment of a method 1100 for fabricating a microelectronic device assembly incorporating an inductively coupled link (ICL) for data signal transmission and TPVs for power and ground / bias signal transmission according to an embodiment of the present disclosure. In act 1102, active circuitry (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on an active surface of a semiconductor substrate (e.g., a wafer). In one embodiment, the inductively coupled link (ICL) transmitter and ICL receiver may be fabricated in the metallization of the die in back end of line (BEOL) processing as part of the BEOL structure. In act 1104, the wafer is probed to determine the location of a known good die (KGD). In act 1106, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example, to a thickness of about 5 μm to about 200 μm, and as specific non-limiting examples, to a thickness of approximately about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness that does not compromise inductively coupled data signal transmission or induce crosstalk. The wafer is then singulated (i.e., cut) into individual KGDs at act 1108 using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of the carrier film), etc.). In act 1110, a reconstructed wafer or panel of KGDs is then formed by adhering and operably coupling the singulated KGDs by their active surfaces in a spaced relationship to each other on an RDL panel or wafer in a fan-out package (FOP) configuration, the panel or wafer having traces extending from the bond pads of the die to an area outside the die footprint. If the ICL transmitters and ICL receivers are not fabricated on the die, the RDL wafer or panel in the FOP configuration may incorporate the ICL transmitters and ICL receivers therein. In act 1112, a polymer film is laminated over the backside of the spaced KGDs of the reconstructed wafer or panel, the polymer film being, for example, a wafer or panel level film, such as a non-conductive film (NCF) comprising a silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 1114, the polymer film carrying the dies with ICL emitters and ICL receivers and the RDLs of the FOP configuration is singulated, and the individual dies each with the RDLs and the ICL emitters and ICL receivers are inverted and stacked on a base wafer or other substrate to a desired stack height (e.g., four, eight, twelve, sixteen dies). In act 1116, through-holes (which may be referred to as through-poly vias (TPVs)) may be formed, for example, by laser or patterned and anisotropic etching, through the RDLs and polymer film in the KGD stack at the through-hole locations and extended to conductive pads or traces on an adjacent surface of the substrate.In act 1118, a sintered Ag or Cu paste is dispensed, or other conductive material is employed, to fill the vias, for example using an inkjet-type applicator, and form through-polysilicon vias (TPVs). As another approach, the vias may be filled with Sn solder in a wave soldering process. In act 1120, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths extending to conductive pads or traces on the substrate surface adjacent to the KGD stack) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the EMC (if present) and the substrate to form a package. In act 1122, the top of the die stack may be covered with the EMC, or it may be exposed to attach a heat sink with a thermal interface material (TIM).

[0078] Fig. 11B is a side cross-sectional schematic elevation view of a microelectronic device package 1150 according to an embodiment of the present disclosure, and the microelectronic device package can be based on Fig.11A 11. Although shown as a memory device package including a stack of memory dies, the structure is not limited thereto. The microelectronic device package 1150 includes a substrate 1152 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1154 on its upper surface to a conductive element 1156 on its opposite lower surface. The conductive element 1156 may include, for example, a solder ball formed on or applied to a terminal pad of the substrate 1152. A plurality of semiconductor dies 1160A-1160D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1152. Each semiconductor die 1160A-1160D is laminated to a polymer film 1162 on its back side, such as on one or more sides thereof (by way of non-limiting example, Fig.10B1 and 10B2A non-conductive film (NCF), b-stage polyimide film, polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding tube core 1160A-1160D on both sides (shown). An RDL 1166 of a FOP configuration carrying conductive traces 1168 is fixed to the active surface 1170 of each semiconductor tube core 1160A-1160D, and the conductive traces 1168 (i.e., power and ground / bias traces) pass through or cross the RDL 1166 and extend laterally outward from the power and ground / bias bonding pad locations (not shown) on the active surface 1170 of each semiconductor tube core 1160A-1160D, at least to the location of the through hole 1174 filled with conductive material 1176 (i.e., TPV), which extends between the semiconductor tube core 1160A-1160D and extends to the conductive pad 1154 of the substrate 1152. The power and ground / bias signals may be combined for all semiconductor dies 1160A-1160D, or they may be single for at least some or all semiconductor dies 1160A-1160D. The ICL transmitters 1172T and ICL receivers 1172R of the RDL 1166 or incorporated into the die metallization are operably coupled to the data signal pinouts on the active surface 1170 of each semiconductor die 1160A-1160D via the data signal conductive traces 1168. The ICL transmitters 1172T and ICL receivers 1172R may be mounted anywhere within the footprint of each semiconductor die 1160A-1160D, with the ICL transmitters 1172T of one die cooperatively vertically aligned with the ICL receivers 1172R of one or more vertically adjacent dies, as shown. Similarly, an ICL transmitter 1172T and an ICL receiver 1172R may be provided on the upper surface of the substrate 1152, again in vertical alignment with the ICL receiver 1172R and ICL transmitter 1172T of the lowermost semiconductor die 1160A. Notably, sufficiently thinning the semiconductor dies 1160A-1160D (e.g., to about 50 μm or less) allows ICL signals to be transmitted and received between the ICL transmitters and ICL receivers on the active surfaces of vertically adjacent dies, eliminating any need to place ICL transmitters and ICL receivers on both sides of each die. The substrate 1152 may further include a conversion integrated circuit system 1190 operably coupled to the ICL transmitter 1172T and ICL receiver 1172R of the substrate 1152, the conversion integrated circuit system being used to convert the inductive data signal (i.e., the inductive current) into an electrical signal for communication with a higher level package.Alternatively, another lowermost die (not shown) (e.g., a controller die) equipped on its upper surface with an ICL transmitter 1172T and an ICL receiver 1172R to communicate with the semiconductor die 1160A-1160D may incorporate such conversion circuitry and be connected via a DCA or as above. Fig. 9A and 9B The connections depicted and described as being used as DCA connections are operatively coupled to substrate 1152. As shown by dashed lines, semiconductor dies 1160A-1160D may then be encapsulated in, for example, an EMC 1178 extending at least around the lateral periphery of die stack DS and abutting an upper surface of substrate 1152. As shown, EMC 1178 may extend over uppermost semiconductor die 1060D, or may cover only the sides of die stack DS.

[0079] The inductively coupled loop signal transmission implemented using the embodiments of the present disclosure as described above presents a low-power solution for transmitting data signals from one location to another without the need for a continuous physical connection, thereby eliminating the need for expensive TSVs or other physical interconnect devices (such as bonding wires) that present issues with package height and chip spacing to avoid short circuits. Since ICLs cannot provide power or grounding / bias, the use of ICL communications in conjunction with through-polysilicon vias (TPVs) makes it easy to vertically align the ICL transmitter and ICL receiver within the footprint of the die stack, while routing physical power and grounding / bias outside the footprint to the supporting substrate through the TPVs. Therefore, for ICL communications, not only are TSVs eliminated, but also potential tiled or stepped die stacking is eliminated, which would require complex design practices and limit the face-to-face area of ​​the die.

[0080] refer to Fig.12 Yet another embodiment of the present disclosure is shown and described. In this embodiment, both TSVs and TPVs are employed in a microelectronic device. Fig.121 is a side cross-sectional schematic elevation view of a microelectronic device assembly 1200 according to an embodiment of the present disclosure. Although shown as a memory device package including a stack of memory dies, the structure is not limited thereto. The microelectronic device assembly includes a substrate 1202 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1204 on its upper surface to a conductive element 1206 on its opposite lower surface. The conductive element 1206 may include, for example, solder balls formed on or applied to terminal pads of the substrate 1202. A plurality of semiconductor dies 1208A-1208D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1202. Each semiconductor die 1208A-1208D is surrounded by an EMC 1210 at its lateral periphery. A FOP-configured RDL 1212 carrying conductive traces 1214 is secured to an active surface 1216 of each semiconductor die 1208A-1208D, with the conductive traces 1214 (i.e., power and ground / bias traces) extending laterally outward from power and ground / bias bonding pad locations (not shown) on the active surface 1216 of each semiconductor die 1208A-1208D through or over the RDL 1212, at least to the location of a via 1218 filled with a conductive material 1220 (i.e., TPV) extending between the semiconductor die 1208A-1208D and to the conductive pad 1204 of the substrate 1202 for power and ground / bias signal communication. Of course, a FOP-configured RDL is not required, as a dielectric film carrying the conductive traces may be employed. As desired, the power and ground / bias connections may be combined for all semiconductor dies 1208A-1208D, or they may be single for each or at least some of the semiconductor dies 1208A-1208D. All semiconductor dies 1208A-1208C (but not the uppermost semiconductor die 1208D) have been fabricated with TSVs 1222 shown in dashed lines extending through their respective thicknesses from alignment bonding pads (not shown) of the integrated circuit system on active surface 1216 to conductive pads (not shown) on their backsides 1224. The uppermost semiconductor die 1208D has bonding pads on its active surface that align with the TSVs of the next lower semiconductor device 1208C. Conductive elements such as pillars 1226 (e.g., solder capped copper pillars) extend through polymer film 1211 and RDL 1212 between bonding pads and terminal pads, interconnecting semiconductor die 1208A-1208D through TSVs 1222 for data signal communication with conductive pads (not shown) of substrate 1202 within the footprint of the die stack.Instead of the pillar-like conductive elements, conductive material filling the through-holes in the polymer film in the bond wires may be employed, as described above with respect to FIG. Fig. 9A and 9B As shown in dashed lines, semiconductor die 1208A-1208D may then be encapsulated in another EMC 1228, for example, extending around at least the lateral periphery of die stack 1230 and abutting the upper surface of substrate 1202. As shown, EMC 1228 may extend over uppermost semiconductor die 1060D, or may cover only the sides of die stack 1230, leaving uppermost semiconductor die 1208D exposed, for example, for application of a TIM and heat sink structure.

[0081] Now refer to the accompanying drawings Figures 13A-14B , further embodiments of the present disclosure employing an RDL in a FOP configuration in combination with TPV are shown and described. Fig.13A1 is a flow chart of an embodiment of a method 1300 for manufacturing a microelectronic device package using an RDL configured with a FOP according to the present disclosure. In action 1302, active circuit systems (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs are manufactured at die locations on an active surface of a semiconductor substrate (e.g., a wafer). In action 1304, the wafer is probed to determine the location of a known good die (KGD). In action 1306, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness of approximately about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) at action 1308 using conventional processes (saw blades, lasers, stealth (i.e., laser-induced street defects followed by fractures caused by radial expansion of the carrier film), etc.). In act 1310, a reconstructed wafer or panel of KGDs is then formed by placing and adhering the singulated KGDs by their front sides (i.e., active surfaces) in a spaced relationship with each other on the die mounting locations of a panel or wafer, the panel or wafer being configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more layers of conductive (e.g., copper) traces optionally coupled to the bonding pads of the corresponding KGDs and carried by a dielectric material, the conductive traces extending to through-hole locations beyond at least one lateral periphery of the associated die footprint. In act 1312, the reconstructed panel or wafer of KGDs is then encapsulated in an EMC, adhered to a die attach film (DAF) on the side opposite to the RDL, and each KGD, the associated FOP-configured RDL, and the DAF are singulated to form a FOP-configured RDL package. Multiple packages are then stacked. In action 1314, openings are formed at the through-hole locations (e.g., by laser ablation or anisotropic etching) through the DAF, EMC and through the conductive traces of the RDL of the FOP configuration. In action 1316, Ag or Cu paste or other conductive material is dispensed, such as using an inkjet applicator to fill the through-holes to form TPVs. As another example, the through-holes can be filled with Sn solder in a wave soldering process. In action 1318, the stack of FOP packages is placed on a substrate, wherein the TPV is in conductive contact with the terminal pads on the upper surface of the substrate. If desired, the FOP packages can be stacked on the substrate before forming the TPVs. In act 1320, the assembly may (optionally) be encapsulated with another epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the other EMC (if present) and the substrate to form a package.In act 1322 , the top of the die stack may be covered with other EMC (if present), or may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM).

[0082] Fig. 13B is a schematic side cross-sectional view of a microelectronic device package 1350 according to an embodiment of the present disclosure, and the microelectronic device package can be Fig.13A The microelectronic device package 1350 includes a substrate 1352 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1354 on its upper surface to a conductive element 1356 on its opposite lower surface. The conductive element 1356 may include, for example, solder balls formed on or applied to terminal pads on the bottom surface of the substrate 1352. A plurality of semiconductor dies 1360A-1360D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory, all of which have no TSVs) are stacked on the upper surface of the substrate 1352. Each semiconductor die 1360A-1360D is laminated on the active surface 1362 to an RDL 1364 of a FOP configuration, the RDL of the FOP configuration extending beyond at least one lateral periphery of the corresponding die 1360A-1360D on one or more sides thereof (two sides are shown). Each semiconductor die 1360A-1360D is attached to a DAF segment 1366 on its back side 1368. Conductive traces 1370 of the RDL 1364 extend laterally outward from bonding pad locations (not shown) on the active surface 1362 of each semiconductor die 1360A-1360D over an upper surface 1372 of an EMC 1374 surrounding each semiconductor die 1360A-1360D, at least to locations of vias 1376 filled with conductive material 1378 extending between the semiconductor die 1360A-1360D and to conductive pads 1354 of the substrate 1352. As shown in dashed lines, the semiconductor die 1360A-1360D may be encapsulated in, for example, another EMC 1380 extending around at least the lateral periphery of the die stack and abutting the upper surface of the substrate 1352. As shown, EMC 1380 can extend over the uppermost semiconductor die 1360D. Alternatively, other EMC 1380 can leave the active surface 1362 and conductive traces 1370 of the uppermost uncovered semiconductor die 1360D covered by a thin dielectric layer that can include a thermal interface material (TIM) and a heat sink for enhancing heat transfer from the microelectronic device package 1350.

[0083] Fig.14A1400 is a flow chart of an embodiment of a method 1400 for manufacturing a microelectronic device package using an RDL configured with a FOP combined with TPV according to the present disclosure. In 1402, an active circuit system (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is manufactured at the die location on the active surface of a semiconductor substrate (e.g., a wafer). In action 1404, the wafer is probed to determine the location of a known good die (KGD). In action 1406, the wafer is thinned, for example, from an initial thickness of about 600 μm to about 700 μm, for example, to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness of approximately about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. Then, at action 1408, the wafer is singulated (i.e., cut) using conventional processes (saw blades, lasers, stealth (i.e., laser-induced street defects, followed by fractures caused by radial expansion of the carrier film), etc.). In act 1410, a reconstructed wafer or panel of KGDs is then formed by adhering and operably coupling the singulated KGDs by their front sides (i.e., active surfaces) in spaced relation to each other over die mounting locations of a panel or wafer, the panel or wafer being configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more layers of conductive (e.g., copper) traces optionally coupled to bonding pads of respective KGDs and carried by dielectric material, the conductive traces extending to through-hole locations beyond at least one lateral periphery of the associated die footprint. In act 1412, the reconstructed panel or wafer of KGDs is then encapsulated in an EMC. In action 1414, a polymer film is then laminated over the active surfaces of the spaced KGDs of the reconstructed wafer or panel, and the RDLs of each KGD, the surrounding EMC, and the associated FOP configuration, and the polymer film is singulated to form a package. In action 1416, which can be performed before the application of the polymer film and singulation, the KGDs to be placed at the bottom of the die stack are raised with conductive elements in the form of copper pillars or solder bumps, or can be raised with conductive materials (e.g., Ag or Cu paste) placed in through holes in the polymer film. In action 1418, the bottom (i.e., raised) KGD of the stack is inverted and placed on the substrate in a flip-chip orientation, with the active surface facing down, and connected to the terminal pads of the substrate through the polymer film. In act 1420, the remaining KGDs of the stack are then inverted and placed face down on top of the bottom-most KGD. In act 1422, openings are formed at via locations (e.g., by laser ablation or anisotropic etching) through the EMC, through the conductive traces of the RDL of the FOP configuration, and the polymer film.In action 1424, the vias are filled and TSVs are formed using an Ag or Cu paste or other conductive material, such as using an inkjet-type applicator. As another example, the vias may be filled with Sn solder in a wave soldering process. In action 1426, the assembly may be (optionally) encapsulated with another epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stack may be singulated through the other EMC (if present) and the substrate to form a package. In action 1428, the top of the die stack may be covered with other EMC (if present), or it may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM).

[0084] Fig. 14B is a schematic side cross-sectional view of a microelectronic device package 1450 according to an embodiment of the present disclosure, and the microelectronic device package can be Fig.14AThe microelectronic device package 1450 includes a substrate 1452 having traces (not shown) carried in a dielectric material and extending from a conductive pad 1454 on its upper surface to a conductive element 1456 on its opposite lower surface. The conductive element 1456 may include, for example, solder balls formed on or applied to an under bump metallization (UBM) layer of the substrate 1452. A plurality of semiconductor die 1460A-1460D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1452. Each semiconductor die 1460A-1460D is laminated on the active surface 1462 to an RDL 1464 of a FOP configuration, the RDL of the FOP configuration extending beyond at least one lateral periphery of the corresponding die 1460A-1460D on one or more sides thereof (two sides are shown). Conductive traces 1466 of the RDL 1464 extend laterally outward from bonding pad locations (not shown) on the active surface 1462 of each semiconductor die 1460A-1460D over a lower surface 1468 of the EMC 1470 around each semiconductor die 1460A-1460D to at least the locations of vias 1472 filled with a conductive material 1474 extending between the semiconductor die 1460A-1460D and to the conductive pads 1454 of the substrate 1452. A polymer film 1476, such as a wafer or panel level film, such as a non-conductive film (NCF) including a silicon dioxide filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film, is laminated over the RDL 1464 on each semiconductor die 1460A-1460D. Alternatively, a capillary underfill (CUF) may be placed between the semiconductor die 1460A-1460D. Conductive elements 1478 in the form of copper pillars or solder bumps extend through the polymer film 1476 between the bottommost semiconductor die 1460A and the substrate 1452 to contact the terminal pads (not shown) of the substrate 1452. The bottommost semiconductor die 1460A is connected to the substrate through the conductive element 1478 and is connected to the other semiconductor die 1460B-1460D through the conductive traces 1466 of the RDL 1464 and TPV associated therewith. The die stack may be encapsulated in another EMC 1480, for example, extending at least around the lateral periphery of the die stack and abutting the upper surface of the substrate 1452. As shown, the EMC 1480 may extend over the topmost semiconductor die 1460D.Alternatively, the EMC 1480 may have the uncovered backside of the semiconductor die 1460D covered by a thin dielectric layer, which may include a thermal interface material (TIM) and a heat spreader for enhancing heat transfer from the microelectronic device package 1450 .

[0085] Figures 13A-14B Embodiments of the present invention significantly reduce the cost of multi-die stacks and packages by eliminating TSVs and conventional post-wafer manufacturing processes on the die. In addition, these embodiments provide the ability to use different conductive trace designs for each RDL, thereby allowing separate address pins to be used for each die in the stack. Further, the power and ground / bias of the semiconductor dies in the stack can be connected together, or they can be individual for each die. In addition, customizing the trace pattern for each layer of RDL facilitates customization of multi-die package configurations for the same or different die functions.

[0086] Embodiments of the present disclosure include a microelectronic device assembly comprising: a microelectronic device having an active surface facing a substrate; and a preformed hole filled with a conductive material and extending through a dielectric film between an array of bonding pads on the active surface of the microelectronic device and terminal pads on the substrate.

[0087] Embodiments of the present disclosure include a microelectronic device assembly, the microelectronic device assembly comprising: a stack of microelectronic devices on a substrate, each microelectronic device including a TSV extending through its thickness between a bonding pad on an active surface and a terminal pad on a back surface thereof; and a dielectric film inserted between adjacent microelectronic devices of the stack, the dielectric film including preformed holes aligned between the bonding pads and the terminal pads of adjacent microelectronic devices of the stack, the preformed holes being filled with a conductive material that contacts the aligned bonding pads and terminal pads of adjacent microelectronic components.

[0088] An embodiment of the present disclosure includes a method comprising: forming a reconstructed wafer or panel by placing singulated semiconductor die in a spaced relationship with each other and laminating a polymer film over the active surface of the singulated semiconductor die including a bonding pad; forming a through hole through the polymer film to expose the bonding pad on the active surface; filling the through hole with a conductive material; singulating the semiconductor die of the reconstructed panel or wafer through the polymer film; inverting at least one semiconductor die and placing the inverted at least one semiconductor die on a substrate, wherein the through hole filled with the conductive material is aligned with the terminal pad on the substrate; and bonding the polymer film to the substrate, wherein the conductive material is in contact with the terminal pad.

[0089] Additional non-limiting example embodiments of the present disclosure are described below.

[0090] Embodiment 1: A method comprising:

[0091] forming a reconstituted wafer or panel by placing semiconductor dies in spaced relationship with one another and laminating a polymer film over active surfaces of the dies;

[0092] forming openings through the polymer film to expose bonding pads on the active surface;

[0093] forming conductive traces on the polymer film, the conductive traces extending from the bond pads to via locations outside the lateral periphery of the semiconductor die and between the semiconductor die;

[0094] singulating groups of two or more semiconductor dies through the polymer film and stacking the singulated groups of two or more semiconductor dies on a substrate;

[0095] forming a via through the polymer film on the semiconductor die stack at the via location; and

[0096] The vias are filled with a conductive material.

[0097] Embodiment 2: The method according to embodiment 1 further comprises, before forming the reconstructed wafer or panel:

[0098] Fabricating active circuitry on a die site on an active surface of a semiconductor substrate without TSVs;

[0099] Testing is performed to determine the die location of a known good die KGD;

[0100] Thinning the semiconductor substrate from an initial thickness to a thickness of about 5 μm to about 200 μm;

[0101] The semiconductor substrate is singulated into individual KGDs.

[0102] Embodiment 3: The method according to embodiment 1 or 2, further comprising, after filling the through hole with the conductive material:

[0103] encapsulating the singulated stacks of groups of two or more semiconductor dies on the substrate with an epoxy mold compound (EMC);

[0104] applying or forming a conductive element on the substrate opposite the stack of singulated groups of two or more semiconductor dies;

[0105] testing the singulated stacks of groups of two or more semiconductor dies; and

[0106] The singulated stacks of groups of two or more semiconductor dies are singulated through the EMC and the substrate.

[0107] Embodiment 4: The method of Embodiment 3, wherein encapsulating the singulated stacks of groups of two or more semiconductor dies comprises exposing tops of the stacks and applying a thermal interface material (TIM) and a heat spreader to the top of each stack.

[0108] Embodiment 5: The method of any one of Embodiments 1 to 4, wherein providing a singulated semiconductor die comprises providing a DRAM, NAND flash memory, or 3D XPoint (SXP) memory die.

[0109] Embodiment 6: The method of Embodiment 1, further comprising, prior to laminating the polymer film over the spaced apart semiconductor dies, placing the semiconductor dies by their backsides in spaced apart relationship on an adhesive film.

[0110] Embodiment 7: The method of Embodiment 6, wherein placing the semiconductor dies by their backsides in spaced relationship with each other on an adhesive film comprises placing the semiconductor dies on a die attach film (DAF) or film on die (FOD) material.

[0111] Embodiment 8: The method according to any one of embodiments 1, 5 or 6, wherein the laminated polymer film comprises a laminated non-conductive film (NCF), a b-staged polyimide film or a polytetrafluoroethylene (PTFE) film.

[0112] Embodiment 9: The method according to embodiment 2, wherein:

[0113] Fabricating active circuitry at a die location on an active surface of a semiconductor substrate without TSVs includes:

[0114] Fabricating active circuitry that exhibits a first function at a die location on an active surface of a first semiconductor substrate includes fabricating a memory die configured to operate as a slave die in a master / slave memory architecture; and

[0115] Fabricating active circuitry that exhibits at least one second different function at a die location on the active surface of the second semiconductor substrate includes fabricating a memory die configured to operate as a master die in a master / slave memory architecture.

[0116] Embodiment 10: The method of Embodiment 9, further comprising singulating groups of two or more main dies and placing the groups of two or more main dies on a substrate; and

[0117] A plurality of groups of two or more slave dies are stacked on the plurality of groups of two or more master dies.

[0118] Embodiment 11: The method of embodiment 9, wherein forming the reconstructed panel or wafer comprises:

[0119] forming a first reconstituted wafer by placing a master die in spaced relationship adjacent to one or more slave dies;

[0120] singulating groups of two or more semiconductor dies through the polymer film includes singulating primary dies grouped with one or more slave dies;

[0121] forming a second reconstituted wafer by placing the slave dies in spaced relationship to one another;

[0122] Singulating multiple groups of two or more semiconductor dies includes singulating multiple groups of two or more slave dies; the method further includes:

[0123] placing a plurality of sets of main dies having one or more singulations from the die on a substrate; and

[0124] The singulated groups of two or more slave dies are stacked on the groups of main dies having one or more slave dies, respectively.

[0125] Embodiment 12: The method according to embodiment 2, wherein:

[0126] Fabricating active circuitry at a die location on an active surface of a semiconductor substrate without TSVs includes:

[0127] Fabricating active circuitry that exhibits a first function at a die location on an active surface of a first semiconductor substrate includes fabricating a memory die; and

[0128] Fabricating active circuitry that exhibits at least one second different function at a die location on the active surface of the second semiconductor substrate includes fabricating a logic die configured to operate as a memory controller.

[0129] Embodiment 13: The method of Embodiment 12, further comprising singulating groups of two or more logic dies and placing the groups of two or more logic dies on a substrate; and

[0130] Groups of two or more memory dies are stacked on groups of two or more logic dies, respectively.

[0131] Embodiment 14: The method of embodiment 12, wherein forming the reconstituted panel or wafer comprises:

[0132] forming a first reconstituted wafer by placing a logic die in spaced relationship adjacent to one or more memory dies;

[0133] singulating groups of two or more semiconductor dies through the polymer film includes singulating a logic die grouped with one or more memory dies;

[0134] forming a second reconstituted wafer by placing the memory dies in spaced relationship with each other;

[0135] Singulating the plurality of groups of two or more semiconductor dies includes singulating the plurality of groups of two or more memory dies; the method further comprising:

[0136] Placing singulated groups of logic dies having one or more memory dies on the substrate; and stacking the singulated groups of two or more memory dies on the groups of one or more main dies, respectively.

[0137] Embodiment 15: A microelectronic device assembly comprising:

[0138] a substrate having a conductor exposed on a surface thereof;

[0139] two or more stacks of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having a bonding pad operably coupled to a first conductive trace extending over a dielectric material to a through-hole location beyond at least one side of the stacked microelectronic device and to a second conductive trace extending between at least some of the microelectronic devices in the two or more stacks of two or more microelectronic devices; and

[0140] A via extends through the dielectric material at the via location and includes conductive material contacting at least some of the conductive traces of each of the two or more stacks of two or more microelectronic devices and extends to an exposed conductor of the substrate.

[0141] Embodiment 16: A microelectronic device assembly according to embodiment 15, wherein at least some of the through holes comprising conductive material are configured to route signals between different stacked microelectronic devices in conjunction with conductive traces of selected microelectronic devices of the two or more microelectronic devices in the stack.

[0142] Embodiment 17: The microelectronic device assembly of Embodiment 15 or 16, wherein the microelectronic device comprises a semiconductor die.

[0143] Embodiment 18: A microelectronic device assembly according to embodiment 17, wherein the semiconductor die includes a master memory die on a substrate located at at least one stacked base of the microelectronic device, and the remainder of the semiconductor die in the microelectronic device assembly includes a slave memory die, wherein the microelectronic device assembly is configured with a master / slave DDR architecture.

[0144] Embodiment 19: The microelectronic device assembly of Embodiment 18, further comprising a main memory die on the substrate at the base of each microelectronic device stack.

[0145] Embodiment 20: The microelectronic device assembly of Embodiment 17, wherein the semiconductor die is configured as a memory die and a logic die, and the logic die is positioned at at least one of the stacked substrates.

[0146] Embodiment 21: The microelectronic device assembly of Embodiment 20, wherein a logic die is positioned at the substrate of each stack.

[0147] Embodiment 22: The microelectronic device assembly of Embodiment 17, wherein the microelectronic device includes a semiconductor die that exhibits at least two different functions.

[0148] Embodiment 23: A method comprising:

[0149] forming a reconstructed panel or wafer by placing singulated semiconductor dies in spaced relationship with one another and laminating a polymer film over active surfaces of the dies, the singulated semiconductor dies including an iRDL including traces that reroute bond pad locations into an array of iRDL pads;

[0150] forming a through hole through the polymer film to expose the iRDL pad on the active surface;

[0151] filling the vias with a conductive material;

[0152] singulating the semiconductor die through the polymer film; and

[0153] inverting at least one of the semiconductor dies and placing the inverted at least one semiconductor die on a substrate with the conductive material filled vias aligned with terminal pads on the substrate; and

[0154] The polymer film is bonded to the substrate, and the conductive material is bonded to the terminal pads.

[0155] Embodiment 24: The method of embodiment 23 further comprises, before forming the reconstituted wafer or panel:

[0156] fabricating active circuitry on die sites on an active surface of a semiconductor substrate and forming an iRDL on each die site with traces to reroute bond pad sites into iRDL pads;

[0157] testing the semiconductor substrate to determine die locations of known good dies (KGDs);

[0158] thinning the semiconductor substrate from an initial thickness to a thickness of about 5 μm to about 200 μm; and

[0159] The semiconductor substrate is singulated into individual KGDs.

[0160] Embodiment 25: The method according to embodiment 1 or 2 further includes stacking an additional semiconductor die on the corresponding semiconductor die placed on the substrate, and operably coupling the additional semiconductor die to the terminal pad of the substrate through a conductive via, wherein the conductive via extends through the dielectric material outside the periphery of the additional semiconductor die and electrically communicates with the additional semiconductor die through a trace, wherein the trace is carried by the dielectric material and extends to a bonding pad on the active surface of the additional semiconductor die.

[0161] Embodiment 26: A microelectronic device assembly comprising:

[0162] a microelectronic device, a surface of the microelectronic device facing the substrate;

[0163] a conductive material-filled hole extending through a dielectric film between an array of iRDL pads on the active surface of the microelectronic device and terminal pads on the substrate; and

[0164] Additional microelectronic devices are stacked on the semiconductor die, each having a dielectric film over a surface thereof and extending beyond at least one periphery, each carrying a conductive trace extending from a bonding pad on the surface of the microelectronic device to and in contact with a conductive material-filled through-hole in the dielectric film, the through-hole extending to a terminal pad on the substrate.

[0165] Embodiment 27: A microelectronic device assembly comprising:

[0166] a stack of microelectronic devices on the substrate, each microelectronic device including TSVs extending through its thickness between bonding pads on an active surface and terminal pads on a back surface thereof;

[0167] a dielectric film interposed between adjacent microelectronic devices of the stack, the dielectric film including holes aligned between bond pads and terminal pads of adjacent microelectronic devices of the stack;

[0168] The holes filled with the conductive material contact the aligned bond pads and terminal pads of an adjacent microelectronic component.

[0169] Embodiment 28: The microelectronic device assembly of Embodiment 27, wherein the dielectric film comprises a prefabricated polymer film and the conductive material comprises a conductive metal paste.

[0170] Embodiment 29: A microelectronic device assembly according to embodiment 27, wherein the dielectric film extends beyond at least one side of the stack and carries a conductive trace from an unaligned bonding pad or terminal pad to a conductive via positioned beyond the at least one side of the stack, the conductive via extending to a terminal pad on the substrate, the conductive trace and conductive via being operably coupled for power and grounding or bias transmission between the substrate and the microelectronic device of the stack.

[0171] Embodiment 30: A microelectronic device assembly according to Embodiment 29, wherein the TSV and the conductive material in contact with the aligned bonding pads and terminal pads are operably coupled for data signal transmission between the stacked microelectronic devices and between the stacked microelectronic devices and the substrate.

[0172] Embodiment 31: A method comprising:

[0173] forming a reconstituted wafer or panel of semiconductor dies by attaching the semiconductor dies by their active surfaces in spaced relationship to one another on a FOP configuration RDL wafer or panel having traces extending from bond pads to areas on the RDL outside the footprint of each semiconductor die;

[0174] placing one or more surface mount components on the RDL of the FOP configuration outside of the footprint of the laterally associated semiconductor die at locations where vias will not be formed;

[0175] laminating a polymer film over a backside of the semiconductor die of the reconstituted wafer or panel;

[0176] singulating the polymer film and RDL wafer or panel between the semiconductor dies;

[0177] inverting the semiconductor die and stacking the inverted semiconductor die on a substrate, wherein the one or more surface mount components are within the die stack;

[0178] forming a via through the polymer film and the RDL at a via location extending to a conductive pad on the substrate; and

[0179] The vias are filled with a conductive material.

[0180] Embodiment 32: The method of Embodiment 31, wherein placing one or more surface mount components comprises placing one or more capacitors, inductors, or resistors.

[0181] Embodiment 33: The method of Embodiment 31 or 32, further comprising placing one or more surface mount components on the top RDL of the inverted semiconductor die stack.

[0182] Embodiment 34: A method according to any one of Embodiments 31, 32 or 33, wherein placing at least one surface mount component on the top layer RDL of the semiconductor die stack includes at least one of the following: placing at least one surface mount component above the top layer RDL of the semiconductor die stack or placing at least one surface mount component below the top layer RDL of the stack and outside the footprint of the semiconductor die of the stack.

[0183] Embodiment 35: The method of any one of Embodiments 31 to 34, wherein the semiconductor die have at least two different sizes, and wherein, when the inverted semiconductor die are stacked, at least one surface mount component is positioned within the footprint of a vertically adjacent semiconductor die.

[0184] Embodiment 36: A method comprising:

[0185] forming a reconstituted wafer or panel of semiconductor dies by attaching the semiconductor dies by the active surfaces in spaced relationship to each other on a FOP configuration RDL panel or wafer having traces extending from bond pads to areas on the RDL outside the footprint of each semiconductor die;

[0186] laminating a polymer film over a backside of the semiconductor die of the reconstituted wafer or panel;

[0187] singulating the polymer film and the RDL between the semiconductor dies;

[0188] inverting the semiconductor die and stacking the inverted semiconductor die on a substrate;

[0189] forming a via through the polymer film and the RDL at a via location extending to a conductive pad on the substrate;

[0190] filling the through-hole with a conductive material; and

[0191] One or more surface mount components are placed on the top RDL of the semiconductor die stack.

[0192] Embodiment 37: The method of Embodiment 36, wherein placing one or more surface mount components comprises placing one or more capacitors, inductors, or resistors.

[0193] Embodiment 38: A microelectronic device assembly comprising:

[0194] a substrate having a conductor exposed on a surface thereof;

[0195] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having a bonding pad operably coupled to a conductive trace extending over a dielectric material to a via location outside a footprint of the associated microelectronic device;

[0196] a via extending through the dielectric material at the via location and including a conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extending to an exposed conductor of the substrate; and

[0197] One or more surface mount components operably coupled to the conductive traces of at least one dielectric material.

[0198] Embodiment 39: The microelectronic device assembly of Embodiment 38, wherein the one or more surface mount components are mounted to the at least one dielectric material at locations outside the footprint of the microelectronic device associated with the dielectric material.

[0199] Embodiment 40: The microelectronic device assembly of Embodiment 38 or 39, wherein the one or more surface mount components are mounted to an upper surface of the at least one dielectric material.

[0200] Embodiment 41: A microelectronic device assembly according to Embodiment 38 or 39, wherein the one or more surface mount components are mounted to a lower surface of the at least one dielectric material.

[0201] Embodiment 42: A microelectronic device assembly according to any one of Embodiments 38, 39, or 40, wherein the one or more surface mount components are positioned on an uppermost dielectric material above at least one through-hole.

[0202] Embodiment 43: A microelectronic device assembly according to Embodiment 38, wherein the one or more surface mount components are positioned on a dielectric material within the stack where no through vias are positioned.

[0203] Embodiment 44: A microelectronic device assembly according to any one of Embodiments 38, 39, 40 or 43, wherein at least one microelectronic device of the stack is smaller than at least one other adjacent microelectronic device of the stack, and the one or more surface mount components are mounted to the at least one dielectric material within the footprint of the at least one other adjacent microelectronic device of the stack.

[0204] Embodiment 45: A microelectronic device assembly according to any one of Embodiments 38 to 44, wherein the conductive trace on the dielectric material extending to a via location outside the footprint of an associated microelectronic device comprises a redistribution layer of a fan-out package configuration (RDL of a FOP configuration) structure.

[0205] Embodiment 46: A microelectronic device assembly according to any one of Embodiments 38 to 45, wherein the microelectronic device includes a semiconductor die.

[0206] Embodiment 47: A microelectronic device assembly according to any one of Embodiments 38 to 46, wherein the one or more surface mount components include one or more capacitors, inductors, or resistors.

[0207] Embodiment 48: A method comprising:

[0208] forming a reconstituted wafer or panel of semiconductor dies by attaching the semiconductor dies by active surfaces in spaced relationship to each other on a FOP configuration RDL panel or wafer having traces extending from bond pads of each semiconductor die to an area on an associated RDL outside a footprint of the semiconductor die, wherein at least one of each semiconductor die or associated RDL includes at least one ICL transmitter and at least one ICL receiver;

[0209] laminating a polymer film over a backside of the semiconductor die of the reconstituted wafer or panel;

[0210] singulating the polymer film and RDL panel or wafer between the semiconductor dies;

[0211] inverting the semiconductor dies and stacking the inverted semiconductor dies on a substrate, wherein the at least one ICL emitter of each semiconductor die or associated RDL is vertically aligned with the at least one ICL receiver of an adjacent semiconductor die or associated RDL, and the at least one ICL receiver of each semiconductor die or associated RDL is vertically aligned with the at least one ICL emitter of an adjacent semiconductor die or associated RDL;

[0212] forming a via through the polymer film and the RDL at a via location extending to a conductive pad on the substrate; and

[0213] The vias are filled with a conductive material.

[0214] Embodiment 49: The method of Embodiment 48, further comprising forming the at least one ICL transmitter and the at least one ICL receiver on the semiconductor die in BEOL processing of a wafer before singulating the semiconductor die from the wafer.

[0215] Embodiment 50: The method according to Embodiment 48 further comprises forming or placing the at least one ICL transmitter and the at least one ICL receiver for each semiconductor die on the RDL panel or wafer of the FOP configuration before forming the reconstructed panel or wafer of the semiconductor die.

[0216] Embodiment 51: A method according to any one of embodiments 48, 49 or 50, further comprising providing the substrate with at least one ICL transmitter and at least one ICL receiver before stacking the inverted semiconductor die on the substrate, and vertically aligning the at least one ICL transmitter of an adjacent semiconductor die or an associated RDL with the at least one ICL receiver of the substrate and aligning the at least one ICL receiver of an adjacent semiconductor die or an associated RDL with the at least one ICL transmitter of the substrate.

[0217] Embodiment 52: The method according to embodiment 48 or 51 further includes providing multiple ICL transmitters and multiple ICL receivers for each semiconductor die or associated RDL, and stacking the inverted semiconductor dies, wherein the ICL transmitters of the stacked semiconductor dies or associated RDLs are vertically aligned with the ICL receivers of adjacent stacked semiconductor dies or associated RDLs, and the ICL receivers of the stacked semiconductor dies or associated RDLs are vertically aligned with the ICL transmitters of adjacent stacked semiconductor dies or associated RDLs.

[0218] Embodiment 53: A microelectronic device assembly comprising:

[0219] a substrate having a conductor exposed on a surface thereof;

[0220] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having a bonding pad operably coupled to a conductive trace extending over a dielectric material to a via location outside a footprint of the associated microelectronic device;

[0221] a via for power and ground / bias, the via extending through the dielectric material at the via location and including a conductive material in contact with at least some of the conductive traces of each of the two or more microelectronic devices; and

[0222] The microelectronic device or the associated RDL includes at least one ICL transmitter and at least one ICL receiver within the coverage area of ​​the corresponding microelectronic device, and the at least one ICL transmitter of each microelectronic device or the associated RDL is vertically aligned with the at least one ICL receiver of an adjacent microelectronic device or the associated RDL, and the at least one ICL receiver of each microelectronic device or the associated RDL is vertically aligned with the at least one ICL transmitter of an adjacent microelectronic device or the associated RDL for data signal communication.

[0223] Embodiment 54: The microelectronic device assembly of Embodiment 53, wherein the at least one ICL transmitter and the at least one ICL receiver are positioned within a BEOL structure of the respective microelectronic device.

[0224] Embodiment 55: The microelectronic device assembly of Embodiment 53, wherein the at least one ICL transmitter and the at least one ICL receiver are positioned on an RDL associated with a respective microelectronic device.

[0225] Embodiment 56: A microelectronic device assembly according to any one of Embodiments 53, 54 or 55, wherein the substrate includes at least one ICL transmitter and at least one ICL receiver, and the at least one ICL transmitter of an adjacent microelectronic device or an associated RDL is vertically aligned with the at least one ICL receiver of the substrate, and the at least one ICL receiver of the adjacent microelectronic device or an associated RDL is vertically aligned with the at least one ICL transmitter of the substrate.

[0226] Embodiment 57: A microelectronic device assembly according to Embodiment 53 or 56, wherein each microelectronic device or associated RDL includes multiple ICL transmitters and multiple ICL receivers, and the ICL transmitters of the stacked microelectronic devices or associated RDLs are vertically aligned with the ICL receivers of adjacent stacked microelectronic devices or associated RDLs, and the ICL receivers of the stacked microelectronic devices or associated RDLs are vertically aligned with the ICL transmitters of adjacent stacked microelectronic devices or associated RDLs.

[0227] Embodiment 58: A microelectronic device assembly according to any one of Embodiments 53 to 57, wherein the conductive trace on the dielectric material extending to a via location outside the footprint of an associated microelectronic device comprises a redistribution layer of a fan-out package configuration (RDL of a FOP configuration) structure.

[0228] Embodiment 59: A microelectronic device assembly according to any one of Embodiments 53 to 58, wherein the microelectronic device includes a semiconductor die.

[0229] Embodiment 60: An assembly of microelectronic devices according to any one of Embodiments 53 to 59, wherein power and ground / bias signal communications through the conductive traces and vias are combined for all of the microelectronic devices.

[0230] Embodiment 61: An assembly of microelectronic devices as in any one of Embodiments 53 to 59, wherein power and ground / bias communications through the conductive traces and vias are separate for at least some of the microelectronic devices.

[0231] Embodiment 62: A microelectronic device assembly comprising:

[0232] a substrate having a conductor exposed on a surface thereof;

[0233] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having power and ground / bias pads operably coupled to conductive traces extending over a dielectric material to through-hole locations beyond a footprint of an associated microelectronic device, and TSVs for data signal communication extending through the microelectronic device in alignment with TSVs of at least one of an adjacent microelectronic device;

[0234] a via for power and ground\bias communications, the via extending through the dielectric material at the via location and including a conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extending to at least some of the exposed conductors of the substrate; and

[0235] A conductive element extends through the dielectric material between adjacent microelectronic devices aligned with the TSV for data signal communication.

[0236] Embodiment 63: An assembly of microelectronic devices according to Embodiment 62, wherein power and ground / bias signal communications through the conductive traces and vias are combined for all of the microelectronic devices.

[0237] Embodiment 64: The microelectronic device assembly of Embodiment 62, wherein power and ground / bias communications through the conductive traces and vias are separate for at least some of the microelectronic devices.

[0238] Embodiment 65: The microelectronic device assembly of any one of Embodiments 62 to 64, further comprising an additional, uppermost microelectronic device in the stack without TSVs and having bonding pads aligned with the TSVs of the next lower microelectronic device in the stack.

[0239] Embodiment 66: The microelectronic device assembly of any one of Embodiments 62 to 65, wherein each microelectronic device is laterally surrounded by an EMC through which the through-via extends.

[0240] Embodiment 67: The microelectronic device assembly of any one of Embodiments 62 to 66, further comprising a conductive element extending through a dielectric material between a TSV of a lowermost microelectronic device and a conductor on the upper surface of the substrate for data signal communication.

[0241] Embodiment 68: A method comprising:

[0242] forming a reconstituted wafer or panel of semiconductor dies by attaching the semiconductor dies by their active surfaces in spaced relationship to one another on a FOP configuration RDL wafer or panel having traces extending from bond pads to areas on the RDL outside the footprint of each semiconductor die;

[0243] laterally encapsulating the semiconductor dies of the reconstituted wafer or panel of semiconductor dies in an EMC;

[0244] attaching the reconstituted wafer or panel of semiconductor dies to a DAF on a side of the EMC opposite the FOP configured wafer or panel;

[0245] Singulating the semiconductor die, the RDL wafer or panel in the FOP configuration, the EMC, and the DAF;

[0246] Stack singulated semiconductor die, RDL, EMC and DAF in FOP configuration;

[0247] forming openings through the singulated RDL, EMC, and DAF at via locations that communicate with traces outside of a footprint of the stacked semiconductor die; and

[0248] The opening is filled with a conductive material.

[0249] Embodiment 69: The method of Embodiment 68, further comprising stacking the singulated semiconductor die, the FOP-configured RDL, the EMC, and the DAF on a substrate; and

[0250] Wherein filling the opening with a conductive material includes filling the opening with a conductive material to contact a conductor on an upper surface of the substrate.

[0251] Embodiment 70: A microelectronic device assembly comprising:

[0252] a substrate having a conductor exposed on a surface thereof;

[0253] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having a bonding pad operably coupled to a conductive trace extending over a dielectric material to a via location outside a footprint of the associated microelectronic device;

[0254] an EMC laterally surrounding each of the two or more microelectronic devices;

[0255] a DAF over each of said microelectronic devices and said surrounding EMC; and

[0256] A via extends through the dielectric material, the EMC, and the DAF at the via location and includes a conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extends to an exposed conductor of the substrate.

[0257] Embodiment 71: The microelectronic device assembly of Embodiment 70, wherein the conductive trace extending over the dielectric material to a via location outside a footprint of an associated microelectronic device comprises a redistribution layer of a fan-out package configuration (RDL of a FOP configuration) structure.

[0258] Embodiment 72: A method comprising:

[0259] forming a reconstituted wafer or panel of semiconductor dies by attaching singulated semiconductor dies by active surfaces in spaced relationship to each other on a FOP configured RDL wafer or panel having traces extending from bond pads to areas on the RDL outside the footprint of each semiconductor die;

[0260] laterally encapsulating the semiconductor dies of the reconstituted wafer or panel of semiconductor dies in an EMC;

[0261] laminating a polymer film over the RDL;

[0262] singulating the semiconductor die, EMC, RDL wafer or panel and polymer film;

[0263] Inverting and stacking singulated semiconductor die, RDL, EMC and polymer film in FOP configuration;

[0264] forming openings through the singulated RDL, EMC, and polymer film at via locations; and

[0265] The opening is filled with a conductive material.

[0266] Embodiment 73: The method according to embodiment 72, further comprising:

[0267] Prior to inverting and stacking the singulated semiconductor die, FOP configured RDL, EMC and polymer film, raising the selected microelectronic device with conductive elements on its active surface;

[0268] wherein inverting and stacking the singulated semiconductor die, the RDL of the FOP configuration, the EMC, and the polymer film comprises inverting and stacking a raised microelectronic device on a substrate, wherein the conductive element contacts a conductor of the substrate through the polymer film; and

[0269] The remaining microelectronic devices are inverted and stacked.

[0270] Embodiment 74: A microelectronic device assembly comprising:

[0271] a substrate having a conductor exposed on a surface thereof;

[0272] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface facing the substrate and having a bonding pad operably coupled to a conductive trace extending over the dielectric material to a through-hole location outside a footprint of the associated microelectronic device;

[0273] a polymer film over the dielectric material and the conductive traces;

[0274] an EMC laterally surrounding each of the two or more microelectronic devices;

[0275] a via extending through the dielectric material, the polymer film, and the EMC at the via location and including a conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extending to an exposed conductor of the substrate; and

[0276] Another microelectronic device beneath the stack is adjacent to the substrate and has an active surface facing the substrate, the bonding pads of the other microelectronic device communicating with and contacting the conductors of the substrate via conductive elements extending through the polymer film.

[0277] Embodiment 75: The microelectronic device assembly of Embodiment 74, wherein the conductive trace extending over the dielectric material to a via location outside a footprint of an associated microelectronic device comprises a redistribution layer of a fan-out package configuration (RDL of a FOP configuration) structure.

[0278] Embodiment 76: A microelectronic device assembly comprising:

[0279] a substrate having a conductor exposed on a surface thereof;

[0280] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having a bonding pad operably coupled to a conductive trace extending over a dielectric material to a via location beyond all sides of the stack;

[0281] a via extending through the dielectric material at the via location and including a conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extending to an exposed conductor of the substrate;

[0282] The combined vias include a ground stitching structure that provides electromagnetic interference (EMI) protection;

[0283] a ground structure extending over the uppermost microelectronic device and operably coupled to the ground stitching structure, the ground structure and the ground stitching structure together providing a Faraday cage; and

[0284] A radio frequency antenna is disposed above and dielectrically isolated from the faraday cage and is operably coupled to the stacked one or more microelectronic devices.

[0285] Embodiment 77: A microelectronic device assembly comprising:

[0286] a substrate having a conductor exposed on a surface thereof;

[0287] a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having a bonding pad operably coupled to a conductive trace extending over a dielectric material to a via location outside a footprint of the associated microelectronic device;

[0288] an uppermost microelectronic device of the stack, the uppermost microelectronic device being configured as a relatively high power density device compared to a power density of one or more other microelectronic devices of the stack;

[0289] a heat spreader structure positioned between the uppermost microelectronic device of the stack and a remainder of the stack of microelectronic devices; and

[0290] A via extends through the dielectric material at the via location and includes a conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extends to an exposed conductor of the substrate.

[0291] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, it will be recognized and appreciated by those skilled in the art that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure, such as those claimed below, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device assembly, comprising: a microelectronic device, the active surface of the microelectronic device facing the substrate; as well as a plurality of holes prefilled with a single conductive material that contacts an array of bonding pads on the active surface of the microelectronic device and extends through each of the plurality of holes in a single preformed dielectric film that is in direct contact with the active surface of the microelectronic device and the substrate, the single conductive material prefilled into the plurality of holes contacting terminal pads on the substrate.

2. The microelectronic device assembly of claim 1 , further comprising a stack of additional microelectronic devices on the microelectronic device, each additional microelectronic device having an additional preformed dielectric film over its surface and extending beyond at least one side of the stack of additional microelectronic devices, the additional preformed dielectric films each carrying a conductive trace extending from a bonding pad on the surface of the additional microelectronic device to and in contact with a conductive material-filled through-hole in the additional preformed dielectric film positioned beyond the at least one side of the stack of additional microelectronic devices, and to a terminal pad on the substrate.

3. The microelectronic device assembly of claim 1, wherein the bonding pad array is bonding pads of an iRDL structure.

4. The microelectronic device assembly of claim 1, wherein the single preformed dielectric film is a NCF, a b-stage polyimide film, or a PTFE film.

5. The microelectronic device assembly of claim 1, wherein the conductive material comprises Ag paste, Cu paste, or solder.

6. The microelectronic device assembly according to claim 2, further comprising a preformed die attach film (DAF) or a preformed film-on-die (FOD) material directly between the back side of the microelectronic device and the additional microelectronic device stack.

7. The microelectronic device assembly of claim 2, wherein bonding pads of the additional microelectronic device are positioned on an active surface thereof facing away from the microelectronic device.

8. The microelectronic device assembly of claim 2, further comprising discrete conductive elements on a surface of the substrate opposite the additional microelectronic device stack, the stack being encapsulated in an epoxy mold compound.

9. A microelectronic device assembly comprising: a stack of microelectronic devices on the substrate, each microelectronic device including TSVs extending through its thickness between bonding pads on an active surface and terminal pads on a back surface thereof; as well as A preformed discrete dielectric film is inserted between and in direct contact with adjacent microelectronic devices of the stack, the preformed discrete dielectric film including holes extending through and aligned between bond pads and terminal pads of adjacent microelectronic devices of the stack, the holes being filled with a single conductive material in contact with the aligned bond pads and terminal pads of adjacent microelectronic components.

10. The microelectronic device assembly of claim 9, wherein the preformed discrete dielectric film comprises a polymer film and the single conductive material comprises a conductive metal paste or solder.

11. The microelectronic device assembly of claim 10, wherein the polymer film comprises NCF, b-stage polyimide film, or PTFE film.

12. The microelectronic device assembly of claim 9 further comprising an additional microelectronic device without TSVs, the additional microelectronic device being located on top of the microelectronic device stack and having bonding pads in contact with the conductive material in the holes in the preformed dielectric film, the dielectric film being positioned between the additional microelectronic device and terminal pads of an adjacent lower microelectronic device.

13. The microelectronic device assembly of claim 11, further comprising an epoxy mold compound (EMC) encapsulating the microelectronic device stack and abutting a surface of the substrate and discrete conductive elements on an opposing surface of the substrate.

14. A method of manufacturing a microelectronic device assembly, the method comprising: forming a reconstituted wafer or panel by placing singulated semiconductor dies in spaced relationship with one another and laminating a polymer film over active surfaces of the singulated semiconductor dies including bonding pads; forming a through hole through the polymer film to expose a bonding pad on the active surface; filling the through-hole with a conductive material; singulating the semiconductor dies of the reconstituted wafer or panel through the polymer film; inverting at least one semiconductor die and placing the inverted at least one semiconductor die on a substrate with the conductive material filled through-holes aligned with terminal pads on the substrate; as well as The polymer film is bonded to the substrate, wherein the conductive material is in contact with the terminal pads.

15. The method according to claim 14, further comprising: Before forming a reconstituted wafer or panel: Fabricating active circuitry at a die site on an active surface of a semiconductor substrate; Testing the semiconductor substrate to determine the die location of a known good die KGD; as well as The semiconductor substrate is singulated into individual KGDs.

16. The method according to claim 15, further comprising: Prior to testing the semiconductor substrate, an iRDL is formed at each die location with traces to reroute bond pad locations on the active surface into an iRDL bond pad array at locations to be exposed through the vias in the polymer film.

17. The method of claim 14, further comprising stacking an additional semiconductor die on the at least one semiconductor die disposed on the substrate, and operably coupling the additional semiconductor die to terminal pads of the substrate via conductive vias extending through a plurality of dielectric materials extending over an active surface of the additional semiconductor die to a position outside a periphery of the additional semiconductor die, and the conductive vias being in electrical communication with the additional semiconductor die via traces carried by the plurality of dielectric materials and extending to bonding pads on the active surface of the additional semiconductor die.

18. The method of claim 14, further comprising: Before forming a reconstituted wafer or panel: fabricating active circuitry on a die site on an active surface of a semiconductor substrate and forming TSVs extending from terminal pads on a back side of the semiconductor substrate and the bonding pads on the active surface; Testing the semiconductor substrate to determine the die location of a known good die KGD; as well as The semiconductor substrate is singulated into individual KGDs.

19. The method according to claim 18, further comprising: After inverting the at least one semiconductor die and placing the inverted at least one semiconductor die on the substrate with the conductive material filled through-holes aligned with the terminal pads on the substrate, inverting one or more additional semiconductor dies identified as KGD and stacking the one or more additional semiconductor dies on the at least one semiconductor die, the at least one semiconductor die having the through-holes filled with the conductive material of each additional semiconductor die aligned with the terminal pads of the next lower adjacent semiconductor die; as well as Bonding the polymer film between adjacent semiconductor die and the conductive material, the conductive material being between and in contact with its bonding pad and terminal pad, substantially simultaneously bonding the polymer film of at least one semiconductor die to the substrate having its conductive material, thereby bonding to the terminal pad of the substrate.

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