Optical collimator, semiconductor device and method for forming the same

Abstract

Embodiments of the present disclosure disclose an optical collimator, a semiconductor device, and a method of forming the same. In one embodiment, the optical collimator includes: a dielectric layer; a substrate; and a plurality of through holes, wherein the dielectric layer is formed above the substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, wherein the substrate has an overall impurity doping concentration equal to or greater than 1×10<supgt;19< / supgt; cm<supgt;‑3< / supgt; and a first thickness, and wherein the overall impurity doping concentration and the first thickness of the substrate are configured to allow the optical collimator to filter light in a wavelength range.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to an optical collimator, a semiconductor device and a method for forming the same. Background Art

[0002] In order to prevent noise from ambient infrared (IR) sources, contact image sensors (CIS) (e.g., fingerprint sensors) typically use glass filters. Glass filters in such applications are typically thick (e.g., 400-500 μm) to provide effective filtering of ambient IR noise, especially at large incident angles (>15°). This results in bulky components and high costs. There is a need to develop cost-effective methods to filter ambient IR light to reduce noise in contact image sensors. Summary of the invention

[0003] In some embodiments, an optical collimator is provided, the optical collimator comprising a dielectric layer; a substrate; and a plurality of through holes, wherein the dielectric layer is formed above the substrate, wherein the plurality of through holes are arranged in an array extending in a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, wherein the substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the substrate and the first thickness are configured to allow the optical collimator to filter a range of wavelengths of light.

[0004] In some other embodiments, a semiconductor device is provided, the semiconductor device including at least one optical sensing element; and an optical collimator; wherein the optical collimator comprises: a first dielectric layer, a first substrate, and a plurality of through holes, wherein the first dielectric layer is formed above the first substrate, wherein the plurality of through holes are arranged in an array extending in a lateral direction of a first surface of the first dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the first dielectric layer through the first dielectric layer and the first substrate to a second surface of the first substrate, wherein the first substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the first substrate and the first thickness are configured to allow the optical collimator to filter a range of wavelengths of light.

[0005] In some other embodiments, a method for forming a semiconductor device is provided, the method comprising forming a collimator structure on a first substrate having a first dielectric layer, wherein the collimator structure comprises a plurality of through holes, wherein each of the plurality of through holes extends in a vertical direction from a first surface of a second dielectric layer through the second dielectric layer and the second substrate to a second surface of the second substrate, wherein the second substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the second substrate and the first thickness are configured to allow the collimator structure to filter a range of wavelengths of light. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present invention can be better understood according to the following detailed description and in conjunction with the drawings of the specification. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make clear descriptions. It should also be emphasized that the drawings only show typical embodiments of the present invention and therefore should not be regarded as limiting the scope. The present invention can be equally applied to other embodiments.

[0007] Figure 1 A flow chart is shown of an exemplary method of forming a semiconductor device according to some embodiments of the present invention.

[0008] Figure 2A , 2B 2C, 2D, 2E and 2F show some embodiments of the present invention, by Figure 1 Schematic cross-sectional views of an exemplary semiconductor device with a collimator during various stages of fabrication in accordance with a method of manufacturing the semiconductor device.

[0009] Figure 3 An exemplary cross-sectional view of a semiconductor device having a collimator according to some embodiments of the present invention is shown.

[0010] Figure 4 Illustrative cross-sectional diagrams showing sidewall profiles of etched openings in a collimator structure according to some embodiments of the present invention.

[0011] Figure 5A An exemplary top view of a semiconductor device with a collimator according to some embodiments of the present invention is shown.

[0012] Figure 5B An exemplary top view of a semiconductor device with a collimator according to some embodiments of the present invention is shown.

[0013] Description of reference numerals:

[0014] 100: Methods

[0015] 102,104,106,108,110,112,114: Operation

[0016] 200, 300, 500: Semiconductor devices

[0017] 202: First Base

[0018] 204: First dielectric layer

[0019] 206: Conductive parts

[0020] 208: Optical sensor area

[0021] 210,210': Opening

[0022] 212: Second base

[0023] 212': Thinned second substrate

[0024] 214: Second dielectric layer

[0025] 216: Patterned photoresist layer

[0026] 218: Opening

[0027] 220: Through hole

[0028] 222: Top surface

[0029] 224,310: Sidewall

[0030] 302,304: Thickness

[0031] 306: Diameter

[0032] 308: Size

[0033] 400: Sidewall profile

[0034] 402: First Profile

[0035] 404: Second Profile

[0036] 406: The Third Profile

[0037] 408: The Fourth Profile

[0038] 410: The Fifth Profile

[0039] 412: Sixth Profile

[0040] 414: The Seventh Profile

[0041] 416: The Eighth Profile

[0042] 418: Ripple

[0043] 420: Scratches

[0044] 422: Corner

[0045] 424: Undercut

[0046] 502: Square unit

[0047] 504: Diamond Unit DETAILED DESCRIPTION

[0048] It will be appreciated that the following disclosure provides many different embodiments or examples to implement the different components of the subject provided. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, it will be understood that when an element is described as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or one or more intermediate elements may be present.

[0049] Thick infrared glass can be used to filter the unwanted ambient noise of the contact image sensor. This design results in a bulky structure and increases the cost of such a contact image sensor. The present invention presents various embodiments of methods that integrate the filtering function into the collimator to simultaneously collimate the incident light and filter the ambient noise in a compact design and at low cost.

[0050] Figure 1 A flowchart of a method 100 for forming a multifunctional collimator structure on a semiconductor device according to some embodiments of the present invention is shown. It should be noted that the method 100 is merely an example and is not intended to limit the embodiments of the present invention. Figure 1 Additional operations are provided before, during, and after method 100, and only some other operations are briefly described herein. In some embodiments, the operations of method 100 may be different from those of Figure 2A , 2B , 2C, 2D, 2E and 2F are associated with the cross-sectional schematic diagrams of the semiconductor device at various manufacturing stages, which will be discussed in further detail below.

[0051] According to some embodiments, please refer to Figure 1, method 100 begins at operation 102, where a first substrate is provided. In some embodiments, the first substrate includes at least one optical sensing element and at least one conductive component for contacting. According to some embodiments, method 100 continues to operation 104, where a first dielectric layer is deposited on the surface of the first substrate. In some embodiments, the first dielectric layer includes silicon dioxide for planarization. In some embodiments, the first dielectric layer also provides a silicon-to-oxide fusion-bond surface. In some embodiments, a shallow opening (i.e., a partial etching in the first dielectric layer) is also performed. According to some embodiments, method 100 continues to operation 106, where a second substrate is bonded above the first dielectric layer on the first substrate. In some embodiments, the second substrate is bonded to the first dielectric layer by a wafer bonding process. In some embodiments, the second substrate has an overall impurity doping level equal to or greater than 1×10 19 cm -3 According to some embodiments, the method 100 continues to operation 108, wherein the second substrate is thinned. In some embodiments, the thinned second substrate has a thickness equal to or greater than 75 μm. According to some embodiments, the method 100 continues to operation 110, wherein a second dielectric layer is deposited on the first surface of the thinned second substrate. In some embodiments, the second dielectric layer includes silicon dioxide. According to some embodiments, the method 100 continues to operation 112, wherein a photoresist layer is patterned on the second dielectric layer. In some embodiments, the patterned photoresist layer provides a pattern of collimator structures. According to some embodiments, the method 100 continues to operation 114, wherein a plurality of through holes are formed through the second dielectric layer and the thinned second substrate. In some embodiments, the second dielectric layer is etched using the patterned first photoresist layer as a soft mask, and then the thinned second substrate is etched using the patterned second dielectric layer as a hard mask to form a plurality of through holes. In some embodiments, at least one opening is also etched in the first dielectric layer to expose at least one conductive component in the first substrate for contact purposes. In some embodiments, a chemical etching process is performed to remove the photoresist layer. In some embodiments, the semiconductor device having the first substrate and the collimator structure through the second dielectric layer and the thinned second substrate is then wafer cut to form a plurality of dies. In some embodiments, each of the plurality of dies is then wafer bonded to a third substrate and further wire bonded. In some embodiments, each of the plurality of dies is embedded in a mold and packaged.

[0052] As mentioned above, Figures 2A-2F Display by Figure 1The semiconductor device 200 is a cross-sectional view of a portion of a semiconductor device 200 at various stages of manufacturing. The semiconductor device 200 may be included in an integrated circuit (IC). Figures 2A-2F Although the figures show semiconductor device 200, it is understood that the integrated circuit may include many other devices, such as resistors, capacitors, inductors, fuses, etc. For the sake of clarity, Figures 2A-2F Other devices are not shown.

[0053] Figure 2A is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1 102 and 104, a cross-sectional schematic diagram of a semiconductor device 200 including a first substrate 202 and a first dielectric layer 204. In some embodiments, the first substrate 202 includes at least one optical sensing element (not shown) in an optical sensing element region 208 (sometimes referred to simply as an optical sensing region). In some embodiments, each of the at least one optical sensing element is a contact image sensor (CIS). In some embodiments, a contact image sensor is an image sensor that is in direct contact with an object to be imaged or scanned. In some embodiments, the contact image sensor includes a plurality of detectors. In some embodiments, the plurality of detectors detect light emitted from a surface of an object. In some embodiments, each of the plurality of detectors includes one of the following: a charge coupled device (CCD) sensor and a complementary metal-oxide semiconductor (CMOS) sensor. In some embodiments, the first substrate 202 also includes two conductive components 206.

[0054] In some embodiments, the first substrate 202 is a silicon substrate. Alternatively, the first substrate 202 may include other elemental semiconductor materials, such as germanium. The first substrate 202 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The first substrate 202 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the first substrate 202 includes an epitaxial layer. For example, the first substrate 202 may have an epitaxial layer above a bulk semiconductor. Furthermore, the first substrate 202 may include a semiconductor-on-insulator (SOI) structure. For example, the first substrate 202 may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0055] In some embodiments, the first substrate 202 also includes various p-type doped regions and / or n-type doped regions implemented by, for example, ion implantation and / or diffusion. These doped regions include n-type wells, p-type wells, lightly doped drains (LDDs), heavily doped sources and drains (S / Ds), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as complementary metal oxide semiconductor field-effect transistors (CMOS field-effect transistors, CMOS-FETs), image sensors, and / or light emitting diodes (LEDs). The first substrate 202 may also include other functional components, such as resistors or capacitors formed in or on the substrate. The first substrate 202 also includes lateral isolation components configured to separate various components formed in the first substrate 202, such as shallow trench isolation (STI). The various components in the first substrate 202 also include silicides, gates, and other component components disposed on the source and drain to reduce contact resistance and enhance process compatibility when coupling between devices through local interconnects.

[0056] In some embodiments, the first substrate 202 includes at least one conductive component. In some embodiments, the at least one conductive component may be a source, drain, or gate electrode. Alternatively, the at least one conductive component may be a silicide component, which is typically disposed on the source, drain, or gate electrode by a sintering process that includes at least one of thermal heating, laser irradiation, or ion beam mixing. The silicide component may be formed on a polysilicon gate (commonly referred to as a "polycide gate") or on a source / drain (commonly referred to as a "silicide") by self-aligned silicide technology. In another embodiment, the at least one conductive component may include an electrode of a capacitor or one end of a resistor. In another embodiment, the at least one conductive component is a contact connected to a contact image sensor in the first substrate 202.

[0057] In some embodiments, the first dielectric layer 204 includes one of the following materials: silicon dioxide, a low-k material, other suitable dielectric materials, or a combination thereof. The low-k material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), black diamond (trademarked by Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), SiLK (trademarked by Dow Chemical, Midland, Michigan), polyimide, and / or other low-k dielectric materials to be developed in the future. In some embodiments, the first dielectric layer 204 is deposited using plasma enhanced chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the first dielectric layer 204 is deposited using a physical vapor deposition (PVD) process.

[0058] Figure 2B is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1Operation 104 of the present invention is a schematic cross-sectional view of a semiconductor device 200 including a first substrate 202 and a first dielectric layer 204. In the embodiment shown, two shallow openings 210 in the first dielectric layer 204 are located at positions corresponding to the positions where two conductive features 206 are formed in the first substrate 202. In some embodiments, a photolithography process is performed and dry etching or wet etching is used to perform a partial etching in the first dielectric layer 204.

[0059] Figure 2C is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1 Operation 106 of the present invention is a schematic cross-sectional view of a semiconductor device 200 including a first substrate 202, a first dielectric layer 204, and a second substrate 212. In some embodiments, the second substrate 212 includes a silicon substrate. In some embodiments, the second substrate 212 has an impurity doping level (i.e., a carrier concentration) equal to or greater than 1×10 19 cm -3 The second substrate 212 may be a p-type substrate or an n-type substrate. Due to the bandgap offset, the high concentration of impurity doping in the second substrate 212 leads to increased light absorption in the near infrared (IR) region, which affects phonon-assisted absorption and free carrier absorption. Therefore, the use of the second substrate 212 with a high carrier concentration can reduce noise by limiting the ambient near infrared light from reaching at least one optical sensing element in the first substrate 202. Alternatively, the second substrate 212 may include other elemental semiconductor materials, such as germanium, depending on the optical properties of the material. The second substrate 212 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The second substrate 212 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, the selection of the impurity doping concentration of the second substrate 212 and the second substrate 212 may depend on the desired operating wavelength range, such as between 780nm and 1100nm. In one embodiment, the second substrate 212 includes an epitaxial layer. For example, the second substrate 212 may have an epitaxial layer above a bulk semiconductor. Furthermore, the second substrate 212 may include a semiconductor on insulator (SOI) structure. For example, the second substrate 212 may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and polishing.

[0060] In some embodiments, the second substrate 212 is bonded to the region of the first dielectric layer 204 corresponding to the optical sensing element region 208 by a wafer bonding process. In some embodiments, the wafer bonding process is a direct bonding without any additional intermediate layer. In some embodiments, the wafer bonding process includes at least one of the following steps: surface pretreatment, pre-bonding at room temperature, and annealing at high temperature. In another embodiment, surface activation may be used to avoid high temperature annealing.

[0061] Figure 2D is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1 Operations 108 and 110 of the present invention are schematic cross-sectional views of a semiconductor device 200 including a second dielectric layer 214 on a thinned second substrate 212'. In some embodiments, after the second substrate 212 is bonded to the first dielectric layer 204, the second substrate 212 is further thinned to a first thickness, wherein the first thickness depends on the absorption coefficient of the desired filtering wavelength range (between 780 nm and 1100 nm). In some embodiments, the second substrate 212 is in cm -1 The absorption coefficient of unit is a function of the impurity doping concentration of the second substrate 212 and the band gap of the second substrate 212. For example, when the second substrate 212 is a silicon substrate, as the doping concentration increases, the band gap of the second substrate 212 decreases and the absorption coefficient increases. In some embodiments, the second substrate 212 is etched by dry etching and / or wet etching. In some embodiments, the thinned second substrate 212' has a thickness equal to or greater than 75 μm. In some embodiments, the second dielectric layer 214 is deposited on the thinned second substrate 212'. In some embodiments, the second dielectric layer 214 includes one of the following materials: silicon dioxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination of the foregoing. The low dielectric constant material may include fluorinated quartz glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), black diamond (registered by Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), SiLK (registered by Dow Chemical, Midland, Michigan), polyimide and / or other low dielectric constant dielectric materials to be developed in the future. In some embodiments, the second dielectric layer 214 is deposited using plasma-assisted chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the second dielectric layer 214 is deposited using a physical deposition process (e.g., sputtering or evaporation). In some embodiments, the second dielectric layer 214 is deposited using an atomic layer deposition (ALD) process. In some embodiments, the second dielectric layer 214 has a thickness equal to or greater than 3 μm. In some embodiments, before depositing the second dielectric layer 214 , the surface of the second substrate that is not in direct contact with the first dielectric layer 204 is further planarized by chemical-mechanical polishing (CMP) after being etched.

[0062] Figure 2E is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 200 according to operation 112 of FIG. 1 , wherein a photoresist is patterned on a second dielectric layer 214. As described below, a patterned photoresist layer 216 having a plurality of openings 218 is used as a mask for etching the second dielectric layer 214 and the thinned second substrate 212′ to form a plurality of through holes (i.e., collimator structures) on top of the first dielectric layer 204 on the first substrate 202. Thus, in some embodiments, after a conventional patterning (e.g., photolithography) process, the patterned photoresist layer 216 is formed to align the collimator structures with at least one optical sensing element in the optical sensing element region 208 of the first substrate 202.

[0063] In some embodiments, the initial photoresist prior to the patterning process may include a negative or positive photoresist layer patterned in response to a lithography light source. In some other embodiments, the initial photoresist may include an electron beam (e-beam) photoresist layer (e.g., polymethyl methacrylate, methyl methacrylate, etc.) patterned in response to an electron beam lithography energy source. In some embodiments, the initial photoresist is formed over the second dielectric layer 214 by using a deposition process known in the art (e.g., spin coating, spray coating, dip coating, roller coating, or the like). Next, the initial photoresist is patterned in a photolithography process that may involve various exposure, development, baking, stripping, etching, and cleaning processes. Thus, a patterned photoresist layer 216 is formed so that a plurality of openings 218 expose at least a portion of the top surface of the second dielectric layer 214, such as Figure 2E In some embodiments, the plurality of openings 218 in the patterned photoresist layer 216 are circular and have a diameter of 4.2 μm. In some embodiments, the diameter of the plurality of openings 218 is in the range of 2-5 μm.

[0064] Figure 2F is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 11 is a cross-sectional schematic diagram of a semiconductor device 200 according to operation 114, wherein a plurality of through holes 220 are formed in a second dielectric layer 214 and a thinned second substrate 212', the patterned photoresist layer 216 is removed, and at least one conductive component 206 exposes the first dielectric layer 204. In some embodiments, the second dielectric layer 214 is first etched to transfer the pattern of the plurality of openings 218 in the patterned photoresist layer 216 to the second dielectric layer 214. In some embodiments, the thinned second substrate 212' is then further etched through the patterned second dielectric layer 214 to transfer the pattern of the second dielectric layer 214 to the thinned second substrate 212'. In some embodiments, the etching of the second dielectric layer 214 and the thinned second substrate 212' is performed by a dry etching process and / or a wet etching process.

[0065] In some embodiments, the patterned photoresist layer 216 is removed before etching the thinned second substrate 212'. In some embodiments, the patterned photoresist layer 216 can be removed by one or more chemical cleaning processes using acetone, N-methylpyrrolidone (1-Methyl-2-pyrrolidone, NMP), dimethyl sulfoxide (Dimethyl sulfoxide, DMSO) or other suitable removal chemicals. In some embodiments, it may be necessary to heat the chemicals used to a temperature above room temperature to effectively dissolve the patterned photoresist layer 216. The choice of remover depends on the type and chemical structure of the patterned photoresist layer 216, the second dielectric layer 214 and the thinned second substrate 212' to ensure the chemical compatibility of these layers with the chemical cleaning process. In some embodiments, the cleaning process is followed by washing with isopropyl alcohol or the like, followed by deionized water. As a result of this process, a plurality of through holes 220 (i.e., collimator structures) are formed through the second dielectric layer 214 and the thinned second substrate 212'. In some embodiments, the collimator structure includes a top surface 222 and sidewalls 224 of the second dielectric layer 214. In some embodiments, the at least one conductive feature 206 is exposed by etching two shallow openings 210 in the first dielectric layer 204 using a wet etching process or a dry etching process to form an opening 210′ ​​to provide an electrical contact to at least one optical sensing element in the optical sensing element region 208 in the first substrate 202.

[0066] In some embodiments, when light reaches at least one optical sensing element in the optical sensing element region 208 of the first substrate 202, the collimator structure narrows the incident light and allows the incident light to be aligned in a specific direction. 19 cm -3The collimator structure formed in the thinned second substrate 212' is further capable of filtering out unwanted ambient noise (e.g., near infrared light) and preventing such noise from reaching at least one optical sensing element. Therefore, the collimator structure in the embodiment of the present invention provides multiple functions, enabling the use of ordinary glass during packaging, thereby reducing costs, and further enabling the use of contact image sensor devices in limited space applications.

[0067] Figure 3 An exemplary cross-sectional view of a semiconductor device 300 having a collimator structure according to some embodiments of the present invention is shown. Figure 1 The method 100 described herein fabricates a collimator structure. Specifically, the semiconductor device 300 includes a first substrate 202 having an optical sensor device region 208 , a first dielectric layer 204 , a plurality of through holes 220 in a thinned second substrate 212 ′, and a second dielectric layer 214 .

[0068] In some embodiments, the patterned second dielectric layer 214 has a thickness 302 in the range of 1.5-2.5 μm. In some embodiments, the thinned second substrate 212' has a thickness 304 in the range of 72-78 μm. In some embodiments, the diameter 306 of each of the plurality of through holes 220 is in the range of 3-5 μm. In some embodiments, the spacing dimension 308 is in the range of 2.6-3.4 μm.

[0069] In the illustrated embodiment, the sidewalls 310 of the plurality of through holes 220 etched into the second dielectric layer 214 and the thinned second substrate 212' are perpendicular to the exposed surface of the first dielectric layer 204. The profile obtained under ideal etching conditions with ideal sidewall protection in the semiconductor device 300 is for illustrative purposes and is not intended to be limiting. Actual etching conditions (i.e., etching rates in different directions) may result in, for example, tapers, undercuts, notches, bows, ripples, etc., which may change the sidewall profile of the through hole 220. It should be noted that different sidewall profiles that may be obtained from actual etching conditions are within the scope of the embodiments of the present invention.

[0070] Figure 4Various sidewall profiles 400 of etched vias in the second dielectric layer 214 and the thinned second substrate 212 ′ of the semiconductor device 300 are shown in accordance with some embodiments of the present invention. The various sidewall profiles 400 include a first profile 402 having a vertical sidewall 310 under ideal etching conditions, a second profile 404 having a tapered sidewall 310 and a complete undercut 424 under the second dielectric layer 214 caused by strong sidewall protection, a third profile 406 having a tapered sidewall 310 and a partial undercut 424 under the second dielectric layer 214 caused by a spontaneous etching reaction, a fourth profile 408 having a sidewall 310 including ripples 418, a fifth profile 410 having a smoothly curved sidewall 310, a sixth profile 412 having a tapered sidewall 310 and a notch 420 at the bottom of the via in the thinned second substrate 212' caused by distorted ion trajectories and / or chemical etching, a seventh profile 414 having an inversely tapered sidewall 310, and an eighth profile 416 having a tapered sidewall 310 and an etched corner 422 in the second dielectric layer 214. It should be noted that Figure 4 The sidewall profiles in the figure are for illustrative purposes and are not limiting. Different sidewall profiles that can be obtained from various etching conditions are within the scope of embodiments of the present invention. Different profiles of the sidewall 310 of the through hole 220 can be made and used, which are within the scope of embodiments of the present invention.

[0071] Figure 5A An exemplary top view of a semiconductor device 500 with a collimator structure according to some embodiments of the present invention is shown. The collimator structure in the semiconductor device 500 includes 64 through-holes 220. In the embodiment shown, each through-hole 220 has a circular cross-section. In some other embodiments, a cross-section of the through-hole 220 of a different shape (e.g., square) may be used and is within the scope of embodiments of the present invention. In the embodiment shown, the through-holes 220 are arranged in an 8×8 array of square cells 502. It should be noted that Figure 5A The semiconductor device 500 in FIG. 1 is for illustration purposes only; any number of through-holes 220 may be used and is within the scope of embodiments of the present invention.

[0072] Figure 5B An exemplary top view of a semiconductor device 500 with a collimator structure according to some embodiments of the present invention is shown. The collimator structure in the semiconductor device 500 includes 60 through holes 220. In the embodiment shown, each through hole 220 has a circular cross-section. In some other embodiments, a cross-section of the through hole 220 of a different shape (e.g., square) may be used and is within the scope of the embodiments of the present invention. In the embodiment shown, the through holes 220 are arranged in an array of diamond units 504. It should be noted that Figure 5B The semiconductor device 500 in FIG. 1 is for illustration purposes only; any number of through-holes 220 may be used and is within the scope of embodiments of the present invention.

[0073] In one embodiment, the optical collimator comprises: a dielectric layer; a substrate; and a plurality of through holes, wherein the dielectric layer is formed above the substrate, wherein the plurality of through holes are arranged in an array extending in a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, wherein the substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the substrate and the first thickness are configured to allow the optical collimator to filter a range of wavelengths of light.

[0074] In some other embodiments, the substrate comprises silicon.

[0075] In some other embodiments, the first thickness of the substrate is equal to or greater than 75 μm.

[0076] In some other embodiments, the second thickness of the dielectric layer is in the range of 1.5-2.5 μm.

[0077] In some other embodiments, each of the plurality of through holes has a diameter in the range of 3-5 μm.

[0078] In some other embodiments, the dielectric layer comprises silicon dioxide.

[0079] In some other embodiments, the filtered wavelength range is between 780 nm and 1100 nm.

[0080] In another embodiment, a semiconductor device includes: at least one optical sensing element; and an optical collimator; wherein the optical collimator includes: a first dielectric layer, a first substrate, and a plurality of through holes, wherein the first dielectric layer is formed above the first substrate, wherein the plurality of through holes are arranged in an array extending in a lateral direction of a first surface of the first dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the first dielectric layer through the first dielectric layer and the first substrate to a second surface of the first substrate, wherein the first substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the first substrate and the first thickness are configured to allow the optical collimator to filter a range of wavelengths of light.

[0081] In some other embodiments, at least one optical sensing element is formed in a second substrate, wherein the second substrate is further coated with a second dielectric layer, and wherein the optical collimator is formed above the second dielectric layer.

[0082] In some other embodiments, the first substrate comprises silicon.

[0083] In some other embodiments, the first thickness of the first substrate is equal to or greater than 75 μm.

[0084] In some other embodiments, the second thickness of the first dielectric layer is in the range of 1.5-2.5 μm.

[0085] In some other embodiments, each of the plurality of through holes has a diameter in the range of 3-5 μm.

[0086] In some other embodiments, the first dielectric layer comprises silicon dioxide.

[0087] In some other embodiments, the filtered wavelength range is between 780 nm and 1100 nm.

[0088] In another embodiment, a method for forming a semiconductor device includes: forming a collimator structure on a first substrate having a first dielectric layer, wherein the collimator structure includes a plurality of through holes, wherein each of the plurality of through holes extends in a vertical direction from a first surface of a second dielectric layer through the second dielectric layer and the second substrate to a second surface of the second substrate, wherein the second substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the second substrate and the first thickness are configured to allow the collimator structure to filter a range of wavelengths of light.

[0089] In some other embodiments, the method further includes forming and bonding a second substrate to a first dielectric layer on a first substrate, wherein the first substrate includes at least one optical sensing element, wherein the at least one optical sensing element is aligned with a collimator structure, and wherein the first dielectric layer is disposed between the collimator structure and the first substrate.

[0090] In some other embodiments, the second substrate comprises silicon.

[0091] In some other embodiments, the first thickness of the second substrate is equal to or greater than 75 μm, and the second thickness of the second dielectric layer is in the range of 1.5-2.5 μm.

[0092] In some other embodiments, each of the plurality of through holes has a diameter in the range of 3-5 μm.

[0093] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive concept and scope of the present invention. Various changes, substitutions or modifications may be made to the embodiments of the present invention without departing from the inventive concept and scope of the present invention.

Claims

1. An optical collimator, comprising: a dielectric layer; a base; as well as Multiple through holes, wherein the dielectric layer is formed above the substrate, wherein the plurality of through holes are arranged in an array extending in a lateral direction along a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, wherein the substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the substrate and the first thickness are configured to allow the optical collimator to filter light over a range of wavelengths, wherein the first thickness of the substrate and a diameter of each of the plurality of through holes are greater than a second thickness of the dielectric layer.

2. The optical collimator of claim 1, wherein the substrate comprises silicon. 3 . The optical collimator as claimed in claim 1 , wherein the first thickness of the substrate is equal to or greater than 75 μm. 4 . The optical collimator of claim 1 , wherein the second thickness of the dielectric layer is in the range of 1.5-2.5 μm. 5 . The optical collimator of claim 1 , wherein each of the plurality of through holes has the diameter in the range of 3-5 μm. The optical collimator of claim 1 , wherein the dielectric layer comprises silicon dioxide.

7. The optical collimator as claimed in claim 1, wherein the wavelength range is between 780 nm and 1100 nm.

8. A semiconductor device comprising: at least one optical sensing element; an optical collimator; The optical collimator comprises: a first dielectric layer, a first substrate and a plurality of through holes, wherein the first dielectric layer is formed above the first substrate, wherein the plurality of through holes are arranged in an array extending in a lateral direction along a first surface of the first dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the first dielectric layer through the first dielectric layer and the first substrate to a second surface of the first substrate, wherein the first substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the first substrate and the first thickness are configured to allow the optical collimator to filter a range of wavelengths of light; a second dielectric layer formed below the first substrate; and A second substrate is formed below the second dielectric layer, wherein the second dielectric layer has an opening exposing at least one conductive component in the second substrate, and the at least one conductive component is electrically connected to the at least one optical sensing element in the second substrate. 9 . The semiconductor device of claim 8 , wherein the optical collimator is formed above the second dielectric layer.

10. The semiconductor device as claimed in claim 8, wherein the first substrate comprises silicon. 11 . The semiconductor device as claimed in claim 8 , wherein a first thickness of the first substrate is equal to or greater than 75 μm. 12 . The semiconductor device of claim 8 , wherein a second thickness of the first dielectric layer is in the range of 1.5-2.5 μm.

13. The semiconductor device of claim 8, wherein each of the plurality of through holes has a diameter in the range of 3-5 μm. The semiconductor device of claim 8 , wherein the first dielectric layer comprises silicon dioxide.

15. The semiconductor device as claimed in claim 8, wherein the wavelength range is between 780 nm and 1100 nm.

16. A method for forming a semiconductor device, comprising: A collimator structure is formed on a first substrate having a first dielectric layer, wherein the collimator structure includes a plurality of through holes, wherein each of the plurality of through holes extends in a vertical direction from a first surface of a second dielectric layer through the second dielectric layer and a second substrate to a second surface of the second substrate, wherein the second substrate has an overall impurity doping concentration equal to or greater than 1×10 19 cm -3 and a first thickness, and wherein the overall impurity doping concentration of the second substrate and the first thickness are configured to allow the collimator structure to filter a range of wavelengths of light, The first dielectric layer has an opening exposing at least one conductive component in the first substrate, and the at least one conductive component is electrically connected to at least one optical sensing element in the first substrate.

17. The method for forming a semiconductor device according to claim 16, The at least one optical sensing element is aligned with the collimator structure, and the first dielectric layer is disposed between the collimator structure and the first substrate.

18. The method for forming a semiconductor device as claimed in claim 16, wherein the second substrate comprises silicon. 19 . The method for forming a semiconductor device as claimed in claim 16 , wherein the first thickness of the second substrate is equal to or greater than 75 μm, and a second thickness of the second dielectric layer is in the range of 1.5-2.5 μm.

20. The method for forming a semiconductor device as claimed in claim 16, wherein each of the plurality of through holes has a diameter in the range of 3-5 μm.

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