Clock frequency detection circuit, clock control circuit, and clock frequency detection method

Abstract

The application provides a clock frequency detection circuit, a clock control circuit and a clock frequency detection method. The clock control circuit comprises a measurement module, a comparison module and a control chain module. The measurement module comprises a first clock counter configured to obtain a count value of a first clock signal in a first period. The comparison module is configured to compare the count value with an expected value of the first clock signal in the first period to obtain a comparison result. The control chain module is configured to obtain the expected value according to a chained test vector, send the expected value to the comparison module, obtain the comparison result according to the chained test vector, and perform frequency detection on a to-be-tested clock according to the comparison result. Through the application, the problem of high test cost and large test design complexity in the related art during the detection of the frequency of the clock network in a chip is solved, so that the equipment and time cost during the detection of the frequency of the clock network in the chip is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronics, and in particular, to a clock frequency detection circuit, a clock control circuit and a clock frequency detection method. BACKGROUND

[0002] With the increasing scale and complexity of current digital chip designs, the requirements and challenges for design for test (DFT) in the chip design process are also increasing: currently, DFT needs to improve test quality while minimizing test time, reducing test pin resource requirements, and reducing the complexity of test circuit design and integration.

[0003] There are many clock generation or processing modules on the internal clock network of a chip, such as phase-locked loops, frequency dividers, clock switching circuits, etc. Traditional DFT test methods such as scan chain (SCAN) and memory built-in self-test (MBIST) cannot directly cover the test of the clock generation and processing modules on the above clock network. In related technologies, the clock generation and processing modules are usually tested by a direct test method, i.e., the output of the clock or the output after frequency division is connected to the chip pins for measurement. The above test method is subject to the performance of the automatic test equipment (ATE) machine used for testing, specifically, the measurement accuracy is subject to the maximum sampling number of the ATE machine per unit time, and the measurement accuracy is inversely proportional to the frequency of the clock circuit, the higher the frequency of the clock circuit, the higher the requirement for measurement accuracy, and accordingly, the higher the requirement for the performance of the ATE machine; therefore, to ensure the measurement accuracy of the measurement of the high-frequency clock circuit, the ATE machine needs to have good performance, thereby causing the increase of the measurement cost.

[0004] At the same time, when the chip is subjected to chip probing (CP), the test pins are very sensitive to frequency, and generally cannot be directly used as CP test items, which will have limitations in test applications and will also indirectly increase the test cost; the above test method also needs additional test pin resources when subjected to CP testing, and in many projects, the available pin resources for testing are limited, which easily leads to conflicts in pin resource requirements, and the additional pin settings also require higher pin driving capability for the output clock, thereby increasing the test design complexity.

[0005] In addition, there is an indirect clock control circuit design based on the principle of digital circuit in the related art, and a common test method is to test the internal high-speed clock by using the interface clock, that is, the interface clock and the internal high-speed clock are started to count at the same time, the frequency of the internal high-speed clock is calculated according to the count value in a certain count interval and the known interface clock frequency, so as to determine whether there is a deviation between the frequency of the internal high-speed clock and the design value. The above test method needs to set a test vector separately to cover the clock circuit to be tested in the test process, and an additional test control pin is needed in the test process. Therefore, in the case that the internal clock network of the chip is complex and there are many test points, the test time cost will be significantly increased, and the complexity of the test design will be greatly improved.

[0006] In view of the problem of high test cost and large test design complexity in the process of detecting the frequency of the internal clock network in the related art, the related art has not yet proposed an effective solution. SUMMARY

[0007] Embodiments of the present application provide a clock frequency detection circuit, a clock control circuit and a clock frequency detection method to at least solve the problem of high test cost and large test design complexity in the process of detecting the frequency of the internal clock network in the related art.

[0008] According to an embodiment of the present application, a clock frequency detection circuit is provided, comprising:

[0009] a measurement module comprising a first clock counter configured to count a first clock signal in a first period to obtain a count value of the first clock signal in the first period, wherein the first clock signal is a clock signal input by a clock to be tested;

[0010] a comparison module configured to compare the calculation value with an expected value of the first clock signal in the first period to obtain a comparison result;

[0011] a control chain module configured to obtain the expected value according to a chained test vector, and send the expected value to the comparison module, and obtain the comparison result according to the chained test vector, and perform frequency detection on the clock to be tested according to the comparison result.

[0012] According to another embodiment of the present application, a clock control circuit is also provided, comprising the clock control circuit in the above-mentioned embodiment, and the clock control circuit in the present embodiment further comprises:

[0013] a first input module configured to input the first clock signal;

[0014] The control module is configured to control the first clock signal, and obtain the serial chain test vector and send the serial chain test vector to the control chain module in the clock frequency detection circuit.

[0015] According to another embodiment of the present application, a chip is also provided, which comprises the clock control circuit as described in the above embodiments.

[0016] According to another embodiment of the present application, a clock frequency detection method is also provided, which comprises:

[0017] obtaining an expected value of counting of a first clock signal in a first period, wherein the first clock signal is a clock signal input of a clock under test;

[0018] obtaining a counting value of counting of the first clock signal in the first period;

[0019] comparing the counting value and the expected value according to a serial chain test vector to obtain a comparison result, so as to detect the frequency of the clock under test.

[0020] According to another embodiment of the present application, a clock frequency detection device is also provided, which comprises:

[0021] a first obtaining module, configured to obtain an expected value of counting of a first clock signal in a first period, wherein the first clock signal is a clock signal input of a clock under test;

[0022] a second obtaining module, configured to obtain a counting value of counting of the first clock signal in the first period;

[0023] a comparison module, configured to compare the counting value and the expected value according to a serial chain test vector to obtain a comparison result, so as to detect the frequency of the clock under test.

[0024] According to another embodiment of the present application, a computer readable storage medium is also provided, which stores a computer program, wherein the computer program is set to execute the steps in any of the above method embodiments when running.

[0025] According to another embodiment of the present application, an electronic device is also provided, which comprises a memory and a processor, the memory stores a computer program, and the processor is set to run the computer program to execute the steps in any of the above method embodiments.

[0026] According to the application, the control chain module is configured to obtain the expected value according to the serial chain test vector, and send the expected value to the comparison module, and the comparison module obtains the comparison result between the expected value and the count value of the first clock signal in the first period obtained by the first clock counter in the measurement module according to the serial chain test vector, and detects the frequency of the clock to be tested according to the comparison result; therefore, the application can solve the problem of high test cost and large test design complexity in the related art, so as to reduce the equipment and time cost of the chip clock network frequency detection, and reduce the complexity of the test design. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings:

[0028] Figure 1 is a functional schematic diagram of a clock frequency detection circuit according to an embodiment of the application (one);

[0029] Figure 2 is a functional schematic diagram of a clock frequency detection circuit according to an embodiment of the application (two);

[0030] Figure 3 is a functional schematic diagram of a clock frequency detection circuit according to an embodiment of the application (three);

[0031] Figure 4 is a functional schematic diagram of a clock frequency detection circuit according to an embodiment of the application (four);

[0032] Figure 5 is a circuit schematic diagram of a clock frequency detection circuit according to an embodiment of the application;

[0033] Figure 6 is a functional schematic diagram of a clock control circuit according to an embodiment of the application (one);

[0034] Figure 7 is a functional schematic diagram of a clock control circuit according to an embodiment of the application (two);

[0035] Figure 8 is a circuit schematic diagram of a clock control circuit according to an embodiment of the application;

[0036] Figure 9 is a flowchart of clock frequency detection of a clock control circuit according to an embodiment of the application;

[0037] Figure 10 is a flow chart of a clock frequency detection method according to an embodiment of the present application;

[0038] Figure 11 is a structural block diagram of a clock frequency detection device according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0040] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence.

[0041] Embodiment 1

[0042] The present embodiment provides a clock frequency detection circuit, Figure 1 is a functional schematic diagram (one) of a clock frequency detection circuit according to an embodiment of the present application, as Figure 1 indicated, the clock frequency detection circuit in the present embodiment comprises:

[0043] The measurement module 102 comprises a first clock counter 1022, which is configured to count the first clock signal in the first period to obtain the count value of the first clock signal in the first period; wherein the first clock signal is the clock signal input by the clock to be measured.

[0044] The comparison module 104 is configured to compare the calculation value with the expected value of the first clock signal in the first period to obtain a comparison result.

[0045] The control chain module 106 is configured to obtain the expected value according to the chained test vector, and send the expected value to the comparison module 104, and obtain the comparison result according to the chained test vector, and perform frequency detection on the clock to be measured according to the comparison result.

[0046] It should be further noted that the clock frequency detection circuit in the present embodiment can realize frequency detection on the clock corresponding to the first clock signal. In the above measurement module, the first clock counter is configured to count the first clock signal in the first period, which can indicate that the first clock counter counts the first clock signal in the preset first period, or can indicate that the first clock counter takes other devices, such as other counters, as the reference for counting, for example, the first clock counter counts according to the start counting of the other counter, and stops counting according to the end counting of the other counter.

[0047] In the control chain module 106, the serial chain test vector is the test vector issued by the control chain module. Since the serial chain test vector is the existing vector for controlling the clock in the control chain module, no separate test phasor needs to be set for the clock frequency detection in the embodiment.

[0048] In the clock frequency detection circuit in the embodiment, the control chain module is configured to obtain the expected value according to the serial chain test vector, and send the expected value to the comparison module. The comparison module obtains a comparison result between the expected value and a count value of the first clock signal in the first period obtained by the first clock counter in the measurement module according to the serial chain test vector, and detects the frequency of the to-be-measured clock according to the comparison result. Therefore, the clock frequency detection circuit in the embodiment can solve the problems of high test cost and large test design complexity in the related art during the detection of the frequency of the clock network in the chip, so as to reduce the equipment and time cost during the detection of the frequency of the clock network in the chip, and reduce the complexity of the test design.

[0049] In an optional embodiment, the measurement module 102 further includes a second clock counter 1024, which is configured to count the second clock signal in a second period.

[0050] The second clock signal is a clock signal input by an automated test equipment (ATE) of a peripheral device, and the second period is a preset inherent period of the second clock signal. The first period is synchronous with the second period.

[0051] It should be further noted that the first period synchronous with the second period indicates that the first period in which the first clock counter counts is referenced to the second period and is synchronous with the second period, that is, the actual period in which the first clock counter counts is the second period. The first clock counter counts in the second period. The specific period information of the second period can be sent to the control part of the first clock counter for control, or the first clock counter can be caused to count when the second clock counter starts counting and stop counting when the second clock counter finishes counting, that is, the first clock counter counts based on the second clock counter. The specific counting manner of the first clock counter is not limited in the present application. Figure 2 FIG. 2 is a functional schematic diagram of the clock frequency detection circuit according to an embodiment of the present application (II), and the structure of the measurement module in the optional embodiment is shown in FIG. 2. Figure 2

[0052] ​In an optional embodiment, the expected value is obtained according to the following object:

[0053] the frequency information of the second clock signal.

[0054] It should be further explained that the frequency information of the first clock signal is the clock frequency of the first clock signal, and the frequency information of the second clock signal is the clock frequency of the second clock signal. Assuming that the second period is Cnt_R, the frequency information of the first clock signal is Frq_T, the frequency information of the second clock signal is Cnt_R, and the expected value of the first clock signal in the first period is Int_M, the expected value can be obtained by the following formula:

[0055] Int_M = [Cnt_R * Frq_T / Frq_R];

[0056] The [] represents the rounding up of the calculation result of Cnt_R * Frq_T / Frq_R.

[0057] It should be further explained that the formula for obtaining the expected value Int_M is only an optional way, and other ways can be used to determine the expected value according to the actual detection environment or requirements, and the present application does not limit this.

[0058] In an optional embodiment, the comparison module 104 comprises:

[0059] an expected value storage unit 1042 configured to store the expected value;

[0060] a comparison unit 1044 configured to obtain the count value and the expected value, and compare the count value with the expected value to obtain a comparison result.

[0061] It should be further explained that the expected value storage unit stores the expected value, that is, the expected value can be sent into the expected value storage unit by the serial test vector. Figure 3 is a functional schematic diagram (three) of the clock frequency detection circuit provided by the embodiment of the present application, and the composition of the comparison module in the optional embodiment is as shown in Figure 3 .

[0062] In an optional embodiment, the comparison unit 1044 is further configured to:

[0063] remove the error in the count value according to the preset error bit;

[0064] compare the count value after removing the error with the expected value to obtain a comparison result.

[0065] It needs to be further explained that, during the counting process of the first clock counter, the first clock counter can take the counting of other counters for other clock signals as a reference, that is, to control by using asynchronous clock, so that the first clock counter can have errors during the counting start and end process. The setting of the comparison unit can effectively eliminate the errors that may exist in the count value, thereby improving the accuracy of clock frequency detection. It needs to be explained that, during the comparison of the error-eliminated count value and the expected value, the count value can be directly compared with the expected value which is processed by using the corresponding code bit, or the code bit which may have errors can be directly removed during the determination of the expected value, and the present application does not limit this.

[0066] In an optional embodiment, the control chain module 106 includes an expected value register 1062 and a comparison result register 1064; the control chain module 106 is further configured to,

[0067] According to the serial test vector, the expected value register acquires the expected value in the serial data shift mode and sends the expected value to the comparison module; and / or,

[0068] According to the serial test vector, the comparison result register acquires the comparison result in the serial data acquisition mode and performs frequency detection on the to-be-tested clock according to the comparison result.

[0069] It needs to be further explained that, during the counting process of the first clock counter, the first clock counter can take the counting of other counters for other clock signals as a reference, that is, to control by using asynchronous clock, so that the first clock counter can have errors during the counting start and end process. The setting of the comparison unit can effectively eliminate the errors that may exist in the count value, thereby improving the accuracy of clock frequency detection. It needs to be explained that, during the comparison of the error-eliminated count value and the expected value, the count value can be directly compared with the expected value which is processed by using the corresponding code bit, or the code bit which may have errors can be directly removed during the determination of the expected value, and the present application does not limit this. Figure 4 is a functional schematic diagram (four) of a clock frequency detection circuit according to an embodiment of the present application, and the composition of the control chain module in the optional embodiment is as shown in Figure 4 .

[0070] In an optional embodiment, the control chain module 106 is further configured to send the comparison result to an automatic test equipment (ATE) of a peripheral device to perform frequency detection on the to-be-tested clock.

[0071] To further illustrate the clock frequency detection circuit in the embodiment, the circuit structure and working mode of the clock frequency detection circuit are illustrated by means of specific embodiments below. Specific embodiment one

[0073] Figure 5 is a circuit schematic diagram of a clock frequency detection circuit according to a specific embodiment of the present application, and the input signal, output signal and specific composition of the clock frequency detection circuit in the present specific embodiment are illustrated below. Figure 5

[0074] The input signal of the clock frequency detection circuit in the present specific embodiment includes:

[0075] ​1) SI: input control signal of the scan chain;

[0076] 2) PLL CLK: high-speed clock signal, which is from the phase-locked loop output inside the chip, and is the first clock signal in the above embodiment. In this embodiment, the PLL CLK is the clock signal to be detected;

[0077] 3) ATE CLK: low-speed clock signal, which is directly input by the peripheral ATE test machine, and is the second clock signal in the above embodiment. The inherent period of the ATE CLK is the second period in the above embodiment;

[0078] 4) OCC_RST: OCC reset signal;

[0079] The output signal of the clock frequency detection circuit in this embodiment is SO.

[0080] The clock frequency detection circuit in this embodiment specifically includes: a to-be-detected clock counter 003, a reference clock counter 006, and a TEST_ON module 005. The to-be-detected clock counter 003 corresponds to the first clock counter in the above embodiment, and is used to access the PLL CLK. The reference clock counter 006 corresponds to the second clock counter in the above embodiment, and is used to access the ATE CLK. The TEST_ON module 005 is used to access the OCC_RST and is controlled by the OCC_RST. Specifically, after the OCC_RST is reset and released, the TEST_ON module 005 sends an enable signal counter_en to the to-be-detected clock counter 003 and the reference clock counter 006, indicating that the to-be-detected clock counter 003 and the reference clock counter 006 start counting work on the PLL CLK and the ATE CLK respectively.

[0081] Further, the reference clock counter 006 stores the inherent period of the ATE CLK, that is, the second period in the above embodiment. When the reference clock counter 006 counts the ATE CLK to reach the inherent period, the reference clock counter 006 stops counting. At this time, the TEST_ON module 005 closes the corresponding enable signal, so that the to-be-detected clock counter 003 also stops counting the PLL CLK.

[0082] For different PLL CLK, theoretically, the count result of the clock counter 003 in the corresponding count period, i.e. the inherent period of ATE CLK, is different, which is set as the expected value of the clock counter 003 counting the PLL CLK in the inherent period of ATE CLK. The expected value can be determined in the following way: setting the inherent period of ATE CLK as Cnt_R, the clock frequency of PLL CLK as Frq_T, the clock frequency of ATE CLK as Cnt_R, the expected value as Int_M, the expected value can be obtained by the following formula:

[0083] Int_M=[Cnt_R*Frq_T / Frq_R];

[0084] The above [] represents the calculation result of Cnt_R*Frq_T / Frq_R is rounded up.

[0085] The clock frequency detection circuit in the embodiment further comprises an expected value storage logic 007 and a counter comparison circuit 004, the expected value obtained by theoretical calculation can be stored in the expected value storage logic 007. The count value of PLL CLK obtained by the clock counter 003 and the expected value of the expected value storage logic 007 are sent to the counter comparison circuit 004 at the same time for comparison processing. Here, the counter comparison circuit 004 can use "1" to represent that the comparison result between the count value of PLL CLK and the expected value is consistent, i.e. "true", and use "0" to represent that the comparison result between the count value of PLL CLK and the expected value is not consistent, i.e. "false"; therefore, according to the level of the output signal of the counter comparison circuit 004, the comparison result between the count value of PLL CLK and the expected value can be determined. In the case that the comparison result between the count value of PLL CLK and the expected value is consistent, i.e. the frequency test result of the clock circuit corresponding to PLL CLK is correct, the clock circuit is normal, otherwise, in the case that the comparison result between the count value of PLL CLK and the expected value is not consistent, i.e. the frequency test result of the clock circuit corresponding to PLL CLK is incorrect, the clock circuit is faulty.

[0086] It needs to be further explained that the counter comparison circuit 004 can also realize the mask function, i.e. removing the error bits that may exist in the comparison data. Since the clock counter 003 is controlled by the reference clock counter 006 asynchronously, the clock counter 003 may have errors in the process of counting PLL CLK in the process of starting and ending counting. The counter comparison circuit 004 can remove the errors in the count value of PLL CLK by the mask function, and then compare it with the expected value, so as to improve the accuracy of comparison.

[0087] The clock frequency detection circuit in the embodiment further comprises a frequency detection control chain 001 and a frequency detection feedback register 002, which form a complete shift register chain. The frequency detection control chain 001 can make the shift register chain send the control register data of the OCC and the expected value corresponding to the PLL CLK into the expected value storage logic 007 through shifting in the scan shift mode according to the input SI, and sample the output result of the counter comparison circuit 004 into the frequency detection feedback register 002 in the scan capture mode, and then send the output result as the output signal SO to the ATE platform for test comparison through scan shift. Therefore, the SI described above constitutes the serial test vector in the embodiment, that is, the data shifting and collection are realized.

[0088] Embodiment 2

[0089] The embodiment provides a clock control circuit comprising the clock frequency detection circuit described in embodiment 1, Figure 6 is a functional schematic diagram (one) of the clock control circuit provided according to the embodiment of the present application, as Figure 6 indicated, the clock control circuit in the embodiment comprises:

[0090] The first input module 202 is configured to input the first clock signal;

[0091] The control module 204 is configured to control the first clock signal, and acquire and send the serial test vector to the control chain module in the clock frequency detection circuit.

[0092] It needs to be further explained that the clock control circuit in the embodiment can be the OCC circuit, or other circuits for realizing the related clock control function, and the present application does not limit this.

[0093] It needs to be further explained that the control module in the embodiment is the corresponding module for control processing in the clock control circuit, and the control module described above can realize the clock control requirement of the clock control circuit in the DFT. On this basis, the control module in the embodiment can also acquire the serial test vector by controlling the first clock signal and sending it to the clock frequency detection circuit, that is, the clock control module in the embodiment can also realize the clock frequency detection.

[0094] By the clock control circuit in this embodiment, the clock frequency detection circuit in the above embodiment can be set in the clock control circuit, the first clock signal is controlled by the control module, the serial chain test vector is obtained, and the serial chain test vector is sent to the control chain module in the clock frequency detection circuit. Therefore, the clock control circuit in this embodiment can solve the problem of high test cost and high test design complexity in the related art chip clock network frequency detection process, so as to reduce the equipment and time cost of chip clock network frequency detection, and reduce the complexity of test design.

[0095] The serial chain test vector is the existing vector of the control module in the process of controlling the clock control circuit to control the clock. By sending the serial chain test vector to the control chain module in the clock frequency detection circuit to perform the corresponding operation, the detection of the clock frequency in the clock frequency detection circuit can be realized on the basis of the existing serial chain test vector. Therefore, the clock frequency detection process in this embodiment is completely based on the control mode of the existing clock control circuit, and does not involve additional test pins or test neighbors for detection.

[0096] Generally, the clock control circuit in this embodiment is designed for DFT, so that the clock control circuit covers the entire clock network in the chip. Therefore, the clock control circuit in this embodiment can detect the quality of all clocks in the chip, thereby significantly improving the coverage of clock quality test.

[0097] In addition, the devices involved in the clock control circuit in this embodiment can be realized by using resources in the standard cell library in the circuit design. Therefore, the clock control circuit in this embodiment does not bring additional design and integration costs during implementation. On the other hand, the serial chain test vector in the clock control circuit in this embodiment is used for clock control, so that the control of the serial chain test vector for clock frequency detection can be completed in the process of clock control, so that the clock frequency detection process can be completed at the same time as the scan test, thereby avoiding additional time overhead and significantly reducing the time cost.

[0098] In an optional embodiment, the clock control circuit further comprises:

[0099] The second input module 206 is configured to input a second clock signal;

[0100] The control module 204 is further configured to control the second clock signal.

[0101] It should be further pointed out that, Figure 7 is a functional diagram of the clock control circuit according to an embodiment of the present application (two), and the second input module is set asFigure 7 as shown.

[0102] In an optional embodiment, the control module 204 is configured to:

[0103] control the turn-off and turn-on of the first clock signal and / or the second clock signal, and output a corresponding output clock signal.

[0104] The clock frequency detection circuit included in the clock control circuit in the embodiment includes:

[0105] a measurement module including a first clock counter configured to count the first clock signal in a first period to obtain a count value of the first clock signal in the first period, wherein the first clock signal is a clock signal input by the to-be-tested clock;

[0106] a comparison module configured to compare the count value with an expected value of the first clock signal in the first period to obtain a comparison result;

[0107] a control chain module configured to obtain the expected value according to a chained test vector, send the expected value to the comparison module, obtain the comparison result according to the chained test vector, and perform frequency detection on the to-be-tested clock according to the comparison result.

[0108] In an optional embodiment, the measurement module further includes a second clock counter configured to count the second clock signal in a second period.

[0109] The second clock signal is a clock signal input by an automated test equipment (ATE) of a peripheral device, and the second period is a preset inherent period of the second clock signal. The first period is synchronous with the second period.

[0110] In an optional embodiment, the expected value is obtained according to the following objects:

[0111] the second period, frequency information of the first clock signal, and frequency information of the second clock signal.

[0112] In an optional embodiment, the comparison module includes:

[0113] an expected value storage unit configured to store the expected value;

[0114] a comparison unit configured to obtain the count value and the expected value, compare the count value with the expected value, and obtain a comparison result.

[0115] In an optional embodiment, the comparison circuit is further configured to:

[0116] remove errors in the count value according to a preset error bit;

[0117] The count value after removing the error is compared with the expected value to obtain a comparison result.

[0118] In an optional embodiment, the control chain module comprises an expected value register and a comparison result register; the control chain module is further configured to,

[0119] According to the serial test vector, the expected value register obtains the expected value in the serial data shift mode and sends the expected value to the comparison module; and / or,

[0120] According to the serial test vector, the comparison result register obtains the comparison result in the serial data collection mode and performs frequency detection on the to-be-tested clock according to the comparison result.

[0121] In an optional embodiment, the control chain module is further configured to send the comparison result to an automated test equipment (ATE) of an external device to perform frequency detection on the to-be-tested clock.

[0122] The remaining optional technical solutions and technical effects of the clock frequency detection circuit in this embodiment correspond to those of the clock frequency detection circuit in Embodiment 1, and thus will not be described here again.

[0123] To further illustrate the clock control circuit in this embodiment, the composition and working mode of the clock control circuit in this embodiment are described below through specific embodiments. Specific Embodiment Two

[0125] Figure 8 is a circuit schematic diagram of the clock control circuit provided according to a specific embodiment of the present application, and the following describes the clock control circuit in this embodiment in combination with Figure 8 The input, output and internal composition of the clock control circuit in this specific embodiment are described in detail.

[0126] In the clock control circuit in this specific embodiment, the input signals comprise:

[0127] 1) ATE_CLK: a low-speed clock signal, i.e., the second clock signal in the above embodiments, which is directly input by an ATE test machine of an external device;

[0128] 2) PLL_CLK: a high-speed clock signal, i.e., the first clock signal in the above embodiments, which is output from a phase-locked loop in the chip; in this specific embodiment, the PLL_CLK indicates the clock signal to be detected in the clock control circuit;

[0129] 3) OCC_CTRLs: general control signals of OCC, which can have multiple types according to different control requirements or purposes, for example, shift enable signal shift_en, data capture signal capture_en, OCC reset signal OCC_RST, and the like;

[0130] 4) SCAN_IN: input signal of the OCC internal clock control chain.

[0131] In the clock control circuit in the embodiment, the output signals include:

[0132] 1) OCC_CLK: clock signal, which is output from PLL_CLK in the functional mode, ATE_CLK in the scan shift and low-speed capture modes, and PLL_CLK in the high-speed capture mode.

[0133] 2) SCAN_OUT: output signal of the OCC internal clock control chain.

[0134] The internal structure of the clock control circuit in the embodiment specifically includes:

[0135] ATE clock gating 011, PLL clock gating 012, OCC clock selector 013, and OCC control module 014; wherein the ATE clock gating 011 is used to access the ATE_CLK sent by the external ATE tester, and the PLL clock gating 012 is used to access the to-be-tested clock signal PLL_CLK output by the phase-locked loop inside the chip. The above-mentioned ATE clock gating 011 can be controlled by the OCC control module 014 to realize the functions of clock opening of ATE_CLK in the shift mode and the low-speed capture mode and clock shutting down in the high-speed capture mode. Correspondingly, the PLL clock gating 012 is also controlled by the OCC control module 014 to realize the functions of clock shutting down of PLL_CLK in the shift mode and the low-speed capture mode and clock opening and output clock number control in the high-speed capture mode.

[0136] The OCC clock selector 013 is controlled by the OCC control module 014 to control the selection of OCC_CLK in different DFT modes. The control of the ATE clock gating 011, the PLL clock gating 012, and the OCC clock selector 013 by the OCC control module 014 is realized by the OCC_CTRLs signals, that is, the OCC control module 014 is controlled by the externally input OCC_CTRLs, and at the same time, the OCC control module 014 is also controlled by the OCC control chain 015.

[0137] The OCC control chain 015 accesses the external input SCAN IN to control the OCC control chain 015 to work in different modes. The OCC control chain 015 can include a plurality of shift registers, and according to the indication of the SCAN IN, the OCC control chain 015 can send the control signals for the OCC into the OCC control module 014 by shifting in the scan shift mode.

[0138] The clock control circuit in the embodiment further includes a clock frequency detection module, which is the clock frequency detection circuit in the first embodiment. In the embodiment, the clock frequency detection module corresponds to the clock frequency detection circuit in the first embodiment in terms of the structure and working mode, and thus will not be described herein.

[0139] It should be further noted that the clock frequency detection module can be arranged inside the clock control circuit or outside the clock control circuit, i.e., arranged independently of the clock control circuit. In the embodiment, the clock frequency detection module is integrated inside the clock control circuit.

[0140] In the embodiment, the ATE clock gating 011 and the PLL clock gating 012 can respectively input the ATE CLK and the PLL CLK into the reference clock counter and the clock under test counter of the clock frequency detection module. Meanwhile, the shift register chain formed by the frequency measurement control chain and the frequency measurement shift register inside the clock frequency detection module can further form a longer OCC internal shift register chain together with the OCC control chain 015 in the embodiment. The OCC internal shift register chain can send the control register data of the OCC and the expected value of the PLL CLK clock counter into the shift register chain by shifting in the scan shift mode.

[0141] The specific method for the clock control circuit to detect the clock frequency will be described below. Figure 9 The specific method for the clock control circuit to detect the clock frequency is shown in the flowchart of the clock control circuit to detect the clock frequency according to the embodiment of the present application, as shown in Figure 9 The specific method for the clock control circuit to detect the clock frequency can be performed in the following manner.

[0142] S1, theoretically calculate the expected value Int_M, specifically, theoretically calculate the expected value Int_M of the clock to be detected in the corresponding first period, for the above to be detected clock PLL CLK, obtain the PLL CLK clock frequency information Frq_T, the ATE machine input of the peripheral ATE CLK clock frequency Frq_R, and the fixed period Cnt_R corresponding to the ATE CLK, according to the above information, the expected value of the to-be-detected clock counter to PLL CLK in the fixed period can be calculated, that is:

[0143] [Cnt_R*Frq_T / Frq_R]; [] represents rounding up;

[0144] It should be further pointed out that if there are multiple to-be-detected clocks, the above Int_M calculation process needs to be repeated for each to-be-detected clock;

[0145] S2, add ATPG constraints, specifically, add related constraints in the scan ATPG environment, that is, indicate that the expected value obtained in S1 above is sent into the corresponding register, and the expected comparison result output value is set in the counter comparison circuit in the clock frequency detection module; The process of adding ATPG constraints includes: guiding the tool to send the expected value Int_M of each to-be-detected clock PLL CLK into the clock frequency detection module of the clock control circuit of each to-be-detected clock in the scan shift process, and adding ATPG constraints so that the input value of the frequency feedback register corresponding to all to-be-detected clocks is "1", that is, the input state is "true";

[0146] S3, scan ATPG and test, specifically, generate vectors by ATPG and perform simulation or ATE test, if the clock frequency of the OCC on the clock network is abnormal (the expected value and the measured value are inconsistent), the scan simulation or ATE test will have an error, thereby the chip with clock abnormality can be screened out through the scan vector, and through ATPG diagnose (diagnosis) analysis, it can be determined which frequency feedback register in the OCC fails, and it can be further determined which clock has a problem.

[0147] Embodiment 3

[0148] The embodiment provides a chip, which comprises the clock control circuit described in embodiment 2, and the clock control circuit in the chip corresponds to the technical scheme and technical effect of embodiment 2, so the details are not repeated here.

[0149] Embodiment 4

[0150] The embodiment provides a clock frequency detection method, Figure 10 is a flow chart of the clock frequency detection method provided by the embodiment of the application, as shown in the figure, the frequency detection method in the embodiment comprises: Figure 10

[0151] S302, obtaining an expected value of counting of the first clock signal in the first period, wherein the first clock signal is a clock signal input by the to-be-tested clock;

[0152] S304, obtaining a counting value of counting of the first clock signal in the first period;

[0153] S306, obtaining a comparison result of comparison of the counting value and the expected value according to the serial chain test vector, so as to detect the frequency of the to-be-tested clock.

[0154] Through the clock frequency detection method in the embodiment, the expected value and the counting value of counting of the first clock signal in the first period can be obtained, and the comparison result of comparison of the counting value and the expected value according to the serial chain test vector is obtained, so as to detect the frequency of the to-be-tested clock. Therefore, the clock frequency detection method in the embodiment can solve the problems of high test cost and large test design complexity in the related art during detection of the frequency of the clock network in the chip, so as to reduce the equipment and time cost during detection of the frequency of the clock network in the chip, and reduce the complexity of the test design.

[0155] In an optional embodiment, in the step S304, the counting value of counting of the first clock signal in the first period comprises:

[0156] configuring the second clock signal to count in the second period, wherein the second clock signal is a clock signal input by an automatic test equipment (ATE) of a peripheral device, and the second period is a preset inherent period of the second clock signal;

[0157] synchronizing the first period and the second period, so as to obtain the counting value of counting of the first clock signal in the first period.

[0158] ​It needs to be further explained that the first period is synchronized with the second period, and the first clock counter counts the first period with the second period as a reference. The first clock counter counts in the second period, and the specific period information of the second period can be sent to the control part of the first clock counter for control. When the second clock counter counts in the inherent period, that is, the second period, the first clock counter starts counting when the second clock counter starts counting, and stops counting when the second clock counter ends counting, that is, the first clock counter counts based on the second clock counter. The specific counting method of the first clock counter is not limited in the application.

[0159] In an optional embodiment, in the step S302, the expected value of the first clock signal counting in the first period is obtained, comprising:

[0160] The expected value is obtained according to the following objects: the second period, the frequency information of the first clock signal, and the frequency information of the second clock signal.

[0161] In an optional embodiment, in the step S306, the comparison result of the count value and the expected value is obtained according to the serial chain test vector, comprising:

[0162] The error in the count value is removed according to the preset error bit;

[0163] The comparison result of the count value after removing the error and the expected value is obtained according to the serial chain test vector.

[0164] It needs to be further explained that during the counting process of the first clock counter, the first clock counter can take the counting of other clock signals by other counters as a reference, that is, use asynchronous clock for control. Therefore, errors can occur during the start and end of the counting of the first clock counter. The comparison unit can effectively eliminate the possible errors in the count value, thereby improving the accuracy of the clock frequency detection. It needs to be explained that during the comparison of the count value after removing the error and the expected value, the count value can be directly compared with the expected value after corresponding processing of the corresponding code bit, or the code bit with possible errors can be directly removed during the determination of the expected value, and the application does not limit this.

[0165] In an optional embodiment, in the step S306, the comparison result of the count value and the expected value is obtained according to the serial chain test vector, comprising:

[0166] In the case where the count value and the expected value are consistent, it is judged that the frequency of the to-be-tested clock is normal; or,

[0167] In the case that the count value does not match the expected value, it is determined that the frequency of the clock under test is abnormal.

[0168] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software on a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the method described in each embodiment of the present application.

[0169] Embodiment 5

[0170] The present embodiment provides a clock frequency detection device, which is used to implement the above embodiments and preferred embodiments, and has been described above. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, implementation of hardware, or a combination of software and hardware, is also possible and contemplated.

[0171] Figure 11 is a structural block diagram of a clock frequency detection device provided according to an embodiment of the present application, as shown in Figure 11 , the device comprises:

[0172] The first acquisition module 402 is configured to acquire an expected value of counting of the first clock signal in the first period, wherein the first clock signal is a clock signal input by the clock under test;

[0173] The second acquisition module 404 is configured to acquire a count value of counting of the first clock signal in the first period;

[0174] The comparison module 406 is configured to compare the count value with the expected value according to the concatenated test vector to obtain a comparison result, and perform frequency detection on the clock under test.

[0175] The clock frequency detection device in the embodiment can solve the problems of high test cost and large test design complexity in the process of detecting the frequency of the clock network in the chip in the related art, so as to reduce the equipment and time cost in the process of detecting the frequency of the clock network in the chip, and reduce the complexity of the test design.

[0176] The remaining optional technical solutions and technical effects of the clock frequency detection device in the embodiment correspond to the clock frequency detection method in Embodiment 3, and therefore will not be described here.

[0177] In an optional embodiment, the obtaining of the count value of the first clock signal counted in the first period includes:

[0178] The second clock signal is configured to be counted in a second period, where the second clock signal is a clock signal input by an automatic test equipment (ATE) of the peripheral device, and the second period is a preset inherent period of the second clock signal;

[0179] The first period is set to be synchronized with the second period, so as to obtain the count value of the first clock signal counted in the first period.

[0180] In an optional embodiment, the obtaining of the expected value of the first clock signal counted in the first period includes:

[0181] The expected value is obtained according to the following objects: the second period, the frequency information of the first clock signal, and the frequency information of the second clock signal.

[0182] In an optional embodiment, the comparison result of the comparison of the count value with the expected value according to the serial test vector includes:

[0183] The error in the count value is removed according to a preset error bit;

[0184] The comparison result of the comparison of the count value after the error removal with the expected value is obtained according to the serial test vector.

[0185] In an optional embodiment, the comparison result of the comparison of the count value with the expected value according to the serial test vector is used to detect the frequency of the to-be-tested clock, including:

[0186] In a case where the count value is consistent with the expected value, it is determined that the frequency of the to-be-tested clock is normal; or

[0187] In a case where the count value is not consistent with the expected value, it is determined that the frequency of the to-be-tested clock is abnormal.

[0188] It should be noted that the above various modules can be implemented by software or hardware, and for the latter, the implementation can be achieved by the following ways, but is not limited thereto: the above modules are located in the same processor; or the above various modules are located in different processors in any combination.

[0189] Embodiment 6

[0190] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is configured to execute the steps in any of the above method embodiments when running.

[0191] Optionally, in the embodiment, the above computer readable storage medium can be configured to store a computer program for executing the following steps:

[0192] S1, obtaining an expected value of counting of a first clock signal in a first period, wherein the first clock signal is a clock signal of a clock input to be tested;

[0193] S2, obtaining a counting value of counting of the first clock signal in the first period;

[0194] S3, obtaining a comparison result of comparing the counting value with the expected value according to a serial chain test vector, so as to detect the frequency of the clock to be tested.

[0195] Optionally, the specific examples in the embodiment can refer to the examples described in the above embodiments and optional implementation manners, and the embodiment will not be described here.

[0196] Optionally, in the embodiment, the above storage medium can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various storage media that can store computer programs.

[0197] Embodiment 7

[0198] The embodiments of the present application also provide an electronic device, which comprises a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to execute the steps in any of the above method embodiments.

[0199] Optionally, the above electronic device can further comprise a transmission device and an input and output device, wherein the transmission device is connected with the above processor, and the input and output device is connected with the above processor.

[0200] Optionally, in the embodiment, the processor can be configured to execute the following steps by a computer program:

[0201] S1, obtaining an expected value of counting of the first clock signal in the first period, wherein the first clock signal is a clock signal of the clock input to be measured;

[0202] S2, obtaining a counting value of counting of the first clock signal in the first period;

[0203] S3, obtaining a comparison result of comparing the counting value with the expected value according to the serial chain test vector, so as to detect the frequency of the clock to be measured.

[0204] Optionally, the specific examples in the embodiment can refer to the examples described in the above embodiments and optional implementation manners, and the embodiment will not be described here.

[0205] Obviously, those skilled in the art should understand that the modules or steps of the application described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and optionally, they can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the application is not limited to any specific combination of hardware and software.

[0206] The above only describes the preferred embodiments of the application and is not used to limit the application. For those skilled in the art, the application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the application shall be included in the protection scope of the application.

Claims

1. A clock frequency detection circuit, characterized by, The clock frequency detection circuit comprises: a measurement module comprising a first clock counter configured to count a first clock signal in a first period to obtain a count value of the first clock signal in the first period, wherein the first clock signal is a clock signal input by a clock under test; a comparison module configured to compare the count value with an expected value of the first clock signal in the first period to obtain a comparison result; a control chain module configured to obtain the expected value according to a serial chain test vector, and send the expected value to the comparison module, and obtain the comparison result according to the serial chain test vector, and perform frequency detection on the clock under test according to the comparison result; the control chain module comprises an expected value register and a comparison result register; the control chain module is further configured to instruct the expected value register to obtain the expected value in a serial chain data shift mode according to the serial chain test vector, and send the expected value to the comparison module; and / or instruct the comparison result register to obtain the comparison result in a serial chain data collection mode according to the serial chain test vector, and perform frequency detection on the clock under test according to the comparison result; the serial chain test vector is a test vector issued in the control chain module, the serial chain test vector itself is used for clock control, and the control of the serial chain test vector on the clock frequency detection is completed in the process of clock control; the measurement module further comprises a second clock counter configured to count a second clock signal in a second period; wherein the second clock signal is a clock signal input by an automatic test equipment (ATE) of a peripheral device, and the second period is a preset inherent period of the second clock signal; and the first period is synchronous with the second period.

2. The circuit of claim 1, wherein, The expected value is obtained according to the following objects: the second period, frequency information of the first clock signal, and frequency information of the second clock signal.

3. The circuit of claim 1, wherein, The comparison module comprises: an expected value storage unit configured to store the expected value; a comparison unit configured to obtain the count value and the expected value, and compare the count value with the expected value to obtain the comparison result.

4. The circuit of claim 3, wherein, The comparison unit is further configured to: remove errors in the count value according to preset error bits; and compare the count value after the errors are removed with the expected value to obtain the comparison result.

5. The circuit of claim 1, wherein, The control chain module is further configured to send the comparison result to an automatic test equipment (ATE) of a peripheral device to perform frequency detection on the clock under test.

6. A clock control circuit, characterized by comprising: The clock control circuit comprises any one of claims 1 to 5; the clock control circuit further comprises: a first input module configured to input the first clock signal; a control module configured to control the first clock signal, and obtain the serial chain test vector and send the serial chain test vector to the control chain module in the clock frequency detection circuit.

7. The circuit of claim 6, wherein, the clock control circuit further comprises: a second input module configured to input the second clock signal; The control module is further configured to control the second clock signal.

8. The circuit of claim 7, wherein, The control module is configured to: control the first clock signal and / or the second clock signal to be off, on, and output a corresponding output clock signal.

9. A chip, characterized by The clock control circuit according to any one of claims 6-8.

10. A clock frequency detection method based on the clock frequency detection circuit according to claim 1, characterized by, The method comprises: obtaining an expected value of counting of a first clock signal in a first period, wherein the first clock signal is a clock signal input by a to-be-tested clock; obtaining a counting value of counting of the first clock signal in the first period, comprising: configuring a second clock signal to count in a second period, wherein the second clock signal is a clock signal input by an automatic test equipment (ATE) of a peripheral device, and the second period is a preset inherent period of the second clock signal; and setting the first period to be synchronized with the second period to obtain the counting value of counting of the first clock signal in the first period; comparing the counting value with the expected value according to a serial chain test vector to obtain a comparison result, and performing frequency detection on the to-be-tested clock, comprising: obtaining the expected value in a serial chain data shift mode according to the serial chain test vector; and / or obtaining the comparison result in a serial chain data collection mode according to the serial chain test vector, and performing frequency detection on the to-be-tested clock according to the comparison result, wherein the serial chain test vector is a test vector issued by the control chain module, the serial chain test vector itself is used for clock control, and control of the serial chain test vector on clock frequency detection is completed in the process of clock control.

11. The method of claim 10, wherein, The obtaining of the expected value of counting of the first clock signal in the first period comprises: obtaining the expected value according to the following objects: the second period, frequency information of the first clock signal, and frequency information of the second clock signal.

12. The method according to any one of claims 10 to 11, characterized in that, The obtaining of the comparison result of the counting value and the expected value according to the serial chain test vector comprises: removing errors in the counting value according to preset error bits; obtaining the comparison result of the counting value after the errors are removed and the expected value according to the serial chain test vector.

13. The method according to any one of claims 10 to 11, characterized in that, The obtaining of the comparison result of the counting value and the expected value according to the serial chain test vector to perform frequency detection on the to-be-tested clock comprises: in a case where the counting value is consistent with the expected value, determining that the frequency of the to-be-tested clock is normal; or in a case where the counting value is not consistent with the expected value, determining that the frequency of the to-be-tested clock is abnormal.

14. A computer readable storage medium, characterized in that, The computer program is stored in the computer-readable storage medium, and the computer program is set to execute the method according to any one of claims 10-13 when running. 15.An electronic device comprising a memory and a processor, the electronic device characterized by, The computer program is stored in the memory, and the processor is set to execute the method according to any one of claims 10-13 when running the computer program.

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