Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a substrate, a support structure, and a first antenna. The substrate has a first surface and a second surface opposite the first surface. The support structure is disposed on the first surface of the substrate. The first antenna is disposed on the support structure. The first antenna has a first surface facing the first surface of the substrate, a second surface opposite the first surface, and a lateral surface extending between the first and second surfaces of the first antenna. The lateral surface of the first antenna is exposed to an exterior of the semiconductor device package. The first antenna includes a dielectric layer and an antenna pattern disposed within and penetrating the dielectric layer.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package and a method for manufacturing the semiconductor device package. Background Technology

[0002] Wireless communication devices, such as cellular phones, typically include antennas for transmitting and receiving radio frequency (RF) signals. In recent years, with the continuous development of mobile communications and the urgent need for high data rates and stable communication quality, relatively high-frequency wireless transmission (e.g., 28 GHz or 60 GHz) has become one of the most important topics in the mobile communications industry. In contrast, the antenna is placed within or on a dielectric layer, and the RF signal is transmitted or received by the antenna through the dielectric layer. However, due to the increased frequency of the transmitted or received RF signal, signal attenuation or loss of the RF signal transmitted within the dielectric layer becomes a critical issue / problem. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes a substrate, a support structure, and a first antenna. The substrate has a first surface and a second surface opposite to the first surface. The support structure is disposed on the first surface of the substrate. The first antenna is disposed on the support structure. The first antenna has a first surface facing the substrate, a second surface opposite to the first surface, and a lateral surface extending between the first and second surfaces of the first antenna. The lateral surface of the first antenna is exposed to the exterior of the semiconductor device package. The first antenna includes a dielectric layer and an antenna pattern disposed within and penetrating the dielectric layer.

[0004] In one or more embodiments, a semiconductor device package includes a substrate and a first antenna. The substrate has a first surface and a second surface opposite to the first surface. The first antenna is disposed on the first surface of the substrate. The first antenna has a dielectric layer and an antenna pattern. The dielectric layer has a first surface facing away from the substrate, a second surface opposite to and spaced apart from the first surface of the substrate, and a third surface in contact with the first surface of the substrate. The antenna pattern is disposed within the dielectric layer and exposed from the first surface and the second surface of the dielectric layer.

[0005] In one or more embodiments, a method of manufacturing a semiconductor device package includes (a) providing a carrier; (b) forming an antenna layer on the carrier; (c) forming a first dielectric layer on the carrier to cover the antenna layer and expose an upper surface of the antenna layer; and (d) forming a second dielectric layer on the first dielectric layer and adjacent to the periphery of the first dielectric layer to expose the antenna layer. Attached Figure Description

[0006] The aspects of this disclosure will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 1B A perspective view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0009] Figure 1C A cross-sectional view illustrating an antenna structure according to some embodiments of the present disclosure.

[0010] Figure 1D A cross-sectional view illustrating an antenna structure according to some embodiments of the present disclosure.

[0011] Figure 1E A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0012] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0013] Figure 2B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0014] Figure 2C A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0015] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K and Figure 3L This is a cross-sectional view of an antenna structure manufactured at various stages according to some embodiments of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4K '、 Figure 4L , Figure 4M and Figure 4N This is a cross-sectional view of an antenna structure manufactured at various stages according to some embodiments of the present disclosure.

[0017] Common reference numerals are used throughout the accompanying drawings and embodiments to indicate the same or similar elements. This disclosure will become more apparent from the following embodiments in conjunction with the accompanying drawings. Detailed Implementation

[0018] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific instances and arrangements of components are described below. Of course, these components and arrangements are merely examples and are not intended to be limiting. In this disclosure, references to a first feature being formed on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0020] Figure 1A This illustration shows a cross-sectional view of a semiconductor device package 1A according to some embodiments of the present disclosure. The semiconductor device package 1A includes a substrate 10, a support structure 11, an antenna 12, electronic components 14, and electrical contacts 15.

[0021] For example, substrate 10 may be a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. Substrate 10 may include opposing surfaces 101 and 102 (e.g., an upper surface and a lower surface). Substrate 10 may include interconnect structures (e.g., electrical connections), such as a redistribution layer (RDL). Substrate 10 may include metal layers 10c1 and 10c2 on its surfaces 101 and 102, respectively. In some embodiments, metal layer 10c1 is a ground layer.

[0022] A support structure 11 is disposed on the surface 101 of the substrate 10. For example, the support structure 11 is connected to the surface 101 of the substrate 10 via a connecting element 10a. In some embodiments, the support structure 11 is formed of or contains a dielectric material. For example, the support structure 11 may comprise a molding compound, prepreg composite fibers (e.g., a prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins containing fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets.

[0023] Antenna 12 is mounted on support structure 11. Antenna 12 is spaced from surface 101 of substrate 10. For example, a gap exists between antenna 12 and substrate 10. Antenna 12 includes dielectric layer 12d and antenna pattern 12a. Antenna pattern 12p is embedded in dielectric layer 12d and exposed from surfaces 12d1 and 12d2 of dielectric layer 12d. For example, surface 12p1 of antenna pattern 12p is substantially coplanar with surface 12d1 of dielectric layer 12d, and surface 12p2 of antenna pattern 12p is substantially coplanar with surface 12d2 of dielectric layer 12d. For example, the thickness of antenna pattern 12p is substantially the same as the thickness of dielectric layer 12d. For example, surfaces 12p1 and 12p2 of antenna pattern 12a are exposed to air. For example, surfaces 12p1 and 12p2 of antenna pattern 12a are in direct contact with air. In some embodiments, the semiconductor device package 1A is disposed within a vacuum space or vacuum cavity, and thus the surfaces 12p1 and 12p2 of the antenna pattern 12a are exposed to the vacuum. In some embodiments, the antenna pattern 12p is or comprises a conductive material, such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0024] Antenna pattern 12p can be electrically connected to metal layer 10c1 via connection structure 12f. In some embodiments, connection structure 12f can act as a feed element to provide a signal to antenna pattern 12p. In some embodiments, connection structure 12f connects antenna pattern 12p to ground via metal layer 10c1. In some embodiments, connection structure 12f may include, but is not limited to, solder balls, metal pillars, bonding wires, or stacked vias. In some embodiments, connection structure 12f comprises Au, Ag, Al, Cu, or alloys thereof. In some embodiments, connection structure 12f is omitted, and metal layer 10c1 can be electromagnetically coupled to antenna pattern 12p. In some embodiments, metal layer 10c1 and antenna 12 can be referred to as antenna structure.

[0025] In some embodiments, the antenna pattern 12p can be as follows: Figure 1A The diagram shows a uniform width. In some embodiments, such as... Figure 1C and Figure 1D As shown in the cross-sectional view of antenna 12 according to some embodiments of this disclosure, antenna pattern 12p includes a non-uniform width. For example, as... Figure 1C As shown, the width of surface 12p1 of antenna pattern 12p is greater than the width of surface 12p2 of antenna pattern 12p. For example, as... Figure 1D As shown, the width of the antenna pattern 12p between surface 12p1 and surface 12p2 is greater than the width of surface 12p1 or 12p2 of the antenna pattern 12p.

[0026] A dielectric layer 12d is disposed on a support structure 11. In some embodiments, the dielectric layer 12d is in direct contact with the support structure 11. In some embodiments, the dielectric layer 12d has a lateral surface 12d3 exposed to air. In some embodiments, the lateral surface 12d3 of the dielectric layer 12d is exposed to the exterior of the semiconductor device package 1A. In some embodiments, the lateral surface 12d3 of the dielectric layer 12d is substantially coplanar with the lateral surface 113 of the support structure 11. In some embodiments, the dielectric layer 12d may comprise a molding compound, a prepreg composite fiber (e.g., a prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins containing fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets. In some embodiments, the dielectric layer 12d and the support structure 11 are formed of or comprise the same material. For example, both the dielectric layer 12d and the support structure 11 are formed of a molding compound. Alternatively, the dielectric layer 12d and the support structure 11 are formed of different materials. In some embodiments, the antenna 12 and the support structure 11 may be collectively referred to as an antenna structure.

[0027] In some embodiments, such as Figure 1A and Figure 1B (The explanation is as follows) Figure 1A As shown in the perspective view of the semiconductor device package 1A, the substrate 10, support structure 11, and antenna 12 define an air gap. For example, there is no dielectric material between the antenna 12 and the metal layer 10c1. Therefore, RF signals are transmitted or received by the antenna 12 via air. Since the Df / Dk (i.e., 0 / 1) of air is lower than that of any dielectric material, the signal attenuation or loss of the RF signal can be reduced, which will improve the performance of the antenna 12 (e.g., more preferably 1.3 to 2.3 times). In addition, since the antenna pattern 12p is not required to be connected to the dielectric layer in a direction perpendicular to the surfaces 12p1 or 12p2 of the antenna pattern 12p, the surfaces 12p1 and 12p2 of the antenna pattern 12p are relatively smooth (e.g., no roughness is required on the surfaces 12p1 and 12p2 of the antenna pattern 12p), which will improve the performance of the antenna 12.

[0028] Return to reference Figure 1A Electronic component 14 is disposed on surface 102 of substrate 10 and electrically connected to substrate 10 via, for example, flip-chip or wire bonding technology. Electronic component 14 may be a chip or die, comprising a semiconductor substrate, one or more integrated circuit devices, and one or more overlay interconnect structures thereon. Integrated circuit devices may comprise active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof.

[0029] Electrical contact 15 is disposed on surface 102 of substrate 10 and electrically connected to metal layer 10c2 exposed from protective layer 10s (e.g., solder mask or solder resist). In some embodiments, electrical contact 15 is a solder ball. In other embodiments, electrical contact 15 may be a copper pillar or any other suitable electrical contact.

[0030] Figure 1E This illustration shows a cross-sectional view of a semiconductor device package 1E according to some embodiments of the present disclosure. The semiconductor device package 1E is similar to... Figure 1A The semiconductor device package 1A shown is described below, and the differences therebetween are described in detail below.

[0031] The antenna 12 further includes a conductive layer 12p disposed within the dielectric layer 12d. The support structure 11 includes a through-hole 11v penetrating the support structure 11 and electrically connecting the conductive layer 12p to the substrate 10 (e.g., to the connection element 10a). In some embodiments, the through-hole 11v comprises Au, Ag, Al, Cu, or an alloy thereof. The through-hole 11v may enhance the strength of the support structure 11.

[0032] Figure 2AThis illustration shows a cross-sectional view of a semiconductor device package 2A according to some embodiments of the present disclosure. Except that the semiconductor device package 2A further includes an antenna structure (including support structure 21 and antenna 22) disposed on antenna 12, the semiconductor device package 2A is similar to... Figure 1A The semiconductor device package 1A shown is illustrated.

[0033] A support structure 21 is disposed on the surface 12d1 of the dielectric layer 12d. In some embodiments, the support structure 21 is formed of or contains a dielectric material. For example, the support structure 21 may comprise a molding compound, a prepreg composite fiber (e.g., a prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins containing fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets.

[0034] Antenna 22 is mounted on support structure 21. Antenna 22 is spaced from antenna 12 via support structure 21. For example, there is a gap between antenna 12 and antenna 22. Antenna 22 includes dielectric layer 22d and antenna pattern 22a. Antenna pattern 22p is embedded in dielectric layer 22d and exposed from surfaces 22d1 and 22d2 of dielectric layer 22d. For example, surface 22p1 of antenna pattern 22p is substantially coplanar with surface 22d1 of dielectric layer 22d, and surface 22p2 of antenna pattern 22p is substantially coplanar with surface 22d2 of dielectric layer 22d. For example, the thickness of antenna pattern 22p is substantially the same as the thickness of dielectric layer 22d. For example, surfaces 22p1 and 22p2 of antenna pattern 22a are exposed to air. For example, surfaces 22p1 and 22p2 of antenna pattern 22a are in direct contact with air. In some embodiments, the semiconductor device package 2A is disposed within a vacuum space or vacuum cavity, and thus the surfaces 22p1 and 22p2 of the antenna pattern 22a are exposed to the vacuum. In some embodiments, the antenna pattern 22p is or comprises a conductive material, such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Al, Cu, or alloys thereof.

[0035] Antenna pattern 22p is substantially aligned with antenna pattern 11p. Antenna pattern 22p is electromagnetically coupled to antenna pattern 12p. In some embodiments, antenna pattern 22p can be as follows: Figure 2A , Figure 2B as well as Figure 2C The diagram shows a uniform width. In some embodiments, depending on different design requirements, the antenna pattern 22p may include, as shown below. Figure 1C or Figure 1D The shape shown.

[0036] A dielectric layer 22d is disposed on a support structure 21. In some embodiments, the dielectric layer 22d is in direct contact with the support structure 21. In some embodiments, the dielectric layer 22d has a lateral surface 22d3 exposed to air. In some embodiments, the lateral surface 22d3 of the dielectric layer 22d is exposed to the exterior of the semiconductor device package 2A. In some embodiments, the lateral surface 22d3 of the dielectric layer 22d is substantially coplanar with the lateral surface 12d3 of the dielectric layer 12d and the lateral surface 213 of the support structure 21. In some embodiments, the dielectric layer 22d may comprise a molding compound, a prepreg composite fiber (e.g., a prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins containing fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets. In some embodiments, the dielectric layer 22d and the support structure 21 are formed of or comprise the same material. For example, both the dielectric layer 22d and the support structure 21 are formed of a molding compound. Alternatively, the dielectric layer 22d and the support structure 21 are formed of different materials.

[0037] Figure 2B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 2B Semiconductor device packaging in the context of semiconductors is similar to... Figure 2A The semiconductor device package 2A shown is described below, and the differences therebetween are described in detail below.

[0038] Antenna 22 further includes a conductive layer 22p disposed within dielectric layer 22d. Support structure 21 includes a through-hole 21v penetrating support structure 21 and electrically connecting conductive layer 22p to conductive layer 12p. In some embodiments, through-hole 21v comprises Au, Ag, Al, Cu, or an alloy thereof. Through-hole 21v may enhance the strength of support structure 21.

[0039] Figure 2C A cross-sectional view of a semiconductor device package according to some embodiments of this disclosure is shown. (Except for...) Figure 2C The antenna 22 further includes a dielectric layer 22d that penetrates the antenna 22 to expose the opening 22h of the antenna 12. Figure 2C Semiconductor device packaging in the context of semiconductors is similar to... Figure 2A The semiconductor device package 2A shown is illustrated. In some embodiments, the opening 22h is positioned adjacent to the periphery of the antenna 22.

[0040] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F, Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K and Figure 3L The figures are cross-sectional views of antenna structures manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for a preferred understanding of aspects of the present disclosure. Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K and Figure 3L The operation shown is a method for manufacturing an antenna structure including a support structure 11 and an antenna 12. Alternatively, Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K and Figure 3L The operation shown is a method for manufacturing other antenna structures.

[0041] refer to Figure 3A A carrier 39 is provided. The carrier 39 may be a metal plate, such as a copper plate. In some embodiments, the carrier 39 has seed layers 39s disposed on its two surfaces. A patterned photoresist 39a (e.g., a mask) is disposed on the carrier 39.

[0042] refer to Figure 3B Antenna pattern 12p is formed on carrier 39. In some embodiments, antenna pattern 12p is formed by, for example, sputtering, coating, electroplating or any other suitable operation. In some embodiments, a portion of antenna pattern 12p (e.g., the portion enclosed by dotted circle 12m1) may be used as an alignment mark.

[0043] refer to Figure 3C Photoresist 39a is removed from carrier 39. Then, as follows... Figure 3D The diagram shows a dielectric layer 12d' formed on the antenna pattern 12p to completely cover the antenna pattern 12p. For example, the dielectric layer 12d' is formed on the outer surface of the antenna pattern 12p and within the gap defined by the antenna pattern 12p.

[0044] refer to Figure 3EA portion of dielectric layer 12d' is removed to form dielectric layer 12d, thereby exposing the upper surface of antenna pattern 12p. In some embodiments, the upper surface of antenna pattern 12p is substantially coplanar with the upper surface of dielectric layer 12d. In some embodiments, the upper surface of antenna pattern 12p is recessed from the upper surface of dielectric layer 12d. In some embodiments, the upper surface of antenna pattern 12p protrudes beyond the upper surface of dielectric layer 12d. In some embodiments, a portion of dielectric layer 12d' is removed by, for example, etching, polishing, laser treatment, or any other suitable operation.

[0045] refer to Figure 3F A photoresist 39b (e.g., a dry film) is disposed on the antenna pattern 12p and the dielectric layer 12d to cover the antenna pattern 12p and the dielectric layer 12d. Subsequently, as... Figure 3G The photoresist 39 is shown to be removed to form photoresist 39b'.

[0046] refer to Figure 3H A protective layer 11' (e.g., a dielectric layer) is formed to cover the photoresist 39' and a portion of the dielectric layer 12d exposed from the photoresist 39'. Subsequently, as... Figure 3I The protective layer 11' shown is removed, for example, by grinding, to form the support structure 11.

[0047] refer to Figure 3J Remove the carrier 39. In some embodiments, the seed layer 39s may remain on the dielectric layer 12d and the antenna pattern 12p. Subsequently, as follows Figure 3K The seed layer 39s is removed by, for example, etching or any other suitable process.

[0048] refer to Figure 3L The photoresist 39' is removed by, for example, development or any other suitable process to form a shape such as Figure 1A The antenna structure shown includes a support structure 11 and an antenna 12.

[0049] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M and Figure 4N These are cross-sectional views of antenna structures manufactured at various stages according to some embodiments of the present disclosure. The various figures have been simplified for a preferred understanding of aspects of the present disclosure. In some embodiments, Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M and Figure 4N The operation shown is for manufacturing such as Figure 2C The method shown includes an antenna structure comprising support structures 11 and 21 and antennas 12 and 22. Alternatively, Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M and Figure 4N The operation shown is a method for manufacturing other antenna structures.

[0050] In some embodiments, Figure 4A Operations in Figure 3I This will be implemented after the operation. (See reference) Figure 4A Remove the carrier 39 containing the seed layer 39s.

[0051] refer to Figure 4B Photoresist 39c (e.g., dry film) is formed on the dielectric layer 12d and the surface of the antenna pattern 12p opposite to the photoresist 39b'.

[0052] refer to Figure 4C A portion of photoresist 39c is removed to form photoresist 39c'. In some embodiments, photoresist 39c' is substantially aligned with photoresist 39b'.

[0053] refer to Figure 4D A seed layer 12s is formed on the exposed portions of the photoresist 39c' and the antenna pattern 12p, and on the dielectric layer 12d. Subsequently, as... Figure 4E The photoresist 39d is formed on the seed layer 12s, as shown in the figure.

[0054] refer to Figure 4F A portion of the photoresist 39d is removed to form an opening 39dh, thereby exposing the seed layer for 12s. Subsequently, as... Figure 4G As shown, a metal layer 22p' is formed within the opening 39dh to contact the seed layer 12s.

[0055] refer to Figure 4H and Figure 4I ,like Figure 4I The image shows the removal of a portion of the photoresist 39d, the seed layer 12s, and the metal layer 22p' to form the antenna pattern 22p.

[0056] refer to Figure 4J A photoresist 39e (e.g., a dry film) is formed to cover the dielectric layer 12d, the antenna pattern 12p, the photoresist 39c', and the antenna pattern 22p. In some embodiments, the photoresist 39e and photoresistors 39b', 39c' comprise different types of photoresist. For example, if photoresist 39e is a positive photoresist, then photoresistors 39b' and 39c' are negative photoresistors, and vice versa.

[0057] refer to Figure 4K A portion of photoresist 39e is removed to form photoresist 39e'. For example... Figure 4K and Figure 4K As shown in the figure, photoresist 39e' is positioned adjacent to the edge of photoresist 39c'.

[0058] refer to Figure 4L A protective layer (e.g., a dielectric layer) 22' is formed to cover the dielectric layer 12d, the antenna pattern 12p, the photoresist 39c', the antenna pattern 22p, and the photoresist 39e'.

[0059] refer to Figure 4M A portion of the protective layer 22' is removed to form a support structure and expose the antenna pattern 22p.

[0060] refer to Figure 4N The photoresist 39b', 39c', and 39e' are removed by, for example, development or any other suitable process to form a shape such as Figure 2C The antenna structure shown includes support structures 11 and 21 and antennas 12 and 22.

[0061] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” “right,” and the like are used to describe the relationship of one element or feature to other elements or features illustrated in the diagrams. In addition to the orientations depicted in the diagrams, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intervening elements.

[0062] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation clearly occurred or instances where the event or situation is very close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “generally coplanar” may refer to two surfaces that lie within a few micrometers (μm) along the same plane (e.g., within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane). When referring to a value or characteristic as “generally” the same, the term may mean that the value is within ±10%, ±5%, ±1%, or ±0.5% of the average of the values.

[0063] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation has clearly occurred or instances where the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values ​​can be considered “generally” or “about” the same. For example, "generally parallel" can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "generally perpendicular" can refer to a variation of ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0064] For example, if the displacement between two surfaces is equal to or less than 5 µm, equal to or less than 2 µm, equal to or less than 1 µm, or equal to or less than 0.5 µm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between any two points on a surface relative to the flat surface is equal to or less than 5 µm, equal to or less than 2 µm, equal to or less than 1 µm, or equal to or less than 0.5 µm, then the surface can be considered planar or substantially planar.

[0065] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are generally those that exhibit minimal or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material has a conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0066] Unless the context clearly specifies otherwise, the singular terms “a” and “described” as used herein may include multiple indicators. In the description of some embodiments, a component disposed “on” or “above” another component may cover situations where the former component is directly on the latter component (e.g., in physical contact with it), and situations where one or more intervening components are located between the former component and the latter component.

[0067] Unless otherwise specified, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” and “below” refer to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangement.

[0068] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between artistic representations in this disclosure and actual devices due to variables in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and accompanying drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

[0069] The foregoing summarizes several embodiments and detailed features of this disclosure. The embodiments described in this disclosure can be readily used as the basis for designing or modifying other programs and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor packaging apparatus, comprising: A substrate having a first surface and a second surface opposite to the first surface; A support structure disposed on the first surface of the substrate; A first antenna, mounted on the support structure, has a first surface facing the substrate, a second surface opposite the first surface, and a lateral surface extending between the first and second surfaces of the first antenna, wherein the lateral surface of the first antenna is exposed to the outside of the semiconductor packaging device. The first antenna includes a dielectric layer and an antenna pattern disposed within and penetrating the dielectric layer; as well as A metal layer disposed on the first surface of the substrate and electrically connected to the antenna pattern via a connection structure; An electronic component disposed on and electrically connected to the second surface of the substrate, wherein the semiconductor packaging device is disposed within a vacuum space, and the top and bottom surfaces of the antenna pattern of the first antenna are exposed to the vacuum.

2. The semiconductor packaging apparatus according to claim 1, wherein... The dielectric layer of the first antenna has a first surface facing away from the substrate and a second surface opposite to the first surface; The first surface of the dielectric layer is substantially coplanar with the top surface of the antenna pattern; and The second surface of the dielectric layer is substantially coplanar with the bottom surface of the antenna pattern, and the first and second surfaces of the dielectric layer are exposed to a vacuum.

3. The semiconductor packaging apparatus according to claim 1, further comprising: A conductive layer disposed within the dielectric layer of the first antenna; and A conductive via is disposed within the support structure and electrically connects the conductive layer to the substrate.

4. The semiconductor packaging apparatus of claim 1, wherein the metal layer is disposed in a vacuum cavity defined by the substrate and the first antenna.

5. The semiconductor packaging apparatus of claim 1, further comprising a second antenna disposed on the first antenna, wherein the second antenna comprises: A supporting structure, which is mounted on the first antenna; A dielectric layer disposed on the support structure of the second antenna; and An antenna pattern disposed within and penetrating the dielectric layer of the second antenna.

6. The semiconductor packaging apparatus of claim 1, further comprising a connection structure that directly contacts the first antenna and the metal layer.

7. The semiconductor packaging apparatus of claim 6, wherein the connection structure is disposed in a vacuum cavity defined by the substrate, the support structure and the first antenna.

8. The semiconductor packaging apparatus of claim 1, wherein the support structure has a lateral surface that is substantially coplanar with the lateral surface of the first antenna.

9. A semiconductor packaging apparatus, comprising: A substrate having a first surface and a second surface opposite to the first surface; A first antenna is disposed on the first surface of the substrate. The first antenna has a dielectric layer and an antenna pattern. The dielectric layer has a first surface facing away from the substrate and a second surface opposite to and spaced apart from the first surface of the substrate. The antenna pattern is disposed within the dielectric layer and exposed from the first and second surfaces of the dielectric layer; as well as A metal layer disposed on the first surface of the substrate and electrically connected to the antenna pattern via a connection structure; An electronic component disposed on and electrically connected to the second surface of the substrate, wherein the semiconductor packaging device is disposed within a vacuum space, and the top and bottom surfaces of the antenna pattern of the first antenna are exposed to the vacuum.

10. The semiconductor packaging apparatus of claim 9, wherein the first surface of the substrate and the first antenna define a vacuum cavity.

11. The semiconductor packaging apparatus according to claim 9, wherein The first surface of the dielectric layer is substantially coplanar with the top surface of the antenna pattern; and The second surface of the dielectric layer is substantially coplanar with the bottom surface of the antenna pattern.

12. The semiconductor packaging apparatus of claim 9, further comprising a second antenna disposed on the first antenna, the second antenna having a first surface facing away from the first antenna, a second surface facing the first antenna and spaced apart from the first antenna, and a third surface in contact with the first surface of the first antenna, wherein the antenna pattern of the second antenna is disposed within the dielectric layer of the second antenna and exposed from the first surface and the second surface of the dielectric layer of the second antenna.

13. The semiconductor packaging apparatus of claim 12, wherein the antenna pattern of the first antenna is substantially aligned with the antenna pattern of the second antenna.

14. A method for manufacturing a semiconductor packaging device, comprising: (a) Provide a carrier; (b) Forming an antenna layer on the carrier; (c) A first dielectric layer is formed on the carrier to cover the antenna layer and expose the upper surface of the antenna layer; and (d) A second dielectric layer is formed on and adjacent to the periphery of the first dielectric layer to expose the antenna layer; The method further includes: A metal layer is formed on the upper surface of the carrier, which is electrically connected to the antenna pattern of the antenna layer via a connection structure; as well as Electronic components are disposed on and electrically connected to the lower surface of the carrier, wherein the semiconductor packaging device is disposed in a vacuum space, and the top and bottom surfaces of the antenna pattern of the antenna layer are exposed to the vacuum.

15. The method of claim 14, wherein operation (c) further comprises: The first dielectric layer is formed on the carrier to completely cover the antenna layer; and The first dielectric layer is thinned to expose the upper surface of the antenna layer.

16. The method of claim 14, wherein operation (d) further comprises: A first sacrificial layer is formed on the upper surface of the antenna layer exposed from the first dielectric layer; A second dielectric layer is formed on a portion of the dielectric layer exposed from the first sacrificial layer; and Remove the first sacrificial layer to expose the upper surface of the antenna layer.

17. The method of claim 14, wherein the antenna pattern comprises a first antenna pattern and a second antenna pattern.

18. The method of claim 17, wherein the projection of the second dielectric layer onto the carrier is spaced apart from the projection of the first antenna pattern onto the carrier.

19. The method of claim 17, further comprising: Remove the carrier to expose the lower surface of the first antenna pattern opposite to the upper surface of the antenna pattern and the surface of the first dielectric layer that is substantially coplanar with the lower surface of the first antenna pattern; A second sacrificial layer is formed on the lower surface of the first antenna; and A second antenna pattern is formed on the second sacrificial layer. The second antenna pattern is substantially aligned with the first antenna pattern.

20. The method of claim 19, further comprising: A third dielectric layer is formed on the surface of the first dielectric layer, the third dielectric layer covering a first portion of the lateral surface of the second sacrificial layer and exposing a second portion of the lateral surface of the second sacrificial layer and the surface of the second antenna pattern facing away from the first antenna pattern; and The second sacrificial layer is removed to form a cavity between the first antenna pattern and the second antenna pattern.

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