Integrated Circuit Device

Abstract

An integrated circuit device is disclosed. The integrated circuit device according to the inventive concept includes: a lower wiring structure located on a substrate; an air gap disposed between the lower wiring structures; a capping layer covering an upper surface of the air gap; an etch stop layer conformally covering upper surfaces of the lower wiring structures and the capping layer and having a protruding and recessed structure; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer and connected to an upper surface of the lower wiring structure not covered by the etch stop layer, wherein the upper wiring structure covers a part of the upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structure.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0134103, filed on Oct. 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device including a multilayer wiring structure and a method of manufacturing the same. Background Art

[0003] With the rapid development of the electronics industry and in response to requests from users, electronic devices have been reduced in size and / or provided with various functions. Accordingly, the miniaturization of integrated circuit devices has also been rapidly progressing, and the line width and pitch of the multilayer wiring structures included in the integrated circuit devices are being reduced. Therefore, it is increasingly beneficial to develop an integrated circuit device having a multilayer wiring structure in which current leakage is reduced or suppressed and / or parasitic capacitance is reduced, thereby exhibiting improved electrical characteristics and / or reliability. Summary of the Invention

[0004] The inventive concept provides an integrated circuit device and a method of manufacturing the same having improved electrical characteristics and / or reliability by reducing or minimizing parasitic capacitance by forming an air gap around a wiring on which a via is located.

[0005] The inventive concept also provides an integrated circuit device and a method of manufacturing the same having improved electrical characteristics and / or reliability by reducing or preventing time-dependent dielectric breakdown (TDDB) that may occur in the integrated circuit device by reducing or suppressing current leakage in the multilayer wiring structure.

[0006] Problems to be solved by the inventive concept are not limited to the above problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following disclosure.

[0007] According to an aspect of the inventive concept, there is provided an integrated circuit device including: a lower wiring structure located on a substrate, the lower wiring structure including an air gap disposed between the lower wiring structures; a capping layer covering an upper surface of the air gap; an etch stop layer conformally covering an upper surface of the lower wiring structure and the capping layer and having a protruding and recessed structure; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer and connected to an upper surface of the lower wiring structure not covered by the etch stop layer, wherein the upper wiring structure covers a part of the upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structure.

[0008] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a lower wiring structure spaced apart in a first direction on an upper surface of a substrate, extending in a second direction perpendicular to the first direction, and flush with each other in a third direction perpendicular to the upper surface of the substrate, an air gap being located between the lower wiring structures and having a first width and a second width different from each other in the first direction; a capping layer covering an upper surface of the air gap and having the first width or the second width; an insulating barrier layer surrounding side surfaces and a lower surface of the air gap; an etch stop layer conformally covering an upper surface of the lower wiring structure, side surfaces of the insulating barrier layer, an upper surface of the insulating barrier layer, and an upper surface of the capping layer; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer and connected to an upper surface of the lower wiring structure not covered by the etch stop layer, wherein the first width of the air gap is less than a thickness of the capping layer in the third direction.

[0009] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a first lower wiring structure and a second lower wiring structure located on a substrate with an air gap therebetween; a capping layer covering an upper surface of the air gap; an insulating barrier layer surrounding side surfaces of the air gap; an etch stop layer conformally covering an upper surface of the second lower wiring structure, side surfaces of the insulating barrier layer, an upper surface of the insulating barrier layer, and an upper surface of the capping layer; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer, connected to an upper surface of the first lower wiring structure, and having a protrusion covering a part of the upper surface of the capping layer, wherein a shortest distance between the first lower wiring structure and the second lower wiring structure closest thereto is smaller than a shortest distance between the protrusion and the second lower wiring structure closest thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figures 1A to 1D is a view showing an integrated circuit device according to an embodiment of the inventive concept;

[0012] Figures 2 to 4 is a cross-sectional view showing an integrated circuit device according to an embodiment of the inventive concept;

[0013] Figure 5 is a flowchart showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0014] Figures 6A to 6L is a cross-sectional view showing the sequence of processes of a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept; and

[0015] Figure 7It is a configuration diagram of a system showing an integrated circuit device according to an embodiment of the inventive concept. Detailed Description

[0016] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0017] Figures 1A to 1D It is a diagram showing an integrated circuit device according to an embodiment of the inventive concept.

[0018] Specifically, Figure 1A It is a cross-sectional view of the integrated circuit device 10, Figure 1B is Figure 1A an enlarged cross-sectional view of region BB of Figure 1C is Figure 1A an enlarged cross-sectional view of region CC of Figure 1D is a cross-sectional view taken along line DD of Figure 1A the same.

[0019] Referring together to Figures 1A to 1D , the integrated circuit device 10 includes a lower wiring structure 120 formed on a substrate 100, an air gap AG disposed between the lower wiring structures 120, a capping layer 160 covering an upper surface of the air gap AG, an etch stop layer 170 having a protruding and recessed structure, an insulating layer 210 covering the etch stop layer 170, and / or an upper wiring structure 220 electrically connected to the lower wiring structure 120.

[0020] The substrate 100 may include a wafer containing silicon (Si). In some embodiments, the substrate 100 may include a wafer containing a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In addition, the substrate 100 may have a silicon-on-insulator (SOI) structure. In addition, the substrate 100 may have a device region, an active region, a field region, etc. including a transistor TR.

[0021] An interlayer dielectric 101 and a contact plug 102 penetrating the interlayer dielectric 101 may be formed on the substrate 100. In some embodiments, the interlayer dielectric 101 may include a silicon-based insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The contact plug 102 may be a conductive structure including a metal. The metal may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), etc. In some embodiments, the contact plug 102 may be electrically connected to an active region formed on the substrate 100. For example, the contact plug 102 may be connected to a source / drain region or a gate electrode of a transistor TR formed on the substrate 100.

[0022] The lower support layer 110 may be disposed on the upper surface of the substrate 100. The lower support layer 110 may include an insulating material. In addition, the lower support layer 110 may include a material having an etch selectivity different from that of the lower wiring structure 120. For example, the material of the lower support layer 110 may be one selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. However, the material of the lower support layer 110 is not limited thereto. In some embodiments, the contact plug 102 may penetrate the lower support layer 110 to be electrically connected to the lower wiring structure 120.

[0023] The lower wiring structure 120 may be disposed on the lower support layer 110. On the upper surface of the substrate 100, the lower wiring structures 120 may be spaced apart in a first direction (X direction), may extend in a second direction (Y direction) perpendicular to the first direction (X direction), and may be substantially flush with each other in a third direction (Z direction) perpendicular to the upper surface of the substrate 100. The lower wiring structures 120 may be spaced apart by an equal pitch 120P in the first direction (X direction). That is, the plurality of lower wiring structures 120 may have the same width 120W, and a plurality of air gaps AG corresponding to the gaps between adjacent lower wiring structures in the lower wiring structure 120 may be formed to have the same width AGW. However, the embodiments are not limited thereto.

[0024] The lower wiring structure 120 may be a conductive structure including a metal. For example, the lower wiring structure 120 may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or a combination thereof. The lower wiring structure 120 may be electrically connected to the contact plug 102, and the lower wiring structure 120 may be electrically connected to the upper wiring structure 220.

[0025] In some embodiments, the lower wiring structure 120 may include a first lower wiring structure 121 electrically connected to the upper wiring structure 220 and a second lower wiring structure 122 not electrically connected to the upper wiring structure 220. However, this division is merely for convenience, so the second lower wiring structure 122 may also be electrically connected to the upper wiring structure 220 in another region not shown in the drawings.

[0026] The air gap AG may be disposed between the lower wiring structures 120. The air gap AG may include air having a relatively low dielectric constant. That is, since the air gap AG including air having a relatively low dielectric constant is formed around the lower wiring structure 120, the parasitic capacitance between the lower wiring structures 120 may be reduced and / or the crosstalk between the lower wiring structures 120 may be reduced.

[0027] As the space occupied by the air gap AG increases, the parasitic capacitance and / or crosstalk between the lower wiring structures 120 can be further reduced. Thus, in some embodiments, the level of the upper surface AGS of the air gap AG can be substantially the same as the level of the upper surface 120S of the lower wiring structure 120.

[0028] The air gap AG can be arranged to be completely surrounded by an insulating material. That is, the air gap AG can be sealed to have a space completely independent of the lower wiring structure 120 by an insulating barrier layer 140 surrounding the side surface and the lower surface of the air gap AG and a cap layer 160 covering the upper surface AGS of the air gap AG. The insulating barrier layer 140 and the cap layer 160 can include different materials. Optionally, the insulating barrier layer 140 and the cap layer 160 can include substantially the same material, but can have different densities.

[0029] The upper surface AGS of the air gap AG is covered by the cap layer 160, and the upper surface 120S of the lower wiring structure 120 is not covered by the cap layer 160. In other words, the cap layer 160 can be selectively arranged only on the upper surface AGS of the air gap AG.

[0030] The insulating barrier layer 140 can be arranged to surround the side surface and the lower surface of the air gap AG. That is, the insulating barrier layer 140 can be conformally formed along the upper surface of the substrate 100, the side surface of the lower support layer 110, the side surface of the lower wiring structure 120, and the side surface of the cap layer 160. The insulating barrier layer 140 can not only separate the space in which the air gap AG is formed but also reduce or prevent the diffusion of the metal material included in the lower wiring structure 120 by being formed on the side surface of the lower wiring structure 120.

[0031] In some embodiments, the insulating barrier layer 140 can include a material selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In other embodiments, the insulating barrier layer 140 can include a material selected from high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), and tonen silicon nitride (TOSZ).

[0032] The cap layer 160 can be arranged to cover the upper surface AGS of the air gap AG. The cap layer 160 can include a first cap layer 161 that conformally covers a part of the side surface of the insulating barrier layer 140 and the upper surface AGS of the air gap AG and a second cap layer 163 that fills the space formed by the first cap layer 161.

[0033] The first capping layer 161 and the second capping layer 163 may include different materials. Optionally, the first capping layer 161 and the second capping layer 163 may include substantially the same materials, but may have different densities. Optionally, the first capping layer 161 and the second capping layer 163 may include the same materials, but may be formed using different methods.

[0034] In some embodiments, the capping layer 160 may include a material having a density that allows carbon (C) to pass through. This configuration is used to provide a space through which carbon (C), which is the main material of the second sacrificial layer 150 (see Figure 6D ), can be smoothly discharged during the process of removing the second sacrificial layer 150 (see Figure 6D ) to form the air gap AG.

[0035] The relationship between the capping layer 160 and the lower wiring structure 120 is described as follows. The lower wiring structure 120 may have a first thickness 120T, and the capping layer 160 may have a second thickness 160T that is smaller than the first thickness 120T. In addition, the level of the upper surface 120S of the lower wiring structure 120 may be lower than the level of the upper surface of the capping layer 160. That is, the lower wiring structure 120 and the capping layer 160 may be formed into a protruding and recessed structure having a height difference.

[0036] The etch stop layer 170 may be disposed to conformally cover the upper surface 120S of the lower wiring structure 120, the side surface of the capping layer 160, and the upper surface of the capping layer 160. That is, the etch stop layer 170 may be formed into a protruding and recessed structure. The etch stop layer 170 may include a material having an etch selectivity different from that of the insulating layer 210. In addition, the material of the etch stop layer 170 may have a dielectric constant greater than that of the material of the insulating layer 210. To meet such conditions, the material of the etch stop layer 170 may include a material containing aluminum (Al), for example, aluminum oxide (Al x O y ), aluminum nitride (Al x N y ), aluminum oxynitride (Al x O y N z ) or any one selected from zirconium oxide (Zr x O y ) and hafnium oxide (Hf x O y ). However, the material of the etch stop layer 170 is not limited thereto.

[0037] The insulating layer 210 may be disposed on the etch stop layer 170. The lower surface of the insulating layer 210 may be arranged to conformally cover the upper surface of the etch stop layer 170. That is, the lower surface of the insulating layer 210 may form a protruding and recessed structure having a phase opposite to that of the protruding and recessed structure formed by the etch stop layer 170.

[0038] In some embodiments, the insulating layer 210 may include a silicon-based insulating material. For example, the insulating layer 210 may include materials such as plasma enhanced oxide (PEOX), TEOS, boron TEOS (B-TEOS), phosphorus TEOS (P-TEOS), boron phosphorus TESO (BP-TEOS), BSG, PSG, BPSG, etc. In other embodiments, the insulating layer 210 may include a dielectric layer having a low dielectric constant from about 2.2 to about 3.0, such as a SiOC layer or a SiCOH layer. However, the material of the insulating layer 210 is not limited thereto. The insulating layer 210 and the capping layer 160 may include different materials, or include the same material but have different densities.

[0039] The upper wiring structure 220 may penetrate the insulating layer 210 to electrically connect to the lower wiring structure 120. The upper wiring structure 220 may include a metal layer 223 and a conduction barrier layer 221 surrounding the metal layer 223. The metal layer 223 may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or a combination thereof. In addition, the conduction barrier layer 221 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof. The capping layer 160 and the etch stop layer 170 may not be formed on the upper surface 120S of the lower wiring structure 120 connected to the upper wiring structure 220.

[0040] In some embodiments, the upper wiring structure 220 may include an upper structure and a lower structure. The upper structure may be a wiring (not shown) extending in a direction perpendicular to the lower wiring structure 120, and the lower structure may be a via disposed at a position where the wiring intersects the lower wiring structure 120. For convenience, only the lower structure (e.g., via) of the upper wiring structure 220 is shown in the drawings. That is, the lower wiring structure 120 may correspond to the first layer of metal wiring (the first layer of an integrated circuit), the upper structure may correspond to the second layer of metal wiring (the second layer of an integrated circuit), and the lower structure may correspond to a conductive via that electrically connects the first layer of metal wiring and the second layer of metal wiring.

[0041] In some embodiments, the upper wiring structure 220 may be formed as a stepped structure including a portion of the upper surface of the contact capping layer 160, side surfaces of the etch stop layer 170, and protrusions 225 on the upper surface of the insulating barrier layer 140. Further, in a cross-sectional view, a plurality of etch stop layers 170 may be provided such that the etch stop layers 170 are spaced apart from the upper wiring structure 220 located therebetween, and side surfaces of the upper wiring structure 220 are respectively in contact with side surfaces of adjacent etch stop layers 170.

[0042] The relationship between the upper wiring structure 220 and the lower wiring structure 120 will be described below. The shortest distance between the first lower wiring structure 121 and the second lower wiring structure 122 closest thereto is defined as the first shortest distance MMX. Further, the shortest distance between the protrusion 225 where the upper wiring structure 220 covers the upper surface of the capping layer 160 and the second lower wiring structure 122 closest thereto is defined as the second shortest distance VMX. In this case, the first shortest distance MMX may be less than the second shortest distance VMX. This may be caused by a design in which the width of the air gap AG in the first direction (X direction) is less than the thickness 160T of the capping layer 160 in the third direction (Z direction).

[0043] Generally, for an integrated circuit device including ultra-miniature devices, when performing a lithography process, process margins of the lower wiring structure and the upper wiring structure are reduced, which may make it difficult to ensure reliability. To solve this problem, a fully aligned via (FAV) process has been proposed. The FAV process requires a process of forming a protruding and recessed structure by relatively recessing the upper surface of the lower wiring structure with respect to the peripheral structure and a process of forming an etch stop layer on the formed protruding and recessed structure. These processes make it more difficult to form an air gap between adjacent lower wiring structures of the lower wiring structure.

[0044] To solve this problem, by forming the air gap AG using a sacrificial layer and forming the capping layer 160 having a predetermined (or optionally, desired) thickness or greater thickness on the upper surface AGS of the air gap AG, the integrated circuit device 10 according to the inventive concept may allow the FAV process to be relatively easily used while forming the air gap AG between the lower wiring structures 120. Accordingly, the integrated circuit device 10 may have one or more of the following advantages.

[0045] Since the air gap AG including air having a low dielectric constant is formed between the lower wiring structures 120, the parasitic capacitance between the lower wiring structures 120 may be reduced and / or crosstalk between the lower wiring structures 120 may be reduced. Additionally, since the air gap AG is also formed around the first lower wiring structure 121 on which the via is located, the reduction amount of the parasitic capacitance may be increased or maximized.

[0046] Next, since current leakage in the multilayer wiring structure can be suppressed by the capping layer 160, time-dependent dielectric breakdown (TDDB) of the integrated circuit device 10 can be reduced or prevented. In addition, when the line width and pitch of the lower wiring structure 120 are scaled down, the capping layer 160 is formed thick enough to ensure a predetermined (or optionally, desired) separation distance between the upper wiring structure 220 and the lower wiring structure 120. That is, when performing a photolithography process for forming the upper wiring structure 220, even if an accidental misalignment occurs due to insufficient process margin, the possibility of a short circuit occurring between the upper wiring structure 220 and the adjacent lower wiring structure 120 can be significantly reduced.

[0047] As a result, the integrated circuit device 10 according to the inventive concept can have improved electrical characteristics and / or reliability.

[0048] Figures 2 to 4 is a cross-sectional view showing an integrated circuit device according to an embodiment of the inventive concept.

[0049] Most of the components of the integrated circuit devices 20, 30, and 40 described below, as well as the materials of the components, are substantially the same as or similar to those described above with reference to Figures 1A to 1D Therefore, for convenience, the following description focuses on the differences between the above-described integrated circuit device 10 (see Figure 1A ) and the integrated circuit devices 20, 30, and 40.

[0050] Referring to Figure 2 , the integrated circuit device 20 includes a lower wiring structure 120 formed on a substrate 100 and having different pitches, an air gap AG disposed between the lower wiring structures 120 and having different widths, a capping layer 160 covering the upper surface of the air gap AG and having different widths, an etch stop layer 170 having a protruding and recessed structure, an insulating layer 210 covering the etch stop layer 170, and an upper wiring structure 220 electrically connected to the lower wiring structure 120.

[0051] The lower wiring structure 120 may be disposed on the lower support layer 110. On the upper surface of the substrate 100, the lower wiring structures 120 may be spaced apart in a first direction (X direction), may extend in a second direction (Y direction) perpendicular to the first direction (X direction), and may be substantially flush with each other in a third direction (Z direction) perpendicular to the upper surface of the substrate 100. The lower wiring structures 120 may be spaced apart by a first pitch 120P1 or a second pitch 120P2 in the first direction (X direction). The second pitch 120P2 may be larger than the first pitch 120P1. That is, the plurality of lower wiring structures 120 may have the same width 120W, and a plurality of air gaps AG corresponding to the gaps between adjacent lower wiring structures in the lower wiring structures 120 may be formed to have a first width AG1W or a second width AG2W different from each other. However, the embodiments are not limited thereto.

[0052] As the space occupied by the air gap AG increases, the parasitic capacitance and crosstalk between the lower wiring structures 120 may be further reduced. Accordingly, the air gap AG may include a first air gap AG1 having a first width AG1W and a second air gap AG2 having a second width AG2W larger than the first width AG1W. The air gap AG may have a rectangular cross section.

[0053] The cover layer 160 may be disposed to cover the upper surface AGS of the air gap AG. The cover layer 160 may include a first cover layer 161 that conformally covers a part of the side surface of the insulating barrier layer 140 and the upper surface AGS of the air gap AG and a second cover layer 163 that fills the first cover layer 161. The cover layer 160 may have a width substantially the same as the width of the air gap AG. That is, the width of the cover layer 160 covering the upper surface AGS of the first air gap AG1 may be the same as the first width AG1W of the first air gap AG1, and the width of the cover layer 160 covering the upper surface AGS of the second air gap AG2 may be the same as the second width AG2W of the second air gap AG2.

[0054] As a result, since the air gap AG may also be formed between the lower wiring structures 120 having different pitches (a plurality of pitches) in the integrated circuit device 20 according to the inventive concept, the integrated circuit device 20 may have improved electrical characteristics and / or reliability.

[0055] Referring to Figure 3 , the integrated circuit device 30 includes a lower wiring structure 120 formed on a substrate 100, an air gap AG3 disposed between the lower wiring structures 120 and having an upper surface AGS lower than the upper surface 120S of the lower wiring structure 120, a cover layer 160 covering the upper surface AGS of the air gap AG3, an etch stop layer 170 having a protruding and recessed structure, an insulating layer 210 covering the etch stop layer 170, and an upper wiring structure 220 electrically connected to the lower wiring structure 120.

[0056] The air gap AG3 may be disposed between the lower wiring structures 120. Since the air gap AG3 including air having a low dielectric constant is formed around the lower wiring structures 120, the parasitic capacitance between the lower wiring structures 120 can be reduced and / or the crosstalk between the lower wiring structures 120 can be reduced.

[0057] As the space occupied by the air gap AG3 increases, the parasitic capacitance and crosstalk between the lower wiring structures 120 can be further reduced. However, in this case, since the structural stability may be reduced, the space occupied by the air gap AG3 can be adjusted in consideration of the relationship with other components. Therefore, in some embodiments, the level of the upper surface AGS of the air gap AG3 may be formed lower than the level of the upper surface 120S of the lower wiring structure 120. The air gap AG3 may have a rectangular cross section.

[0058] The relationship between the capping layer 160 and the lower wiring structure 120 is described as follows. The level of the upper surface 120S of the lower wiring structure 120 may be lower than the level of the upper surface of the capping layer 160. In addition, the level of the upper surface 120S of the lower wiring structure 120 may be higher than the level of the lower surface of the capping layer 160. That is, the side surfaces of the lower wiring structure 120 and the side surfaces of the capping layer 160 may have regions facing each other.

[0059] As a result, since the air gap AG3 having structural stability can be formed between the lower wiring structures 120 in the integrated circuit device 30 according to the inventive concept, the integrated circuit device 30 can have improved electrical characteristics and / or reliability.

[0060] Referring to Figure 4 , the integrated circuit device 40 includes a lower wiring structure 120 formed on a substrate 100, an air gap AG4 disposed between the lower wiring structures 120 and having an upper surface AGS higher than the upper surface 120S of the lower wiring structure 120, a capping layer 160 covering the upper surface AGS of the air gap AG4, an etch stop layer 170 having a protruding and recessed structure, an insulating layer 210 covering the etch stop layer 170, and an upper wiring structure 220 electrically connected to the lower wiring structure 120.

[0061] The air gap AG4 may be disposed between the lower wiring structures 120. Since the air gap AG4 including air having a relatively low dielectric constant is formed around the lower wiring structures 120, the parasitic capacitance between the lower wiring structures 120 can be reduced and / or the crosstalk between the lower wiring structures 120 can be reduced.

[0062] As the space occupied by the air gap AG4 increases, the parasitic capacitance and crosstalk between the lower wiring structures 120 can be further reduced. Accordingly, in some embodiments, the level of the upper surface AGS of the air gap AG4 can be formed higher than the level of the upper surface 120S of the lower wiring structure 120. The air gap AG4 can have a rectangular cross-section.

[0063] The relationship between the capping layer 160 and the lower wiring structure 120 is described below. The level of the upper surface 120S of the lower wiring structure 120 can be lower than the level of the upper surface of the capping layer 160. In addition, the level of the upper surface 120S of the lower wiring structure 120 can be lower than the level of the lower surface of the capping layer 160. That is, the side surfaces of the lower wiring structure 120 and the side surfaces of the capping layer 160 may not have regions facing each other.

[0064] As a result, since the space occupied by the air gap AG4 in the integrated circuit device 40 according to the inventive concept can be relatively large, the reduction amount of the parasitic capacitance can be increased or maximized, thereby improving the electrical characteristics and / or reliability.

[0065] Figure 5 is a flowchart illustrating a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept.

[0066] Referring to Figure 5 , a method (S10) of manufacturing an integrated circuit device includes: a first process (S110) of forming a lower wiring structure and a first sacrificial pattern; a second process (S120) of conformally forming an insulating barrier layer forming layer; a third process (S130) of forming a second sacrificial layer; a fourth process (S140) of forming a capping layer forming layer; a fifth process (S150) of polishing the capping layer forming layer and the insulating barrier layer forming layer; a sixth process (S160) of forming an air gap by removing the first sacrificial pattern and the second sacrificial layer; a seventh process (S170) of conformally forming an etch stop layer; an eighth process (S180) of forming an insulating layer; and a ninth process (S190) of forming an upper wiring structure penetrating the insulating layer.

[0067] The method (S10) of manufacturing an integrated circuit device may include the above processes S110 to S190. In cases where some embodiments may be implemented differently, specific processes may be performed in an order different from the order described herein. For example, two processes described as being performed continuously may be performed simultaneously or may be performed in an order opposite to the order described herein.

[0068] Will refer to Figures 6A to 6L The technical features related to the first process S110 to the ninth process S190 will be described in detail.

[0069] Figures 6A to 6LIt is a cross-sectional view according to the process sequence showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept.

[0070] Referring to Figure 6A , a lower support layer formation layer 110L, a lower wiring structure formation layer 120L, a first sacrificial layer 130L, and a first mask pattern M1 are sequentially formed on a substrate 100.

[0071] The lower support layer formation layer 110L may be formed on the substrate 100. The lower support layer formation layer 110L may include a material having an etching selectivity different from that of the lower wiring structure formation layer 120L. For example, the material of the lower support layer formation layer 110L may be selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0072] The lower wiring structure formation layer 120L may be formed on the lower support layer formation layer 110L. The lower wiring structure formation layer 120L may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or a combination thereof.

[0073] The first sacrificial layer 130L may be formed on the lower wiring structure formation layer 120L. The material of the first sacrificial layer 130L may include an insulating material. For example, materials such as BPSG, SOG, PSG, TEOS, and PE-TEOS may be used in the first sacrificial layer 130L.

[0074] The first mask pattern M1 is formed on the first sacrificial layer 130L through a lithography process. The first mask pattern M1 may be a photoresist or a hard mask. When forming an air gap AG (see Figure 6H ), a first opening region M1H may be defined. In addition, an anti-reflection coating (ARC) (not shown) may be formed on the first sacrificial layer 130L.

[0075] Referring to Figure 6B , using the first mask pattern M1 (see Figure 6A ) as an etching mask, the first sacrificial layer 130L (see Figure 6A ), the lower wiring structure formation layer 120L (see Figure 6A ), and the lower support layer formation layer 110L (see Figure 6A ) are sequentially etched, and the first mask pattern M1 (see Figure 6A ) is removed.

[0076] Through an etching process, a plurality of first holes 120H may be formed, and the upper surface of the substrate 100 may be exposed through the first holes 120H. In addition, through the etching process, the first sacrificial layer 130L (see Figure 6A ) becomes a first sacrificial pattern 130, and the lower wiring structure formation layer 120L (see Figure 6A) is transformed into the lower wiring structure 120, and the lower support layer forms layer 110L (see Figure 6A ) is transformed into the lower support layer 110. In some embodiments, the plurality of lower wiring structures 120 may have the same width 120W.

[0077] In the case where the etching process is a dry etching process, the plurality of first holes 120H may be tapered such that their lower line width is less than their upper line width. However, for convenience, the first holes 120H are shown as vertically straight in the drawings.

[0078] Referring to Figure 6C , an insulating barrier layer forming layer 140L is conformally formed on the entire surface of the resulting structure of the etching process.

[0079] The insulating barrier layer forming layer 140L can be conformally formed along the upper surface of the substrate 100, the side surfaces of the lower support layer 110, the side surfaces of the lower wiring structures 120, the side surfaces of the first sacrificial pattern 130, and the upper surface of the first sacrificial pattern 130. Accordingly, the insulating barrier layer forming layer 140L can prevent the diffusion of the metal material included in the lower wiring structure 120.

[0080] The insulating barrier layer forming layer 140L may include a material selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. Optionally, the insulating barrier layer forming layer 140L may include a material selected from HDP oxide, TEOS, PE-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, and TOSZ.

[0081] The insulating barrier layer forming layer 140L can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0082] Referring to Figure 6D , a second sacrificial layer 150 is formed that partially fills each of the plurality of first holes 120H.

[0083] The second sacrificial layer 150 can be formed as a carbon-containing layer. The carbon-containing layer can be a spin-on hard mask (SOH) or an amorphous carbon layer (ACL). In some embodiments, the carbon-containing layer can be a heat-eliminable polymer (HELP) that can be removed by heat treatment. However, the material of the second sacrificial layer 150 is not limited thereto.

[0084] The second sacrificial layer 150 may be formed using a spin coating or chemical vapor deposition process. An example of a process for forming the second sacrificial layer 150 is described below. The second sacrificial layer 150 is formed to completely fill each of the plurality of first holes 120H. Next, an etching process may be performed by recessing the upper surface of the second sacrificial layer 150 such that the level of the upper surface of the lower wiring structure 120 is substantially the same as the level of the upper surface of the second sacrificial layer 150. Thus, the second sacrificial layer 150 is formed to partially fill each of the plurality of first holes 120H.

[0085] In other embodiments, the level of the upper surface of the second sacrificial layer 150 may be different from the level of the upper surface shown in the drawings. That is, the level of the upper surface of the second sacrificial layer 150 may be higher or lower than the level of the upper surface of the lower wiring structure 120.

[0086] Referring to Figure 6E , a capping layer forming layer 160L is formed on the exposed upper surface of the second sacrificial layer 150 and the insulating barrier layer forming layer 140L.

[0087] The capping layer forming layer 160L may include a first capping layer forming layer 161L and a second capping layer forming layer 163L. More specifically, the first capping layer forming layer 161L is conformally formed on the upper surface of the second sacrificial layer 150, the side surfaces of the insulating barrier layer forming layer 140L, and the upper surface of the insulating barrier layer forming layer 140L, and the second capping layer forming layer 163L is formed on the first capping layer forming layer 161L.

[0088] The first capping layer forming layer 161L and the second capping layer forming layer 163L may include different materials. Optionally, the first capping layer forming layer 161L and the second capping layer forming layer 163L may include substantially the same material, but may have different densities.

[0089] Optionally, the first capping layer forming layer 161L and the second capping layer forming layer 163L may include the same material, but may be formed using different methods. For example, the first capping layer forming layer 161L may be formed by atomic layer deposition, while the second capping layer forming layer 163L may be formed by chemical vapor deposition. However, the forming methods are not limited thereto.

[0090] Referring to Figure 6F , the capping layer forming layer 160L (see Figure 6E ) and the insulating barrier layer forming layer 140L (see Figure 6E ) are etched such that the upper surface of the first sacrificial pattern 130 is exposed.

[0091] The etching process (or polishing process) may be a chemical mechanical polishing (CMP) process or a back etching process.

[0092] Through the etching process, the upper surface of the first sacrificial pattern 130 is completely exposed. In addition, through the etching process, the insulating barrier layer forming layer 140L (see Figure 6E ) becomes the insulating barrier layer 140, and the capping layer forming layer 160L (see Figure 6E ) becomes the capping layer 160.

[0093] In addition, through the etching process, the second capping layer 163 is only retained in the first capping layer 161. As a result, the capping layer 160 can be formed only on the upper surface of the second sacrificial layer 150.

[0094] Referring to Figure 6G , the upper surface of the lower wiring structure 120 is exposed by completely removing the first sacrificial pattern 130 (see Figure 6F ).

[0095] The etching process can vary according to the constituent material of the first sacrificial pattern 130 (see Figure 6F ). For example, when the first sacrificial pattern 130 (see Figure 6F ) is silicon oxide or silicon nitride, the first sacrificial pattern 130 (see Figure 6F ) can be removed by dry etching.

[0096] During the process of removing the first sacrificial pattern 130 (see Figure 6F ), as the thickness ratio occupied by the first sacrificial pattern 130 (see Figure 6F ) and the density of its constituent material decrease, the influence of the removal process on other components may increase. Therefore, the removal of the first sacrificial pattern 130 (see Figure 6F ) can be performed under conditions that suppress the influence of the removal process on the lower wiring structure 120 and the insulating barrier layer 140.

[0097] Referring to Figure 6H , the second sacrificial layer 150 (see Figure 6G ) is completely removed, and an air gap AG is formed in the position from which the second sacrificial layer 150 has been removed.

[0098] The etching process can vary according to the constituent material of the second sacrificial layer 150 (see Figure 6G ). For example, when the second sacrificial layer 150 (see Figure 6G ) is a carbon-containing layer, the second sacrificial layer 150 (see Figure 6G ) can be removed by an ashing process.

[0099] During the process of removing the second sacrificial layer 150 (see Figure 6G ), as the thickness ratio occupied by the second sacrificial layer 150 (see Figure 6G) As the occupied thickness ratio and the density of the constituent materials decrease, the impact of the removal process on other components may increase. Therefore, the removal of the second sacrificial layer 150 (see Figure 6G ) can be performed under conditions that suppress the impact of the removal process on the lower wiring structure 120 and the insulating barrier layer 140.

[0100] Here, the capping layer 160 can include a material having a density that allows carbon (C) to pass through. This configuration is used to provide a space through which carbon (C), which is the main material of the second sacrificial layer 150 (see Figure 6G ), can be smoothly discharged during the ashing process for removing the second sacrificial layer 150.

[0101] Referring to Figure 6I , an etch stop layer 170 is formed to conformally cover the upper surface of the lower wiring structure 120, the insulating barrier layer 140, and the capping layer 160.

[0102] The etch stop layer 170 can be formed to have a protruding and recessed structure. That is, the etch stop layer 170 can be formed to have a protruding and recessed structure having the same phase as the protruding and recessed structure formed by the lower wiring structure 120 and the capping layer 160.

[0103] The material of the etch stop layer 170 can include a material containing aluminum (Al), for example, aluminum oxide (Al x O y ), aluminum nitride (Al x N y ), aluminum oxynitride (Al x O y N z ) or any one selected from zirconium oxide (Zr x O y ) and hafnium oxide (Hf x O y ). However, the material of the etch stop layer 170 is not limited thereto.

[0104] Referring to Figure 6J , an insulating layer 210 is formed to cover the etch stop layer 170, and a second mask pattern M2 is formed on the insulating layer 210.

[0105] The insulating layer 210 is formed such that its lower surface covers the upper surface of the etch stop layer 170. Therefore, the lower surface of the insulating layer 210 can be formed to have a protruding and recessed structure having a phase opposite to that of the protruding and recessed structure of the etch stop layer 170.

[0106] A second mask pattern M2 is formed on the insulating layer 210 through a photolithography process. The second mask pattern M2 is formed by applying a photoresist and patterning the photoresist through exposure and development. Here, when forming the upper wiring structure 220 (see Figure 1A ), a second opening region M2H can be defined.

[0107] Referring to Figure 6K , the insulating layer 210 is etched using the second mask pattern M2 as an etching mask.

[0108] By adjusting the etching conditions, the etching stop layer 170 can stop the etching process. Thus, the etching process can be performed such that the upper surface of the etching stop layer 170 is exposed. That is to say, a first groove 210H1 can be formed in the insulating layer 210. The etching process for the insulating layer 210 can be a dry etching process.

[0109] Thereafter, the second mask pattern M2 can be removed using an ashing and stripping process. The process of removing the second mask pattern M2 can be performed under conditions that suppress damage to the insulating layer 210 and the etching stop layer 170.

[0110] Referring to Figure 6L , the exposed portion of the etching stop layer 170 is etched using the insulating layer 210 as an etching mask.

[0111] The etching conditions can be adjusted to etch only the exposed portion of the etching stop layer 170 without etching the insulating layer 210, the insulating barrier layer 140, and the capping layer 160. Thus, the etching process can be performed such that the upper surface of the insulating barrier layer 140 and a portion of the capping layer 160 are exposed. That is to say, a second groove 210H2 can be formed in the insulating layer 210. The etching process for the exposed portion of the etching stop layer 170 can be a wet etching process.

[0112] Returning to refer to Figure 1A , a conduction barrier layer 221 is formed on the inner wall of the second groove 210H2, and a metal layer 223 filling the second groove 210H2 is formed on the conduction barrier layer 221.

[0113] The conduction barrier layer 221 can be conformally formed to cover the insulating layer 210, the insulating barrier layer 140, and the capping layer 160 exposed in the second groove 210H2. A metal layer 223 filling the second groove 210H2 is formed on the conduction barrier layer 221.

[0114] Thereafter, the resulting structure including the conduction barrier layer 221 and the metal layer 223 is polished by a chemical mechanical polishing process such that the upper surface of the insulating layer 210 is exposed, so that the conduction barrier layer 221 and the metal layer 223 remain only in the second groove 210H2. As a result, an upper wiring structure 220 that fills the second groove 210H2 and is electrically connected to the lower wiring structure 120 can be formed.

[0115] The integrated circuit device 10 according to the inventive concept can be manufactured by the above manufacturing process, and the integrated circuit device 10 can have improved electrical characteristics and reliability.

[0116] Figure 7 is a configuration diagram of a system of an integrated circuit device according to an embodiment of the inventive concept.

[0117] Referring to Figure 7 , the system 1000 includes a controller 1010, an input / output device 1020, a memory 1030, an interface 1040, and a bus 1050.

[0118] The system 1000 can be a mobile system or a system for sending or receiving information. In some embodiments, the mobile system can be a portable computer, a tablet computer, a mobile phone, a digital music player, a memory card, etc.

[0119] The controller 1010 that controls the running programs in the system 1000 can include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0120] The controller 1010 can be implemented by using a processing circuit such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0121] The input / output device 1020 can be used to input or output data of the system 1000. The system 1000 can be connected to an external device such as a computer or a network through the input / output device 1020 and can exchange data with the external device. The input / output device 1020 can be, for example, a touchpad, a keyboard, a mouse, or a display.

[0122] The memory 1030 can store data for operating the controller 1010 or can store data processed by the controller 1010. The memory 1030 can include those described above with reference to the inventive concept Figures 1A to 4Any one of the described integrated circuit devices 10 to 40.

[0123] The interface 1040 may be a data transmission path between the system 1000 and an external device. The controller 1010, the input / output device 1020, the memory 1030, and the interface 1040 may communicate with each other via the bus 1050.

[0124] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: A lower wiring structure located on a substrate, the lower wiring structure including air gaps between adjacent lower wiring structures in the lower wiring structure; A capping layer covering the upper surface of the air gap, the width of the capping layer being the same as the width of the air gap; An etch stop layer conformally covering the upper surface of the lower wiring structure and the capping layer and having a protruding and recessed structure; An insulating layer covering the etch stop layer; And An upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered by the etch stop layer, wherein the upper wiring structure covers a part of the upper surface of the capping layer, the level of the upper surface of the capping layer is higher than the level of the upper surface of the lower wiring structure, and the vertical thickness of the capping layer is configured to ensure a predetermined separation distance between the upper wiring structure and the lower wiring structure horizontally adjacent to the upper wiring structure in the lower wiring structure.

2. The integrated circuit device according to claim 1, wherein, In a cross-sectional view, the lower wiring structure includes: A first lower wiring structure connected to the upper wiring structure; and A second lower wiring structure not connected to the upper wiring structure, wherein the shortest distance between the first lower wiring structure and the second lower wiring structure closest to it is smaller than the shortest distance between the portion of the upper surface of the capping layer covered by the upper wiring structure and the second lower wiring structure closest to it.

3. The integrated circuit device according to claim 1, the integrated circuit device further comprising an insulating barrier layer surrounding the side surface and the lower surface of the air gap, Among them, the insulating barrier layer and the capping layer comprising different materials.

4. The integrated circuit device according to claim 3, wherein the insulating barrier layer covers the side surface of the capping layer, and the etch stop layer covers the upper surface of the capping layer and the upper surface of the insulating barrier layer.

5. The integrated circuit device according to claim 3, wherein, The capping layer includes: A first capping layer conformally covering a part of the side surface of the insulating barrier layer and the upper surface of the air gap; and A second capping layer filling the first capping layer.

6. The integrated circuit device according to claim 1, wherein, The horizontal width of the air gap is less than the vertical thickness of the capping layer.

7. The integrated circuit device according to claim 1, wherein, The insulating layer and the capping layer include different materials, or include the same material but have different densities.

8. The integrated circuit device according to claim 1, wherein, The lower surface of the insulating layer is a protruding and recessed structure having a phase opposite to the phase of the protruding and recessed structure of the etch stop layer.

9. The integrated circuit device according to claim 1, wherein the level of the upper surface of each lower wiring structure is higher than the level of the upper surface of the air gap, and the level of the upper surface of each lower wiring structure is higher than the level of the lower surface of the capping layer.

10. The integrated circuit device according to claim 1, wherein the level of the upper surface of each lower wiring structure is lower than the level of the upper surface of the air gap, and the level of the upper surface of each lower wiring structure is lower than the level of the lower surface of the capping layer.

11. An integrated circuit device, the integrated circuit device comprising: A lower wiring structure spaced apart along a first direction on the upper surface of a substrate, extending in a second direction perpendicular to the first direction, and flush with each other in a third direction perpendicular to the upper surface of the substrate, air gaps being located between the lower wiring structures, a first plurality of air gaps in the air gaps having a first width, and the remaining air gaps in the air gaps having a second width different from the first width, the first width and the second width being in the first direction; A capping layer covers the upper surface of the air gap and has the first width or the second width, and the width of one of the capping layers in the capping layer is the same as the width of the corresponding air gap in the air gap; An insulating barrier layer surrounds the side surface and the lower surface of the air gap; An etch stop layer conformally covers the upper surface of the lower wiring structure, the side surface of the insulating barrier layer, the upper surface of the insulating barrier layer, and the upper surface of the capping layer; An insulating layer covers the etch stop layer; And An upper wiring structure penetrates the insulating layer and is connected to the upper surface of the lower wiring structure that is not covered by the etch stop layer, wherein the thickness of the capping layer in the third direction is configured to ensure a predetermined distance between the upper wiring structure and the lower wiring structure adjacent to the upper wiring structure in the first direction in the lower wiring structure, and the first width of the air gap is smaller than the thickness of the capping layer in the third direction.

12. The integrated circuit device according to claim 11, wherein, The upper surface of the capping layer is higher in level than the upper surface of the lower wiring structure.

13. The integrated circuit device according to claim 11, wherein, The lower surface of the insulating layer is a protruding and recessed structure that conformally covers the upper surface of the etch stop layer.

14. The integrated circuit device according to claim 11, wherein, A part of the upper wiring structure contacts the capping layer and the insulating barrier layer.

15. The integrated circuit device according to claim 11, wherein, the lower wiring structure forms a first layer of metal wiring, and the upper layer wiring structure forms a via connecting the first layer of metal wiring and a second layer of metal wiring located on the first layer of metal wiring.

16. An integrated circuit device, the integrated circuit device comprising: A first lower wiring structure and a second lower wiring structure are located on a substrate and an air gap is located between the first lower wiring structure and the second lower wiring structure; A capping layer covers the upper surface of the air gap, and the width of the capping layer is the same as the width of the air gap; An insulating barrier layer surrounds the side surface of the air gap; An etch stop layer conformally covers the upper surface of the second lower wiring structure, the side surface of the insulating barrier layer, the upper surface of the insulating barrier layer, and the upper surface of the capping layer; An insulating layer covers the etch stop layer; And An upper wiring structure penetrates the insulating layer, is connected to the upper surface of the first lower wiring structure, and has a protruding portion covering a part of the upper surface of the capping layer, wherein the vertical thickness of the capping layer is configured to ensure a predetermined distance between the upper wiring structure and the second lower wiring structure, and the predetermined distance is the shortest distance between the protruding portion and the second lower wiring structure closest to it, and the shortest distance between the first lower wiring structure and the second lower wiring structure closest to it is smaller than the shortest distance between the protruding portion and the second lower wiring structure closest to it.

17. The integrated circuit device according to claim 16, wherein, the etch stop layer has a protruding and recessed structure, and the etch stop layer includes an insulating material containing aluminum.

18. The integrated circuit device according to claim 16, wherein, The upper surface of the capping layer is higher in level than the upper surface of the second lower wiring structure.

19. The integrated circuit device according to claim 16, wherein, The air gap is sealed by different insulating materials and separated from the first lower wiring structure and the second lower wiring structure.

20. The integrated circuit device according to claim 16, wherein, The capping layer includes: A first capping layer conformally covers a part of the side surface of the insulating barrier layer and the upper surface of the air gap; and A second capping layer fills the space formed by the first capping layer and includes a material different from that of the first capping layer.

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