Driver circuit, system with driver circuit, and method for calibrating driver circuit

Abstract

A drive circuit, a system having the drive circuit, and a calibration procedure are disclosed herein. A driver circuit (10) is provided herein. The driver circuit (10) has a power transistor (14) and a gate driver circuit arrangement (11). The driver circuit (10) is integrated in a package. Additionally, the driver circuit (10) has a connector (12) for an external transistor (13). The external transistor (13) and the power transistor (14) are driven correspondingly to each other by the gate driver circuit arrangement (11).

Description

Technical Field

[0001] This application relates to driver circuits, systems having such driver circuits, and methods for calibrating driver circuits. Background Technology

[0002] Driver circuits are used to drive transistors, such as power transistors. These power transistors are used in various applications to convert high currents and / or high voltages. Such driver circuits typically include gate drivers for controlling the gate connections of the transistors, as well as various diagnostic and protection functions. When a driver circuit is used to drive an external transistor—that is, a transistor located outside the driver circuit—the external transistor is controlled and driven through corresponding pins on the driver circuit. Multiple transistors can also be simultaneously driven connected to these pins.

[0003] To measure the current flowing through this or these external transistors, an external measuring resistor is typically used, connected in series with the external transistor. The current is then measured by the voltage drop across the resistor. In the event of an overcurrent, this or these external transistors are turned off. Such an external resistor incurs additional cost and requires a corresponding pin on the driver circuitry to supply the tapped voltage to the driver circuitry. Summary of the Invention

[0004] A driver circuit, system, and method for calibrating the driver circuit are provided herein.

[0005] According to one embodiment, a driver circuit is provided, comprising: a gate driver circuit device, a power transistor coupled to the gate driver circuit device, and at least one connection terminal coupled to the gate driver circuit device. The driver circuit is integrated in a package. The gate driver circuit device is configured to drive the power transistor and at least one external transistor coupled to the driver circuit at the at least one connection terminal, respectively.

[0006] According to another embodiment, a system is provided having such a driver circuit and at least one external transistor coupled to at least one output.

[0007] Finally, a method for calibrating such a driver circuit is provided, the method comprising: providing calibration data for an external transistor, and storing the calibration data in the driver circuit.

[0008] Calibration data can indicate the parameters of an external transistor.

[0009] The above overview is only a brief summary of some embodiments and should not be construed as limiting, as other embodiments may have features other than those described above. Attached Figure Description

[0010] Figure 1 A block diagram of a system according to one embodiment is shown.

[0011] Figure 2A A block diagram of a system according to one embodiment is shown.

[0012] Figure 2B A detailed block diagram of a system according to one embodiment is shown.

[0013] Figure 3 A circuit diagram of a system according to one embodiment is shown.

[0014] Figure 4 A circuit diagram of a system according to one embodiment is shown.

[0015] Figure 5A A block diagram of a system according to one embodiment is shown.

[0016] Figure 5B A detailed block diagram of a system according to one embodiment is shown.

[0017] Figure 6 A circuit diagram of a system according to one embodiment is shown.

[0018] Figure 7 A circuit diagram of a system according to one embodiment is shown.

[0019] Figure 8 A circuit diagram of a system according to one embodiment is shown.

[0020] Figure 9 A circuit diagram of a system according to one embodiment is shown.

[0021] Figure 10 A circuit diagram according to some embodiments is shown to illustrate the probing of connected transistors.

[0022] Figure 11 A flowchart is shown to illustrate a method according to various embodiments. Detailed Implementation

[0023] Various embodiments are explained in detail below with reference to the accompanying drawings. These embodiments are for illustrative purposes only and should not be construed as limiting. In other embodiments, some features or components shown or described may be omitted or replaced by alternative features and components. In addition to the features and components explicitly described, other features or components may be provided, such as those also used in conventional driver circuits and corresponding systems.

[0024] Features of different embodiments can be combined with each other. For example, variations or modifications described with respect to one embodiment can also be applied to other embodiments, and therefore will not be repeated.

[0025] To simplify the description and facilitate better understanding, corresponding parts or elements in different figures have the same reference numerals and will not be described again.

[0026] Figure 1 A block diagram of a system 15 according to one embodiment is shown. System 15 has a driver circuit 10. The driver circuit 10 includes a gate driver circuit device 11, a power transistor 14, and a connection terminal 12. The connection terminal is, in this sense, an element of the driver circuit 10, through which external elements can communicate with the driver circuit 10. In the case of system 15, an external transistor 13 is connected to the connection terminal 12 to communicate with the driver circuit 10.

[0027] The driver circuitry 10 is integrated into a single package. Then, depending on the implementation and type of the package, the connection terminal 12 is a pin, pad, or similar connection terminal of the package. Components of the driver circuitry 10, particularly the gate driver circuitry 11 and the power transistor 14, can be monolithically integrated onto a single chip. In other embodiments, the components of the driver circuitry 10 may also be implemented on separate chips, and then arranged together in a single package.

[0028] Gate driver circuitry 11 drives power transistor 14 and external transistor 13 to control them, for example, to turn them on and off. The control is mutual; that is, external transistor 13 and power transistor 14 are switched together so that they have the same switching characteristics, such as simultaneous on and off. This applies to limits such as the difference in signal propagation time from gate driver circuitry 11 to external transistor 13 and power transistor 14, implementation differences between external transistor 13 and power transistor 14, and / or limits determined by other tolerances or fluctuations.

[0029] External transistor 13 can also be a power transistor. A power transistor is understood as a transistor designed to convert high voltage and / or high current. The on-chip size of a power transistor can be greater than 0.5 mm. 2 The size is such that it can conduct such a large current, and it can be greater than 10mm. 2 The resistance Ron when switched on can be 20mΩ / mm. 2 Within a certain range, the total resistance Ron can be less than 100mΩ. Power transistors can, for example, conduct currents greater than 10A, such as up to 40A, and / or convert voltages greater than 10V, such as several hundred volts.

[0030] It should be noted that Figure 1 Only some possible components of system 15 are shown. Therefore, multiple external transistors can be used instead of a single external transistor. Additionally, driver circuitry 10 may have diagnostic and / or measurement functions. In some embodiments, measurements can be performed on power transistor 14, such as measurements of the current through power transistor 14, and the current through external transistor 13 can be derived based on this. Examples of this will now be explained in detail with reference to additional figures.

[0031] Figure 2A A block diagram of a system according to one embodiment is shown. Figure 2A The system includes a driver circuit 231. The driver circuit 231 has an internal power transistor 25. The power transistor 25 may be, for example, a DMOS transistor. The driver circuit 231 also has a control function 232, a protection function 234, and a diagnostic function 235. The control function 232 is specifically used to drive the power transistor 25 and to drive external transistors controlled by the driver circuit 231. As an example, in Figure 2A The diagram shows three external transistors 215A, 215B, and 215C, which are driven via a gate resistor through a single connection terminal GATE1 of driver circuit 231. Hereinafter, external transistors 215A, 215B, and 215C will be collectively referred to as external transistor 215. The number of three external transistors 215 should be understood as an illustrative example only, and fewer external transistors 215 may also be provided, such as one or two external transistors 215, or more than three external transistors 215.

[0032] An external transistor 215 is connected in parallel with a power transistor 25 between a positive supply voltage 217 and a load 218, so as to selectively couple the load 218 to the positive supply voltage 217.

[0033] The driver circuit 231 is controlled by a microcontroller 230. The microcontroller can exchange various control and diagnostic signals with the driver circuit 231. See later. Figure 2B To explain this example in more detail, driver circuit 231 drives power transistor 25 and external transistor 215 respectively, such that they have essentially the same switching characteristics. Additionally, in Figure 2AIn this embodiment, the external transistor 215 and the power transistor 25 have similar parameters, such as resistance in the on-state, breakdown voltage, startup voltage, steepness, and overcurrent stability. Therefore, the protection function 234 and the diagnostic function 235 can deduce the current and voltage at the external transistor 215 by measuring the current and voltage at the power transistor 25, without requiring, for example, an external measuring resistor for measuring the current through the external transistor 215. This will be explained in more detail later. The current measurement result through the power transistor 25 can be output at output IS by the driver circuit 231 and sent to the analog-to-digital converter input of the microcontroller 230, which will also be explained in more detail later.

[0034] The external wiring of driver circuit 231 can also be as follows Figure 2A As shown.

[0035] Now refer to Figure 2B More detailed descriptions of the possible details of this driver circuit 231 are provided below. Figure 2B A detailed block diagram of a system according to one embodiment is shown. It can be... Figure 2B The driver circuit 20 is considered as Figure 2A An example of the implementation of the driver circuit 231.

[0036] Figure 2B The system includes a driver circuit 20 and one or more external transistors 215, of which three external transistors 215A, 215BGB, and 215C are shown in the example. The number of three external transistors is again for illustrative purposes only, and different numbers of external transistors may be provided depending on the implementation.

[0037] In the illustrated embodiment, the external transistor 215 is a power transistor implemented as a MOSFET.

[0038] Similar to Figure 1 The driver circuits 10 and 20 are integrated in a single package and can also be monolithically integrated into a single chip or provided on multiple chips within the package. The driver circuit 20 has a connection terminal GATE1 coupled to the gate connection terminal of the transistor 215.

[0039] The driver circuit 20 also includes a power transistor 25, which is also implemented as a MOSFET. Figure 2BIn one embodiment, power transistor 25 and external transistor 215 have similar parameters. For example, these transistors can nominally be implemented in the same way regarding their size and construction, such that differences in parameters can only occur due to process variations, manufacturing tolerances, etc. Similar parameters mean that parameters such as startup voltage, breakdown voltage, steepness, and resistance Ron in precise state are approximately the same, i.e., differing by a maximum of 10%, such as a maximum of 5% or a maximum of 1%. In other embodiments, the size of transistor 215 may differ from that of power transistor 25 in driver circuit 20. This will be described in detail later.

[0040] In the illustrated embodiment, power transistor 25 and external transistor 215 are connected in parallel between positive power supply voltage 217 and load 218 via their drain-source paths to optionally supply power to load 218. For this purpose, power transistor 25 and external transistor 215 are driven correspondingly to each other, specifically turned on and off together, such that power transistor 25 and external transistor 215 are both turned on to disconnect load 218 from positive power supply voltage 217, or both transistors are both turned off to connect load 218 to positive power supply voltage 217, thereby supplying power to load 218.

[0041] Therefore, the power supply voltage 217 of the driver circuit 20 is transmitted to the connection terminal VS. As shown, the connection terminal VS is connected to the drain connection terminal of the power transistor 25. The source connection terminal of the power transistor 25 is connected to the connection terminal AUS0 of the driver circuit 20. The load 218 is connected to the source connection terminal and the connection terminal OUT0 of the transistor 215, as shown. Figure 2B As shown.

[0042] The connection terminal VS is also connected to circuit block 21. Circuit block 21 has a power supply voltage monitor that monitors whether the power supply voltage 217 is within an acceptable range. Furthermore, circuit block 21 has an overvoltage protector, which acts as a protection mechanism in case of excessive voltage. Automatic restart control can also be provided in the event of a temporary failure of voltage 217. Additionally, an internal power supply voltage is generated in block 21 from the power supply voltage 217, which supplies power to the various components of the driver circuit 20. Finally, the sensing output IS is operated via circuit block 21, at which the detected current can be output, as described later. Circuit block 21 can be designed as in a conventional driver circuit and also includes components other than those shown.

[0043] Circuit block 22 is connected to terminals UV_SD, IN0, IN1, DEN, DSEL, and IOC, through which driver circuit 20 can communicate with external components such as a microcontroller. In the event of undervoltage, circuit block 22 can be shut down via terminal UV_SD. Terminals IN0, IN1, DEN, and DSEL are used for operation and diagnostics, and primarily connect to protection circuitry and input logic for electrostatic discharge (ESD) protection, which may convert the levels at these terminals to internal levels and / or have signals at these terminals. Furthermore, circuit block 22 is grounded via terminal GND, and the corresponding circuit section (GND circuitry) handles and connects to the ground within driver circuit 20.

[0044] Additionally, circuit block 22 features polarity reversal protection. If the positive power supply voltage 217 and ground are connected in reverse order, i.e., the positive power supply voltage is connected to terminal GND and ground is connected to terminal VS, the polarity reversal protection will protect driver circuit 20. This protection is also known as reverse polarity protection. Circuit block 22 can also be designed as in a conventional driver circuit.

[0045] The signals on terminals IN0, IN1, DEN, and DSEL can be provided, for example, by an external microcontroller to control and monitor the switching of power transistor 25 and external transistor 215. The signal on terminal IN0 is used to control power transistor 25 and external transistors 215A to 215C. This forms the first channel. Figure 2B Channel 0 is represented in this context. In some embodiments, another channel may be provided and controlled by a signal at connection terminal IN1. This channel has another power transistor inside the driver circuit 20 and another external transistor, which are coupled through another connection terminal GATE1. This is in... Figure 1 Not explicitly shown, and can be designed as the first channel (channel 0) described below. In other embodiments, only a single channel or two or more channels may exist. Diagnostic functions can be triggered by signals on the connection terminals DEN and DSEL, wherein diagnostics are activated by a signal on the connection terminal DEN, and the channel used for diagnostics is selected by a signal on the connection terminal DSEL.

[0046] Diagnostics, monitoring, and control of the first channel are performed in circuit block 23, which includes power transistor 25. This circuit block 23 is described in more detail below. The control is discussed first, followed by various diagnostic possibilities.

[0047] To control power transistors 25 and 215, a signal from the connection terminal IN0 is supplied to driver logic 28, which in turn drives a gate controller along with a charge pump 210 to generate a corresponding voltage to drive transistors 25 and 215. In the illustrated embodiment, the output signals of the gate controller and charge pump 210 are supplied to the gate connection terminal of power transistor 25. Furthermore, this signal is supplied to the gate connection terminal of external transistor 215 via gate controller 24 and connection terminal GATE1. In this way, power transistor 25 and external transistor 215 are driven correspondingly to each other. In some embodiments, gate controller 24 may optionally decouple the signal from the gate controller and charge pump 210 from connection terminal GATE1, allowing operation even without external transistor 215, and / or amplify, buffer, or voltage-shift the signal to match transistor 215 if the voltage requirement of the transistor differs from that of power transistor 25. Details of this circuitry will be described in more detail later. Additionally, gate controller 24 may provide electrostatic discharge (ESD) protection for connection terminal GATE1.

[0048] Next, the diagnostic and protection functions of circuit block 23 will be described.

[0049] For diagnostic purposes, a load current detector 212 is provided that detects the current flowing through the power transistor (i.e., the drain-source current), or in other words, the current flowing from the positive supply voltage 217 through the power transistor 25 to the load 218. The detected current can be forwarded by the driver logic and output, for example, at the output IS, particularly when a corresponding diagnostic request is present at the connection DEN. Furthermore, the load current can be monitored by an overcurrent limiter 213, which, in the event of an overcurrent (i.e., when the current exceeds a predetermined threshold), shuts off transistor 25 and, via gate controller 24, shuts off external transistor 215. In this way, in some embodiments, damage to the power transistor 25 and external transistor 215 due to excessive current can be avoided.

[0050] exist Figure 2B In the embodiment, the following fact is utilized: the external transistor 215 has similar parameters to the power transistor 25 as described above. Therefore, in the on-state, approximately the same current will flow through each of the external transistor 215 and the power transistor 25. In this case, the overcurrent at the power transistor 25 therefore means that an overcurrent also exists at the external transistor 215, since the transistors have exactly the same parameters, including their overcurrent characteristics. Therefore, in Figure 2BIn this embodiment, no external measuring resistor or other external measuring device is required to monitor the current through the external transistor 215, but this can be accomplished by measuring the current through the power transistor 25.

[0051] Any conventional circuitry used for current sensing can be used in the load current detector 212, such as the internal measuring resistor or measuring transistor within the driver circuit 20. The use of the measuring transistor will be explained in more detail later.

[0052] If the diagnostic function requires total current, then the total current through the load is equal to the detected current through the power transistor multiplied by the total number of transistors, i.e., in Figure 2B In the example, multiply by 4 (power transistor 25 + three external transistors 215). This can also be used to provide overcurrent monitoring for load 218, since the current through the load is also known in this way.

[0053] In addition, Figure 2B In this embodiment, a temperature sensor 26 is assigned to the power transistor 25. A temperature detector 29 checks whether the temperature detected by this temperature sensor 26 is higher than a threshold. If so, a warning can be output and / or the power transistor 25 can be turned off along with the external transistor 215. Finally, a voltage sensor 27 is provided for measuring the voltage across the power transistor 25. Additionally, a clamping device 214 is provided to limit the drain-source voltage to a maximum value to prevent avalanche breakdown. Figure 2A In this case, the clamping device is used for both the power transistor 25 and the external transistor 215. The clamping device can be designed as a passive clamping device alone by means of a Zener diode, for example, or as an active clamping device together with a transistor driven by a Zener diode (in the latter case, it is also called "active Zener").

[0054] Finally, the driver circuit 20 includes circuit 211, which turns on power transistor 25 and external transistor 215 in an inverted state. This inverted state occurs when the voltage at connection terminal OUT0 is higher than the voltage at connection terminal VS. In this case, in a conventional power transistor implementation, the body diode of power transistor 25 and external transistor 215 would become on, which could result in relatively high power loss. This power loss can be limited by turning on the transistors.

[0055] It should be noted that various diagnostic functions can be implemented in ways already known. However, only certain diagnostic functions or other conventional diagnostic functions can be provided. Unlike conventional methods, by providing diagnostic functions, the power transistor 25 also provides monitoring of the external transistor 215.

[0056] Now for reference Figure 3 Examples illustrating load current measurement and overcurrent detection. Figure 3 A portion of the driver circuit 30 is shown, particularly the current detection and overcurrent detection, as discussed above. Figure 1 , 2A Used in the driver circuit of 2B or one of the driver circuits discussed below.

[0057] The driver circuit 30 has the power transistor 25 already discussed. As an example, two external transistors 215, labeled 215A and 215B, are also shown. The power transistor 25 and the external transistors 215 are connected in parallel with each other between the power supply voltage 217 already discussed and the load 218 already discussed. Figure 3 In this context, it is again assumed that the external transistor 215 has similar parameters to the power transistor 25.

[0058] Furthermore, the driver circuit 30 has a detection transistor 31 connected in parallel with the power transistor 25 and scaled proportionally relative to the power transistor. The detection transistor 31 may be specifically connected to the power transistor 25 in a current mirror configuration. The scaling factor between the detection transistor 31 and the power transistor 25 is denoted by k and is also referred to as k0. ILIS factor.

[0059] The current through load 218 consists of the current IDMOS through power transistor 25, the current Iext_1 through external transistor 215A, and the current Iext_2 through external transistor 215B. The current Isense through sensing transistor 31 is scaled relative to the current through power transistor 25 by a scaling factor k. The total current Iload through load 218 is scaled relative to current Isense by a factor K of n*k, where n is the number of transistors (power transistor 25 + external transistors). Figure 3 In this example, it is therefore 3*k. The current Isense flows through resistor 32 to the connection terminal OUT. Resistor 32 serves as a measuring resistor for the Isense current. For this purpose, a corresponding voltage is tapped across resistor 32 and fed to the first input of comparator 33.

[0060] In addition, reference current source 35 generates a reference current Iref, which is measured by means of measuring resistor 34. The voltage at measuring resistor 34 is fed to the second input of the comparator.

[0061] If the current Isense exceeds the current Iref, then the power transistor 25 and the external transistor 215 are disconnected based on the output of comparator 33, and... Figure 3 In the example, the detection transistor 31 is disconnected. Overcurrent protection can be achieved in this way.

[0062] It should be noted that two separate detection transistors can be provided for both current-only detection and overcurrent monitoring. Figure 4 The corresponding embodiments are shown in the figure, which illustrate more details of current detection and overcurrent monitoring.

[0063] Figure 4 A system according to another embodiment is shown. According to Figure 4 The system will be explained in more detail below regarding the possible implementations of current detection and current measurement.

[0064] Figure 4 The system illustrates a driver circuit 40 with a gate driver 42 and a power transistor 25. As described above for the driver circuit, the driver circuit 40 can also be arranged in a package, particularly monolithically integrated on a single chip or distributedly integrated on multiple chips arranged within the package. The gate driver 42 drives the power transistor 25 and drives one or more external transistors 215 via a connection terminal GATE1, of which three external transistors 215A to 215C are shown here. As in the above embodiment, the power transistor 25 and the external transistors 215 are connected in parallel between a positive supply voltage 217 and a load 218 to optionally power the load. The gate driver 42 has sufficient strength to drive the power transistor 25 and the multiple external transistors designed for the driver circuit 40, and ensures sufficiently fast switching, particularly through the corresponding rise or fall rates of the respective gate-source voltages.

[0065] exist Figure 4 In one embodiment, the driver circuit 40 has an ESD protection circuit 43 coupled to the connection terminal GATE1.

[0066] Gate driver 42 contains logic and can be connected via interface 41, such as an SPI (Serial Peripheral Interface) interface, to, for example, a... Figure 2A The microcontroller shown is used for control. The driver circuit 40 also has a first detection transistor device 44 for overcurrent detection and a second detection transistor device 45 for current measurement. As shown, detection transistor devices 44 and 45 each have two transistors, as already referred to... Figure 3 As explained with regard to the detection transistor 31, the two transistors are scaled relative to the power transistor 25, and in particular have a smaller size.

[0067] exist Figure 4In this embodiment, each of the first detection transistors in each detection transistor device 44, 45 is always active, and for detection transistor device 44, the second transistor can be turned on via switch 46, and for detection transistor device 45, the second transistor can be turned on via switch 47. In this embodiment, switches 46, 47 can be closed when the external transistor 215 is connected to the connection terminal GATE0 of the driver circuit 40.

[0068] If no external transistor is connected, the switch can be turned off. This changes the effective scaling ratio between the sensing transistor devices 44, 45 and the power transistor 25, and can be used to provide current measurements corresponding to the total current flowing through transistors 25, 215. (Reference) Figure 3 This means that by turning on one or more transistors k, the supply is effectively changed, making the... Figure 3 The current generated by K in the transistor is set by sensing transistor device 44 or 45. Whether an external transistor 215 is provided can be detected by circuitry in the driver circuitry, which will be described in detail later, or it can be communicated via interface 41.

[0069] A detection transistor device 44 is used for overcurrent detection. For this purpose, a measuring resistor 48 is connected in series with the detection transistor device 44. The voltage across the measuring resistor 48 is measured by a differential amplifier 49 and supplied to the logic of the gate driver 42. This voltage is a measure of the current flowing through the detection transistor device 44, and therefore a measure of the total current flowing through the power transistors 25 and 215. The logic of the gate driver 42 can compare this provided value with a threshold value, and detect overcurrent when the measured current exceeds the threshold.

[0070] The sensing transistor device 45 is also used to provide current measurement. The source connection of the power transistor and the source connection of the sensing transistor device 45 are connected to the differential amplifier 410, the output of which is connected to the gate connection of the transistor 411. The source voltage of the sensing transistor device 45 is regulated to the source voltage of the power transistor 25 via components 410 and 411. Since the drain connections are respectively connected to the power supply voltage 217, this means that the voltage drop through the sensing transistor device 45 is exactly the same as the voltage drop through the power transistor 25 (within the regulation accuracy range), which can improve the accuracy of current measurement in some embodiments. As shown, transistor 411 is connected to the output IS of the driver circuit 40, so that in this case, the current flowing through the sensing transistor device 45 can be shunt at the output IS. It should be noted that in the case of the sensing transistor device 44, such components 410 and 411 are not required, because the drain connection of the sensing transistor device 44 and the drain connection of the power transistor 25 are also connected to each other.

[0071] It should also be noted that in other embodiments, the detection transistor arrangement 45 may be omitted, and the output of the differential amplifier 49 may be output at an output such as output IS as a measure of the flowing current.

[0072] In the embodiments discussed above, the corresponding driver circuit has a single connection terminal (GATE1) to which one or more external transistors are coupled. Other embodiments, explained in more detail below, have several separate connections for multiple external transistors, as in the first embodiment. Figure 5A As shown in the diagram. Apart from the variations explained below, Figure 5A The embodiments in the example correspond to Figure 2A The embodiments in the figures are shown, and corresponding elements have the same reference numerals. Therefore, only variations will be described below.

[0073] replace Figure 2A The driver circuit 231, Figure 5A The system has a driver circuit 531 with three terminals GATE1, GATE2, and GATE3. Corresponding external transistors 215A, 215B, and 215C are connected to each of terminals GATE1, GATE2, and GATE3, respectively. The driving of transistor 215 in relation to power transistor 25 is achieved through driver circuit 531, as explained in Figure 2 for power transistor 25 and external transistor 215. The provision of three terminals is merely an example; two or more terminals may also be provided to drive a corresponding number of external transistors 215.

[0074] In some implementations, the connection terminals GATE1, GATE2, and GATE3 may be optionally disabled. For example, only external transistor 215A may be provided, and the connection terminals GATE1 and GATE2 of the driver circuit 531 may be disabled. The controller 232, and in particular its driver, then outputs control signals only to the power transistor 25 and the connection terminal GATE0 to drive the external transistor 215A. For this purpose, the driver circuit 531 may also be configured to automatically identify whether the external transistor is connected to the connection terminals GATE1, GATE2, and GATE3, and to which connection terminal. This will be described in detail later.

[0075] Figure 5B A more detailed block diagram is shown. Figure 5B The system is Figure 2B The system is a variant, and the same components have the same reference numerals, which will not be described again.

[0076] Figure 5B The system has a driver circuit 50. The following describes the... Figure 2B The difference between driver circuit 20.

[0077] Similar to Figure 5A The driver circuit 531, Figure 5B The driver circuit 50 has three separate gate connections GATE1, GATE2, and GATE3, with one of transistors 215A, 215B, and 215C connected to each of these connections. Each of the connections GATE1, GATE2, and GATE3 is coupled to a corresponding gate controller 53A, 53B, or 53C, which provides a gate control for each of the connections GATE1, GATE2, and GATE3 respectively. Figure 2B The function of gate controller 24. To optionally disable connections GATE1, GATE2, and GATE3, gate controllers 53A, 53B, and 53C can be optionally disabled, for example, turned off, and respectively – similar to Figure 2B The gate controller 24 is driven by the gate controller and the charge pump 210.

[0078] Next, we will discuss circuit block 51 of driver circuit 50 and... Figure 2B The differences between the corresponding circuit blocks 23 of the driver circuit 20. In addition to circuit block 23, circuit block 51 also includes an availability check circuit 54, which checks which of the connections GATE1, GATE2, and GATE3 the external transistor 215 is connected to. This implementation example will be described later. Those connections GATE1 through GATE3 to which no external transistor is connected can subsequently be disabled. Additionally, the load current detection can be adjusted accordingly, for example, as referenced. Figure 4 As explained, this is achieved using switches 46 and 47.

[0079] The results of availability checker 54 can also be transmitted to another unit, such as microcontroller 230 (see [link]). Figure 5A This can be used to affect various functions. For example, the absence of an external transistor 215 that should actually be present can also indicate a defective transistor. In this case, for example, certain functions in the system can be shut down. As an example, load 218 can include various loads in a car, some of which may be more important than others. If one of the external transistors 215 is unavailable, secondary functions, especially those unrelated to safety (such as seat heating), can be shut down to limit the maximum current consumption through load 218.

[0080] It should be noted that the availability checker 54 can operate at system startup and also during system operation to, for example, prevent malfunctions. The strength of the gate controller and charge pump 210 can also be adjusted if some or all of the external transistors 215 are unavailable.

[0081] Providing multiple external transistors 215 may also include redundancy. For example, only one of the external transistors 215 can always be activated, and if one of the transistors is found to be unavailable, another of the external transistors 215 is activated.

[0082] Additionally, circuit block 51 has a calibration memory 52. ​​Compared to the embodiments described above, this calibration memory can be used if the external transistor 215 does not have any parameters similar to those of the power transistor 25. In this case, for example, the current flow through each external transistor 215 may differ from the current flow through the power transistor 25, and / or the breakdown and / or breakdown conditions or overcurrent conditions may differ. These different characteristics can be stored in the calibration memory 52 and then considered by the driver logic. For example, the current through the external transistor 215 can be inferred from the relationship between the resistance (typically referred to as Ron) of the external transistor 215 in its on-state and the current detected by the load current detector 212, and a shutdown behavior can be initiated in the event of a corresponding overcurrent.

[0083] Refer to later Figure 11 Let's explain some details of the calibration in more detail.

[0084] Figure 6 A circuit diagram of a system according to one embodiment is shown, which illustrates... Figure 5A and 5B Possible implementation details of the system. Figure 6 The system has a driver circuit 60, and the three external transistors 215A, 215B and 215C discussed are connected in the driver circuit at three connection terminals GATE1, GATE2 and GATE3, where the number of three external transistors is again used as an example. Figure 6 The driver circuit shown is already referenced Figure 4 The detection transistor devices 44 and 45 and their corresponding wiring are discussed. Additionally, the driver circuit has a driver 61 with logic units that drives the detection transistor devices 44 and 45 and the power transistor 25. The driver 61 can be driven via the already described interface 41.

[0085] Furthermore, driver 61 can drive external transistor 215 via gate controllers 62, 63, and 64. For clarity, connections from driver 61 to gate controllers 62, 63, and 64 are not shown. Connections GATE1, GATE2, and GATE3 can be optionally disabled via gate controllers 62, 63, and 64, or external transistors 215A, 215B, and 215C can be optionally driven.

[0086] In addition, the driver circuit 16 includes an availability check circuit 65, which is configured to check which external transistor 215 is available, that is, to check which external transistor is connected to the corresponding connection terminals GATE1, GATE2, GATE3 and is operable, for example, without faults.

[0087] To this end, as shown in the figure, the availability checker 65 is connected to each of the terminals GATE1, GATE2, and GATE3 on one hand, and to the terminal OUT on the other hand through a resistor 66. By connecting to terminals GATE1, GATE2, and GATE3, the availability check circuit 65 "knows" which external transistor 215 should be turned on. For example, to test availability, the driver 61 can sequentially drive the gate controllers 62, 63, and 64 to turn on the corresponding transistors 215A, 215B, and 215C. The resistor 66 can then be used to detect whether this turn-on causes a corresponding voltage change at the terminal OUT. If so, the corresponding transistor is available.

[0088] Such tests can be performed during startup and operation of the driver circuit 60, for example, during a phase when the load 218 does not require power.

[0089] Figure 7 Another embodiment of the system is shown, which is a... Figure 6 A variant of the system.

[0090] Figure 7 The system includes driver circuitry 70. Distinguished from... Figure 6The driver circuits 60 and 70 have individual gate drivers 71, 72, and 73 for each connection point GATE1, GATE2, and GATE3. These individual gate drivers can be controlled by the logic of gate driver 61 or directly by the microcontroller via interface 41. During operation, gate drivers 61 and 71 to 73 are controlled in such a way that power transistor 25 and external transistor 215 are driven correspondingly to each other, as already described. If the availability check circuit 65 indicates that one or more external transistors 215 are unavailable, the corresponding gate driver 71, 72, or 73 is deactivated, thereby deactivating the corresponding output GATE1, GATE2, or GATE3.

[0091] exist Figure 8 An example implementation of this gate driver is shown in the figure. Figure 8 A system having a portion of driver circuitry 80 is shown, which is exemplarily connected to three external transistors 215 at corresponding connection terminals GATE1, GATE2, and GATE3. Other portions of driver circuitry 80 may be implemented as described in the above embodiment.

[0092] In block 82, driver circuit 80 has the previously discussed power transistor 25 along with detection transistors 44 and 45. Power transistor 25 and detection transistors 44 and 45 are driven by a first driver 86. As shown, the first driver 86 primarily has a high-side switch and a low-side switch, which allow the driver's output node to be selectively connected to either a high-side or low-side current source. The first driver is connected between the power supply voltage VCP 85 provided by the charge pump and the output OUT via resistor 83.

[0093] To drive external transistors 215A, 215B, and 215C, corresponding second drivers 81A, 81B, and 81C are provided, constructed similarly to the first driver 86. To turn on power transistor 25 and external transistor 215, the first driver 86 and the second drivers 81A to 81C are driven with an ON signal to close the high-side switch when the low-side switch is open. To turn off the transistors, drivers 86, 81A, 81B, and 81C are correspondingly driven with an OFF signal to close the low-side switch when the high-side switch is open. In this embodiment, this driving is performed jointly for all drivers 86, 81A, 81B, and 81C, allowing transistors to be driven correspondingly to each other. If an availability checker is provided as described above, some of the drivers 81A to 81C can be disabled (where no external transistor 215 is available at the associated connection terminals GATE1 to GATE2), for example, in drivers where both the high-side and low-side switches are open.

[0094] exist Figure 9 Another system is shown in the figure. Figure 9 The system has a driver circuit 90 with the power transistor 25 already discussed, which, as an example, connects two external transistors 215A and 215B at two connection terminals GATE1 and GATE2. Again, the number of the two external transistors is merely an example.

[0095] Other parts of the driver circuit 90, particularly the part for current detection, can be implemented as described in the previous embodiments. Figure 9 The main purpose is to provide another example for implementing a gate driver.

[0096] The driver circuit 90 has a charge pump 91, which provides voltage for all the gate drivers described below. In the example shown, the charge pump 91 is a Dickson charge pump. Other types of charge pumps may also be used.

[0097] A driver circuit 94 is provided for driving the power transistor 25, and driver circuits 96A and 96B are provided for driving external transistors 215A and 215B. Similar to reference... Figure 8 The driver circuits discussed, 86, 81A to 81C, and driver circuits 94, 96A, and 96B, feature a high-side switch, a low-side switch, a high-side current source, and a low-side switch. (As already referenced...) Figure 8 In the discussed embodiments, the high-side and low-side switches of the driver circuit are controlled by a common control signal ( Figure 8 The ON and OFF controls in the circuits cause the power transistor 25 and the external transistor 215 to be driven correspondingly to each other. The drive circuits 94, 96A, and 96B control at least the high-side current sources to provide the same current or currents with a predetermined relationship to each other. This is in... Figure 9 This is achieved by providing all driver circuits 94, 96A, and 96B with the same reference current iRef, upon which the current source is adjusted. The reference current iRef can be generated by a reference current source. In other embodiments, the current from the high-side current source of one of the driver circuits (e.g., driver circuit 94) can be supplied to other driver circuits (e.g., 96A, 96B) as a reference current using a current mirror.

[0098] Additionally, clamping device 95 is assigned to driver 94, and corresponding clamping devices 97A and 97B are assigned to drivers 96A and 96B. These clamping devices are as described in reference... Figure 2B Like the clamping device 214 described herein, it is used to limit the drain-source voltage of the corresponding transistor to a maximum value to prevent avalanche breakdown. As described for clamping device 214, it can be implemented using a Zener diode. Distinguished from... Figure 2B ,exist Figure 9 Each transistor (power transistor 25 and external transistor 215) is provided with a single clamping device.

[0099] Figure 10 A more detailed embodiment of the availability check circuit, as used in various embodiments, is shown. This circuit is illustrated in an example using an external transistor 215 driven by driver 1003A. Other drivers (as indicated by 1003B) may be provided for other external transistors.

[0100] Figure 10 The circuit is based on the fact that, when monitoring the charging of the transistor, the gate-source voltage (or gate voltage) should rise to the level of the external transistor 215 (in...). Figure 10 The example shows the Miller steady-state of a MOSFET. In the absence of an external transistor 215, a current source can be used to pull the gate-source voltage or gate voltage to 0V.

[0101] To check availability, a high-side switch 1001 or a low-side switch 1002 connected to the corresponding current source is provided. This switch can be switched at frequencies, for example, within a 1 kHz range, to attempt to pull the gate-source voltage low. This can be done, for example, with external transistor 215 turned on by driver 1003A. If external transistor 215 is available and its gate is fully charged, it is nearly impossible to pull the gate voltage to 0V at this frequency; the gate voltage will only change slightly, for example, within a 100mV range. Conversely, if external transistor 215 is unavailable, for example, not connected or faulty, the voltage can be pulled down to approximately 0V. A comparator can be used to probe this.

[0102] Drivers 1003A and 1003B are supplied via charge pump 96. As a comparator, for example, a set-reset trigger 1005 can be used together with a preamplifier Schmitt trigger, which is optionally connected to output OUT via resistor 1008 via switch 1007.

[0103] As already explained, the current threshold can be set based on availability, or the driver strength can be set accordingly.

[0104] If you have already referred to Figure 5B As explained, in embodiments where the parameters of the external transistor differ from the parameters of the power transistor in the driver circuit, calibration data can be stored in a calibration memory. Now refer to... Figure 11 Describe the appropriate methods used for this purpose.

[0105] At 1100, Figure 11The method includes providing calibration data. If the driver manufacturer also provides a specific transistor as an external transistor for the driver circuitry, this provision can be made by the manufacturer of the corresponding driver circuitry (see the driver circuitry described above). However, this can also be done by the system manufacturer (a system with both driver circuitry and external transistors), for example, by combining external transistors from one manufacturer with driver circuitry from another manufacturer to produce a system. Calibration data may include parameters of the external transistor, such as resistance Ron in the on-state, breakdown voltage, overcurrent source, application, etc., or ratios of these parameters to the parameters of the power transistor (e.g., 25) of the driver circuitry. These parameters can be provided by the manufacturer of the external transistor. They can also be determined repeatedly, for example at predetermined time intervals, during operation by appropriate measurements to adapt the calibration to the aging of the external transistor.

[0106] In 1101, the method includes storing calibration data in a driver circuit.

[0107] At 1102, the calibration data is then used during the operation of the driver circuit to enable... Figure 5B The conclusions about the current through the external transistor are derived from calibration data from current measurements and / or overcurrent monitoring for the external transistor is provided with the aid of calibration data. The circuit measurement is based on the current through the power transistor of the driver circuit.

[0108] The following examples define some implementation schemes:

[0109] Example 1. The driver circuit includes:

[0110] Gate driver circuit device,

[0111] Power transistors, coupled to gate driver circuitry, and

[0112] At least one connection terminal is coupled to the gate driver circuitry.

[0113] The gate driver circuitry is configured to drive a power transistor and at least one external transistor corresponding to each other, the at least one external transistor being coupled to the driver circuitry at the at least one connection terminal.

[0114] The driver circuitry is integrated into a single package.

[0115] Example 2. The driver circuit according to Example 1 also includes a current monitoring circuit configured to monitor the current passing through the power transistor.

[0116] Example 3. A driver circuit according to Example 1 or 2, wherein the current monitoring circuit includes a detection transistor scaled relative to the power transistor and is configured to monitor the current through the power transistor based on the current through the detection transistor.

[0117] Example 4. The driver circuit according to Example 2 or 3 further includes a calibration memory storing information about the performance of at least one external transistor compared to the power transistor, wherein the current monitoring circuit is configured to monitor the current flow through the at least one external transistor based on the current through the power transistor and the information.

[0118] Example 5. A driver circuit according to any one of Examples 2 to 4, wherein the driver circuit is configured to turn off the power transistor and the at least one external transistor when the current through the power transistor indicates an overcurrent event.

[0119] Example 6. A driver circuit according to any one of Examples 1 to 5, wherein at least one connection terminal can be optionally disabled.

[0120] Example 7. The driver circuit according to Example 6, wherein at least one connection terminal includes a plurality of connection terminals, wherein each of the plurality of connection terminals can be optionally deactivated.

[0121] Example 8. The driver circuit according to Example 6 or 7 further includes an availability checker configured to detect whether an external transistor is available at at least one connection end, and optionally disable at least one connection end based on the detection.

[0122] Example 9. According to any one of Examples 1 to 8, the gate driver circuit device has a single gate driver for driving a power transistor and at least an external transistor.

[0123] Example 10. A driver circuit according to any one of Examples 1 to 8, wherein the gate driver circuit arrangement has a first gate driver for driving the power transistor and at least one second gate driver for driving the at least one external transistor.

[0124] Example 11. A driver circuit according to any one of Examples 10 and 6 to 8, wherein optional deactivation includes optionally deactivating at least one second gate driver associated with the at least one connection terminal.

[0125] Example 12. A driver circuit based on any one of Examples 1 to 11, wherein the driver circuit is monolithically integrated on a chip.

[0126] Example 13. A driver circuit according to any one of Examples 1 to 11, wherein the driver circuit is integrated on two or more chips arranged in a package.

[0127] Example 14. A system comprising:

[0128] At least one external transistor, and

[0129] The driver circuit includes:

[0130] Gate driver circuit device,

[0131] Power transistors, coupled to gate driver circuitry, and

[0132] At least one connection terminal is coupled to the gate driver circuitry.

[0133] The driving circuit is integrated into a single package.

[0134] At least one external transistor is coupled to at least one connection terminal, and

[0135] The gate driver circuit is configured to drive the power transistor and at least one external transistor in a corresponding manner.

[0136] Example 15. The driver circuit of the system according to Example 14 is designed according to any one of Examples 1 to 13.

[0137] Example 16. A system according to Example 14 or 15, wherein the driver circuitry includes a current monitoring circuitry configured to monitor the current passing through the power transistor.

[0138] Example 17. The system according to Example 16, wherein the current monitoring circuit includes a detection transistor that is scaled relative to the power transistor, and the current monitoring circuit is configured to monitor the current through the power transistor based on the current through the detection transistor.

[0139] Example 18. A system according to Example 16 or 17, wherein the driver circuitry further includes a calibration memory storing information about the performance of at least one external transistor compared to the power transistor, wherein the current monitoring circuitry is configured to monitor the current flow through at least one external transistor based on the current through the power transistor and the information.

[0140] Example 19. A system according to any one of Examples 16 to 18, wherein the driver circuit is configured to turn off the power transistor and at least one external transistor when the current through the power transistor indicates an overcurrent event.

[0141] Example 20. A system according to any one of Examples 14 to 19, wherein at least one connection end can be optionally disabled.

[0142] Example 21. The system according to Example 20, wherein at least one connection end includes a plurality of connection ends, wherein each of the plurality of connection ends can be optionally deactivated.

[0143] Example 22. The system according to Example 20 or 21, wherein the driver circuitry further includes an availability checker configured to detect whether an external transistor is available at at least one connection terminal, and optionally disable at least one connection terminal based on the detection.

[0144] Example 23. A system according to any one of Examples 14 to 22, wherein the gate driver circuitry has a single gate driver for driving a power transistor and at least an external transistor.

[0145] Example 24. A system according to any one of Examples 14 to 23, wherein the gate driver circuit arrangement has a first gate driver for driving a power transistor and at least one second gate driver for driving at least one external transistor.

[0146] Example 25. A system according to any one of Examples 24 and 20 to 22, wherein optional deactivation includes deactivating at least one second gate driver associated with the at least one connection terminal.

[0147] Example 26. A system according to any one of Examples 14 to 25, wherein the driver circuitry is monolithically integrated on a chip.

[0148] Example 27. A system according to any one of Examples 14 to 25, wherein the driver circuitry is integrated on two or more chips arranged in a package.

[0149] Example 28. A system according to any one of Examples 14 to 27, wherein at least one external transistor and a power transistor have similar parameters.

[0150] Example 29. The system according to Example 28, wherein the parameters include one or more of the following parameters:

[0151] The resistance of at least one external transistor in the ON state.

[0152] The startup voltage of at least one external transistor.

[0153] The breakdown voltage of at least one external transistor.

[0154] The steepness of the characteristic curve of at least one external transistor.

[0155] At least one type of external transistor, or

[0156] Overcurrent stability of at least one external transistor.

[0157] Example 30. A system according to any one of Examples 14 to 29, wherein at least one external transistor includes a plurality of external transistors, and wherein at least one connection terminal includes a single connection terminal coupled to the plurality of transistors.

[0158] Example 31. A system according to any one of Examples 14 to 29, wherein at least one transistor includes a plurality of external transistors, and wherein at least one connection terminal includes a plurality of connection terminals, each of the plurality of connection terminals being coupled to one of the plurality of transistors.

[0159] Example 32. A method for calibrating a driver circuit, the driver circuit comprising:

[0160] Gate driver circuit device,

[0161] Power transistors, coupled to gate driver circuitry, and

[0162] At least one connection terminal is coupled to the gate driver circuitry, and

[0163] Calibration memory,

[0164] The driver circuitry is integrated into a single package, and

[0165] The gate driver circuitry is arranged such that it drives a power transistor and at least one external transistor corresponding to each other, with the at least one external transistor connected to the driver circuitry at the at least one connection terminal.

[0166] The method includes:

[0167] Provide calibration data for at least one external transistor, and

[0168] The calibration data is stored in the calibration memory.

[0169] Example 33. The method of Example 32, wherein the method is performed in one or more of the following cases:

[0170] Manufacturing drive circuits,

[0171] Manufacturing systems that include drive circuitry, or

[0172] Repeatedly throughout the lifespan of the driver circuit.

[0173] Example 34. The method according to Example 32 or 33, wherein the calibration data is based on one or more of the following parameters:

[0174] The resistance of at least one external transistor in the ON state.

[0175] The startup voltage of at least one external transistor.

[0176] The breakdown voltage of at least one external transistor.

[0177] The steepness of the characteristic curve of at least one external transistor, or

[0178] Overcurrent stability of at least one external transistor.

[0179] Example 35. The method of any one of Examples 32 to 34, wherein the driver circuit is designed according to any one of Examples 1 to 13, and / or the driver circuit of the system is designed according to any one of Examples 1 to 31.

[0180] Although specific embodiments have been shown and described in this specification, those skilled in the art will recognize that various alternatives and / or equivalent implementations can be chosen instead of the specific embodiments shown and described herein without departing from the scope of the invention shown. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) comprising: Gate driver circuit device (11). Power transistors (14; 25) are coupled to the gate driver circuitry (11), and At least one connection terminal (12; GATE1, GATE2, GATE3) is coupled to the gate driver circuit device (11). The gate driver circuit device (11) is configured to drive the power transistor (14; 25) and at least one external transistor (13; 25) corresponding to each other, wherein the at least one external transistor is coupled to the driver circuit (10; 20; 30; 40; 50; 60; 60; 70; 80; 90; 231; 531; 1000) at at least one connection terminal (12; GATE1, GATE2, GATE3). The driver circuitry (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated into a single package. The drain-source path of the power transistor and the drain-source path of the at least one external transistor are connected in parallel.

2. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to claim 1 further includes a current monitoring circuit configured to monitor the current through the power transistor (14; 25).

3. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to claim 2, wherein the current monitoring circuit includes a detection transistor (31; 44, 45) scaled relative to the power transistor (14; 25), and the current monitoring circuit is configured to monitor the current through the power transistor (14; 25) based on the current through the detection transistor (31; 44, 45).

4. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to claim 2 or 3 further includes a calibration memory (52) storing information about the performance of the at least one external transistor (13; 25) compared to the power transistor (14; 25), wherein the current monitoring circuit is configured to monitor the current flow through the at least one external transistor (13; 25) based on the current through the power transistor (14; 25) and the information.

5. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to claim 2 or 3, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is configured to turn off the power transistor (14; 25) and the at least one external transistor (13; 25) when an overcurrent event is observed in the current through the power transistor (14; 25).

6. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to any one of claims 1 to 3, wherein the at least one connection terminal (12; GATE1, GATE2, GATE3) can be optionally deactivated.

7. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to claim 6, wherein the at least one connection terminal (12; GATE1, GATE2, GATE3) includes a plurality of connection terminals, wherein each of the plurality of connection terminals can be optionally deactivated.

8. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to claim 7 further includes an availability checker configured to detect whether an external transistor (13; 25) is available at the at least one connection terminal (12; GATE1, GATE2, GATE3), and optionally disable the at least one connection terminal (12; GATE1, GATE2, GATE3) based on the detection.

9. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) according to claim 8, wherein the gate driver circuit device (11) has a single gate driver (42; 61) for driving the power transistor (14; 25) and the at least one external transistor (13; 25).

10. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) according to any one of claims 1 to 3, wherein the gate driver circuit device (11) has a first gate driver (61) for driving the power transistor (14; 25) and at least one second gate driver (71, 72, 73) for driving the at least one external transistor (13; 25).

11. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) according to any one of claims 6 to 8, wherein the optional deactivation includes optionally deactivating the at least one second gate driver (71, 72, 73) associated with the at least one connection terminal (12; GATE1, GATE2, GATE3).

12. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) according to any one of claims 1 to 3, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) is monolithically integrated on a chip, or wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated on two or more chips arranged in the package.

13. A system having a driver circuit, comprising: At least one external transistor (13; 25), and The driver circuit includes: Gate driver circuit device (11). Power transistors (14; 25) are coupled to the gate driver circuitry (11), and At least one connection terminal (12; GATE1, GATE2, GATE3) is coupled to the gate driver circuit device (11). The driver circuitry (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated into a single package. The at least one external transistor (13; 25) is coupled to the at least one connection terminal (12; GATE1, GATE2, GATE3), and The gate driver circuit device (11) is configured to drive the power transistor (14; 25) and the at least one external transistor (13; 25) respectively. The drain-source path of the power transistor and the drain-source path of the at least one external transistor are connected in parallel.

14. The system of claim 13, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is designed according to any one of claims 1 to 12.

15. The system according to claim 13 or 14, wherein the at least one external transistor (13; 25) and the power transistor (14; 25) have similar parameters.

16. The system of claim 15, wherein the parameters include one or more of the following parameters: The resistance of the at least one external transistor (13; 25) in the ON state, The startup voltage of the at least one external transistor (13; 25), The breakdown voltage of the at least one external transistor (13; 25), The steepness of the characteristic curve of the at least one external transistor (13; 25), The type of the at least one external transistor (13; 25), or Overcurrent stability of the at least one external transistor (13; 25).

17. The system according to claim 13 or 14, wherein, The at least one external transistor (13; 25) includes a plurality of external transistors (13; 25), and the at least one connection terminal (12; GATE1, GATE2, GATE3) includes a single connection terminal (12; GATE1, GATE2, GATE3), which is coupled to the plurality of external transistors (13; 25), or The at least one transistor (13; 25) includes a plurality of external transistors (13; 25), and the at least one connection terminal (12; GATE1, GATE2, GATE3) includes a plurality of connection terminals, wherein each of the plurality of connection terminals (12; GATE1, GATE2, GATE3) is coupled to one of the transistors (13; 25) of the plurality of external transistors (13; 25).

18. A method for calibrating a driver circuit, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) includes: Gate driver circuit device (11). Power transistors (14; 25) are coupled to the gate driver circuitry (11), and At least one connection terminal (12; GATE1, GATE2, GATE3) is coupled to the gate driver circuit device (11), and Calibration memory (52). The driver circuitry (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated into a single package, and The gate driver circuit device (11) is configured to drive the power transistor (14; 25) and at least one external transistor (13; 25) corresponding to each other, wherein the at least one external transistor is coupled to the driver circuit (10; 20; 30; 40; 50; 60; 60; 70; 80; 90; 231; 531; 1000) at at least one connection terminal (12; GATE1, GATE2, GATE3). The drain-source path of the power transistor and the drain-source path of the at least one external transistor are connected in parallel. The method includes: Provide calibration data for the at least one external transistor (13; 25), and The calibration data is stored in the calibration memory (52).

19. The method of claim 18, wherein the method is performed in one or more of the following ways: Manufacturing the driver circuit, Manufacturing a system including the driver circuit, or The driver circuit is repeatedly subjected to this process throughout its service life.

20. The method of claim 18 or 19, wherein the calibration data is based on one or more of the following parameters: The resistance of the at least one external transistor (13; 25) in the ON state, The startup voltage of the at least one external transistor (13; 25), The breakdown voltage of the at least one external transistor (13; 25), The steepness of the characteristic curve of the at least one external transistor (13; 25), or Overcurrent stability of the at least one external transistor (13; 25).

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