Method of manufacturing photomask set and method of manufacturing semiconductor device

Abstract

A method of manufacturing a photomask set includes preparing a mask layout including a plurality of first layout patterns spaced apart from each other in a first region, wherein distances between center points of three first layout patterns adjacent to each other among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns in which distances between center points of two first layout patterns adjacent to each other among the pairs of first layout patterns do not have a minimum value among the different values, and dividing the mask layout into at least two mask layout patterns; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in a corresponding mask layout among the mask layouts divided into the at least two mask layouts.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Korean Patent Application No. 10-2019-0134791, entitled “Method of Manufacturing Photomask Set for Forming Patterns, and Method of Manufacturing Semiconductor Device Using the Photomask Set,” filed on October 28, 2019, in the Korean Intellectual Property Office, are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method of manufacturing a photomask set for forming a pattern and a method of manufacturing a semiconductor device by using the photomask set. Background Art

[0004] With the rapid development of the electronics industry and user needs, electronic devices are becoming increasingly compact and lightweight. Consequently, semiconductor devices used in electronic devices need to be highly integrated, and the design rules for configuring semiconductor devices are decreasing. Consequently, the complexity of the process for forming patterns for semiconductor devices is increasing. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a method for manufacturing a photomask group, the method comprising: preparing a mask layout, the mask layout comprising a plurality of first layout patterns spaced apart from each other in a first region, wherein distances between center points of three adjacent first layout patterns in the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, wherein the distance between center points of two adjacent first layout patterns in the pairs of first layout patterns does not have a minimum value among the different values, and dividing the mask layout into at least two mask layout patterns; and forming a photomask group comprising at least two photomasks, each of the photomasks comprising a mask pattern corresponding to the first layout pattern included in a corresponding mask layout in the mask layout divided into the at least two mask layout patterns.

[0006] According to another aspect of the disclosure, there is provided a method of manufacturing a semiconductor device by using a photomask set, the method including: forming a plurality of bit line structures having bit lines extending in parallel with each other in a first horizontal direction on a substrate; forming a plurality of buried contacts filling a lower portion of spaces between the plurality of bit line structures on the substrate; and forming a plurality of landing pads filling an upper portion of the spaces between the plurality of bit line structures and extending onto the plurality of bit line structures by using a photomask set including a first photomask and a second photomask, the plurality of landing pads including first, second, and third landing pads adjacent to each other, wherein a triangle connecting a center point of a top surface of the first landing pad, a center point of a top surface of the second landing pad, and a center point of a top surface of the third landing pad includes a scalene triangle, and forming the plurality of landing pads includes forming a landing pad material layer filling the upper portion of the spaces between the plurality of bit line structures and covering the plurality of bit line structures, forming a plurality of first hard mask patterns on the landing pad material layer by using the first photomask, forming a plurality of second hard mask patterns in spaces between the plurality of first hard mask patterns on the landing pad material layer by using the second photomask, and patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as etching masks.

[0007] According to yet another aspect of the disclosure, there is provided a method of manufacturing a semiconductor device, the method including: forming, on a substrate, a plurality of word lines crossing a plurality of active regions and extending parallel to each other in a first horizontal direction, the plurality of active regions being defined by an isolation layer in the substrate; forming, on the substrate, a plurality of bit line structures having bit lines extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction; forming, on the substrate, a plurality of buried contacts filling a lower portion of spaces between the plurality of bit line structures and connected to the plurality of active regions; forming a plurality of landing pads connected to the plurality of buried contacts, filling an upper portion of the spaces between the plurality of bit line structures, extending onto the plurality of bit line structures, and each having a top surface of a circular shape, by using a photomask set including a first photomask and a second photomask; and forming a plurality of storage nodes connected to the plurality of landing pads on the plurality of bit line structures, wherein the forming of the plurality of landing pads includes: forming a landing pad material layer filling the upper portion of the spaces between the plurality of bit line structures and covering the plurality of bit line structures; forming a plurality of first hard mask patterns and a plurality of second hard mask patterns separated from the plurality of first hard mask patterns on the landing pad material layer by sequentially using the first photomask and the second photomask; and patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as etching masks, wherein lengths of three sides of a triangle connecting center points of top surfaces of three landing pads adjacent to each other in the plurality of landing pads have a base distance of 3F (feature size) in value, a first side distance greater than the base distance, and a second side distance smaller than the base distance, respectively, and lengths of three sides of a triangle connecting center points of top surfaces of three storage nodes adjacent to each other in the plurality of storage nodes have a value of 3F (feature size) when the plurality of storage nodes are formed. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A schematic top view of a mask layout for a photomask set for forming a pattern is shown according to an example embodiment;

[0010] Figure 2A and Figure 2B A schematic top view of a process of designing a unit region of a mask layout for a photomask set for forming a pattern is shown according to an example embodiment;

[0011] Figure 3a schematic top view of a process of dividing a mask layout for manufacturing a set of photomasks for forming a pattern according to an example embodiment is shown;

[0012] Figure 4A , Figure 4B , Figure 5A and Figure 5B a schematic top view of a set of photomasks for forming a pattern according to an example embodiment is shown;

[0013] Figure 6 a schematic top view of a process of dividing a mask layout for manufacturing a set of photomasks for forming a pattern according to an example embodiment is shown;

[0014] Figure 7A , Figure 7B , Figure 8A and Figure 8B a schematic top view of a set of photomasks for forming a pattern according to an example embodiment is shown;

[0015] Figures 9A-9B a schematic cross-sectional view of a set of photomasks for forming a pattern according to an example embodiment is shown;

[0016] Figures 10A-10H a cross-sectional view of stages in a method of forming a pattern by using a set of photomasks according to an example embodiment is shown;

[0017] Figure 11A a schematic top layout of a semiconductor device manufactured by using a set of photomasks according to an example embodiment is shown;

[0018] Figure 11B a top layout selectively showing some of the main configurations in Figure 11A is shown;

[0019] Figures 12A-12C a schematic top layout of an arrangement of landing pads included in a semiconductor device manufactured by using a set of photomasks according to an example embodiment is shown;

[0020] Figures 13A-13B a schematic top layout of landing pads included in a semiconductor device formed in correspondence with photomasks included in a set of photomasks according to an example embodiment is shown; and

[0021] Figures 14A-21D a cross-sectional view of stages in a method of manufacturing a semiconductor device according to an example embodiment is shown. DETAILED DESCRIPTION

[0022] Figure 1 is a schematic top view of a mask layout ML for manufacturing a set of photomasks for forming a pattern according to an example embodiment.

[0023] Referring to Figure 1 The mask layout ML can include a plurality of first layout patterns MLC, a plurality of second layout patterns MLX, and a plurality of third layout patterns MLY.

[0024] The plurality of first layout patterns MLC can be island-shaped layout patterns spaced apart from each other. The plurality of first layout patterns MLC can respectively correspond to a plurality of contact patterns or a plurality of holes in the semiconductor device. The plurality of first layout patterns MLC can be arranged in a honeycomb shape in which rows are arranged in a first horizontal direction (X direction) and are arranged in a zigzag shape in a second horizontal direction (Y direction) on a plane, for example, the rows of the first layout patterns MLC in the first horizontal direction (X direction) can be offset with respect to each other in the second horizontal direction (Y direction). The plurality of first layout patterns MLC can be arranged in rows having a first unit pitch PXC in the first horizontal direction (X direction). Among the plurality of first layout patterns MLC, the rows arranged in the first horizontal direction (X direction) can be arranged to have a second unit pitch PYC in the second horizontal direction (Y direction). In an embodiment, the first unit pitch PXC can have a value greater than that of the second unit pitch PYC. For example, the first unit pitch PXC can have a value of 3 times a feature size (3F), and the second unit pitch PYC can have a value of 2.6 times a feature size (2.6F). The plurality of first layout patterns MLC can be formed to have a squashed honeycomb shape, which will be described with reference to Figure 2A and Figure 2B This will be described in detail.

[0025] The plurality of second layout patterns MLX can be a plurality of linear layout patterns extending generally in the first horizontal direction (X direction) and arranged to be spaced apart from each other in the second horizontal direction (Y direction). The plurality of second layout patterns MLX can respectively correspond to a plurality of line patterns included in the semiconductor device. The plurality of third layout patterns MLY can be a plurality of linear layout patterns extending generally in the second horizontal direction (Y direction) and arranged to be spaced apart from each other in the first horizontal direction (X direction). The plurality of second layout patterns MLX can have a first core pitch PYL as a minimum pitch in the second horizontal direction (Y direction), and the plurality of third layout patterns MLY can have a second core pitch PXL as a minimum pitch in the first horizontal direction (X direction). In some embodiments, the first core pitch PYL and the second core pitch PXL can have a value of 3F (feature size).

[0026] The plurality of third layout patterns MLY can respectively correspond to a plurality of line patterns included in the semiconductor device. The plurality of third layout patterns MLY can be a plurality of line-shaped layout patterns for forming a plurality of line-shaped patterns extending generally in the second horizontal direction (Y direction) in the semiconductor device. The first horizontal direction (X direction) and the second horizontal direction (Y direction) can be perpendicular to each other.

[0027] The second layout patterns MLX and the third layout patterns MLY are "generally" line-shaped patterns extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. However, this does not mean that the second layout patterns MLX and the third layout patterns MLY are straight line-shaped patterns extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), but means that the second layout patterns MLX and the third layout patterns MLY are generally similar to patterns forming lines extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), even if there are some bent portions or width variations.

[0028] The region in which the first layout patterns MLC are arranged can be referred to as a first region CELL, and the region in which the second layout patterns MLX and the third layout patterns MLY are arranged can be referred to as a second region CORE. The first region CELL can correspond to a cell region of the semiconductor device, and the second region CORE can correspond to a core region of the semiconductor device, but embodiments are not limited thereto. The region in which the second layout patterns MLX and the third layout patterns MLY are arranged can be referred to as a first line region CORE-H and a second line region CORE-V, respectively. In this specification, regions corresponding to the first region CELL, the second region CORE, the first line region CORE-H, and the second line region CORE-V of the mask layout ML can also be referred to as the first region CELL, the second region CORE, the first line region CORE-H, and the second line region CORE-V in the photomask and the semiconductor device.

[0029] The planar shapes of the plurality of first layout patterns MLC, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY are schematically shown to show the positions at which the first layout patterns MLC to the third layout patterns MLY are arranged. Accordingly, the planar shapes can be different from the planar shapes of the actual layout patterns of the mask layout ML. For example, the planar shapes of the plurality of first layout patterns MLC, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY can be a result of performing optical proximity correction (OPC) for forming the plurality of contact patterns, the plurality of holes, or the plurality of line patterns included in the semiconductor device into desired shapes.

[0030] Figure 2A and Figure 2Ba schematic top view for describing a process of designing a unit region of a mask layout of a photomask set for forming a pattern according to an example embodiment. In detail, Figure 2B is a top view showing an arrangement of a plurality of first layout patterns MLC in a unit region of a mask layout of a photomask set for forming a pattern according to an example embodiment, Figure 2A is a top view showing an arrangement of a plurality of virtual reference layout patterns MLCR referred to in the arrangement of the plurality of first layout patterns MLC shown in Figure 2B

[0031] Referring to Figure 2A , the plurality of virtual reference layout patterns MLCR can have a honeycomb shape arranged in a row in a first horizontal direction (X direction) and in a zigzag in a second horizontal direction (Y direction) on a plane. The plurality of reference layout patterns MLCR indicate a case in which a triangle connecting center points of three reference layout patterns MLCR adjacent to each other is an equilateral triangle, and at least two of three internal angles of the triangle connecting the center points of the three reference layout patterns MLCR adjacent to each other have the same value.

[0032] Among the three reference layout patterns MLCR adjacent to each other, a reference base distance LRB (i.e., a distance between the center points of two reference layout patterns MLCR adjacent to each other in the first horizontal direction (X direction)) and a first reference side distance LR1 and a second reference side distance LR2 (i.e., distances between the center points of two reference layout patterns MLCR adjacent to each other in the first horizontal direction (X direction) and the center point of one reference layout pattern MLCR adjacent to the two reference layout patterns MLCR in the second horizontal direction (Y direction), respectively) can have a value of 3F (feature size), i.e., the same value. The value of the reference base distance LRB can be the same as the value of the first unit pitch PXC. The distance having a value of 3F can be referred to as a reference distance.

[0033] Referring to Figure 2B , the plurality of first layout patterns MLC can have a honeycomb shape arranged in a row in a first horizontal direction (X direction) and in a zigzag in a second horizontal direction (Y direction) on a plane. Among the plurality of first layout patterns MLC, a triangle connecting center points of three first layout patterns MLC adjacent to each other can be a scalene triangle.

[0034] ​In the three first layout patterns MLC adjacent to each other, the bottom side distance LB (i.e., the distance between the center points of two first layout patterns MLC adjacent to each other in the first horizontal direction (X direction)) and the first side distance L1 and the second side distance L2 (i.e., the distance between the center point of two first layout patterns MLC adjacent to each other in the first horizontal direction (X direction) and the center point of one first layout pattern MLC adjacent to the two first layout patterns MLC in the second horizontal direction (Y direction), respectively) can have different values. In some embodiments, the value of the first side distance L1 can be greater than the value of the bottom side distance LB, and the value of the second side distance L2 can be less than the value of the bottom side distance LB. For example, the first side distance L1 can have a value greater than 3F (feature size), and the second side distance L2 can have a value less than 3F (feature size). The value of the bottom side distance LB can be the same as the value of the first unit pitch PXC.

[0035] Compared with the plurality of reference layout patterns MLCR( Figure 2A ), in the plurality of first layout patterns MLC, the center points of the plurality of first layout patterns MLC can be offset from the center points of the plurality of reference layout patterns MLCRby a certain distance in the first horizontal direction (X direction) or the direction opposite to the first horizontal direction (-X direction). Compared with the plurality of reference layout patterns MLCR, in the plurality of first layout patterns MLC, the rows arranged in the first horizontal direction (X direction) can be alternately moved in the first horizontal direction (X direction) by a first movement distance CM1 and in the direction opposite to the first horizontal direction (X direction) by a second movement distance CM2 in the second horizontal direction (Y direction). In some embodiments, the first movement distance CM1 and the second movement distance CM2 can have the same value.

[0036] Figure 3 is a schematic top view for describing a process of dividing a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment, Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B are each a schematic top view of a photomask set for forming a pattern according to an example embodiment.

[0037] Referring to Figure 3 , the mask layout ML can include a plurality of first layout patterns MLC, a plurality of second layout patterns MLX, and a plurality of third layout patterns MLY (refer to Figure 1The plurality of first layout patterns MLC is grouped into a plurality of first even layout patterns MLC1 and a plurality of first odd layout patterns MLC2, the plurality of second layout patterns MLX is grouped into a plurality of second even layout patterns MLX1 and a plurality of second odd layout patterns MLX2, and the plurality of third layout patterns MLY is grouped into a plurality of third even layout patterns MLY1 and a plurality of third odd layout patterns MLY2.

[0038] For example, the plurality of first layout patterns MLC can be grouped by selecting a group of first layout patterns MLC in which the distance between the center points of two first layout patterns MLC adjacent to each other is greater than the second side distance L2 (see Figure 2B ) and grouping the selected layout patterns into the plurality of first even layout patterns MLC1 and the plurality of first odd layout patterns MLC2. The plurality of first even layout patterns MLC1 and the plurality of first odd layout patterns MLC2 can each be obtained by selecting pairs of layout patterns MLC adjacent to each other in which the distance between the center points of two first layout patterns MLC is equal to the base distance LB (see Figure 2B ) and grouping the pairs of layout patterns. For example, the plurality of first even layout patterns MLC1 and the plurality of first odd layout patterns MLC2 can be obtained by alternately selecting rows arranged in the first horizontal direction (X direction) from the plurality of first layout patterns MLC.

[0039] The plurality of second even layout patterns MLX1 and the plurality of second odd layout patterns MLX2 can be obtained by alternately selecting the plurality of second layout patterns MXL arranged apart from each other in the second horizontal direction (Y direction). The plurality of third even layout patterns MLY1 and the plurality of third odd layout patterns MLY2 can be obtained by alternately selecting the plurality of third layout patterns MLY arranged apart from each other in the first horizontal direction (X direction).

[0040] Referring to Figure 4A and Figure 4BThe photomask set PM1 and PM2 can include a first photomask PM1 including a first mask pattern MK1 and a second photomask PM2 including a second mask pattern MK2. The first mask pattern MK1 can include a plurality of first even mask patterns MKC1 arranged in the first area CELL, a plurality of second even mask patterns MKX1 arranged in the first line area CORE-H of the second area CORE, and a plurality of third even mask patterns MKY1 arranged in the second line area CORE-V of the second area CORE. The second mask pattern MK2 can include a plurality of first odd mask patterns MKC2 arranged in the first area CELL, a plurality of second odd mask patterns MKX2 arranged in the first line area CORE-H of the second area CORE, and a plurality of third odd mask patterns MKY2 arranged in the second line area CORE-V of the second area CORE.

[0041] The plurality of first even mask patterns MKC1, the plurality of second even mask patterns MKX1, and the plurality of third even mask patterns MKY1 can be formed from a plurality of first even layout patterns MLC1, a plurality of second even layout patterns MLX1, and a plurality of third even layout patterns MLY1, respectively. The plurality of first odd mask patterns MKC2, the plurality of second odd mask patterns MKX2, and the plurality of third odd mask patterns MKY2 can be formed from a plurality of first odd layout patterns MLC2, a plurality of second odd layout patterns MLX2, and a plurality of third odd layout patterns MLY2, respectively.

[0042] The plurality of first even mask patterns MKC1 and the plurality of first odd mask patterns MKC2 can be arranged to have a pitch of a first unit pitch PXC in a first horizontal direction (X direction), and arranged to have a pitch of twice a second unit pitch PYC (2*PYC) in a second horizontal direction (Y direction), respectively. The plurality of second even mask patterns MKX1 and the plurality of second odd mask patterns MKX2 can be arranged to have a pitch of twice a first core pitch PYL (2*PYL) as a minimum pitch in the second horizontal direction (Y direction), respectively. The plurality of third even mask patterns MKY1 and the plurality of third odd mask patterns MKY2 can be arranged to have a pitch of twice a second core pitch PXL (2*PXL) as a minimum pitch in the first horizontal direction (X direction), respectively.

[0043] Referring to Figure 5A and Figure 5B, the photomask set PM1a and PM2a can include a first photomask PM1a including a first mask pattern MK1a and a second photomask PM2a including a second mask pattern MK2a. The first mask pattern MK1a can include a plurality of first even mask patterns MKC1 arranged in the first area CELL, a plurality of second mask patterns MKX arranged in the first line area CORE-H of the second area CORE, and a plurality of third mask patterns MKY arranged in the second line area CORE-V of the second area CORE. The second mask pattern MK2a can include a plurality of second odd mask patterns MKC2 arranged in the first area CELL. The second mask pattern MK2a included in the second photomask PM2a can not be arranged in the second area CORE.

[0044] The plurality of first even mask patterns MKC1, the plurality of first odd mask patterns MKC2, the plurality of second mask patterns MKX, and the plurality of third mask patterns MKY can be formed from the plurality of first even layout patterns MLC1, the plurality of first odd layout patterns MLC2, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY, respectively.

[0045] The plurality of first even mask patterns MKC1 and the plurality of first odd mask patterns MKC2 can be arranged to have a pitch of a first unit pitch PXC in a first horizontal direction (X direction) and a pitch of twice a second unit pitch PYC (2*PYC) in a second horizontal direction (Y direction), respectively. The plurality of second mask patterns MKX can be arranged to have a pitch of a first core pitch PYL, which is a minimum pitch, in the second horizontal direction (Y direction). The plurality of third mask patterns MKY can be arranged to have a pitch of a first core pitch PLY, which is a minimum pitch, in the first horizontal direction (X direction).

[0046] Figure 6 is a schematic top view for describing a process of dividing a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment, Figure 7A , Figure 7B , Figure 8A and Figure 8B are each a schematic top view of a photomask set for forming a pattern according to an example embodiment.

[0047] Referring to Figure 6 , the plurality of first layout patterns MLC are divided into a plurality of first even layout patterns MLC1b and a plurality of first odd layout patterns MLC2b, the plurality of second layout patterns MLX are divided into a plurality of second even layout patterns MLX1 and a plurality of second odd layout patterns MLX2, and the plurality of third layout patterns MLY are divided into a plurality of third even layout patterns MLY1 and a plurality of third odd layout patterns MLY2.

[0048] Among the plurality of first layout patterns MLC, a pair of first layout patterns MLC in which the distance between the center points of two first layout patterns MLC adjacent to each other has a value greater than the second side distance L2 as the minimum distance value (see Figure 2B ), and the selected plurality of first layout patterns MLC can be classified into a plurality of first even layout patterns MLC1b and a plurality of first odd layout patterns MLC2b. The plurality of first even layout patterns MLC1b and the plurality of first odd layout patterns MLC2b can each be obtained by selecting a pair of layout patterns MLC in which the distance between the center points of two first layout patterns MLC adjacent to each other has the first side distance L1 having the maximum value (see Figure 2B ) from among the plurality of layout patterns MLC and grouping the pair of layout patterns. For example, the plurality of first even layout patterns MLC1b and the plurality of first odd layout patterns MLC2b can be obtained by alternately selecting rows arranged in a zigzag shape in the second horizontal direction (Y direction) from among the plurality of first layout patterns MLC.

[0049] Referring to Figure 7A and Figure 7B , the photomask set PM1b and PM2b can include a first photomask PM1b including a first mask pattern MK1b and a second photomask PM2b including a second mask pattern MK2b. The first mask pattern MK1b can include a plurality of first even mask patterns MKC1b arranged in the first area CELL, a plurality of second even mask patterns MKX1 arranged in the first line area CORE-H of the second area CORE, and a plurality of third even mask patterns MKY1 arranged in the second line area CORE-V of the second area CORE. The second mask pattern MK2b can include a plurality of first odd mask patterns MKC2b included in the first area CELL, a plurality of second odd mask patterns MKX2 arranged in the first line area CORE-H of the second area CORE, and a plurality of third odd mask patterns MKY2 arranged in the second line area CORE-V of the second area CORE.

[0050] The plurality of first even mask patterns MKC1b, the plurality of second even mask patterns MKX1, and the plurality of third even mask patterns MKY1 can be formed from the plurality of first even layout patterns MLC1b, the plurality of second even layout patterns MLX1, and the plurality of third even layout patterns MLY1, respectively. The plurality of first odd mask patterns MKC2b, the plurality of second odd mask patterns MKX2, and the plurality of third odd mask patterns MKY2 can be formed from the plurality of first odd layout patterns MLC2b, the plurality of second odd layout patterns MLX2, and the plurality of third odd layout patterns MLY2, respectively. Figure 6The plurality of first odd layout patterns MLC2b, the plurality of second odd layout patterns MLX2, and the plurality of third odd layout patterns MLY2 are formed as illustrated in FIG. 2B. The plurality of first even mask patterns MKC1b and the plurality of first odd mask patterns MKC2b can be arranged to have a pitch of twice the first unit pitch PXC (2*PXC) in the first horizontal direction (X direction) and arranged to have a pitch of the second unit pitch PYC in the second horizontal direction (Y direction).

[0051] Referring to Figure 8A and Figure 8B , the photomask set PM1c and PM2c can include a first photomask PM1c including first mask patterns MK1c and a second photomask PM2c including second mask patterns MK2c. The first mask patterns MK1c can include a plurality of first even mask patterns MKC1b arranged in the first area CELL, a plurality of second mask patterns MKX arranged in the first line area CORE-H of the second area CORE, and a plurality of third mask patterns MKY arranged in the second line area CORE-V of the second area CORE. The second mask patterns MK2c can include a plurality of first odd mask patterns MKC2b arranged in the first area CELL. The second mask patterns MK2c included in the second photomask PM2c can not be arranged in the second area CORE.

[0052] The plurality of first even mask patterns MKC1b, the plurality of first odd mask patterns MKC2b, the plurality of second mask patterns MKX, and the plurality of third mask patterns MKY can be respectively formed as illustrated in Figure 6 The plurality of first even layout patterns MLC1b, the plurality of first odd layout patterns MLC2b, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY are formed as illustrated in FIG. 1B. The plurality of first even mask patterns MKC1b and the plurality of first odd mask patterns MKC2b can be respectively arranged to have a pitch of twice the first unit pitch PXC (2*PXC) in the first horizontal direction (X direction) and respectively arranged to have a pitch of the second unit pitch PYC in the second horizontal direction (Y direction).

[0053] Figure 9A and Figure 9B are schematic cross-sectional views of photomask sets 500-1 and 500-2 for forming a pattern according to example embodiments.

[0054] Referring to Figure 9A and Figure 9B , the photomask sets 500-1 and 500-2 can respectively include a first photomask 500-1 and a second photomask 500-2. Although Figure 9A and Figure 9BThe first and second photomasks 500-1 and 500-2 are shown as reflective masks, but the first and second photomasks 500-1 and 500-2 are not limited thereto. For example, the first and second photomasks 500-1 and 500-2 can be used in a photolithography process using extreme ultraviolet (EUV) light (e.g., light having a wavelength of 13.5 nm). The first photomask 500-1 can be any one of the first photomasks PM1, PM1a, PM1b, and PM1c shown in FIGS. 1A, 1B, 1C, and 1D, respectively, and the second photomask 500-2 can be any one of the second photomasks PM2, PM2a, PM2b, and PM2c shown in FIGS. 2A, 2B, 2C, and 2D, respectively. Figure 4A , Figure 5A , Figure 7A and Figure 8A The first photomask 500-1 can be any one of the first photomasks PM1, PM1a, PM1b, and PM1c shown in FIGS. 1A, 1B, 1C, and 1D, respectively, and the second photomask 500-2 can be any one of the second photomasks PM2, PM2a, PM2b, and PM2c shown in FIGS. 2A, 2B, 2C, and 2D, respectively. Figure 4B , Figure 5B , Figure 7B and 8B The first photomask 500-1 can be any one of the first photomasks PM1, PM1a, PM1b, and PM1c shown in FIGS. 1A, 1B, 1C, and 1D, respectively, and the second photomask 500-2 can be any one of the second photomasks PM2, PM2a, PM2b, and PM2c shown in FIGS. 2A, 2B, 2C, and 2D, respectively.

[0055] The first and second photomasks 500-1 and 500-2 can each include a mask substrate 510 and a reflective layer 520, and include absorption patterns 530-1 and 530-2, respectively. The mask substrate 510 can include, for example, a glass or quartz substrate. The reflective layer 520 can be located on the mask substrate 510 and reflect incident light. The absorption patterns 530-1 and 530-2 can be formed on the reflective layer 520, and the reflective layer 520 can be exposed between the absorption patterns 530-1 and between the absorption patterns 530-2.

[0056] The reflective layer 520 can have a multilayer structure of, for example, thirty to sixty Mo / Si layer repeated stacks. In some embodiments, a cover layer 522 can be located on the reflective layer 520 in order to protect the reflective layer. The cover layer 522 can include, for example, ruthenium oxide (RuO), or the like. In some embodiments, the cover layer 522 can be omitted.

[0057] At a bottom of the mask substrate 510, a base layer 532 for vacuum-attaching the first and second photomasks 500-1 and 500-2 to a stage of an exposure apparatus can be formed. The base layer 532 can include, for example, a chromium nitride (CrN) layer.

[0058] The absorption patterns 530-1 and 530-2 can include a first absorption pattern 530-1 in the first photomask 500-1 and a second absorption pattern 530-2 in the second photomask 500-2. The first absorption pattern 530-1 can be any one of the first mask patterns MK1, MK1a, MK1b, and MK1c shown in FIGS. 1A, 1B, 1C, and 1D, respectively, and the second absorption pattern 530-2 can be any one of the second mask patterns MK2, MK2a, MK2b, and MK2c shown in FIGS. 2A, 2B, 2C, and 2D, respectively. Figure 4A , Figure 5A , Figure 7A and Figure 8A The first absorption pattern 530-1 can be any one of the first mask patterns MK1, MK1a, MK1b, and MK1c shown in FIGS. 1A, 1B, 1C, and 1D, respectively, and the second absorption pattern 530-2 can be any one of the second mask patterns MK2, MK2a, MK2b, and MK2c shown in FIGS. 2A, 2B, 2C, and 2D, respectively. Figure 4B ,Figure 5B 、 Figure 7B and Figure 8B Any one of the second mask patterns MK2, MK2a, MK2b and MK2c shown in .

[0059] In some embodiments, the portion of the reflective layer 520 located between the first absorption patterns 530-1 may be Figure 4A 、 Figure 5A 、 Figure 7A and Figure 8A Any one of the first mask patterns MK1, MK1a, MK1b, and MK1c shown in FIG. 5 , a portion of the reflective layer 520 located between the second absorption patterns 530-2 may be Figure 4B 、 Figure 5B 、 Figure 7B and Figure 8B Any one of the second mask patterns MK2, MK2a, MK2b and MK2c shown in .

[0060] Figures 10A-10H are cross-sectional views illustrating stages in a method of forming a pattern by using a photomask set according to example embodiments.

[0061] Reference Figure 10A , on the base substrate 10, after forming the target layer 20, the hard mask layer 40, and the first coating layer 50 stacked in sequence, a first photoresist layer 90 is formed. In some embodiments, a buffer layer 30 and an auxiliary layer 35 stacked in sequence may be further formed between the target layer 20 and the hard mask layer 40. In some embodiments, a first capping layer 60 stacked on the first coating layer 50 may also be formed.

[0062] The base substrate 10 may include, for example, a semiconductor substrate. The base substrate 10 may further include a conductive material and an insulating layer arranged between the semiconductor substrate and the target layer 20. The target layer 20 may include a conductive material. For example, the target layer 20 may include polysilicon, a metal, a conductive metal nitride, etc. For example, the buffer layer 30 may include an amorphous carbon layer (ACL). The auxiliary layer 35 may prevent the buffer layer 30 from being exposed during the process of patterning the hard mask layer 40. For example, the hard mask layer 40 may include tetraethyl orthosilicate (TEOS). For example, the first coating layer 50 may be a spin-on hard mask (SOH). The first capping layer 60 may protect the top surface of the first coating layer 50. For example, the first capping layer 60 may include silicon oxynitride (SiON).

[0063] Reference Figure 10A and Figure 10B , a first photoresist pattern 92 is formed from the first photoresist layer 90 by using a first photomask. For example, the first photomask may be Figure 5A 、Figure 8A and Figure 9A Any one of the first photomasks PM1a, PM1c, and 500-1 shown in Figure 4A and Figure 7A Any one of the first photomasks PM1 and PM1b shown in Figure 10B The number of the first photoresist patterns 92 in the second region CORE shown in

[0064] Referring to Figure 10B and Figure 10C The preliminary hardmask pattern 52 can be formed by patterning the first coating layer using the first photoresist pattern 92 as an etch mask. In some embodiments, a cover pattern 62 that is part of the first coating layer 60 can be left on the preliminary hardmask pattern 52.

[0065] Referring to Figure 10C and Figure 10D The first hardmask pattern 42 can be formed by patterning the hardmask layer 40 using the preliminary hardmask pattern 52 as an etch mask.

[0066] Referring to Figure 10E After forming the second coating layer 70 that covers the first hardmask pattern 42, a second photoresist layer 95 can be formed. In some embodiments, a second cover layer 80 that is stacked on the second coating layer 70 can also be formed. The second coating layer 70 can include a carbon-containing material. For example, the second coating layer 70 can include SOH. The second cover layer 80 can protect a top surface of the second coating layer 70. For example, the second cover layer 80 can include SiON.

[0067] Referring to Figure 10E and Figure 10F The second photoresist pattern 97 can be formed from the second photoresist layer 95 using a second photomask. For example, the second photomask can be any one of the second photomasks PM2a, PM2c, and 500-2 shown in Figure 5B 、 Figure 8B and Figure 9B For example, the second photomask can be any one of the second photomasks PM2 and PM2b shown in Figure 4B and Figure 7B In this case, the second photoresist pattern 97 can also be patterned in the second region CORE and expose a portion of each of the second coating layer 70 and the second cover layer 80.

[0068] Referring to Figure 10F and Figure 10Gby using the second photoresist pattern 97 as an etching mask to pattern the second coated layer 70 to form a second hard mask pattern 72. In some embodiments, similar to the cover pattern 62 left on the preliminary hard mask pattern 52 not shown in Figure 10G but shown in Figure 10C , a portion of the second cover layer 80 can be left on the second hard mask pattern 72.

[0069] Referring to Figure 10G and Figure 10H , the target layer 20 is patterned by using the first hard mask pattern 42 and the second hard mask pattern 72 as etching masks to form a target pattern 22. Although the target pattern 22 is described as being formed by a PEPE (photo-etch-photo-etch) method with reference to Figures 10A-10H , the present disclosure is not limited thereto, and the present disclosure can include forming the target pattern 22 by using a photo mask set including two or more photo masks and forming the target pattern 22 by a PPE (photo-photo-etch) method.

[0070] Figure 11A is a schematic top layout for describing a main configuration of a semiconductor device 1 manufactured by using a photo mask set according to an example embodiment, Figure 11B is a top layout selectively showing some of the main configurations shown in Figure 11A .

[0071] Referring to Figure 11A and Figure 11B , the semiconductor device 1 can include a plurality of active regions ACT. In some embodiments, the plurality of active regions ACT can each have a long axis in a diagonal direction with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction) that are perpendicular to each other. A plurality of word lines WL intersecting the plurality of active regions ACT can extend parallel to each other in the first horizontal direction (X direction). Above the plurality of word lines WL, a plurality of bit lines BL can extend parallel to each other in the second horizontal direction (Y direction) that crosses the first horizontal direction (X direction). The plurality of bit lines BL can be connected to the plurality of active regions ACT via direct contact DC.

[0072] In some embodiments, among the plurality of bit lines BL, a plurality of buried contacts BC can be formed between two bit lines BL adjacent to each other. In some embodiments, the plurality of buried contacts BC can be arranged in a matrix aligned in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0073] A plurality of landing pads LP can be located on the plurality of buried contacts BC. The plurality of landing pads LP can be arranged to at least partially overlap the plurality of buried contacts BC. In some embodiments, the plurality of landing pads LP can each extend onto any one of the two bit lines BL adjacent to each other. In a planar view, the plurality of landing pads LP can be arranged to be continuously aligned in a first horizontal direction (X direction) and to be zigzag aligned in a second horizontal direction (Y direction).

[0074] The plurality of landing pads LP can be formed by performing a photolithography process twice. For example, the plurality of landing pads LP can be formed by performing the EUV process twice without using a pattern density enhancement technique of performing a photolithography process once. A top surface of each of the plurality of landing pads LP can have a disc shape, the edge of which is substantially circular rather than elliptical.

[0075] A plurality of storage nodes SN can be located on the plurality of landing pads LP. The plurality of storage nodes SN can be located above the plurality of bit lines BL. Each of the storage nodes SN can be a lower electrode of each of the plurality of capacitors. The storage nodes SN can be connected to the active region ACT via the landing pads LP and the buried contacts BC. In a planar view, the plurality of storage nodes can have a hexagonal arrangement structure. For example, the plurality of storage nodes SN can have a honeycomb shape arranged in a row in a first horizontal direction (X direction) and in a zigzag in a second horizontal direction (Y direction) in a planar view.

[0076] The honeycomb shape in which the plurality of landing pads LP are arranged and the honeycomb shape in which the plurality of storage nodes SN are arranged can be different from each other. For example, the storage nodes SN can be arranged in a complete honeycomb shape HMS in which a triangle connecting the center points of three storage nodes SN adjacent to each other is an equilateral triangle, and the plurality of landing pads LP can be arranged in a flattened honeycomb shape HML in which a triangle connecting the center points of three landing pads LP adjacent to each other is a scalene triangle. In this specification, the center points of the landing pads LP and the center points of the storage nodes SN respectively mean the center points of the top surfaces of the landing pads LP and the top surfaces of the storage nodes SN in a planar view (X-Y plane).

[0077] The plurality of landing pads can be aligned in the flattened honeycomb shape HML and arranged between the plurality of buried contacts BC aligned in the matrix RMB and the plurality of storage nodes SN aligned in the complete honeycomb shape HMS, respectively, and electrically connect the plurality of buried contacts BC to the plurality of storage nodes SN, respectively.

[0078] Figures 12A-12Cis a schematic top layout for describing an arrangement of landing pads LP included in a semiconductor device manufactured by using a photomask set according to an example embodiment.

[0079] Referring to Figure 12A The plurality of landing pads LP can have a hexagonal alignment structure on a plane. For example, the plurality of landing pads LP can have a honeycomb shape in which rows are aligned in a first horizontal direction (X direction) and Z-letters are aligned in a second horizontal direction (Y direction). To describe the arrangement of the plurality of landing pads LP, Figure 12A The plurality of landing pads LP and a plurality of virtual reference landing pads LPR are shown. The plurality of reference landing pads LPR indicates a case in which a triangle connecting center points LPR-C of three reference landing pads LPR adjacent to each other is an equilateral triangle. A value of a diameter of the reference landing pad LPR can be the same as a value of the diameter DI-L of the landing pad LP.

[0080] For example, in the three reference landing pads LPR adjacent to each other, a first reference internal angle θ1-R, a second reference internal angle θ2-R, and a third reference internal angle can each have the same value, wherein the first reference internal angle θ1-R and the second reference internal angle θ2-R are respective internal angles between a base and two sides, the base connecting the center points LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X direction), the two sides connecting the center points LPR-C of the two adjacent reference landing pads LPR in the first horizontal direction (X direction) and the center point LPR-C of one adjacent reference landing pad LPR in the second horizontal direction (Y direction), respectively, and the third reference internal angle is an internal angle between two sides connecting the center points LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X direction) to the center point LPR-C of one adjacent reference landing pad LPR in the second horizontal direction (Y direction), respectively. For example, the first reference internal angle θ1-R, the second reference internal angle θ2-R, and the third reference internal angle θ3-R can be 60°, respectively.

[0081] The reference bottom distance LB-R, and the first reference side distance LS-R1 and the second reference side distance LS-R2 can each have the same 3F (feature size) value, among three reference landing pads LPR adjacent to each other, where the reference bottom distance LB-R is a distance between the center points LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X direction), and the first reference side distance LS-R1 and the second reference side distance LS-R2 are respective distances between the center points LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X direction) and the center point LPR-C of one adjacent reference landing pad LPR in the second horizontal direction (Y direction). For example, the 3F (feature size) can have a value of about 25.6 nm, but is not limited thereto.

[0082] A triangle connecting three landing pads LP adjacent to each other among the plurality of landing pads LP (for example, the center points LP-C of two adjacent landing pads LP in the first horizontal direction (X direction) and the center point LP-C of one landing pad LP adjacent to the two adjacent landing pads LP in the first horizontal direction (X direction) in the second horizontal direction (Y direction)) can be a scalene triangle. Among the plurality of landing pads LP, among the three landing pads LP adjacent to each other such that lines connecting the center points LP-C form a triangle, two landing pads LP adjacent to each other in the first horizontal direction (X direction) are respectively referred to as a first landing pad LP1 and a second landing pad LP2, and a landing pad LP adjacent to the first landing pad LP1 and the second landing pad LP2 in the second horizontal direction (Y direction) between the first landing pad LP1 and the second landing pad LP2 can be referred to as a third landing pad LP3.

[0083] The first internal angle θ1 and the second internal angle θ2 can each have different values, where the first internal angle θ1 is an internal angle between a base connecting the center points LP-C of the first landing pad LP1 and the second landing pad LP2 and a side connecting the first landing pad LP1 to the third landing pad LP3, and the second internal angle θ2 is an internal angle between the base connecting the center points LP-C of the first landing pad LP1 and the second landing pad LP2 and a side connecting the second landing pad LP2 to the third landing pad LP3. For example, the first internal angle θ1 can have a value less than 60°, and the second internal angle θ2 can have a value greater than 60°. The third internal angle θ3 can have a value obtained by subtracting the value of the first internal angle θ1 and the value of the second internal angle θ2 from 180°, where the third internal angle θ3 is an internal angle between the side connecting the first landing pad LP1 to the third landing pad LP3 and the side connecting the second landing pad LP2 to the third landing pad LP3.

[0084] The bottom side distance LB, the first side distance LS1, and the second side distance LS2 can have different values, where the bottom side distance LB is a distance between a center point LP-C of the first landing pad LP1 and a center point LP-C of the second landing pad LP2, the first side distance LS1 is a distance between the center point LP-C of the first landing pad LP1 and a center point LP-C of the third landing pad LP3, and the second side distance LS2 is a distance between the center point LP-C of the second landing pad LP2 and the center point LP-C of the third landing pad LP3. The bottom side distance LB can have a value of 3F (feature size), which is the same value as the reference side distance LB-R. The first side distance LS1 can have a value greater than the value of the bottom side distance LB, and the second side distance LS2 can have a value less than the value of the bottom side distance LB. For example, the first side distance LS1 can have a value greater than 3F (feature size), and the second side distance LS2 can have a value less than 3F (feature size).

[0085] The center point LP-C of each of the plurality of landing pads can be offset from the center point LPR-C of each of the plurality of reference landing pads LPR in a first horizontal direction (X direction) or a direction opposite the first horizontal direction (-X direction) and from a bit line BL adjacent thereto. For example, the center points LP-C of the landing pads LP that constitute a row in the first horizontal direction (X direction) can be offset from the center points LPR-C of the reference landing pads LPR that constitute the row in the first horizontal direction (X direction) by a first offset distance CD1 in the first horizontal direction (X direction), and the center points LP-C of the landing pads LP that are adjacent to each other in a second horizontal direction and constitute another row in the first horizontal direction (X direction) can be offset from the center points LPR-C of the reference landing pads LPR that constitute the other row in the first horizontal direction (X direction) by a second offset distance CD2 in a direction opposite the first horizontal direction (-X direction). In some embodiments, the first offset distance CD1 and the second offset distance CD2 can have the same value. For example, the first offset distance CD1 and the second offset distance CD2 can each have a value greater than 0 and less than 0.75F (feature size). In some embodiments, the first offset distance CD1 and the second offset distance CD2 can each have a value of about 1 nm to about 6 nm.

[0086] The first offset distance CD1 and the second offset distance CD2 shown in FIG. 1B can have substantially the same value. Figure 2B The first offset distance CD1 and the second offset distance CD2 shown in FIG. 1B can have substantially the same value. Figure 12A The first offset distance CD1 and the second offset distance CD2 shown in FIG. 1B can have substantially the same value.

[0087] The plurality of landing pads LP according to the example embodiment can be formed by performing two EUV photolithography processes without using a pattern density enhancement technique that performs one photolithography process. Accordingly, a top surface of each of the plurality of landing pads LP can have a disc shape, the edge of which is substantially circular rather than elliptical or quadrilateral.

[0088] Referring to Figure 12B , the plurality of storage nodes SN can be located on the plurality of landing pads LP. As described above with reference to Figure 11A and Figure 11B , the landing pads LP can be arranged in a flattened honeycomb shape. The plurality of storage nodes SN can be arranged in a complete honeycomb shape. A value of a diameter DI-S of the storage nodes SN can be substantially equal to a value of a diameter DI-L of the landing pads LP. For example, the diameter DI-S of the storage nodes SN and the diameter DI-L of the landing pads LP can have a value of about 1.5F (feature size).

[0089] A triangle connecting a center point LP-C of the first landing pad LP1, a center point LP-C of the second landing pad LP2, and a center point LP-C of the third landing pad LP3 can be an isosceles triangle, and a triangle connecting center points SN-C of three storage nodes SN respectively corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3 can be an equilateral triangle. For example, a distance between the center points SN-C of the three storage nodes SN respectively corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3 can have the same value, i.e., a value of 3F (feature size). Accordingly, first, second, and third node internal angles θ1-S, θ2-S, and θ3-S of the triangle connecting the center points SN-C of the three storage nodes SN respectively corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3 can have the same value of 60°.

[0090] Referring to Figure 12C , the center point LP-C of the third landing pad LP3 is spaced apart from a center of a bottom side connecting the center point LP-C of the first landing pad LP1 and the center point LP-C of the second landing pad LP2 and a virtual center extension line HVL extending in a second horizontal direction (Y direction) that is a perpendicular direction of a side connecting the center point LP-C of the first landing pad LP1 and the center point LP-C of the second landing pad LP2 by a center transfer distance TCD in a first horizontal direction (X direction). The center point LP-C of the third landing pad LP3 can be offset from the center extension line HVL by the center transfer distance TCD in the first horizontal direction (X direction). A value of the center transfer distance TCD can be Figure 12AThe sum of the first offset distance CD1 and the second offset distance CD2 is illustrated in the center. The value of the center transfer distance TCD can be greater than 0 and less than half of the bottom side distance LB. For example, the value of the center transfer distance TCD can be greater than 0 and less than 1.5F (feature size). In some embodiments, the value of the center transfer distance TCD can be about 2 nm to about 12 nm.

[0091] Figures 13A-13B is a schematic top layout for classifying and describing landing pads included in a semiconductor device formed by a photomask included in a photomask set according to an example embodiment.

[0092] Referring to Figure 13A , the plurality of landing pads LP can include first landing pads LP1 and second landing pads LP2. The first landing pads LP1 can be formed from a plurality of first even mask patterns MKC1 included in a first photomask PM1 illustrated in Figure 4A or a first photomask PM1a illustrated in Figure 5A . The second landing pads LP2 can be formed from a plurality of first odd mask patterns MKC2 included in a second photomask PM2 illustrated in Figure 4B or a second photomask PM2a illustrated in Figure 5B . A distance between center points of two first landing pads LP1 adjacent to each other can be a bottom side distance LB having a value greater than a value of a second side distance L2.

[0093] Referring to Figure 13B , the plurality of landing pads LP can include first landing pads LP1a and second landing pads LP2a. The first landing pads LP1 can be formed from a plurality of first even mask patterns MKC1b included in a first photomask PM1b illustrated in Figure 7A or a first photomask PM1c illustrated in Figure 8A . The second landing pads LP2 can be formed from a plurality of first odd mask patterns MKC2b included in a second photomask PM2b illustrated in Figure 7B or a second photomask PM2c illustrated in Figure 8B . A distance between center points of two first landing pads LP1 adjacent to each other can be a first side distance L1 having a value greater than a value of a second side distance L2 and a value of a bottom side distance LB.

[0094] Referring to Figure 13A and Figure 13BThe plurality of landing pads LP can be formed by grouping landing pads LP adjacent to each other and performing a photolithography process twice or more using two or more photomasks, each time for landing pads LP adjacent to each other, where the value of the bottom side distance LB or the first side distance L1 of landing pads LP adjacent to each other is greater than the second side distance L2 having the minimum value of the distance between the center points LP-C of two landing pads LP adjacent to each other. Thus, as described above in Figure 12A , even if the center point LP-C of each of the plurality of landing pads LP is offset from the center point LPR-C of each of the plurality of reference landing pads and the distance between two landing pads LP adjacent to each other is reduced, the plurality of landing pads LP can be formed without being affected.

[0095] Figures 14A-21D is a cross-sectional view illustrating each stage in a method of manufacturing a semiconductor device according to an example embodiment. Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A correspond to cross sections along a line A-A' of Figure 11A . Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B correspond to cross sections along a line B-B' of Figure 11A . Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C and Figure 21C correspond to cross sections along a line C-C' of Figure 11A . Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19D , Figure 20D and Figure 21D correspond to cross sections along a line D-D' of Figure 11A .

[0096] Referring to Figures 14A-14D, a device isolation trench 116T may be formed on the substrate 110, and an isolation layer 116 may be formed to fill the device isolation trench 116T. The substrate 110 may include a semiconductor material, such as silicon (Si). The isolation layer 116 may include a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A plurality of active regions 118 may be defined on the substrate 110 by the isolation layer 116. Figure 11A Like the active regions ACT shown in FIG. 1 , the active regions 118 may each be in a relatively long island shape having a short axis and a long axis.

[0097] A plurality of word line trenches 120T may be formed in the substrate 110. The plurality of word line trenches 120T may each have a line shape extending in parallel in a first horizontal direction (X direction), intersecting the active region 118, and arranged at substantially equal intervals in a second horizontal direction (Y direction). In some embodiments, steps may be formed at the bottom surfaces of the plurality of word line trenches 120T. After cleaning the product of forming the plurality of word line trenches 120T, a plurality of gate dielectric films 122, a plurality of word lines 120, and a plurality of buried insulators 124 may be sequentially formed in the plurality of word line trenches 120T. The plurality of word lines 120 may constitute Figure 11A 1. The word lines 120 may extend parallel to each other in a first horizontal direction (X direction), intersect the active regions 118, and be arranged substantially at equal intervals in a second horizontal direction (Y direction). The top surface of each of the word lines 120 may be located at a lower level than the top surface of the substrate 110. For example, the word lines 120 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof.

[0098] The gate dielectric film 122 may include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), or a high-k dielectric film having a higher dielectric constant than that of the silicon oxide film.

[0099] Top surfaces of the plurality of buried insulators 124 may be located at substantially the same level as that of the top surface of the substrate 110. The buried insulator 124 may include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0100] Reference Figures 15A-15Doxide, a metal-based dielectric film, or a combination thereof. In some embodiments, the insulator patterns 112 and 114 can be formed by stacking multiple insulators including the first insulator pattern 112 and the second insulator pattern 114. In some embodiments, the first insulator pattern 112 can include a silicon oxide film, and the second insulator pattern 114 can include a silicon oxynitride film. Thereafter, a direct contact hole 134H is formed through the insulator patterns 112 and 114. The direct contact hole 134H can be formed to expose a source region in the active region 118. In some embodiments, the direct contact hole 134H can extend into the active region 118, i.e., into the source region.

[0101] Referring to Figures 16A-16D , a direct contact conductive layer is formed to fill the direct contact hole 134H and cover the insulator patterns 112 and 114. In some embodiments, the conductive layer for direct contact can include doped polysilicon. Next, after sequentially forming a metal-based conductive layer and an insulating cap layer for covering the insulator patterns 112 and 114 and the direct contact conductive layer and forming a bit line structure 140, a first metal-based conductive layer, a second metal-based conductive layer, and the insulating cap layer are etched to form a plurality of bit lines 147 including linear first metal-based conductive patterns 145 and second metal-based conductive patterns 146 and a plurality of insulating cap lines 148. In some embodiments, the first metal-based conductive patterns 145 can include titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based conductive patterns 146 can include tungsten (W) or W and tungsten silicide (WSi x ). One bit line 147 and one insulating cap line 148 covering the one bit line 147 can together constitute one bit line structure 140. A plurality of bit line structures 140 including the plurality of bit lines 147 and the plurality of insulating cap lines 148 can each extend in parallel in a second horizontal direction (Y direction) parallel to the major surface of the substrate 110. The plurality of bit lines 147 can constitute the plurality of bit lines BL shown in FIG. 1B. In some embodiments, the bit line structure 140 can further include a conductive semiconductor pattern 132 arranged between the insulator patterns 112 and 114 and the first metal-based conductive patterns 145. The conductive semiconductor pattern 132 can include doped polysilicon. Figure 11A

[0102] In the etching process for forming the plurality of bit lines 147, portions of the direct contact conductive layer that are not vertically overlapped with the bit lines can be removed by the etching process to form a plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 can constitute the plurality of direct contact conductive lines 134 shown in FIG. 1B. Figure 11A ​The plurality of bit lines 147 can be electrically connected to the plurality of active regions 118 through the plurality of direct contact conductive patterns 134. The plurality of bit lines 147 can be electrically connected to the plurality of active regions 118 through the plurality of direct contact conductive patterns 134.

[0103] Two sidewalls of each bit line structure of the plurality of bit line structures 140 can be covered by an insulating spacer structure 150. The plurality of insulating spacer structures 150 can each include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 can include a material having a dielectric constant lower than a dielectric constant of the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the second insulating spacer 154 including an oxide film can be removed in a subsequent process, and can be an air spacer.

[0104] A plurality of buried contact holes 170H can be formed between the plurality of bit lines 147. Between two bit lines 147 of the plurality of bit lines 170, an inner surface of the plurality of buried contact holes 170H can be defined by the insulating spacer structure 150 and the active region 118 covering sidewalls of each of the two bit lines. The plurality of buried contact holes 170H can be formed by using the insulator patterns 112 and 114 and a portion of each of the active regions 118 and by using the insulating spacer structure 150 covering two sidewalls of each of the plurality of bit line structures 140.

[0105] Referring to Figures 17A-17D The plurality of buried contacts 170 and the plurality of insulating fences 180 can be alternately arranged between pairs of the insulating spacer structures 150 of the plurality of insulating spacer structures 150 each covering (i.e., in the second horizontal direction (Y direction)) two sidewalls of each of the plurality of bit line structures 140. For example, the plurality of buried contacts 170 can include polysilicon. For example, the plurality of insulating fences 180 can include a nitride film. In some embodiments, the plurality of buried contacts 170 can be arranged along a line in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). Each buried contact 170 can extend from the active region 118 in a vertical direction (Z direction) perpendicular to the substrate 110. The buried contacts 170 can constitute a plurality of buried contact lines 171 each extending in the vertical direction (Z direction) perpendicular to the substrate 110. Figure 11A. The plurality of buried contacts 170 may be arranged in a space defined by the plurality of insulating barriers and the plurality of insulating spacer structures 150, wherein each of the plurality of insulating spacer structures 150 covers two sidewalls of each of the plurality of bitline structures 140. The plurality of buried contacts 170 may each fill a lower portion of a space between the plurality of insulating spacer structures 150, wherein each of the plurality of insulating spacer structures 150 covers two sidewalls of each of the plurality of bitline structures 140.

[0106] The top surfaces of buried contacts 170 may be lower than the top surfaces of insulating cover lines 148. Top surfaces of insulating barriers 180 and insulating cover lines 148 may be at the same level with respect to the vertical direction (Z direction).

[0107] A plurality of landing pad holes 190H may be defined by the plurality of insulating spacer structures 150 and the plurality of insulating fences 180. A plurality of buried contacts 170 may be exposed at the bottoms of the plurality of landing pad holes 190H.

[0108] Reference Figures 18A-18D After filling the plurality of landing holes 190H and forming a landing pad material layer 190P covering the plurality of bit line structures, a plurality of first hard mask patterns HMK1 are formed on the landing pad material layer 190P. The plurality of first hard mask patterns HMK1 can be formed by, for example, an EUV lithography process. The plurality of first hard mask patterns HMK1 located on the landing pad material layer 190P can be formed by the same method as in the reference method. Figures 10A-10D In some embodiments, the first hard mask pattern 42 is formed by a method similar to the method described above for forming the first hard mask pattern 42 on the target layer 20. Figure 10A The buffer layer 30 and auxiliary layer 35 shown in FIG may also be arranged between the landing pad material layer 190P and the first hard mask pattern HMK1. In some embodiments, the landing pad material layer 190P may include a conductive barrier film and a conductive pad material layer located above the conductive barrier film. In some embodiments, the conductive barrier film may have a Ti / TiN stacked structure. In some embodiments, the conductive pad material layer may include tungsten (W).

[0109] Reference Figures 19A-19D , a plurality of second hard mask patterns HMK2 are formed on the landing pad material layer 190P. The plurality of second hard mask patterns HMK2 may be formed by, for example, an EUV photolithography process. The plurality of second hard mask patterns HMK2 may be spaced apart from the plurality of first hard mask patterns HMK1 and arranged between the plurality of first hard mask patterns HMK1. The plurality of second hard mask patterns HMK2 may be spaced apart from the plurality of first hard mask patterns HMK1 and arranged between the plurality of first hard mask patterns HMK1. Figures 10E-10G The second hard mask pattern 72 is formed by a method similar to the method described above for manufacturing the second hard mask pattern 72 .

[0110] Referring to Figures 20A-20D , a plurality of landing pads 190 filling at least a portion of the plurality of landing pad holes 190H and extending onto the plurality of bit line structures 140 are formed. The plurality of landing pads 190 can be disposed on the plurality of buried contacts 170 and extend onto the plurality of bit line structures 140. In some embodiments, the plurality of landing pads 190 can extend onto the plurality of bit lines 147. Since the plurality of landing pads 190 are disposed on the plurality of buried contacts 170, the plurality of buried contacts 170 and the plurality of landing pads 190 corresponding to each other can be electrically connected to each other. The plurality of landing pads 190 can be connected to the active region 118 through the plurality of buried contacts 170. The plurality of landing pads 190 can constitute a plurality of landing pads LP shown in FIG. 1B. Figure 11A

[0111] The buried contact 170 can be disposed between two bit line structures 140 adjacent to each other, and the landing pad 190 can extend from between the two bit line structures 140 adjacent to each other with the buried contact 170 therebetween onto one bit line structure 140. The plurality of landing pads 190 can be separated into a plurality by using a hard mask pattern HMK including a plurality of first hard mask patterns HMK1 and a second hard mask pattern HMK2 shown in FIG. 2B as an etching mask to remove a portion of the landing pad material layer 190P, and then by using a recess unit 190R. The plurality of landing pads 190 can be spaced apart from each other with the recess unit 190R therebetween. Figures 18A-19D

[0112] Referring to Figures 21A-21D , a plurality of lower electrodes 210, a capacitor dielectric film 220, and an upper electrode 230 can be sequentially formed on the plurality of landing pads 190 to form a semiconductor memory device 1 including a plurality of capacitor structures 200. The plurality of lower electrodes 210 can be electrically connected to and correspond to the plurality of landing pads 190, respectively. The capacitor dielectric film 220 can conformally cover the plurality of lower electrodes 210. The upper electrode 230 can cover the capacitor dielectric film 220. The upper electrode 230 can face the lower electrode 210 with the capacitor dielectric film 220 therebetween. In a particular region, the capacitor dielectric film 220 and the upper electrode 230 can be integrally formed to cover the plurality of lower electrodes 210. The plurality of lower electrodes 210 can constitute a plurality of storage nodes SN shown in FIG. 1B. Figure 11A

[0113] ​​​The plurality of lower electrodes 210 can have a cylindrical shape filled to have a circular horizontal cross section, i.e., a columnar shape, but are not limited thereto. In some embodiments, the plurality of lower electrodes 210 can each have a cylindrical shape with a sealed bottom. In some embodiments, the plurality of lower electrodes 210 can be arranged in a honeycomb shape aligned in a zigzag pattern with respect to the first horizontal direction (X direction) or the second horizontal direction (Y direction). The plurality of lower electrodes 210 can include, for example, silicon doped with impurities, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not shown, the semiconductor memory device 1 can further include at least one support pattern contacting side walls of the plurality of lower electrodes 210.

[0114] Before the plurality of capacitor structures 200 are formed, an insulator structure 195 filling the recessed cells 190R can be formed. Although Figure 21A and Figure 21C It is shown that the top surface of the insulator structure 195 and the bottom surface of the lower electrode 210 are at the same horizontal level, but are not limited thereto. For example, the horizontal level of the top surface of the insulator structure 195 can be higher than the horizontal level of the bottom surface of the lower electrode 210, and the lower electrode 210 can extend into the insulator structure 195 toward the substrate 110.

[0115] In the semiconductor memory device 1 according to the present disclosure, the center points of the plurality of landing pads 190 are offset from the adjacent bit line structures 140, and thus, the width of the plurality of landing pads 190 extending in the vertical direction (Z direction) along the side walls of the adjacent bit line structures 140 in the first horizontal direction (X direction) can be lengthened. Accordingly, the margin between the landing pads 190 and the buried contacts 170 corresponding to each other is increased, and the reliability of the electrical connection between the landing pads 190 and the buried contacts 170 corresponding to each other can be increased. In addition, because the distance in the first horizontal direction (X direction) between one landing pad 190 and the buried contact 170 connected to another landing pad 190 adjacent to the one landing pad 190 is increased, bridging between the landing pad and the buried contact 170 adjacent to the landing pad 190 can be prevented.

[0116] In addition, the top surface of each of the plurality of landing pads 190 can have a disc shape, the edge of which is substantially circular rather than elliptical. Accordingly, because the separation distance between the plurality of landing pads 190 is increased, bridging between the adjacent landing pads 190 can be prevented, and the coverage filling property of the insulator structure 195 filled between the plurality of landing pads can be improved. Accordingly, the reliability of the electrical insulation between the plurality of landing pads 190 can be improved.

[0117] The methods, processes and / or operations described herein (e.g., preparation, grouping, dividing, etc. of a pattern layout) can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device (e.g., via simulation to be performed when processing a physical layer on a substrate). The computer, processor, controller, or other signal processing device can be one of those described herein, or one other than an element described herein. Because the algorithms underlying the formation of the methods (or operations of the computer, processor, controller, or other signal processing device) are detailed, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a special purpose processor for performing the methods described herein.

[0118] Additionally, another embodiment can include a computer readable medium, such as a non-transitory computer readable medium, for storing the code or instructions described above. The computer readable medium can be a volatile or non-volatile memory, or other storage device, which can be removably or non-removably coupled to a computer, processor, controller, or other signal processing device that will execute the code or instructions for performing the method embodiments described herein.

[0119] By way of summary and review, example embodiments provide a method of manufacturing a photomask set that can be used to reduce the difficulty of a process of forming a pattern in a process of manufacturing a semiconductor device, and a method of manufacturing a semiconductor device by using the photomask set.

[0120] Example embodiments have been disclosed herein, although specific terminology has been employed, the specific terminology is used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and / or elements described in conjunction with specific embodiments can be used alone or in combination with features, characteristics and / or elements described in conjunction with other embodiments, as would be understood by one skilled in the art. Accordingly, one skilled in the art will recognize that the foregoing description and examples have been presented for purposes of illustration and description only. The description is not intended to be exhaustive or to limit the application to the precise form disclosed, and various modifications and variations are possible in light of the above teachings or can be acquired from practice of the application.

Claims

1. A method of manufacturing a photomask set, the method comprising: preparing a mask layout including a plurality of first layout patterns spaced apart from each other in a first region, and distances between center points of three first layout patterns adjacent to each other among the plurality of first layout patterns respectively having different values; grouping pairs of first layout patterns in which distances between center points of two first layout patterns adjacent to each other among the pairs of first layout patterns do not have a minimum value among the different values, and dividing the mask layout into at least two mask layout patterns; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in a corresponding mask layout pattern among the at least two mask layout patterns, wherein the preparing of the mask layout includes making a triangle connecting the center points of the three first layout patterns adjacent to each other an isosceles triangle. The preparing of the mask layout further includes arranging the plurality of first layout patterns in a first horizontal direction into a row to have a base distance between center points of the plurality of first layout patterns, and arranging the plurality of first layout patterns in a second horizontal direction perpendicular to the first horizontal direction into a zigzag shape.

2. The method of claim 1, wherein, 3.The method of claim 2, wherein: the dividing of the mask layout includes alternately selecting rows arranged in the first horizontal direction from the plurality of first layout patterns, and grouping and dividing the rows into a plurality of first even layout patterns and a plurality of first odd layout patterns, and the forming of the photomask set includes forming a first photomask including a plurality of first even mask patterns corresponding to the plurality of first even layout patterns and a second photomask including a plurality of first odd mask patterns corresponding to the plurality of first odd layout patterns. 4.The method of claim 2, wherein: the dividing of the mask layout includes alternately selecting rows arranged in a zigzag shape in the second horizontal direction from the plurality of first layout patterns, and grouping and dividing the rows into a plurality of first even layout patterns and a plurality of first odd layout patterns, and the forming of the photomask set includes forming a first photomask including a plurality of first even mask patterns corresponding to the plurality of first even layout patterns and a second photomask including a plurality of first odd mask patterns corresponding to the plurality of first odd layout patterns. The dividing of the mask layout includes alternately selecting rows in which values of distances between center points are greater than the base distance.

5. The method of claim 4, wherein, The mask layout further includes a plurality of second layout patterns spaced apart from each other in a second region.

6. The method of claim 1, wherein, 7.The method of claim 6, wherein: the dividing of the mask layout includes alternately selecting the plurality of second layout patterns, grouping and dividing the second layout patterns into a plurality of second even layout patterns and a plurality of second odd layout patterns, and the forming of the photomask set includes forming a first photomask including a plurality of second even mask patterns corresponding to the plurality of second even layout patterns and a second photomask including a plurality of second odd mask patterns corresponding to the plurality of second odd layout patterns. forming the set of photomasks includes forming a first photomask and a second photomask such that the first photomask includes a plurality of second even mask patterns corresponding to the plurality of second even layout patterns and the second photomask includes a plurality of second odd mask patterns corresponding to the plurality of second odd layout patterns.

8. The method of claim 7, wherein, dividing the mask layout includes grouping and dividing the mask layout patterns into the plurality of second even layout patterns and the plurality of second odd layout patterns such that a minimum pitch of the plurality of second even layout patterns and a minimum pitch of the plurality of second odd layout patterns each has a value of twice a minimum pitch of the plurality of second layout patterns.

9. The method of claim 6, wherein, forming the set of photomasks includes forming a first photomask having a plurality of second mask patterns corresponding to the plurality of second layout patterns and forming a second photomask not having the plurality of second mask patterns.

10. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of bit line structures having bit lines extending parallel to each other in a first horizontal direction on a substrate; forming a plurality of buried contacts filling a lower portion of spaces between the plurality of bit line structures on the substrate; and forming a plurality of landing pads filling an upper portion of the spaces between the plurality of bit line structures and extending onto the plurality of bit line structures by using a set of photomasks including a first photomask and a second photomask, wherein the plurality of landing pads include first, second, and third landing pads adjacent to each other, and wherein a triangle connecting a center point of a top surface of the first landing pad, a center point of a top surface of the second landing pad, and a center point of a top surface of the third landing pad includes a scalene triangle, wherein forming the plurality of landing pads includes: forming a landing pad material layer filling the upper portion of the spaces between the plurality of bit line structures and covering the plurality of bit line structures, forming a plurality of first hard mask patterns on the landing pad material layer by using the first photomask, forming a plurality of second hard mask patterns in spaces between the plurality of first hard mask patterns on the landing pad material layer by using the second photomask, and patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as etching masks.

11. The method of claim 10, wherein, forming the plurality of landing pads includes arranging the plurality of landing pads in a row in a second horizontal direction perpendicular to the first horizontal direction to have a base distance between center points of top surfaces thereof and in a zigzag pattern in the first horizontal direction.

12. The method of claim 11, wherein, the first photomask and the second photomask respectively include even layout patterns and odd layout patterns corresponding to rows of the plurality of landing pads arranged in the second horizontal direction alternately.

13. The method of claim 11, wherein, the first photomask and the second photomask respectively include even layout patterns and odd layout patterns corresponding to rows of the plurality of landing pads arranged in a zigzag pattern in the first horizontal direction alternately.

14. The method of claim 13, wherein, The plurality of first hard mask patterns and the plurality of second hard mask patterns respectively correspond to rows of the landing pads in the plurality of landing pads in which distances between center points of top surfaces of the landing pads are alternately greater than the bottom side distance, the rows being arranged in a zigzag shape in the first horizontal direction.

15. The method of claim 10, wherein, Forming the plurality of landing pads includes forming a side of a top surface of each of the plurality of landing pads into a circular shape.

16. A method of manufacturing a semiconductor device, the method comprising: forming, on a substrate, a plurality of word lines crossing a plurality of active regions and extending parallel to each other in a first horizontal direction, the plurality of active regions being defined by an isolation layer in the substrate; forming, on the substrate, a plurality of bit line structures having bit lines extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction; forming, on the substrate, a plurality of buried contacts filling a lower portion of spaces between the plurality of bit line structures and connected to the plurality of active regions; forming a plurality of landing pads connected to the plurality of buried contacts, filling an upper portion of the spaces between the plurality of bit line structures, extending onto the plurality of bit line structures, and each having a circular top surface by using a photomask set including a first photomask and a second photomask; and forming a plurality of storage nodes connected to the plurality of landing pads on the plurality of bit line structures, wherein forming the plurality of landing pads includes: forming a landing pad material layer filling the upper portion of the spaces between the plurality of bit line structures and covering the plurality of bit line structures; forming a plurality of first hard mask patterns and a plurality of second hard mask patterns separate from the plurality of first hard mask patterns on the landing pad material layer by sequentially using the first photomask and the second photomask; and patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as etching masks, wherein lengths of three sides of a triangle connecting center points of top surfaces of three landing pads adjacent to each other in the plurality of landing pads have a bottom side distance having a value of 3 times a feature size, a first side distance greater than the bottom side distance, and a second side distance smaller than the bottom side distance, respectively, and in forming the plurality of storage nodes, lengths of three sides of a triangle connecting center points of top surfaces of three storage nodes adjacent to each other in the plurality of storage nodes have a value of 3 times the feature size.

17. The method of claim 16, wherein, The plurality of first hard mask patterns and the plurality of second hard mask patterns respectively correspond to rows of the landing pads in the plurality of landing pads arranged in the first horizontal direction.

18. The method of claim 16, wherein, The plurality of first hard mask patterns and the plurality of second hard mask patterns respectively correspond to rows of the landing pads in the plurality of landing pads arranged in a zigzag shape in a second horizontal direction, in which rows, distances between center points of top surfaces of the landing pads include the first side distance.

19. The method of claim 16, wherein, The first photomask and the second photomask are each a reflective mask for an extreme ultraviolet lithography process.

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