Apparatus, system, and method for ramp interconnects for semiconductor manufacturing

Abstract

The present disclosure is and includes at least one apparatus, system, and method for a ramped electrical interconnect for use in semiconductor manufacturing. The apparatus, system, and method include: at least one first semiconductor substrate having a first circuit including first electrical components thereon; a second semiconductor substrate at least partially covering the first circuit and having a second circuit including second electrical components thereon; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of priority to U.S. Application No. 16 / 104,716, filed August 17, 2018, entitled “Apparatus, System, and Method for Providing Ramp Interconnects for Semiconductor Manufacturing,” the entire contents of which are incorporated herein by reference, as set forth herein in their entirety. Background Technology Technical Field

[0003] This invention generally relates to semiconductor manufacturing, and more specifically, to an apparatus, system, and method for providing ramp interconnects.

[0004] Public background

[0005] In known semiconductor manufacturing techniques, vertical interconnect channels, or VIAs, are conductive paths used to provide electrical contacts between multiple layers of a multilayer semiconductor device. A VIA consists of a hole running vertically down from one layer to the next. The hole is then filled with a conductive material, such as copper, or its sidewalls are coated to provide the aforementioned conductive path between circuit layers.

[0006] However, known VIAs have several significant drawbacks. For example, difficulties may arise in the process of forming and filling the VIA or arranging the conductive material, because the vertical holes of the VIA must be filled with conductive material from the first circuit layer all the way down, or at least completely covered by its sidewalls, up to and including the plane provided by the second circuit layer to provide the necessary electrical connection between the circuit layers. For example, these difficulties may include the solidification of the conductive material in the hole before it reaches the first circuit layer, resulting in non-conductive gaps in the lower part of the VIA; the VIA walls being too rough, causing the conductive material to be "trapped" along the VIA sidewalls, which hinders or negates conductivity; roughening the conductive material during insertion, resulting in openings in the VIA that adversely affect conductivity; and the mechanical instability of the conductive material in the holes, which adversely affects the conductivity of the VIA, for example, by way of non-limiting example, due to the lack of mechanical support necessary to support the vertical rise of the VIA. Summary of the Invention

[0007] This disclosure is and includes at least one apparatus, system, and method for ramped electrical interconnects used in semiconductor manufacturing. The apparatus, system, and method include: at least one first semiconductor substrate having a first circuit including a first electrical component; a second semiconductor substrate at least partially covering the first circuit and having a second circuit including a second electrical component; a ramp formed through the second semiconductor substrate between the at least one first electrical component and the at least one second electrical component; and additively manufactured conductive traces formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component. Attached Figure Description

[0008] This disclosure is illustrated in the accompanying drawings by way of example rather than limitation, wherein similar reference numerals may indicate similar elements, and wherein:

[0009] Figure 1 A cross-sectional view of an exemplary RIA system is shown;

[0010] Figure 2 An isometric view of the first layer circuit and the second layer circuit according to an embodiment is shown;

[0011] Figure 3 A circuit-level view of a RIA according to some embodiments is shown;

[0012] Figure 4 An exemplary RIA is shown;

[0013] Figure 5 An exemplary RIA is shown;

[0014] Figure 6 A specific implementation of an exemplary RIA is provided;

[0015] Figure 7 The illustration shows the processing of the ramp of the RIA according to some embodiments;

[0016] Figure 8A and 8B The RIA of machining is shown; and

[0017] Figure 8C Shown in isometric view Figure 8B Print RIA. Detailed Implementation

[0018] The accompanying drawings and descriptions provided herein may have been simplified to illustrate aspects relevant to a clear understanding of the apparatuses, systems, and methods described herein, while other aspects that may be found in typical similar apparatuses, systems, and methods have been omitted for clarity. Those skilled in the art will recognize that other elements and / or operations may be desired and / or necessary for implementing the apparatuses, systems, and methods described herein. However, because such elements and operations are well known in the art and do not contribute to a better understanding of this disclosure, a discussion of such elements and operations may not be provided herein. Nevertheless, this disclosure is intended to inherently include all such elements, variations, and modifications to the described aspects that will be known to those skilled in the art.

[0019] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, the singular forms “a,” “an,” and “the” as used herein may also be intended to include the plural forms unless the context clearly indicates otherwise. The terms “comprising,” “including,” “containing,” and “having” are inclusive and thus specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Unless expressly determined as the order of execution, the method steps, processes, and operations described herein should not be construed as requiring them to be performed in the particular order discussed or shown. It should also be understood that additional or alternative steps may be employed.

[0020] When an element or layer is referred to as being “on,” “joined to,” “connected to,” or “linked to” another element or layer, it may be directly on, directly joined to, directly connected to, or directly linked to the other element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as being “directly on,” “directly joined to,” “directly connected to,” or “directly linked to” another element or layer, there may be no intermediate elements or layers present. Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] Although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. That is, unless the context clearly indicates otherwise, terms such as “first,” “second,” and other numerical terms do not imply order or sequence when used herein. Therefore, without departing from the teachings of exemplary embodiments, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0022] The processor-implemented modules, systems, and methods disclosed herein, designed and controlled for use in the production of digital content, can provide access to and transformation of various types of digital content, and can track, deliver, manipulate, transform, and report the accessed content, including but not limited to video, images, text, audio, metadata, algorithms, interactive content, and document content. The embodiments of these modules, systems, and methods are intended to be exemplary and not restrictive. Therefore, it is contemplated that the systems and methods described herein can be modified and extended to provide enhancements and / or additions to the exemplary modules, systems, and methods. Consequently, this disclosure is intended to include all such extensions.

[0023] Examples include using additive manufacturing techniques (i.e., 3D printing) and conductive inks (e.g., nanoparticle conductive inks) in multilayer (e.g., two-layer) circuits to create ramp-type electrical interconnects. As an example, examples may allow for the integration and interconnection of molded top and bottom circuitry, and may additionally include the ability to place surface-mount components within end-molded electronics.

[0024] More specifically, multilayer circuits, such as two-layer circuits, can have a sloping version of the “VIA” (Vertical Interconnect Channel), also referred to herein as a ramped interconnect channel (RIA), which provides a non-vertical VIA connection between two layers of the multilayer circuit. The RIA ramp can be generated by any known method, such as molding, machining, cutting, etc. For example, without departing from this disclosure, laser drilling, laser micromachining, C&C machining, shape molding, etc., can be methods used to generate the ramp in the embodiments. As a particular non-limiting example, a C&C machine can be used to remove a ramp-shaped slice from the second circuit layer substrate, thereby creating a ramp having a high point starting at the plane of the second circuit layer and a low point terminating slightly below, at, or slightly above the plane provided for the first circuit layer. Conductive material can then be added to the ramp to provide the RIA interconnecting the first and second circuit layers.

[0025] Therefore, the embodiments can overcome the shortcomings of typical VIA vertical vias commonly used in the prior art for electrically connecting multilayer circuits. In known VIA cases, the vertical via must be filled with conductive material from the first circuit layer all the way down to include a plane provided by the second circuit layer to provide electrical connection. However, in typical prior art embodiments, difficulties may arise in the process of creating and filling the VIA. For example, these difficulties may include the solidification of the conductive material in the via before it reaches the first circuit layer, resulting in a non-conductive gap at the bottom of the VIA; the VIA walls being too rough, causing the conductive material to be "trapped" along the VIA sidewalls, which hinders or negates conductivity; roughening the conductive material during insertion, resulting in openings in the VIA that adversely affect conductivity; and mechanical instability of the conductive material in the via, which adversely affects the conductivity of the VIA, for example, by way of non-limiting example, due to the lack of mechanical support necessary to support the vertical rise of the VIA.

[0026] In embodiments, once the ramp is created, an additive manufacturing method can be used to additively provide a conductive material that provides a conductive path from the first circuit layer to a second or subsequent circuit layer. As a non-limiting example, such a conductive material can be provided by piezoelectric jet printing, inkjet printing, screen printing, or any similar known method suitable for providing the properties discussed herein. As a non-limiting example, the piezoelectric jet printhead provided by Neotech AMT GmbH can be used to jet ink via a piezoelectric actuator based on applying force to the ink, thereby providing an on-demand inkjet nozzle that allows for adjustment of each printed droplet. The ability to adjust the droplets as they are ejected from the printhead allows for precise control of the ink thus printed, which, as understood by those skilled in the art, improves the conductivity and stability provided by the RIA produced in the embodiments. For example, adjusted inkjet printing can allow pre-selected size droplets to fall from a distance of 5 to 30 mm above the printing surface as needed, and can allow the RIA disclosed herein to be printed in three dimensions, depending, for example, on the ink type and other processing factors discussed herein.

[0027] Of course, typical additive manufacturing process parameters can be considered in the implementation and vary depending on the creation of a particular type of RIA, as those skilled in the art will understand from the discussion herein. For example, a piezoelectric jet printer head with a 50-micron / 03 nozzle type can be used, for example, with a printing frequency of 250 Hz.

[0028] Figure 1A cross-sectional view of an exemplary RIA system 10 according to an embodiment is shown. In the illustration, a first layer circuit 12 and a second layer circuit 14 may be disposed in a first plane and a second plane, respectively. As an example, the first layer circuit 12 may be established on any suitable receiving surface, such as a polycarbonate film, and / or may include one or more traces, boards, or plated traces, such as copper-plated traces. The second layer circuit 14 may be disposed on a surface physically disposed on the first layer circuit 12 that does not interfere with the operation of the first layer circuit 12, such as any manufacturing plastic material, such as molded acrylonitrile butadiene styrene (ABS).

[0029] As shown in the figure, a ramp region 16 can be provided from the second layer circuit 14 "downward" to the first layer circuit 12 at a given angle 20. On this ramp region 16, conductive RIA 22 interconnecting the conductive gas components 12a, 14a of the second layer circuit 14 and the first layer circuit 12 can be additively manufactured. Figure 1 As shown in the example, as a non-limiting example, the tilt angle 20 can vary between approximately 45° and 70°. Furthermore, as a non-limiting example, the slope size can be approximately 500 to 1500 micrometers, or more specifically, 800 to 1000 micrometers.

[0030] Figure 2 An isometric view of a first layer circuit 12 and a second layer circuit 14 according to an embodiment is shown. In this figure, the first layer circuit 12 includes conductive traces 102 and surface mount technology (SMT) elements 104 embedded within a molded substrate 106 on which the second layer circuit 14 is provided. In the illustration, a ramp region 110 may be provided, for example by “drilling,” machining, or otherwise removing or creating a triangular region, to provide an angled ramp 110 from the conductive traces on the second layer circuit 120 to the conductive traces 102 on the first layer circuit 12, as shown. A conductive material 122, such as conductive printing ink, is also shown additionally placed along the entire linear distance of the ramp, thereby conductively connecting the second layer trace 120 to the first layer trace 102. As a non-limiting example, the ink used may be silver conductive ink and may be printed by a piezoelectric inkjet printhead, as discussed throughout this document. Additionally, a "target," such as a target conductive disk, can be provided at the bottom of the slope, i.e., at slope point 3 as discussed here, to electrically connect to the first trace 102. This target can provide enhanced connectivity of the conductive material 122 along the slope to the first layer trace 102. It is worth noting that... Figure 1 Connection point 12a can be, for example, such a target.

[0031] Figure 3 A circuit-level view of the RIA 202 according to some embodiments is shown. Furthermore, Figure 3 Including similar Figure 1 The illustration shows that points 1, 2, and 3 along slope 204 can be compared with... Figure 3 Compared to actual points 1, 2, and 3 in the actual circuit 202, the printed material 122 printed "below" the ramp of RIA 202 can be further... Figure 4 In actual circuits, it is seen that it again includes similar components. Figure 1 The illustration actually compares points 1, 2, and 3 along the slope and is a schematic cross-sectional view.

[0032] It is worth noting, especially regarding Figure 4 As illustrated in the exemplary diagram, a sharp edge at ramp point 1, or a very rough surface near point 2 and along the slope of the ramp, could adversely affect the conductivity of the RIA 202. Thus, the ramp along the slope and / or at points near point 2 can have a suitable roughness matching the printing ink used to provide the RIA, thereby maintaining conductivity; and the uppermost region of the RIA, i.e., the ramp at point 1, can be rounded or otherwise smoothed to eliminate sharp edges, thereby preventing cracks, voids, or thin spots in the printing ink when the RIA initially descends from the first-stage circuit to the second-stage circuit.

[0033] Figure 5 An exemplary RIA 402 with a ramp 404 at an angle of approximately 46° is shown. As illustrated, the ink thickness of the RIA 402 can vary at points along the ramp to maintain conductivity. As a non-limiting example, the ink thickness in micrometers at point 1 of the RIA 402 could be, as a non-limiting example, between 25 and 75 micrometers, or more specifically, between 30 and 45 micrometers, thus resolving the aforementioned issue of a sharper edge at the beginning of the RIA at point 1, thereby maintaining conductivity as the RIA slopes downwards. However, at point 2 of the RIA 402, a different thickness in micrometers can be provided, as a non-limiting example, such as a thickness in the range of 10 to 40 micrometers, or more specifically, 20 to 25 micrometers, said varying thickness could be at least partially based on the roughness of the RIA 402 along the ramp surface, and specifically close to point 2.

[0034] As discussed throughout, various additive manufacturing methods can be employed in the embodiments. For example, although jet inks, such as piezoelectric jet inks, have been discussed here by way of specific examples, other additive manufacturing methods, such as screen printing of inks, can also be used. Similarly, as cited throughout, the inks and printing methods employed can depend on the design requirements of a particular embodiment, such as specific requirements for ink thickness on certain surfaces or in certain operating environments, the ability to appropriately handle surface roughness at the top, bottom, or along the ramp, and / or the contact resistance at one or more points along the RIA. For example, for some RIAs, screen-printed inks can provide a resistance of 1.45 ohms / sq, which is acceptable in some embodiments. However, in some cases, jet inks can provide a contact resistance of 1 / 10 to 1 / 20 or less of that contact resistance, which may be necessary in certain embodiments.

[0035] Figure 6 A specific implementation of RIA 502, as discussed herein, is provided. In this figure, flake-like ink is screen-printed onto a polycarbonate film substrate 504 to provide a first layer circuit 506. Elements 510 of the first layer circuit 506 are suitably and electrically bonded to the first layer circuit 506, and end-mold thermoplastic injection molding is used to provide a substrate 512 for an upper plane on which a second layer circuit 514 is provided.

[0036] A machine such as a biaxial C&C machine can process the molding material 512, which provides a plane for the second-layer circuit 514, and can remove the thin layer at once by interpolation along the cut surface to create a ramp 520. Subsequently, a piezoelectric solder jet can distribute silver nanoparticle ink along the ramp 520 before, during, or after screen printing or similar dispensing to create the second-stage circuit 514. The printed RIA may require curing, for example, at 85°C for a given time period, such as 30 minutes.

[0037] Figure 7 The processing 602 of the ramp 604 according to the embodiment is specifically illustrated. As shown, 602 can be processed one thin layer at a time, such that the layer is removed on one side of the processing area at an increased depth compared to the other side. Thus, a ramp 604 on which an RIA can be created is provided.

[0038] Figure 8A and 8B The diagram shows a machined ramp 702 without ink, and the same machined ramp 702 after ink 704 has been printed on it. Specifically regarding... Figure 8BIt is worth noting that as the ink trace 704 is printed down the ramp, its dimensions can vary based on factors discussed throughout this document, as can its thickness. For example, as a non-limiting example, the dimensions and thickness of the trace 704 can vary based on the roughness of the ramp surface, the sharpness of the starting point of the ramp 702 on the second layer circuit 710, and the steepness of the RIA along the angle of the ramp 702 on which it is printed.

[0039] Figure 8C Shown in isometric view Figure 8B The printed RIA. In addition. Figure 8C It includes things like Figure 1 The diagram shows the inserted cross-section, illustrating points 1, 2, and 3 of the RIA after printing, as discussed throughout the document.

[0040] Based on the discussion herein, it will be understood that various modifications can be made to the embodiments without departing from the scope of this disclosure, and such modifications may depend on the design choices made. For example, the curing of the RIA printed ramp traces discussed herein, for instance, can be carried out at 85°C for 30 minutes, as mentioned, and may depend on the use of certain inks, such as silver nanoparticle inks containing 60 weight percent bulk silver. Needless to say, if other inks with other silver or metal contents are used, curing aspects may be varied or avoided. For example, low-temperature curing nanoparticle conductive inks may be required, for instance, to avoid degradation of temperature-sensitive molded components on which a second layer of circuitry is provided. For example, ABS molded components may have a glass transition temperature of 105°C, therefore the curing of the inks used in the RIA must be carried out at a temperature well below this glass transition temperature.

[0041] As can be seen from the detailed description above, various features are often grouped together in a single embodiment for the purposes of clarity and brevity of this disclosure. This approach of the disclosure should not be construed as reflecting an intent that embodiments require more features than explicitly described herein. Rather, this disclosure will cover all variations and modifications to the disclosed embodiments that will be understood by those skilled in the art based on this disclosure.

Claims

1. A ramped electrical interconnect system comprising: a first semiconductor substrate having a first circuit including first electrical components thereon; a second semiconductor substrate at least partially covering the first circuit and having a second circuit including second electrical components thereon; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component, wherein a thickness of the conductive trace is greatest at a plane provided by an uppermost portion of the second semiconductor substrate, a granularity of the conductive trace matches a roughness of the ramp.

2. The system of claim 1, wherein the additively manufactured conductive trace is 3D printed.

3. The system of claim 1, wherein the additively manufactured conductive trace is screen printed.

4. The system of claim 1, wherein the additively manufactured conductive trace includes a nanoparticle conductive ink.

5. The system of claim 1, wherein the second semiconductor substrate includes a molded substrate molded around at least one of the first electrical components. the ramp is formed by one of molding, machining, drilling, and cutting.

6. The system of claim 1, wherein, the ramp is formed by one of laser drilling, laser micromachining, and shape molding.

7. The system of claim 1, wherein, 8. The system of claim 1, wherein the ramp includes a triangular slice removed from the second semiconductor substrate.

9. The system of claim 1, wherein the conductive trace is one of piezoelectric inkjet printing and inkjet printing.

10. The system of claim 1, wherein the conductive trace is formed from modulated inkjet.

11. The system of claim 1, wherein the first semiconductor substrate includes a polycarbonate film.

12. The system of claim 1, wherein the second semiconductor substrate includes a molded acrylonitrile butadiene styrene (ABS).

13. The system of claim 1, wherein the ramp includes an angle between 45° and 70°.

14. The system of claim 1, wherein the ramp size includes a range of 800 microns to 1000 microns.

15. The system of claim 1, wherein at least one of the first electrical components and the second electrical components includes a surface mount technology (SMT) component.

16. The system of claim 1, wherein the conductive trace is rounded at a plane provided by an uppermost portion of the second semiconductor substrate.

17. The system of claim 1, wherein a thickness of the conductive trace varies between 10 microns and 75 microns.

18. The system of claim 1, wherein the conductive trace includes a contact resistance in a range of 0.10 ohms / square and 1.50 ohms / square. ​ 19. The system of claim 1, wherein the conductive traces comprise a silver nanoparticle ink, the silver nanoparticle ink comprising 60 percent by weight of bulk silver.

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