Display device and method of manufacturing the same

Abstract

In a method for manufacturing a display device, a substrate including a display area and a non-display area is prepared, the display area including a plurality of pixel areas, and the non-display area is arranged at the periphery of the display area. A first switching element is formed in each pixel area, and a circuit element layer is formed, the circuit element layer including a reference voltage line arranged in the non-display area and electrically connected to the first switching element. A pixel electrode is formed, the pixel electrode including a first pixel electrode and a second pixel electrode, the first pixel electrode is arranged on the circuit element layer in the pixel area, respectively, and is electrically connected to the reference voltage line through the first switching element, and the second pixel electrode faces the first pixel electrode. A plurality of light-emitting elements are arranged between the first pixel electrode and the second pixel electrode. A first power supply voltage is applied to the reference voltage line and a second power supply voltage is applied to the second pixel electrode to align the light-emitting elements.

Description

Technical Field

[0001] The present disclosure relates to a display device including a light emitting diode and a method of manufacturing the display device. Background Art

[0002] The display device displays high-quality images by using a light-emitting element such as a light-emitting diode as a light source for a pixel. The light-emitting diode exhibits relatively good durability even under harsh environmental conditions and also exhibits excellent lifespan and brightness.

[0003] Recently, research has been conducted on manufacturing micro light-emitting diodes using materials having a highly reliable inorganic crystal structure and arranging them in display panels so that they can be used as next-generation light sources for pixels. As part of this research, micrometer- or nanometer-scale ultra-small light-emitting diodes are being developed to be used as light sources for each pixel of a light-emitting display device. Summary of the invention

[0004] Technical issues

[0005] Aspects of the present disclosure provide a method of manufacturing a display device, by which light emitting elements can be easily aligned and manufacturing efficiency can be improved, and a display device manufactured by the method.

[0006] These and other aspects, embodiments and advantages of the present disclosure will become immediately apparent to those of ordinary skill in the art after reading the following detailed description and claims.

[0007] Technical Solution

[0008] According to one aspect of the present disclosure, a method for manufacturing a display device is provided, the method comprising the following steps: preparing a substrate, the substrate comprising a display area and a non-display area arranged outside the display area, the display area comprising a plurality of pixel areas; forming a first switching element in each of the plurality of pixel areas, and forming a circuit element layer comprising a reference voltage line arranged in the non-display area and electrically connected to the first switching element; forming a pixel electrode, the pixel electrode being arranged on the circuit element layer in each of the plurality of pixel areas, and comprising a first pixel electrode and a second pixel electrode, the first pixel electrode being electrically connected to the reference voltage line through the first switching element, and the second pixel electrode facing the first pixel electrode; arranging a plurality of light-emitting elements between the first pixel electrode and the second pixel electrode; and aligning the plurality of light-emitting elements by applying a first power supply voltage to the reference voltage line and applying a second power supply voltage to the second pixel electrode.

[0009] The method may further include the following steps: forming first contact electrodes respectively arranged on the first ends of the plurality of light-emitting elements, and connecting the plurality of light-emitting elements to the first pixel electrode; and forming second contact electrodes respectively arranged on the second ends of the plurality of light-emitting elements, to connect the plurality of light-emitting elements to the second pixel electrode.

[0010] An etching process may not be performed between the step of aligning the plurality of light emitting elements and the step of forming the first contact electrode.

[0011] The step of aligning the plurality of light emitting elements may include applying a first control signal for turning on the first switching element to a control electrode of the first switching element.

[0012] The circuit element layer may further include a second switching element connected between the first pixel electrode and the first power terminal and a third switching element connected between a control electrode of the second switching element and the data line.

[0013] The step of aligning the plurality of light emitting elements may further include turning on each of the second switching element and the third switching element, a turn-on voltage for turning on the second switching element is applied to the data line, and a first power supply voltage is applied to the first power supply terminal.

[0014] The circuit element layer may further include a capacitor connected between the first pixel electrode and the control electrode of the second switching element.

[0015] The step of aligning the plurality of light emitting elements may further include turning on a third switching element, and wherein the first power supply voltage is applied to the data line.

[0016] The step of forming the pixel electrode may further include forming a first line connected to the reference voltage line and a connection electrode connecting the first line to the first pixel electrode in the non-display area.

[0017] The first power supply voltage may be applied to the reference voltage line through the first line.

[0018] The method may further include removing the connection electrode to separate the first line from the first pixel electrode.

[0019] The circuit element layer may further include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially stacked on one another between the substrate and the display element layer.

[0020] The reference voltage line may include at least one of: a first sub-line, arranged between the third insulating layer and the fourth insulating layer; a second sub-line, arranged between the second insulating layer and the third insulating layer; a third sub-line, arranged between the first insulating layer and the second insulating layer; and a fourth sub-line, arranged between the substrate and the first insulating layer.

[0021] The first line may include a first sub voltage line disposed on the circuit element layer and directly connected to the reference voltage line and a second sub voltage line disposed on the first sub voltage line, and the conductivity of the second sub voltage line may be greater than that of the first sub voltage line.

[0022] The step of forming the circuit element layer may include forming a scan signal line connected to a control electrode of the first switching element and a first dummy switching element connecting the scan signal line to a dummy line in the non-display area.

[0023] The step of aligning the light emitting element may include: applying a turn-on voltage for turning on the first switching element to the dummy line; and turning on the first dummy switching element.

[0024] The circuit element layer may further include a second dummy switch element connecting the scan signal line with an adjacent scan signal line, and wherein aligning the plurality of light emitting elements further includes turning on the second dummy switch element.

[0025] According to another aspect of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area and a non-display area arranged outside the display area, the display area including a plurality of pixel areas; a circuit element layer including a first switching element formed in each of the plurality of pixel areas, a reference voltage line arranged in the non-display area and electrically connected to the first switching element, and a scanning line connected to a control electrode of the first switching element; and a display element layer including a first pixel electrode, a second pixel electrode, and a plurality of light emitting elements, the first pixel electrode being arranged on the circuit element layer in each of the plurality of pixel areas and being electrically connected to the reference voltage line through the first switching element, the second pixel electrode being arranged to face the first pixel electrode, and the plurality of light emitting elements being arranged between the first pixel electrode and the second pixel electrode. The circuit element layer also includes a dummy line formed in the non-display area and a first dummy switching element connected between the dummy line and the scanning line.

[0026] The circuit element layer may further include a second dummy switching element connecting the scan line with an adjacent scan line.

[0027] According to another aspect of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area and a non-display area arranged outside the display area, the display area including a plurality of pixel areas; a circuit element layer including a circuit element arranged in each of the plurality of pixel areas, and a reference voltage line arranged in the non-display area and electrically connected to the circuit element; and a display element layer including a first pixel electrode, a second pixel electrode, and a plurality of light emitting elements, the first pixel electrode being arranged on the circuit element layer in each of the plurality of pixel areas, the second pixel electrode being arranged to face the first pixel electrode, and the plurality of light emitting elements being arranged between the first pixel electrode and the second pixel electrode. The second pixel electrode surrounds the first pixel electrode.

[0028] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0029] Beneficial Effects

[0030] According to an exemplary embodiment of the present disclosure, an alignment voltage is applied through a reference voltage line connected to a pixel electrode in a display device, so that a process of forming an additional alignment line can be omitted. As a result, the efficiency of manufacturing the display device can be improved.

[0031] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a plan view schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0033] Figure 2 and Figure 3 is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0034] Figure 4 It is shown along Figure 3 A cross-sectional view of an example of a display device taken along lines AA′ and BB′.

[0035] Figures 5 to 9 It shows that along Figure 3 sectional views of various examples of the display device taken along lines AA′ and BB′.

[0036] Fig.10 It is shown Figure 1 A perspective view of an example of a light emitting diode included in a display device.

[0037] Fig.11 It is shown Figure 1A circuit diagram of an example of a display device.

[0038] Fig.12 It is shown Fig.11 A circuit diagram of an example of one pixel among pixels included in a display device of FIG.

[0039] Fig.13 It is shown Fig.11 FIG. 1 is a diagram of an example of a data driver included in a display device.

[0040] Fig.14 is shown applied to Fig.12 FIG. 1 is a waveform diagram of an example of a signal of a pixel.

[0041] Fig.15 It shows that the setting Fig.14 A circuit diagram of an example of a pixel in a pixel area included in a display device.

[0042] Fig.16 and Fig.17 It is shown Fig.14 Circuit diagrams of other examples of pixels included in a display device.

[0043] Fig.18 It is shown in Fig.17 Graph showing an example waveform of a signal measured in a pixel of FIG.

[0044] Fig.19 and Fig. 20 It is shown Figure 1 Circuit diagrams of other examples of display devices.

[0045] Fig.21 It is shown Fig.19 A circuit diagram of an example of one pixel among pixels included in a display device of FIG.

[0046] Fig. 22 It is shown Fig.19 A circuit diagram of an example of a scan driver included in a display device of FIG.

[0047] Fig.23 It is shown Fig.19 0 is a circuit diagram of another example of a display device shown in FIG.

[0048] Figure 24 to Figure 26 It is shown Figure 2 1 and 2 are plan views of other examples of display devices.

[0049] Figures 27 to 34 is a diagram showing various exemplary embodiments Figure 1 FIG. 1 is a diagram of pixels included in a display device.

[0050] Fig.35is a flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The advantages and features of the present disclosure and the methods for achieving them will become apparent through the following description of exemplary embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. Exemplary embodiments are provided to make the disclosure of the present disclosure thorough and to fully convey the scope of the present disclosure to those skilled in the art. It will be noted that the scope of the present disclosure is limited only by the claims.

[0052] As used herein, the phrase “element A on element B” means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Like reference numerals denote like elements throughout the specification.

[0053] Although terms such as "first", "second", etc. are used to arbitrarily distinguish between the elements described by such terms, these terms are not necessarily intended to indicate the time or other priority of such elements. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical scope of the present disclosure, a first element may be a second element.

[0054] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0055] Figure 1 is a plan view schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0056] Reference Figure 1 , the display device 100 may include a substrate SUB and pixels PXL disposed on the substrate SUB.

[0057] The substrate SUB (or the display device 100) may include a display area DA and a non-display area NDA. In the display area DA, an image may be displayed. In the non-display area NDA, an image may not be displayed. The display area DA may be disposed at a central area of ​​the display device 100, and the non-display area NDA may be disposed outside the display area DA to surround the display area DA, or may be disposed at an edge of the display device 100. However, it will be understood that the present disclosure is not limited thereto. For example, the non-display area NDA may be disposed only on one side of the display area DA.

[0058] The substrate SUB may be a rigid substrate or a flexible substrate, and its material or physical properties are not particularly limited here. For example, the substrate SUB may be a rigid substrate made of glass or tempered glass, or a flexible substrate implemented as a film made of plastic or metal.

[0059] The pixel PXL may be disposed in the display area DA on the substrate SUB. The substrate SUB (or the display area DA) may include a plurality of pixel areas, and the pixels PXL may be formed in the pixel areas, respectively. In the non-display area NDA, lines connected to the pixels PXL in the display area DA and / or circuits embedded therein may be disposed.

[0060] The pixel PXL may include a circuit element and a plurality of light emitting diodes LD. The circuit element may transmit a current (or a driving current) to the light emitting diode LD in response to a scan signal and a data signal provided externally, and the light emitting diode LD may emit light having a brightness proportional to the magnitude of the current. The light emitting diode LD may have a size in the micrometer or nanometer scale, may have a rod-like shape, and may be connected in parallel to each other. Fig.10 The configuration of the light emitting diode LD is described in detail.

[0061] Figure 2 and Figure 3 is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0062] Reference Figure 2 , the display device 100 may include a sensing line SSL, a reference voltage line L_VINT, first and second pixel electrodes ELT1 and ELT2 , and a second line AL2 .

[0063] The sensing line SSL may extend in the second direction D2 and may be disposed across (or through) the display area DA.

[0064] The reference voltage line L_VINT may extend in the first direction D1 in the non-display area NDA of the display device 100. The reference voltage line L_VINT may be connected to the sensing line SSL, and the reference voltage line L_VINT may be integrally formed with the sensing line SSL.

[0065] The second pixel electrode ELT2 may extend in the second direction D2 in the display area DA and may be disposed across the plurality of pixel areas PXA. The second pixel electrode ELT2 may include branch electrodes protruding in the first direction D1 in the pixel area PXA.

[0066] The first pixel electrodes ELT1 may be disposed in the pixel area PXA to face the second pixel electrodes ELT2, respectively. The first pixel electrodes ELT1 may be spaced apart from the branch electrodes by a certain distance and may extend along edges of the branch electrodes.

[0067] like Figure 2 As shown in , the second pixel electrode ELT2 may have a “T” shape when viewed from the top, and the first pixel electrode ELT1 may have a “concave” (or “U”) shape surrounding the “T” shape when viewed from the top.

[0068] The second line AL2 may extend in the first direction D1 in the non-display area NDA and may be connected to the second pixel electrode ELT2. The second line AL2 and the second pixel electrode ELT2 may be integrally formed through the same process.

[0069] The first pixel electrode ELT1 may be electrically connected to a reference voltage line L_VINT (or a sensing line SSL).

[0070] During the process of aligning the light emitting diode LD, the first pixel electrode ELT1 is electrically connected to the reference voltage line L_VINT (or the sensing line SSL), and thus a first alignment voltage (e.g., a ground voltage) may be applied to the first pixel electrode ELT1 through the reference voltage line L_VINT. In addition, a second alignment voltage (e.g., an AC voltage) may be applied to the second pixel electrode ELT2 through the second line AL2. An electric field may be generated between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the pixel area PXA, and the light emitting diode LD may be aligned by the electric field.

[0071] Despite Figure 2 In the example shown in FIG. 1 , the display device 100 includes the second line AL2, but the present disclosure is not limited thereto. Figure 3 As shown in , the display device 100_1 may further include a first line AL1. The first line AL1 may be disposed in a non-display area NDA on an opposite side of the second line AL2 relative to the display area DA. The first line AL1 may be formed integrally with the first pixel electrode ELT1 via the same process. The first line AL1 may overlap with the reference voltage line L_VINT or be disposed adjacent to the reference voltage line L_VINT, and may be connected in parallel with the reference voltage line L_VINT through a first contact hole CNT1. Therefore, the resistance of the reference voltage line L_VINT may be reduced, the drop in the voltage (e.g., alignment voltage, reference voltage, etc.) applied to the reference voltage line L_VINT may be reduced, and the light emitting diode LD may be aligned more effectively.

[0072] By the way, after the light emitting diode LD is arranged between the first pixel electrode ELT1 and the second pixel electrode ELT2 based on the alignment voltage applied through the reference voltage line L_VINT and the second line AL2, no additional process may be required for the first pixel electrode ELT1 and the second pixel electrode ELT2. In other words, the first pixel electrode ELT1 and the second pixel electrode ELT2 may be formed via a single process (e.g., an etching process using one mask) instead of multiple processes. As a result, the process of manufacturing the display device 100 may be simplified, and manufacturing efficiency may be improved.

[0073] Figure 4 It is shown along Figure 3 A cross-sectional view of an example of a display device taken along lines AA′ and BB′. Figures 5 to 9 It is shown along Figure 3 sectional views of various examples of the display device taken along lines AA′ and BB′.

[0074] First, refer to Figure 3 and Figure 4 The circuit element layer PCL and the display element layer LDL are sequentially disposed on the substrate SUB in the display area DA. For example, the circuit element layer PCL may be formed on one surface of the substrate SUB, and the display element layer LDL may be formed on the circuit element layer PCL.

[0075] The circuit element layer PCL includes circuit elements disposed in the display area DA. The circuit element layer PCL may include circuit elements formed in the pixel areas PXA, respectively, to form a pixel circuit PXC. For example, the circuit element layer PCL may include at least one transistor T and a storage capacitor Cst disposed in each of the pixel areas PXA.

[0076] Despite Figure 4 In the example shown in FIG. 1 , the pixel PXL includes only one transistor T, but this is merely illustrative. The pixel PXL may include a plurality of transistors, and these transistors may have a cross-sectional structure substantially the same as or similar to the cross-sectional structure of the transistor T. In addition, the structure of the transistor T is not limited to Figure 4 For example, the transistor T may have various cross-sectional structures known in the art. The transistors forming the pixel circuit PXC may have different types and / or structures.

[0077] The circuit element layer PCL includes a plurality of insulating layers. The circuit element layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4 sequentially stacked on a surface of a substrate SUB. The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may be sequentially stacked on each other between the substrate SUB and the display element layer LDL. In addition, the circuit element layer PCL may further include at least one buffer layer BFL disposed between the substrate SUB and the circuit element. At least one of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 and the buffer layer BFL may be formed on a surface of the substrate SUB including the display area DA and the non-display area NDA.

[0078] The buffer layer BFL may prevent impurities from diffusing in the transistor T. The buffer layer BFL may be composed of a single layer or a multilayer of two or more layers. When the buffer layer BFL is composed of a plurality of layers, the layers may be made of the same material or different materials. The buffer layer BFL may be removed.

[0079] The transistor T includes a semiconductor layer SCL, a gate electrode GE, a first electrode ET1, and a second electrode ET2. Figure 4 In the example shown in FIG, the transistor T includes a first electrode ET1 and a second electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, the first electrode ET1 and / or the second electrode ET2 of at least one transistor T disposed in the pixel area PXA may be integrated with the semiconductor layer SCL.

[0080] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may be disposed between the substrate SUB on which the buffer layer BFL is formed and the first insulating layer INS1. The semiconductor layer SCL may include a first region in contact with the first electrode ET1, a second region in contact with the second electrode ET2, and a channel region between the first region and the second region. One of the first region and the second region may be a source region, and the other may be a drain region.

[0081] The semiconductor layer SCL may be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the semiconductor layer SCL may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities, and each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined certain impurities.

[0082] The gate electrode GE may be disposed on the semiconductor layer SCL with the first insulating layer INS1 interposed therebetween. For example, the gate electrode GE may be disposed between the first insulating layer INS1 and the second insulating layer INS2 and may overlap at least one region of the semiconductor layer SCL.

[0083] The first electrode ET1 and the second electrode ET2 may be disposed on the semiconductor layer SCL, and at least one insulating layer (e.g., a plurality of insulating layers) may be disposed between the first electrode ET1 and the second electrode ET2 and the semiconductor layer SCL. For example, the first electrode ET1 and the second electrode ET2 may be disposed between the third insulating layer INS3 and the fourth insulating layer INS4. The first electrode ET1 and the second electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, the first electrode ET1 and the second electrode ET2 may contact the first region and the second region of the semiconductor layer SCL through contact holes penetrating the first insulating layer INS1 to the third insulating layer INS3, respectively.

[0084] One of the first electrode ET1 and the second electrode ET2 may be electrically connected to the first pixel electrode ELT1 disposed on the fourth insulating layer INS4 through at least one contact hole penetrating the fourth insulating layer INS4 .

[0085] The storage capacitor Cst may include a first capacitor electrode CSE1 and a second capacitor electrode CSE2 disposed on different layers and spaced apart from each other. The first capacitor electrode CSE1 may be disposed between the second insulating layer INS2 and the third insulating layer INS3. The second capacitor electrode CSE2 may be disposed on the same layer as at least one conductive layer forming the transistor T (e.g., the semiconductor layer SCL, the gate electrode GE, and at least one of the first electrode ET1 and the second electrode ET2). For example, the second capacitor electrode CSE2 may be disposed between the first insulating layer INS1 and the second insulating layer INS2 together with the gate electrode GE of the transistor T.

[0086] Although for ease of explanation, Figure 4 In the example shown in FIG. 1 , each of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 is composed of a single layer, but the present disclosure is not limited thereto. For example, at least one of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be composed of multiple layers. The stacking structure and / or position of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be changed in various ways.

[0087] According to an exemplary embodiment of the present disclosure, the display element layer LDL may include a plurality of light emitting diodes LD disposed in the display area DA over the circuit element layer PCL. For example, the display element layer LDL may include light emitting diodes LD formed over the circuit element layer PCL in each pixel area PXA and constituting light emitting units.

[0088] Although for ease of explanation, Figure 4 Only one light emitting diode LD is shown in the figure, but a plurality of light emitting diodes LD may be disposed inside the pixel area PXA. In addition, in the pixel area PXA, the light emitting diodes LD may be disposed on substantially the same layer and may have the same or similar cross-sectional structure and / or connection structure. In addition, the structure and arrangement of the light emitting diodes LD are not limited to Figure 4 For example, the light emitting diode LD may have various cross-sectional structures and / or connection structures known in the art.

[0089] The display element layer LDL may include a first pixel electrode ELT1 and a second pixel electrode ELT2 disposed in each of the pixel areas PXA, a light emitting diode LD disposed between the first pixel electrode ELT1 and the second pixel electrode ELT2 facing each other, and a first contact electrode CNE1 and a second contact electrode CNE2 disposed on a first end EP1 and a second end EP2 of each of the light emitting diodes LD. In addition, the display element layer LDL may further include at least one conductive layer and / or an insulating layer. The display element layer LDL may further include at least one of a first partition wall PW1 and a second partition wall PW2, a first cover layer CPL1 and a second cover layer CPL2, and a fifth insulating layer INS5 to a seventh insulating layer INS7.

[0090] The first partition wall PW1 and the second partition wall PW2 may be disposed on the fourth insulating layer INS4 of the circuit element layer PCL. The first partition wall PW1 and the second partition wall PW2 may be disposed on the fourth insulating layer INS4 so that they are spaced apart from each other by a predetermined distance. The first partition wall PW1 and the second partition wall PW2 may define an emission region in each of the pixel regions PXA.

[0091] Each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material including an inorganic material or an organic material, but the constituent materials forming the first partition wall PW1 and the second partition wall PW2 are not limited thereto. Each of the first partition wall PW1 and the second partition wall PW2 has a trapezoidal shape having a side surface inclined at a certain angle, but the shapes of the first partition wall PW1 and the second partition wall PW2 are not limited thereto. For example, Fig. 9 As shown in FIG. 1 , each of the first partition wall PW1 and the second partition wall PW2 may have a semi-elliptical shape, or may have various shapes such as a circle and a square.

[0092] The first and second pixel electrodes ELT1 and ELT2 may be disposed in the pixel area PXA provided with the first and second partition walls PW1 and PW2 and may be spaced apart from each other by a predetermined distance.

[0093] The first pixel electrode ELT1 may be disposed on the first partition wall PW1, and the second pixel electrode ELT2 may be disposed on the second partition wall PW2. One of the first pixel electrode ELT1 and the second pixel electrode ELT2 may be an anode electrode, and the other may be a cathode electrode.

[0094] The first pixel electrode ELT1 and the second pixel electrode ELT2 may have shapes consistent with those of the first partition wall PW1 and the second partition wall PW2. For example, the first pixel electrode ELT1 may have a slope equal to that of the first partition wall PW1, and the second pixel electrode ELT2 may have a slope equal to that of the second partition wall PW2.

[0095] In addition, the first pixel electrode ELT1 and the second pixel electrode ELT2 may be arranged on the same plane and may have the same height. When the first pixel electrode ELT1 and the second pixel electrode ELT2 have the same height, the light emitting diode LD may be more stably connected between the first pixel electrode ELT1 and the second pixel electrode ELT2. However, it will be understood that the present disclosure is not limited thereto. The shape, structure and / or arrangement relationship of the first pixel electrode ELT1 and the second pixel electrode ELT2 may be changed in various ways.

[0096] The first pixel electrode ELT1 and the second pixel electrode ELT2 may be, but are not limited to, reflective electrodes. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 may be made of a conductive material having reflectivity. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 may include, but are not limited to, at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and an alloy), a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), and a conductive polymer such as PEDOT. In addition, each of the first pixel electrode ELT1 and the second pixel electrode ELT2 may be composed of a single layer or a multilayer, and its stacking structure is not limited thereto.

[0097] The first pixel electrode ELT1 and the second pixel electrode ELT2 may guide light emitted from both ends EP1 and EP2 of each of the light emitting diodes LD toward a side on which an image is displayed (e.g., toward the front side of the display device 100). When the first pixel electrode ELT1 and the second pixel electrode ELT2 have an inclination consistent with the shape of the first partition wall PW1 and the second partition wall PW2, light emitted from both ends EP1 and EP2 of the light emitting diode LD may be reflected by the first pixel electrode ELT1 and the second pixel electrode ELT2 to proceed toward the front side. Therefore, the efficiency of light emitted from the light emitting diode LD may be improved.

[0098] In addition, the first and second partition walls PW1 and PW2 may also function as reflective members that improve efficiency of light emitted from each of the light emitting diodes LD together with the first and second pixel electrodes ELT1 and ELT2 disposed thereon.

[0099] The first cover layer CPL1 and the second cover layer CPL2 may be disposed in the pixel area PXA where the first pixel electrode ELT1 and the second pixel electrode ELT1 are disposed. For example, the first cover layer CPL1 may be disposed on the first pixel electrode ELT1 to cover the first pixel electrode ELT1, and the second cover layer CPL2 may be disposed on the second pixel electrode ELT2 to cover the second pixel electrode ELT2.

[0100] The first cover layer CPL1 and the second cover layer CPL2 may be made of a transparent conductive material such as IZO to reduce the loss of light emitted from each of the light emitting diodes LD. However, it will be understood that the present disclosure is not limited thereto. The constituent materials of the first cover layer CPL1 and the second cover layer CPL2 may be changed.

[0101] The first cover layer CPL1 and the second cover layer CPL2 can prevent the first pixel electrode ELT1 and the second pixel electrode ELT2 from being damaged due to defects occurring during the process of manufacturing the light-emitting display device, and can enhance the adhesion between the first pixel electrode ELT1 and the second pixel electrode ELT2 and the circuit element layer PCL. However, it will be understood that at least one of the first cover layer CPL1 and the second cover layer CPL2 may be removed.

[0102] The first insulating pattern INP1 may be disposed in the pixel area PXA in which the first cover layer CPL1 and the second cover layer CPL2 are disposed. The first insulating pattern INP1 may be disposed between the circuit element layer PCL and each of the light emitting diodes LD, and may cover a certain area of ​​the first cover layer CPL1 and the second cover layer CPL2. The first insulating pattern INP1 may stably support the light emitting diode LD and may prevent the light emitting diode LD from shifting. The first insulating pattern INP1 may be formed simultaneously with one of the insulating layers formed in the display element layer LDL, or may be formed independently.

[0103] The light emitting diodes LD may be supplied and aligned in the pixel region PXA provided with the first insulating pattern INP1, etc. The light emitting diodes LD are guided so that they are self-aligned by an electric field formed between the first pixel electrode ELT1 and the second pixel electrode ELT2, and may be arranged between the first pixel electrode ELT1 and the second pixel electrode ELT2 of the pixel region PXA.

[0104] The second insulating pattern INP2 may be disposed in the pixel area PXA provided with the light emitting diode LD to cover a portion of the upper surface of the light emitting diode LD. The second insulating pattern INP2 may be formed simultaneously with one of the insulating layers formed in the display element layer LDL, or may be formed independently.

[0105] The fifth insulating layer INS5 may be formed on a portion of the upper surface of the first capping layer CPL1. The fifth insulating layer INS5 may be formed simultaneously with one of the first insulating pattern INP1 and the second insulating pattern INP2, or may be formed independently. The fifth insulating layer INS5 may be removed.

[0106] The first contact electrode CNE1 may be disposed in the pixel area PXA provided with the second insulating pattern INP2, the fifth insulating layer INS5, etc. The first contact electrode CNE1 may cover the first cover layer CPL1, and may be electrically connected to the first pixel electrode ELT1 through the first cover layer CPL1. When the first cover layer CPL1 is removed, the first contact electrode CNE1 may be directly disposed on the first pixel electrode ELT1, and may be directly connected to the first pixel electrode ELT1. In addition, the first contact electrode CNE1 may cover the first end EP1 of at least one light emitting diode LD disposed in the pixel area PXA, and may connect the first end EP1 of at least one light emitting diode LD to each first pixel electrode ELT1.

[0107] The sixth insulating layer INS6 may be disposed on the first contact electrode CNE1 in the pixel area PXA. The sixth insulating layer INS6 may be disposed to cover the first contact electrode CNE1 and the fifth insulating layer INS5.

[0108] The second contact electrode CNE2 may be disposed in the pixel region PXA provided with the sixth insulating layer INS6 and the like. The second contact electrode CNE2 may cover the second cover layer CPL2 and may be electrically connected to the second pixel electrode ELT2 through the second cover layer CPL2. When the second cover layer CPL2 is removed, the second contact electrode CNE2 may be directly disposed on the second pixel electrode ELT2 and may be directly connected to the second pixel electrode ELT2. In addition, the second contact electrode CNE2 may cover the second end EP2 of at least one light emitting diode LD disposed in the pixel region PXA and may connect the second end EP2 of the at least one light emitting diode LD to the second pixel electrode ELT2.

[0109] The seventh insulating layer INS7, the overcoat layer OC, etc. may be disposed in the pixel area PXA provided with the second contact electrode CNE2, etc. According to an exemplary embodiment, the seventh insulating layer INS7 may be disposed on a surface of the substrate SUB including the display area DA and the non-display area NDA, and the overcoat layer OC may cover an upper surface of the seventh insulating layer INS7.

[0110] The reference voltage line L_VINT and the first line AL1 (and the second line AL2) may be disposed in the non-display area NDA. The reference voltage line L_VINT may be disposed in the non-display area NDA on the substrate SUB, and the first line AL1 may be disposed to overlap the reference voltage line L_VINT.

[0111] Initially, the first line AL1 may be disposed on the fourth insulating layer INS4 of the circuit element layer PCL. The first line AL1 may be disposed on the same layer as at least one of the first pixel electrode ELT1 and the second pixel electrode ELT2. During the process of forming the first pixel electrode ELT1 and the second pixel electrode ELT2, the first line AL1 may be formed on the same layer as the first pixel electrode ELT1 and the second pixel electrode ELT2.

[0112] The first line AL1 may be disposed on the same layer as at least one of the first and second capping layers CPL1 and CPL2 and the first and second contact electrodes CNE1 and CNE2. The first line AL1 may be formed on the same layer as the first and second capping layers CPL1 and CPL2 during a process of forming the first and second capping layers CPL1 and CPL2, or may be formed on the same layer as the first and second contact electrodes CNE1 and CNE2 during a process of forming the contact electrodes CNE1 and CNE2.

[0113] The first line AL1 may have a multi-layer structure including electrodes disposed on different layers and a conductive layer disposed on the same layer among the first pixel electrode ELT1 and the second pixel electrode ELT2, the first cap layer CPL1 and the second cap layer CPL2, and the first contact electrode CNE1 and the second contact electrode CNE2. Figure 8 As shown in FIG. 1 , the first line AL1 may include a first conductive line AL1a and a second conductive line AL1b disposed to overlap the first conductive line AL1a. The first conductive line AL1a may be disposed on the same layer as the first pixel electrode ELT1 and the second pixel electrode ELT2 or the first cover layer CPL1 and the second cover layer CPL2. The second conductive line AL1b may be disposed on the same layer as the first cover layer CPL1 and the second cover layer CPL2 or the first contact electrode CNE1 and the second contact electrode CNE2.

[0114] The reference voltage line L_VINT may be disposed on the same layer as at least one electrode formed in the circuit element layer PCL.

[0115] For example, Figure 4 As shown in FIG, the reference voltage line L_VINT may include a first sub-line SUL1 disposed between the third insulating layer INS3 and the fourth insulating layer INS4 together with the first electrode ET1 of the transistor T. In this case, the first line AL1 may contact the first sub-line SUL1 through a first contact hole CNT1 penetrating the fourth insulating layer INS4.

[0116] As another example, the reference voltage line L_VINT may further include a second sub-line SUL2 (eg, a second sub-line SUL2 disposed between the second insulating layer INS2 and the third insulating layer INS3 together with the first capacitor electrode CSE1. Figure 5 ), or may include a third sub-line SUL3 (as shown in FIG. 1 ) disposed between the first insulating layer INS1 and the second insulating layer INS2 together with the second capacitor electrode CSE2 and the gate electrode GE of the transistor T. Figure 6 As another example, Figure 7 As shown in FIG. 1 , the reference voltage line L_VINT may include a fourth sub-line SUL4 disposed between a buffer layer BFL and a first insulating layer INS1 on a substrate SUB together with a semiconductor layer SCL of a transistor T. As shown in FIG.

[0117] The reference voltage line L_VINT may have a multilayer structure including at least two of the following: a first sub-line SUL1 disposed between the third insulating layer INS3 and the fourth insulating layer INS4 among the sub-lines of each of the first line AL1 and the second line AL2, a second sub-line SUL2 disposed between the second insulating layer INS2 and the third insulating layer INS3, a third sub-line SUL3 disposed between the first insulating layer INS1 and the second insulating layer INS2, and a fourth sub-line SUL4 disposed between the substrate SUB and the first insulating layer INS1.

[0118] As mentioned above Figures 4 to 9 As described, the reference voltage line L_VINT and the first line AL1 may be disposed on the substrate SUB in the non-display area NDA, and may have a single-layer structure or a multi-layer structure. Therefore, the resistance of the reference voltage line L_VINT and the first line AL1 may be reduced, and the drop of the alignment voltage applied during the process of aligning the light emitting diode LD may also be prevented. As a result, the light emitting diode LD may be aligned more effectively. In addition, the drop of the reference voltage applied when driving the display device 100 may be prevented, so that the characteristic information of the pixel PXL may be obtained more accurately.

[0119] Fig.10 It is shown Figure 1 A perspective view of an example of a light emitting diode included in a display device.

[0120] Reference Fig.10 The light emitting diode LD may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. The light emitting diode LD may be configured as a stacked body in which the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 are stacked on each other in this order.

[0121] The light emitting diode LD may have a rod-like shape extending in one direction. Here, the direction along which the light emitting diode LD extends is referred to as a length direction. The light emitting diode LD may have a first end and a second end along the length direction.

[0122] One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at a first end of the light emitting diode LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at a second end of the light emitting diode LD.

[0123] The light emitting diode LD can be manufactured in a rod-like shape. As used herein, the term "rod-like shape" includes a rod-like shape or a strip-like shape that is longer in the longitudinal direction (i.e., an aspect ratio greater than 1), such as a cylinder and a polygonal prism. However, it will be understood that the shape of the cross section is not particularly limited here. For example, the length of the light emitting diode LD may be greater than its diameter (or the width of the cross section).

[0124] The light emitting diode LD may have a micrometer-scale or nanometer-scale size, for example, a micrometer-scale or nanometer-scale diameter and / or length. It will be noted that the size of the light emitting diode LD is not limited thereto. For example, the size of the light emitting diode LD may vary according to the design conditions of the light emitting display device using the light emitting diode LD.

[0125] The first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant such as Si, Ge, and Sn. It will be noted that the constituent material of the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may include various materials.

[0126] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and may be formed as a single quantum well structure or a multi-quantum well structure. A cladding layer (not shown) doped with a conductive dopant may be formed on the active layer 12 and / or below the active layer 12. For example, the cladding layer may be formed as an AlGaN layer or an InAlGaN layer. The active layer 12 may be formed using materials such as AlGaN and AlInGaN, and various other materials may form the active layer 12.

[0127] When an electric field of a voltage equal to or higher than a predetermined level is applied across the light emitting diode LD, electron-hole pairs are generated in the active layer 12 to allow the light emitting diode LD to emit light. The light emitting diode LD can be used as a light source for a pixel by controlling the emission of the light emitting diode LD.

[0128] The second conductive semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. The second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg. It will be noted that the constituent material of the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may include various materials.

[0129] The light emitting diode LD may further include additional elements in addition to the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13. The light emitting diode LD may further include at least one phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer disposed on and / or below the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13.

[0130] In addition, the light emitting diode LD may further include an insulating film 14. The insulating film 14 may be formed to surround at least the outer peripheral surface of the active layer 12, and may also surround at least a portion of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13.

[0131] It will be noted that in order to clearly illustrate the stacked structure of the light emitting diodes LD, Fig.10 The insulating film 14 is partially removed. The insulating film 14 may completely cover the peripheral surface (e.g., the side surface of the cylinder) of the light emitting diode LD except for the two ends. Alternatively, the insulating film 14 may only cover a portion of the side surface of the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13. In addition, the insulating film 14 may be removed.

[0132] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include, but is not limited to, a material made of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 That is, the insulating film 14 can be made of any one of various insulating materials known in the art.

[0133] When the light emitting diode LD includes the insulating film 14, it is possible to prevent the active layer 12 of the light emitting diode LD from being electrically connected to the first pixel electrode ELT1 and the second pixel electrode ELT2 described above (see FIG. Figure 4 ). Therefore, the electrical stability of the light emitting diode LD can be ensured. In addition, since the surface defects of the light emitting diode LD are reduced, the life and efficiency of the light emitting diode LD can be improved. In addition, even when the light emitting diodes LD are arranged close to each other, it is possible to prevent an undesired short circuit between the light emitting diodes LD.

[0134] The light emitting diode LD can be used as a light source in various types of display devices including light emitting display devices. For example, by arranging at least one light emitting diode LD in each pixel area of ​​the display panel, a light emitting unit of each pixel can be formed. It will be noted that the light emitting diode LD can find more applications besides display devices. For example, the light emitting diode LD can also be used in other types of light emitting devices that require a light source, such as an illuminator.

[0135] Despite Fig.10 The light emitting diode LD is a rod-shaped light emitting diode having a cylindrical shape in the example shown in FIG. 1 , but this is merely illustrative. The type and / or shape of the light emitting diode LD is not limited thereto.

[0136] Hereinafter, the function of the reference voltage line L_VINT when driving the display device 100 and during a process of manufacturing the display device 100 (eg, a process of aligning the light emitting diode LD) will be described.

[0137] Fig.11 It is shown Figure 1 A circuit diagram of an example of a display device. Fig.12 It is shown Fig.11 A circuit diagram of an example of one pixel among pixels included in a display device of FIG. Fig.13 It is shown Fig.11 FIG. 1 is a diagram of an example of a data driver included in a display device. Fig.14 is shown applied to Fig.12 FIG. 1 is a waveform diagram of an example of a signal of a pixel.

[0138] First refer to Figure 1 , Figure 2 and Fig.11 , the display device 100 may include a display panel 110, a data driver 120, a timing controller 130, a scan driver 140, and a power source (not shown).

[0139] The display panel 110 may include data lines DL1 to DLm, scan lines SL1 to SLn, sensing lines SSL1 to SSLm, and sensing control lines L1 to Ln, where m and n are integers greater than 1. The data lines DL1 to DLm and the sensing lines SSL1 to SSLm may extend in the first direction D1 and may be arranged in the second direction D2. The scan lines SL1 to SLn and the sensing control lines L1 to Ln may extend in the second direction D2 and may be arranged in the first direction D1. The pixel PXL may be disposed at a position where the data lines DL1 to DLm, the scan lines SL1 to SLn, the sensing lines SSL1 to SSLm, and the sensing control lines L1 to Ln cross each other. The pixel PXL may be connected to one of the data lines DL1 to DLm, one of the scan lines SL1 to SLn, one of the sensing lines SSL1 to SSLm, and one of the sensing control lines L1 to Ln. In addition, the pixel PXL may receive a first power supply voltage VDD and a second power supply voltage VSS.

[0140] The data driver 120 may be connected to the display panel 110 through the data lines DL1 to DLm and the sensing lines SSL1 to SSLm. The data driver 120 may provide data signals to the pixels PXL through the data lines DL1 to DLm under the control of the timing controller 130. In addition, the data driver 120 may provide a reference voltage VINT to the pixels PXL through the sensing lines SSL1 to SSLm, and may receive a sensing current from the pixels PXL through the sensing lines SSL1 to SSLm.

[0141] The timing controller 130 may receive a control signal CS and image signals R, G, and B from an external system. The control signal CS may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and the like. The image signals R, G, and B may contain brightness information of the pixel PXL, and the brightness may have 1024, 256, or 64 gray levels. The timing controller 130 may divide the image signals R, G, and B by frame in response to the vertical synchronization signal (Vsync), and may divide the image signals R, G, and B by scan line in response to the horizontal synchronization signal (Hsync), thereby generating image data DATA. The timing controller 130 may provide control signals CONT1 and CONT2 to the data driver 120 and the scan driver 140, respectively, according to the control signal CS and the image signals R, G, and B. The timing controller 130 may provide the image data DATA together with the control signal CONT1 to the data driver 120, and the data driver 120 may sample and hold the input image data DATA in response to the control signal CONT1, and convert it into an analog voltage to generate a data signal. Subsequently, the data driver 120 may provide the data signal to the pixel PXL through the data lines DL1 to DLm. The timing controller 130 may control the sensing switches SW1 and SW2 to SWm (see Fig.13 ) of the switch operation switch control signal to Provided to the data driver 120.

[0142] The scan driver 140 may be connected to the display panel 110 through the scan lines SL1 to SLn and the sensing control lines L1 to Ln. The scan driver 140 may sequentially apply scan signals to the scan lines SL1 to SLn in response to the control signal CONT2 provided from the timing controller 130. During a sensing period, the scan driver 140 may provide a sensing signal to the pixel PXL through the sensing lines L1 to Ln to measure a current of the pixel PXL.

[0143] A power supply (not shown) may supply a driving voltage to the pixel PXL in response to a control signal received from the timing controller 130. The driving voltage may include a first power voltage VDD and a second power voltage VSS, and the first power voltage VDD may have a higher level than the second power voltage VSS.

[0144] Reference Fig.12 , the pixel PXL may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and a light emitting diode LD.

[0145] The first transistor T1 may include a first electrode receiving a first power supply voltage VDD, a second electrode connected to the first node N1, and a gate electrode (or control electrode) connected to the second node N2. The first transistor T1 may transmit a driving current to the first node N1 based on a voltage at the second node N2.

[0146] The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate electrode receiving the scan signal SC. The second transistor T2 may provide a data signal DATA provided through the data line DL to the second node N2 in response to the scan signal SC.

[0147] The third transistor T3 may include a first electrode connected to the sensing line SSL, a second electrode connected to the first node N1, and a gate electrode receiving a sensing control signal SS. The third transistor T3 may provide a reference voltage VINT provided through the sensing line SSL to the first node N1 in response to the sensing control signal SS.

[0148] The storage capacitor Cst may be connected between the first node N1 and the second node N2 and may store the data signal DATA or maintain it for a predetermined period of time.

[0149] The light emitting diode LD may be connected between the first node N1 and a second power line receiving a second power voltage VSS. The light emitting diode LD may emit light based on a driving current provided through the first transistor T1.

[0150] Reference Fig.11 and Fig.13 , the data driver 120 may include a current measuring unit 121 , a switching unit 123 , and a data providing unit 125 .

[0151] The current measuring unit 121 may be connected to the pixels PX11 to PXnm through the sensing lines SSL1 to SSLm. The current measuring unit 121 may be used as a current integrator during a sensing period. The sensing period may refer to a period for measuring the current flowing through the light emitting diode LD (see Fig.15 ) and can determine a time period for a compensation value of the data signal based on the measured current. For example, the current measuring unit 121 may include an operational amplifier, a capacitor, etc., and may integrate the sensing current provided from at least some of the pixels PX11 to PXnm by using them.

[0152] The current measuring unit 121 may be connected to the sensing lines SSL1 to SSLm through the switching unit 123. The switching unit 123 may include switches SW1 to SWm, and the switches SW1 to SWm may connect the sensing lines SSL1 to SSLm with the current measuring unit 121. The switches SW1 to SWm may operate individually based on a switch control signal provided from the timing controller 130. For example, only the first switch SW1 may be turned on, and then the current measuring unit 121 may measure the characteristics of each of the 11th pixel PX11 to the n1th pixel PXn1 included in the first pixel column through the first sensing line SSL1. For another example, when only the second switch SW2 is turned on, then the current measuring unit 121 may measure the characteristics of each of the 12th pixel PX12 to the n2th pixel PXn2 included in the second pixel column through the second sensing line SSL2. As another example, when all of the first switch SW1 to the mth switch SWm are turned on, the current measuring unit 121 can measure the characteristics of all pixels included in a pixel row (for example, a first pixel row including the 11th pixel PX11 to the 1mth pixel PX1m) through the first sensing line SSL1 to the mth sensing line SSLm.

[0153] As described above, since the first to mth sensing lines SSL1 to SSLm are connected to the reference voltage line V_SEN, a drop in a sensing voltage and attenuation of a sensing current for sensing can be reduced when measuring characteristics of all pixels included in a specific pixel row.

[0154] The data providing unit 125 may include a plurality of digital-to-analog converters DAC. Each of the DACs may receive a data signal DATA through a main data line and may convert the data signal DATA into an analog signal to provide it to the pixels PX11 to PXnm through a plurality of data lines DL1 to DLm.

[0155] Reference Fig.12 and Fig.14 , frame 1F may include a data write period PER_W, an emission period PER_E, and an edge period. As used herein, frame 1F is the duration in which a frame image is displayed. For example, frame 1F may be smaller than 1 / 60 seconds. A single frame 1F may include a number of horizontal times equal to the number of pixel columns (i.e., pixel columns included in the display device 100). For example, frame 1F may include 800 horizontal times (800H) corresponding to 800 columns, and one horizontal time (1H) may be, for example, approximately 16ms.

[0156] The data write period PER_W is a time for providing a data signal DATA to each of the pixels PXL, and may be smaller than one horizontal time (1H). The data write period PER_W is sequentially allocated to the pixels one by one, and the data write period PER_W allocated to each pixel row may be separated by a specific period PER_OE. For example, at the starting point P0, the data write period PER_W may be allocated to the first pixel row. Subsequently, at the first time point P1, the data write period PER_W may be allocated to the second pixel row.

[0157] The emission period PER_E refers to a time when each of the pixels PXL emits light in response to the data signal DATA, and may be, for example, 719 horizontal times (719H). The emission period PER_E may be allocated after a certain period PER_OE has passed since the data write period PER_W.

[0158] A porch period PER_P may be allocated after the emission period PER_E. The porch period PER_P may distinguish a current frame from a subsequent frame and may be, for example, 80 horizontal times (80H).

[0159] Each of the first power voltage VDD, the second power voltage VSS, and the reference voltage VINT may have a constant voltage level during a single frame 1F.

[0160] For example, the data voltage Vdata may vary every horizontal time (1H) in response to the data signal DATA, and may have a voltage level between approximately 1V and 10V.

[0161] During the data writing period PER_W of the first pixel row, the first scan signal SC[1] and the first sensing control signal SS[1] may have a logic high level (or a turn-on voltage level). Then, the pixel PXL (see Fig.12 ) can be turned on in response to the first scan signal SC[1], and a data voltage corresponding to the data signal DATA can be applied to the second node N2. In addition, the third transistor T3 can be turned on in response to the first sensing control signal SS[1], and the reference voltage VINT can be applied to the first node N1. The first transistor T1 can be turned on in response to the node voltage (i.e., the data voltage) at the second node N2, and can transmit it to the first node N1. It will be noted that a current path (i.e., a sensing path) is formed through the third transistor T3, and thus the driving current can be moved to the current measuring unit 121 (see Fig.13 ). In other words, while data is being written to the pixel PXL, the characteristics of the pixel PXL can be measured simultaneously.

[0162] like Fig.14 As shown in , since the data writing period PER_W is sequentially allocated to the pixel rows, the display device 100 can measure the characteristics of the pixels PXL of each pixel row.

[0163] As mentioned above Figures 11 to 14 As described, the display device 100 can measure the characteristics of the pixel PXL by the external compensation method. The display device 100 can measure the characteristics of the pixel PXL while writing data to the pixel PXL. The reference voltage VINT for measuring the characteristics of the pixel PXL can be provided to the pixel PXL through the sensing lines SSL1 and SSL2 to SSLm, and the sensing lines SSL1 and SSL2 to SSLm are connected to each other through the reference voltage line V_SEN. Therefore, the drop of the reference voltage VINT can be reduced. In addition, the attenuation of the sensing current through the sensing lines SSL1 and SSL2 to SSLm can be reduced, and the characteristics of the pixel PXL can be measured more accurately.

[0164] Fig.15 It shows that the setting Fig.14 A circuit diagram of an example of a pixel in a pixel area included in a display device. Fig.15 The pixel PXL with Fig.12 The pixels PXL are substantially the same or similar; therefore, a redundant description will be omitted.

[0165] Reference Fig.12 and Fig.15 During the process of aligning the light emitting diode LD, an AC voltage may be applied to the second pixel electrode ELT2 (ie, the second power terminal) through the second line AL2, and a ground voltage GND may be applied to the first pixel electrode ELT1 through the reference voltage line V_SEN (or the sensing line SSL).

[0166] More specifically, when the sensing control signal SS at the on voltage level is applied to Fig.15 When the third transistor T3 of the pixel PXL is turned on, the third transistor T3 may be turned on and the sensing line SSL may be electrically connected to the first node N1. Therefore, the ground voltage GND applied to the reference voltage line V_SEN may be applied to the first node N1 (ie, the first pixel electrode ELT1) through the sensing line SSL and the third transistor T3.

[0167] According to an exemplary embodiment of the present disclosure, during the process of aligning the light emitting diode LD, the ground voltage GND may be additionally applied to the second node N2 through the data line DL. For example, when the scan signal SC at the on voltage level is applied to the second transistor T2, the second transistor T2 may be turned on, and the second node N2 may be electrically connected to the data line DL, so that the ground voltage GND may be applied to the second node N2 through the data line DL and the second transistor T2. The voltage fluctuation at the first node N1 may be reduced by the node voltage at the second node N2, and the light emitting diode LD may be more effectively aligned between the first pixel electrode ELT1 and the second pixel electrode ELT2.

[0168] According to an exemplary embodiment of the present disclosure, during the process of aligning the light emitting diode LD, the ground voltage GND may be additionally applied to the first node N1 through the first power supply terminal. For example, when a data signal at a turn-on voltage level is applied, a scan signal at a turn-on voltage level is applied, and the first power supply voltage VDD has a ground voltage level, the first transistor T1 may be turned on, and the first power supply terminal may be electrically connected to the first node N1. The ground voltage GND applied through the first power supply terminal increases the ground voltage GND applied to the first node N1 through the third transistor T3, thereby suppressing fluctuations in the ground voltage GND. In addition, the light emitting diode LD may be aligned more effectively.

[0169] As mentioned above Fig.15 As described, the ground voltage GND is applied to the first pixel electrode ELT1 through the third transistor T3 of the pixel PXL in the display device 100, so that the light emitting diode LD can be aligned between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the pixel area PXA without forming or removing the process of the separate first line AL1. In addition, by applying the ground voltage GND as a data signal and turning on the second transistor T2 of the pixel PXL, the fluctuation of the ground voltage GND applied to the first pixel electrode ELT1 can be mitigated by the storage capacitor Cst. In addition, by applying the data signal at the on voltage level and the first power supply voltage VDD at the ground voltage GND level to the pixel PXL and turning on the second transistor T2 and the third transistor T3, the ground voltage GND applied to the first pixel electrode ELT1 can be increased. Therefore, a desired voltage difference is applied between the first pixel electrode ELT1 and the second pixel electrode ELT2, and the light emitting diode LD can be aligned more effectively.

[0170] Despite Fig.15 In the example shown in FIG. 1 , the pixel PXL includes three transistors, but the present disclosure is not limited thereto. The pixel PXL may have a plurality of transistors as will be described later. Fig.21The pixel structure of the pixel PXL_1 described above is the same as the pixel structure.

[0171] Fig.16 and Fig.17 It is shown Fig.14 Circuit diagrams of other examples of pixels included in a display device. Fig.16 and Fig.17 Shows Fig.15 The corresponding pixel of the pixel. Fig.18 It is shown in Fig.17 Graph showing an example waveform of a signal measured in a pixel of FIG.

[0172] Reference Fig.16 Since the common electrode MD1 is connected to the reference voltage line L_SEN, in the process of aligning the light emitting diode LD, the ground voltage GND applied to the first line AL1 can be applied to the reference voltage line L_SEN through the common electrode MD1. In this regard, when the third transistor T3 is turned on in response to the sensing control signal SS, the first node N1 can be electrically connected to the reference voltage line L_SEN. Fig.11 The scan driver 140 is described to provide a sensing control signal SS.

[0173] like Fig.16 As shown in , since the common electrode MD1 and the second pixel electrode ELT2 are disposed adjacent to each other, the common electrode MD1 and the second pixel electrode ELT2 may be capacitively coupled to each other. Fig.18 As shown in , the node voltage V_N1 at the first node N1 may have an AC waveform instead of a constant voltage waveform like the ground voltage V_GND. As the path from the point where the ground voltage V_GND is applied to the first node N1 becomes longer, the resistance component of the path increases, and therefore, the third amplitude (or magnitude) AP3 of the node voltage V_N1 increases. Since the path from the point where the ground voltage V_GND is applied to the first node N1 is formed by the parallel connection of the common electrode MD1 and the reference voltage line L_SEN, the resistance component of the path can be reduced, and the third amplitude AP3 of the node voltage V_N1 can be reduced.

[0174] The AC voltage V_AC applied through the second line AL2 may be reduced by the resistance component of the second pixel electrode ELT2 , and the electrode voltage V_CAT at the second pixel electrode ELT2 may have a second amplitude AP2 smaller than the first amplitude AP1 of the AC voltage V_AC.

[0175] As the voltage difference between the electrode voltage V_CAT and the node voltage V_N1 increases, a larger electric field is formed between the common electrode MD1 and the second pixel electrode ELT2 in the pixel area PXA, so that the light emitting diode LD may be more effectively aligned.

[0176] According to an exemplary embodiment, during the process of aligning the light emitting diode LD, the ground voltage GND may be applied to the data line DL, and the scan signal SC having the on voltage may be applied to the second transistor T2.

[0177] like Fig.17 As shown in , when the second transistor T2 is turned on in response to the scan signal SC, the second node N2 can be electrically connected to the data line DL. In addition, the data line DL and the first node N1 (i.e., the common electrode MD1 and the reference voltage line L_SEN) can be capacitively connected to each other through the storage capacitor Cst. When the data signal DATA having the ground voltage GND is applied, the fluctuation of the node voltage V_N1 can be more suppressed by the storage capacitor Cst.

[0178] [Table 1]

[0179]

[0180] Table 1 shows the voltage difference (ΔV) between the common electrode MD1 and the second pixel electrode ELT2 in the pixel area PXA according to whether the second transistor T2 and the third transistor T3 are turned on or off (i.e., the difference between the second amplitude AP2 of the electrode voltage V_CAT and the third amplitude AP3 of the node voltage V_N1). When the second transistor T2 and the third transistor T3 are turned off, the voltage difference ΔV is equal to approximately 20% of the AC voltage AC. When the second transistor T2 is turned on (i.e., when the storage capacitor Cst is used), the voltage difference ΔV increases to approximately 49% of the AC voltage AC. When the third transistor T3 is turned on (i.e., when the reference voltage line L_SEN is used), the voltage difference ΔV increases to approximately 62% of the AC voltage AC. When the second transistor T2 and the third transistor T3 are turned on, the voltage difference ΔV increases to approximately 87% of the AC voltage AC. That is, during the process of aligning the light emitting diode LD, by turning on the second transistor T2 and the third transistor T3, the alignment efficiency can be improved to approximately 4 times.

[0181] Return to reference Fig.15 Once the light emitting diode LD has been supplied and aligned, the first pixel electrode ELT1 is separated between the pixel regions PXA so that the pixels PXL can be driven independently. For example, the first pixel electrode ELT1 may be formed by removing the connection electrode of the common electrode MD1 through an etching process or the like. The connection electrode may be a portion of the common electrode MD1 located between the pixel region PXA and another pixel region and between the pixel region PXA and the first line AL1.

[0182] The second pixel electrode ELT2 may remain connected between the pixel regions PXA. In addition, the second line AL2 may remain connected to the pixel PXL in the display area DA. However, it will be understood that the present disclosure is not limited thereto. According to another exemplary embodiment, the second pixel electrode ELT2 may also be separated from each other between the pixel regions PXA.

[0183] Subsequently, despite Fig.15 Although not shown in the figure, the first contact electrode CNE1 and the second contact electrode CNE2 are respectively formed at both ends of each of the light emitting diodes LD, so that both ends of each of the light emitting diodes LD are respectively physically and / or electrically connected to the first pixel electrode ELT1 and the second pixel electrode ELT2, as shown in FIG. Figure 4 The process of forming the first contact electrode CNE1 and the second contact electrode CNE2 may be performed prior to the process of forming the first pixel electrode ELT1.

[0184] As mentioned above Figures 16 to 18 As described, during the process of aligning the light emitting diode LD, the third transistor T3 in the pixel PXLa is turned on, and the data signal DATA of the ground voltage GND is applied to turn on the second transistor T2, so that the alignment efficiency of the light emitting diode LD can be greatly improved.

[0185] Fig.19 and Fig. 20 It is shown Figure 1 Circuit diagrams of other examples of display devices. Fig.19 and Fig. 20 yes Fig.11 The corresponding circuit diagram of the circuit diagram. Fig.21 It is shown Fig.19 A circuit diagram of an example of one pixel among pixels included in a display device of FIG.

[0186] Initially, except for the sensing lines SSL1 to SSLm, Fig.19 The display device 100_5 and Fig.11 The display device 100 is substantially identical to the display device 100; therefore, a redundant description will be omitted.

[0187] The sensing lines SSL1 to SSLm may extend in the first direction D1 to pass through the display panel 110, and may be spaced apart from each other in the second direction D2. The sensing lines SSL1 to SSLm may be electrically connected to each other through a reference voltage line at one end (e.g., the non-display area NDA described above) of the display panel 110. The sensing lines SSL1 to SSLm are not connected to the data driver 120 but to a power source (not shown), and a reference voltage VINT may be applied to the sensing lines SSL1 to SSLm from the power source (not shown).

[0188] Despite Fig.19 In the example shown in FIG. 8 , the sensing lines SSL1 to SSLm extend in the first direction D1 , but the present disclosure is not limited thereto.

[0189] Reference Fig. 20 The sensing lines SSL1 to SSLn may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. In addition, the sensing lines SSL1 to SSLn may be electrically connected to each other through a reference voltage line L_VINT and may receive a reference voltage VINT from a power source (not shown).

[0190] Reference Fig.21 , the pixel PXL_1 may include an emission unit EMU for generating light having brightness corresponding to a data signal and a pixel circuit PXC for driving the emission unit EMU.

[0191] The emission unit EMU may include a light emitting diode LD connected in parallel between a first power supply voltage VDD and a second power supply voltage VSS (or a first power supply voltage terminal and a second power supply voltage terminal). The first power supply voltage VDD and the second power supply voltage VSS may have different potentials so that the light emitting diode LD may emit light. For example, the first power supply voltage VDD may be set to a high-level power supply voltage, and the second power supply voltage VSS may be set to a low-level power supply voltage. During the emission period of the pixel PXL, the difference between the first power supply voltage VDD and the second power supply voltage VSS may be set to be equal to or greater than the threshold voltage of the light emitting diode LD.

[0192] The emission unit EMU may emit light having brightness proportional to a driving current supplied through the pixel circuit PXC.

[0193] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0194] In addition, the pixel circuit PXC may also be connected to at least another scan line. For example, each of the pixels PXL arranged in the i-th row of the display area DA may also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1 (or the i-th sensing control line SLi). In addition, in addition to the first power supply voltage VDD and the second power supply voltage VSS, the pixel circuit PXC may also be connected to a third voltage source. For example, the pixel circuit PXC may also be connected to a reference voltage VINT (or a reference voltage power supply or an initialization voltage source).

[0195] The pixel circuit PXC may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0196] One electrode (e.g., source electrode) of the first transistor T1 (driving transistor) may be connected to the first power supply voltage VDD via the fifth transistor T5. The other electrode (e.g., drain electrode) of the first transistor T1 may be connected to one end of each of the light emitting diodes LD via the transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls a driving current flowing between the first power supply voltage VDD and the second power supply voltage VSS via the light emitting diode LD in response to the voltage at the first node N1.

[0197] The second transistor T2 (switching transistor) is connected between the data line Dj and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 is connected to the scan line Si. The second transistor T2 is turned on when a scan signal of a gate-on voltage (e.g., a low voltage) is supplied from the scan line Si to electrically connect the data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the data line Dj is transmitted to the first transistor T1.

[0198] The third transistor T3 is connected between the drain electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 is connected to the scan line Si. The third transistor T3 is turned on when a scan signal of a gate-on voltage is supplied from the scan line Si to electrically connect the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is diode-connected.

[0199] The fourth transistor T4 is connected between the first node N1 and the reference voltage VINT. In addition, the gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. The fourth transistor T4 is turned on when the scan signal of the gate-on voltage is supplied to the i-1th scan line Si-1 to transfer the voltage of the reference voltage VINT to the first node N1. The reference voltage VINT may have a voltage equal to or less than the minimum voltage of the data signal.

[0200] The fifth transistor T5 is connected between the first power supply voltage VDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 is connected to the emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 is turned off when the emission control signal of the gate-off voltage is supplied to the emission control line Ei, otherwise it is turned on.

[0201] The sixth transistor T6 is connected between the first transistor T1 and one end of each of the light emitting diodes LD. In addition, the gate electrode of the sixth transistor T6 is connected to an emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 is turned off when an emission control signal of a gate-off voltage is supplied to the emission control line Ei, otherwise it is turned on.

[0202] The seventh transistor T7 is connected between one end (or the second node N2) of each of the light emitting diodes LD and the reference voltage VINT. In addition, the gate electrode of the seventh transistor T7 is connected to one of the scan lines of the next stage, for example, the i+1 scan line Si+1 (or the i-th sensing control line SLi). The seventh transistor T7 is turned on when a scan signal of a gate-on voltage is supplied to the i+1 scan line Si+1 (or the i-th sensing control line SLi) to supply the reference voltage VINT to one end of each of the light emitting diodes LD.

[0203] The storage capacitor Cst is connected between the first power supply voltage VDD and the first node N1. The storage capacitor Cst stores the data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 in each frame.

[0204] Despite Fig.21 In the example shown in FIG. 1 , the transistors (eg, the first transistor T1 to the seventh transistor T7 ) included in the pixel circuit PXC are all p-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an n-type transistor.

[0205] Return to reference Fig.21 , during the process of aligning the light emitting diode LD in the pixel PXL, the first pixel electrode ELT1 and the second pixel electrode ELT2 of the emission unit EMU may be connected to the first line AL1 and the second line AL2. The AC voltage AC may be applied to the second line AL2, for example, the second power supply voltage VSS connected to the second line AL2, and the ground voltage GND may be applied to the first line AL1, for example, the second node N2 connected to the first line AL1. In addition, the ground voltage GND may be applied to the reference voltage line L_VINT (or the sensing line SSL) connected to the first line AL1, and the seventh transistor T7 is turned on so that the ground voltage GND applied to the second node N2 may be supplemented or enhanced.

[0206] When voltages of different levels are applied to the first and second lines AL1 and AL2 , an electric field is formed between the first and second pixel electrodes ELT1 and ELT2 , so that the light emitting diode LD may be aligned between the two pixel electrodes.

[0207] As mentioned above Figures 19 to 21As described, the display devices 100_5 and 100_6 include a reference voltage line L_VINT connected to the first line AL1, and the ground voltage GND is applied to the first pixel electrode ELT1 (or Fig.21 In this way, the light emitting diode LD can be aligned more effectively.

[0208] Fig. 22 It is shown Fig.19 A circuit diagram of an example of a scan driver included in a display device of FIG.

[0209] Reference Fig. 20 and Fig. 22 , the scan driver 140 may include a plurality of stages STAGE[n] respectively connected to a plurality of pixel rows.

[0210] The n-th stage STAGE[n] may include first to seventh thin film transistors M1 to M7 and first and second capacitors C1 and C2 .

[0211] The first thin film transistor M1 may include a first electrode receiving a start signal FLM, a second electrode connected to a first control node Q, and a gate electrode receiving a first clock signal clk1. The start signal FLM may indicate the start of scanning. The first clock signal clk1 may be a square wave having a logic high level and a logic low level within a certain period of time (e.g., a reference horizontal time 1H). The second clock signal clk2 to be described later may have an inverse waveform of the first clock signal clk1. The high level voltage VGH and the low level voltage VGL may be power supply voltages required by the driving stage STAGE[n] (or the scan driver 140). The high level voltage VGH may have a higher potential than the low level voltage VGL.

[0212] The second thin film transistor M2 includes a first electrode connected to the high level voltage VGH, a second electrode electrically connected to the first control node Q, and a gate electrode connected to the second control node QB.

[0213] The third thin film transistor M3 includes a first electrode connected to the second electrode of the second thin film transistor M2 , a second electrode connected to the first control node Q, and a gate electrode receiving the second clock signal clk2 .

[0214] The fourth thin film transistor M4 includes a first electrode connected to the second control node QB, a second electrode receiving the first clock signal clk1, and a gate electrode connected to the first control node QB.

[0215] The fifth thin film transistor M5 includes a first electrode connected to the second control node QB, a second electrode receiving the low level voltage VGL, and a gate electrode receiving the first clock signal clk1.

[0216] The sixth thin film transistor M6 includes a first electrode for receiving the high level voltage VGH, a second electrode connected to the output terminal, and a gate electrode connected to the second control node QB.

[0217] The seventh thin film transistor M7 includes a first electrode connected to the second clock signal clk2 , a second electrode connected to the output terminal, and a gate electrode connected to the first control node Q.

[0218] The first capacitor C1 may be connected between the output terminal and the first control node Q to boost an output voltage of the output terminal based on a voltage at the first control node Q. The second capacitor C2 may be connected between the second control node QB and the high level voltage VGH.

[0219] The nth stage STAGE[n] can output a signal scan[n] at a turn-on voltage level (e.g., a logic low level) through the first thin film transistor M1, the seventh thin film transistor M7, and the first capacitor C1, and can output a signal at a turn-off voltage level (e.g., a logic high level) using the second thin film transistor M2 to the sixth thin film transistor M6 and the second capacitor C2.

[0220] In the process of aligning the light emitting diode LD, each of the high level voltage VGH and the start signal FLM may have a first voltage level (or a turn-on voltage level, for example, -5V), and the low level voltage VGL may have a second voltage level (for example, -7.5V) greater than the first voltage level. Since the low level voltage VGL is greater than the high level voltage VGH by a threshold voltage Vth of the thin film transistor or more, the sixth thin film transistor M6 may be turned on.

[0221] Each of the first clock signal clk1 and the second clock signal clk2 may have a second voltage level, for example, −10 V. In this case, the fifth thin film transistor M5 may be turned on and an output signal having the same voltage level as the high level voltage VGH (ie, the first voltage level) is output from the nth stage STAGE[n].

[0222] As mentioned above Fig. 22As described, in the process of aligning the light emitting diode LD, when the start signal FLM, the high level voltage VGH, the low level voltage VGL, and the first clock signal clk1 and the second clock signal clk2 applied to the scan driver 140 are set to the voltage, the scan driver 140 can output a control signal having a turn-on voltage level to the sensing line SSL. Therefore, the ground voltage GND (or alignment voltage) applied through the reference voltage line L_VINT can be provided to the first pixel electrode ELT1 through some transistors in the pixel PXL. The light emitting diode LD can be aligned even without an additional first alignment line, so there is no need for an additional process for independently removing the first alignment line or forming the first alignment line. As a result, the manufacturing process of the display device 100 can be simplified.

[0223] Fig.23 It is shown Fig.19 0 is a circuit diagram of another example of a display device shown in FIG. Fig.23 Schematically shows Fig. 20 A portion of each of a display panel 110 and a scan driver 140 included in the display device of FIG.

[0224] Reference Fig.23 , the display device 100 may further include at least one of a first dummy transistor TD1 and a second dummy transistor TD2 disposed between the scan driver 140 and the sensing line SSL and the dummy control line L_EN.

[0225] The first dummy transistor TD1 may include a first electrode receiving a sensing control signal GB, a second electrode connected to a sensing line SSL, and a gate electrode connected to a dummy control line L_EN. The first dummy transistor TD1 may be turned on in response to a dummy control signal EN at a turn-on voltage level (e.g., a logic low level), and may provide the sensing control signal GB at the turn-on voltage level to the pixel PXL. In this case, the seventh transistor T7 of the pixel PXL (or the transistor connected between the first pixel electrode and the reference voltage) may be turned on.

[0226] The second dummy transistor TD2 may include a first electrode connected to a previous sensing line, a second electrode connected to the sensing line SSL, and a gate electrode connected to the dummy control line L_EN. Similar to the first dummy transistor TD1, the second dummy transistor TD2 may be turned on in response to a dummy control signal EN at a turn-on voltage level (e.g., a logic low level), and may provide a sensing control signal GB at a turn-on voltage level to the pixel PXL. In this case, the seventh transistor T7 of the pixel PXL (or the transistor connected between the first pixel electrode and the reference voltage) may be turned on.

[0227] That is, during the process of aligning the light emitting diode LD, the ground voltage GND may be applied from the reference voltage line L_VINT to the first pixel electrode through the dummy control line L_EN and the dummy transistors TD1 and TD2 .

[0228] As mentioned above Fig.23 As described, during the process of aligning the light emitting diode LD, by using the dummy transistors TD1 and TD2 provided between the scan driver 140 and the sensing line SSL, the sensing transistor (e.g., the seventh transistor T7) of the pixel PXL may be turned on, and the ground voltage GND (i.e., the alignment voltage) may be applied to the first pixel electrode from the reference voltage line L_VINT. In this case, the reference voltage may be reduced. Fig.23 The stress of the scan driver 140 (ie, the stress on the transistor circuits in the scan driver 140 due to the DC driving of the scan driver 140) is described.

[0229] Figure 24 to Figure 26 It is shown Figure 2 1 and 2 are plan views of other examples of display devices.

[0230] In addition to the first pixel electrode ELT1, Fig.24 The display device 100_2 and Figure 2 The display device 100 is substantially the same; therefore, a redundant description will be omitted.

[0231] Fig.24 The first pixel electrode ELT1 shown in FIG. 1 may be formed through the same process as the second pixel electrode ELT2 and the second line AL2 .

[0232] Each of the first pixel electrodes ELT1 may include a connecting portion arranged to face a main portion of the second pixel electrode ELT2 (i.e., a portion extending in the second direction D2 to reach other pixel areas PXA) and a branch portion arranged to face a branch portion of the second pixel electrode ELT2 (i.e., a portion extending from the main portion in the first direction D1).

[0233] The connection portion of the first pixel electrode ELT1 extends outward from the outer side of the branch portion of the second pixel electrode ELT2, and when viewed from the top, the first pixel electrode ELT1 has That is, the first pixel electrode ELT1 may include a stub protruding from a connection portion of the first pixel electrode ELT1 in the second direction D2.

[0234] Reference Fig.25 The display device 100_3 may include a first pixel electrode ELT1, and the first pixel electrode ELT1 does not include the above reference Fig.24The connection portion described above includes only the branch portion that is arranged to face the branch portion of the second pixel electrode ELT2.

[0235] The branch portions of the first pixel electrode ELT1 may be electrically connected to the reference voltage line L_VINT (or the sensing line SSL) through a contact hole (not shown), a connection line pattern (not shown), or the like.

[0236] Reference Fig.26 , the display device 100_4 may include a first pixel electrode ELT1 and a second pixel electrode ELT2. The first pixel electrode ELT1 may extend in the first direction D1 and may be formed independently of other electrodes, as described above with reference to Fig.25 The second pixel electrodes ELT2 may be arranged to surround the first pixel electrodes ELT1, respectively. When each of the second pixel electrodes ELT2 forms a closed loop in the pixel area PXA, the resistance is reduced, and thus the drop of the voltage applied by the second pixel electrode ELT2 (for example, an AC voltage as an alignment voltage) may be reduced.

[0237] Although the second pixel electrode ELT2 has a rectangular shape in the drawings, this is merely illustrative. When viewed from the top, the second pixel electrode ELT2 may have a shape such as a circle and a polygon (eg, a pentagon, a hexagon, etc.).

[0238] As mentioned above Figure 24 to Figure 26 As described, the first pixel electrode ELT1 can be connected to the reference voltage line L_VINT, so after they have been formed together with the second pixel electrode ELT2, no additional process is required, such as an etching process to separate them from other pixel electrodes. Therefore, the shape of the first pixel electrode ELT1 is not limited thereto, and a pixel PXL surrounded by the second pixel electrode ELT2 can be applied.

[0239] Figures 27 to 34 is a diagram showing various exemplary embodiments Figure 1 FIG. 1 is a diagram of pixels included in a display device.

[0240] Reference Figure 1 and Fig. 27 The second pixel electrode ELT2 includes a main body (or trunk, trunk electrode) extending in the second direction D2, and a branch (or protrusion or protrusion electrode) extending from the main body in the first direction D1 in the pixel area PXA. The main body may extend to other pixel areas PXA.

[0241] The first pixel electrode ELT1 may be disposed to face the branch portion of the second pixel electrode ELT2 and may extend in the first direction D1. The first pixel electrode ELT1 may protrude from the second pixel electrode ELT2 in the first direction D1. In this case, an alignment area A_AL (i.e., an area where the light emitting diode LD is disposed) may be defined between the first pixel electrode ELT1 and the branch portion of the second pixel electrode ELT2.

[0242] The contact hole CNT through which the first pixel electrode ELT1 is connected to the transistor (not shown) may be formed in a protrusion of the first pixel electrode ELT1 (ie, a portion not overlapping the alignment area A_AL). The transistor may be, for example, the one described above with reference to Fig.12 The first transistor T1 described above may be provided in the Figure 4 Described are transistors in the circuit element layer PCL.

[0243] Reference Fig.28 The first pixel electrode ELT1 and the second pixel electrode ELT2 can be respectively Fig. 27 The described first pixel electrode ELT1 and the second pixel electrode ELT2 are substantially the same; therefore, redundant descriptions will be omitted.

[0244] The first pixel electrode ELT1 may be arranged in the pixel area PXA to face the branch portion of the second pixel electrode ELT2, and one end (e.g., the lower end) of the first pixel electrode ELT1 in the first direction D1 may be aligned with one end (e.g., the lower end) of the branch portion of the second pixel electrode ELT2 in the first direction D1. That is, the first pixel electrode ELT1 may not protrude from the branch portion of the second pixel electrode ELT2 in the first direction D1. In such a case, the alignment area A_AL may overlap with the entire side of the first pixel electrode ELT1 (i.e., the side facing the branch portion of the second pixel electrode ELT2). In addition, the contact hole CNT may be distributed throughout the first pixel electrode ELT1.

[0245] Reference Fig.29 The second pixel electrode ELT2 can be the same as the above reference Fig. 27 The described second pixel electrode ELT2 is substantially the same; therefore, a redundant description will be omitted.

[0246] The first pixel electrode ELT1 may be disposed to face all sides of the branch portions of the second pixel electrode ELT2 .

[0247] like Fig.29As shown in , three sides of the branch portion of the second pixel electrode ELT2 can be exposed except for the side contacting the main body. In this case, the first pixel electrode ELT1 may include: a first branch portion, which is arranged to face a longer side of the branch portion of the second pixel electrode ELT2 and extends in the first direction D1; a connecting portion, which extends from one end of the first branch portion in the second direction D2 and is arranged to face a shorter side of the branch portion of the second pixel electrode ELT2; and a second branch portion, which extends from one end of the connecting portion in the first direction D1 and is arranged to face the other longer side of the branch portion of the second pixel electrode ELT2. That is, the first pixel electrode ELT1 has a "concave" shape or a "U" shape when viewed from the top, and may be arranged to surround the branch portion of the second pixel electrode ELT2. The corner where the first branch portion and the second branch portion of the first pixel electrode ELT1 meet the connecting portion has an obtuse angle or has an edge processing shape (e.g., a rounded edge shape), and does not include a stub.

[0248] The alignment area A_AL may overlap the longer sides of the branches of the second pixel electrode ELT2 and the first and second branches of the first pixel electrode ELT1. The contact hole CNT may be formed in the connection portion of the first pixel electrode ELT1 and may not overlap the alignment area A_AL.

[0249] In addition to the second pixel electrode ELT2 including two branch portions, Fig.30 The first pixel electrode ELT1 and the second pixel electrode ELT2 are respectively Fig. 27 The described first pixel electrode ELT1 and the second pixel electrode ELT2 are substantially the same; therefore, redundant descriptions will be omitted.

[0250] The branches of the second pixel electrode ELT2 may be arranged to face the two longer sides of the first pixel electrode ELT1, respectively. In this case, the alignment area A_AL may be formed between the branches of the second pixel electrode ELT2, or may overlap with them. The contact hole CNT may be formed at one end of the first pixel electrode ELT1 that does not overlap with the alignment area A_AL.

[0251] In addition to the second pixel electrode ELT2 including two branch portions, Fig.31 The first pixel electrode ELT1 and the second pixel electrode ELT2 are respectively Fig.28 The described first pixel electrode ELT1 and the second pixel electrode ELT2 are substantially the same; therefore, redundant description will be omitted.

[0252] The branches of the second pixel electrode ELT2 may be disposed to face two longer sides of the first pixel electrode ELT1, respectively. The alignment area A_AL may be formed between the branches of the second pixel electrode ELT2 and may overlap the first pixel electrode ELT1. The contact holes CNT may be distributed throughout the first pixel electrode ELT1.

[0253] In addition to the second pixel electrode ELT2 including two main parts, Fig.32 The first pixel electrode ELT1 and the second pixel electrode ELT2 are respectively Fig.26 The described first pixel electrode ELT1 and the second pixel electrode ELT2 are substantially the same; therefore, redundant descriptions will be omitted.

[0254] The second pixel electrode ELT2 may surround the first pixel electrode ELT1. When viewed from the top, the first pixel electrode ELT1 may have an island structure due to the second pixel electrode ELT2. The second pixel electrode ELT2 may include two main bodies facing each other and extending in the second direction D2 and two branch parts extending in the first direction D1 between the main bodies and connecting the main bodies to each other. In this case, when viewed from the top, the first pixel electrode ELT1 may be arranged in an internal space formed by the main body and the branch parts. The two main bodies of the second pixel electrode ELT2 may extend to other pixel areas PXA in the second direction D2. In this case, the resistance of the second pixel electrode ELT2 may be reduced by the two main bodies, and the drop in the voltage (e.g., alignment voltage, power supply voltage, etc.) applied to the second pixel electrode ELT2 may be reduced.

[0255] The alignment area A_AL may be formed between the branch portions of the second pixel electrode ELT2 and may overlap the first pixel electrode ELT1. In addition, the contact holes CNT may be distributed throughout the first pixel electrode ELT1.

[0256] Reference Fig.33 , the second pixel electrode ELT2 may include two branch portions, and the first pixel electrode ELT1 may include three branch portions. In addition, the first pixel electrode ELT1 and the second pixel electrode ELT2 may be respectively the same as those in the above reference Fig.29 The described first pixel electrode ELT1 and the second pixel electrode ELT2 are substantially the same; therefore, redundant descriptions will be omitted.

[0257] The second pixel electrode ELT2 may include a main body extending in the second direction D2 and two branch portions extending from the main body in the first direction D1 and spaced apart from each other. The first pixel electrode ELT1 may include a through branch portion disposed to face the longer side surface of the second pixel electrode ELT2 and a connection portion connecting the through branch portions. Fig.33As shown in FIG. 1 , when viewed from the top, the second pixel electrode ELT2 may have approximately A “Π” shape or a “Π” shape, and the first pixel electrode ELT1 may have a trident shape facing the second pixel electrode ELT2.

[0258] Despite Fig.33 Each of the branch portions and the connection portion of the first pixel electrode ELT1 forms a right angle, but the present disclosure is not limited thereto. Fig.34 As shown in , each of the branch portions and the connection portion of the first pixel electrode ELT1 may form an obtuse angle or have an edge-processed shape, and may not include a stub.

[0259] As mentioned above Figures 27 to 34 As described, the pixel PXL may include the first pixel electrode ELT1 and the second pixel electrode ELT2 having various shapes as long as the second pixel electrode ELT2 does not include a stub.

[0260] Fig.35 is a flowchart illustrating a method for manufacturing a display device according to an exemplary embodiment of the present disclosure.

[0261] Reference Figure 1 , Figure 2 and Fig.35 , Figure 1 The display device can be Fig.35 method to manufacture.

[0262] Fig.35 The method starts with preparing a substrate SUB for manufacturing the display device 100 (step S2710).

[0263] The substrate SUB may be a substrate for individually manufacturing the display device 100. However, it will be understood that the present disclosure is not limited thereto. For example, the substrate SUB may be a substrate of a mother glass for simultaneously manufacturing a plurality of display devices 100.

[0264] On the substrate SUB, a display area DA and a non-display area NDA may be defined. The display area DA may include a plurality of pixel areas PXA, and the non-display area NDA may be disposed outside the display area DA.

[0265] Once the substrate SUB is prepared, Fig.35 The method may include forming a circuit element layer PCL on a substrate SUB in a display area DA (step S2720). The circuit element layer PCL may include a reference voltage line L_VINT.

[0266] As mentioned above Figure 2As described, the reference voltage line L_VINT may be formed in the non-display area DNA and may be connected to the sensing line SSL. The reference voltage line L_VINT may be composed of a single layer or multiple layers. When the reference voltage line L_VINT includes at least one sub-line SUL, the sub-line SUL may be formed on the same layer during the same process as the process of forming at least one electrode in the circuit element layer PCL. Fig.35 The method can form at least one electrode in the circuit element layer PCL, and at the same time, at least one sub-line can be formed on the same layer as the layer of the at least one electrode, for example, as described above with reference to Figures 4 to 7 At least one of the first to fourth sub-lines SUL1 to SUL4 described.

[0267] A first pixel electrode ELT1 and a second pixel electrode ELT2 may be formed on the substrate SUB in the display area DA (step S2730 ) In addition, a first line AL1 and a second line AL2 may be formed on the substrate SUB in the non-display area NDA.

[0268] The first line AL1 and the second line AL2 may be connected to the first pixel electrode ELT1 and the second pixel electrode ELT2, respectively. The first line AL1 may be electrically connected to the reference voltage line L_VINT through the first contact hole CNT1.

[0269] Then, Fig.35 The method may include supplying or disposing a light emitting diode LD on a substrate SUB on which first and second pixel electrodes ELT1 and ELT2 and first and second lines AL1 and AL2 are formed (step S2740).

[0270] For example, Fig.35 The method may include supplying the light emitting diode LD on the pixel area PXA of the display area DA using various techniques including inkjet printing.

[0271] Then, Fig.35 The method may include applying a first power voltage (or an alignment voltage, such as a ground voltage GND) to a reference voltage line L_VINT to align the light emitting diode LD (step S2750).

[0272] For example, according to Fig.35 According to the method, a voltage is applied to the reference voltage line L_VINT and the second line AL2 while or after the light emitting diode LD is supplied, so that the light emitting diode LD can be aligned between the first pixel electrode ELT1 and the second pixel electrode ELT2 connected to the reference voltage line L_VINT and the second line AL2.

[0273] Then, Fig.35The method may include forming a first contact electrode CNE1 and a second contact electrode CNE2 on a substrate SUB on which a light emitting diode LD is aligned (step S2760).

[0274] As mentioned above Figure 7 As described, the first contact electrode CNE1 can connect the first end EP1 of at least one light emitting diode LD to the first pixel electrode ELT1 disposed in the pixel area PXA. In addition, the second contact electrode CNE2 can connect the second end EP2 of at least one of the light emitting diodes LD to the second pixel electrode ELT2 disposed in the pixel area PXA.

[0275] Although the exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications and changes may be made without departing from the technical concept or basic features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are not restrictive but illustrative in all aspects.

Claims

1. A method for manufacturing a display device, the method comprising the following steps: preparing a substrate, the substrate comprising a display area and a non-display area arranged outside the display area, the display area comprising a plurality of pixel areas; forming a first switching element in each of the plurality of pixel areas, and forming a circuit element layer including a reference voltage line disposed in the non-display area and electrically connected to the first switching element; forming a pixel electrode, the pixel electrode being disposed on the circuit element layer in each of the plurality of pixel areas and comprising a first pixel electrode and a second pixel electrode, the first pixel electrode being electrically connected to the reference voltage line through the first switching element, and the second pixel electrode extending in a first direction and comprising a branch electrode protruding in a second direction perpendicular to the first direction and facing the first pixel electrode; Arranging a plurality of light emitting elements between the first pixel electrode and the second pixel electrode; as well as The plurality of light emitting elements are aligned by applying a first power supply voltage to the reference voltage line and applying a second power supply voltage to the second pixel electrode.

2. The method according to claim 1, further comprising the steps of: forming first contact electrodes respectively disposed on the first ends of the plurality of light emitting elements to connect the plurality of light emitting elements to the first pixel electrode; as well as Second contact electrodes are formed respectively disposed on the second ends of the plurality of light emitting elements to connect the plurality of light emitting elements with the second pixel electrode.

3. The method according to claim 2, wherein: No etching process is performed between the step of aligning the plurality of light emitting elements and the step of forming the first contact electrode.

4. The method according to claim 1, wherein: The step of aligning the plurality of light emitting elements comprises: A first control signal for turning on the first switching element is applied to a control electrode of the first switching element.

5. The method according to claim 4, wherein: The circuit element layer further includes a second switching element connected between the first pixel electrode and a first power supply terminal and a third switching element connected between a control electrode of the second switching element and a data line.

6. The method according to claim 5, wherein: The step of aligning the plurality of light emitting elements further comprises: turning on each of the second switching element and the third switching element, wherein a turn-on voltage for turning on the second switch element is applied to the data line, and Wherein, the first power supply voltage is applied to the first power supply terminal.

7. The method according to claim 5, wherein: The circuit element layer further includes a capacitor connected between the first pixel electrode and the control electrode of the second switching element.

8. The method according to claim 7, wherein: The step of aligning the plurality of light emitting elements further comprises turning on the third switching element, and Wherein, the first power supply voltage is applied to the data line.

9. The method according to claim 1, wherein: The step of forming the pixel electrode further includes: A first line connected to the reference voltage line and a connection electrode connecting the first line with the first pixel electrode are formed in the non-display area.

10. The method according to claim 9, wherein: The first power supply voltage is applied to the reference voltage line through the first line.

11. The method according to claim 9, further comprising: The connection electrode is removed to separate the first line from the first pixel electrode.

12. The method according to claim 1, wherein: The circuit element layer further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially stacked on one another between the substrate and the display element layer.

13. The method according to claim 12, wherein: The reference voltage line includes at least one of the following: a first sub-line, arranged between the third insulating layer and the fourth insulating layer; a second sub-line, arranged between the second insulating layer and the third insulating layer; a third sub-line, arranged between the first insulating layer and the second insulating layer; and a fourth sub-line, arranged between the substrate and the first insulating layer.

14. The method according to claim 9, wherein: The first line includes a first sub-voltage line disposed on the circuit element layer and directly connected to the reference voltage line, and a second sub-voltage line disposed on the first sub-voltage line, and wherein the conductivity of the second sub-voltage line is greater than that of the first sub-voltage line.

15. The method according to claim 1, wherein: The step of forming the circuit element layer includes: A scan signal line connected to a control electrode of the first switching element and a first dummy switching element connecting the scan signal line to a dummy line in the non-display area are formed.

16. The method according to claim 15, wherein: The step of aligning the plurality of light emitting elements comprises: applying an on voltage for turning on the first switching element to the dummy line; and turning on the first dummy switching element.

17. The method according to claim 15, wherein: The circuit element layer further includes a second dummy switch element, the second dummy switch element connects the scan signal line to an adjacent scan signal line, and The step of aligning the plurality of light emitting elements further comprises turning on the second dummy switch element.

18. A display device, comprising: A substrate, comprising a display area and a non-display area arranged outside the display area, wherein the display area comprises a plurality of pixel areas; a circuit element layer including a first switching element formed in each of the plurality of pixel areas, a reference voltage line disposed in the non-display area and electrically connected to the first switching element, and a scanning line connected to a control electrode of the first switching element; as well as The display element layer includes a first pixel electrode, a second pixel electrode, and a plurality of light emitting elements, wherein the first pixel electrode is disposed on the circuit element layer in each of the plurality of pixel areas and is electrically connected to the reference voltage line through the first switching element, the second pixel electrode is disposed to extend in a first direction and include a branch electrode protruding in a second direction perpendicular to the first direction and facing the first pixel electrode, and the plurality of light emitting elements are disposed between the first pixel electrode and the second pixel electrode, The circuit element layer further includes a dummy line formed in the non-display area and a first dummy switch element connected between the dummy line and the scan line.

19. The display device according to claim 18, wherein: The circuit element layer further includes a second dummy switch element connecting the scan line to an adjacent scan line.

20. A display device, comprising: A substrate, comprising a display area and a non-display area arranged outside the display area, wherein the display area comprises a plurality of pixel areas; a circuit element layer including a circuit element disposed in each of the plurality of pixel areas and a reference voltage line disposed in the non-display area and electrically connected to the circuit element; as well as The display element layer includes a first pixel electrode, a second pixel electrode, and a plurality of light-emitting elements, wherein the first pixel electrode is arranged on the circuit element layer in each pixel area of ​​the plurality of pixel areas, the second pixel electrode is arranged to extend in a first direction and include a branch electrode protruding in a second direction perpendicular to the first direction and facing the first pixel electrode, and the plurality of light-emitting elements are arranged between the first pixel electrode and the second pixel electrode. Wherein, the second pixel electrode surrounds the first pixel electrode.

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