Data cache system and control method of data cache system

Abstract

The present application provides a data cache system and a control method for the data cache system, which can improve the management efficiency of the data cache system. The data cache system includes: a cache space, including K address ranges, the K address ranges are respectively used to store K entries, each entry includes an owner flag, the owner flag is used to record a storage identifier or a free identifier, the storage identifier is used to indicate that data is stored in the corresponding entry, and the free identifier is used to indicate that data is not stored in the corresponding entry; a producer control unit is configured to perform the following operations: write data to the first address range indicated by the producer pointer, and update the first owner flag in the first address range to the storage identifier; a consumer control unit is configured to perform the following operations: determine whether to read data from the second address range according to the second owner flag in the second address range indicated by the consumer pointer.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data cache system and a control method of the data cache system. Background Art

[0002] With the rapid growth of Internet users and the rapid expansion of data volume, the demand for computing in data centers is also rising rapidly. In recent years, with the rise of computing-intensive fields such as artificial intelligence, high-performance data analysis, and financial analysis, heterogeneous computing has also become a hot field. A heterogeneous computing system is a computer system built with two processors of different architectures: the main processor and the accelerator. For example, mainstream heterogeneous computer systems include central processor unit (CPU) + application specific integrated circuit (ASIC) ASIC, CPU + field programmable gate array (FPGA), etc.

[0003] In the current communication mechanism of heterogeneous computing systems, the doorbell (Doorbell DB) handshake method can usually be used to transmit commands. In this way, the main processor and the accelerator jointly maintain a data cache system for storing commands. For example, the main processor can maintain the head pointer of the data cache system and use it to write commands to the data cache system; the accelerator is used to maintain the tail pointer of the data cache system and use it to read commands from the data cache system. In this case, frequent communication is required between the main processor and the accelerator to determine the status of the commands currently stored in the data cache system.

[0004] As the computing power of heterogeneous computing systems continues to rise, the relatively lagging data communication capabilities have gradually become a bottleneck for further performance improvement of heterogeneous computing systems. How to avoid frequent data communication between the main processor and the accelerator and improve data transmission efficiency is the key to efficient collaboration and performance optimization of heterogeneous computing systems. Summary of the invention

[0005] The present application provides a data cache system and a control method for the data cache system, which can improve the management efficiency of the data cache system.

[0006] In a first aspect, a data cache system is provided, comprising: a cache space, the cache space comprising K address ranges, the K address ranges being respectively used to store K entries, K being an integer greater than 0, each entry comprising an owner flag, the owner flag being used to record a storage identifier or a free identifier, the storage identifier being used to indicate that data is stored in the corresponding entry, and the free identifier being used to indicate that data is not stored in the corresponding entry; a producer control unit being configured to perform the following operations: write data to a first address range indicated by a producer pointer, and update a first owner flag in the first address range to the storage identifier; and a consumer control unit being configured to perform the following operations: determine whether to read data from a second address range indicated by a consumer pointer according to a second owner flag in the second address range indicated by a consumer pointer.

[0007] Optionally, the producer pointer is used to point to the next address range for writing data among the K address ranges.

[0008] Optionally, the consumer pointer is used to point to the next address range for reading data among the K address ranges.

[0009] Optionally, the cache space can be set in a storage unit in the computer system, and the above-mentioned storage unit includes but is not limited to double data rate synchronous dynamic random access memory (DDR-SDRAM, DDR), read-only memory (ROM), random access memory (RAM), storage array and other storage media that can store data.

[0010] Optionally, the producer control unit and the consumer control unit may be executed by a processor in a computer system. The processor includes but is not limited to a central processor unit (CPU), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The producer control unit and the consumer control unit may be executed by the same processor or by different processors.

[0011] Optionally, the cache space, the producer control unit and the consumer control unit may be arranged in the same device, or may be arranged in different devices respectively.

[0012] In an embodiment of the present application, an owner flag is configured in the entry stored in each address range in the data cache system to indicate whether data is stored in the corresponding entry. The data writing thread can set the owner flag when writing data, and the data reading thread determines whether data is stored in the entry by reading the storage flag or the free flag in the owner flag. This data cache system can reduce the interaction between the data writing thread and the data reading thread, thereby simplifying the management process of the data cache system.

[0013] In combination with the first aspect, in a possible implementation of the first aspect, the consumer control unit is configured to specifically perform the following operations: when the second owner flag is recorded as the storage identifier, read data from the second address range; when the second owner flag is recorded as the free identifier, determine that no data is stored in the second address range.

[0014] In an embodiment of the present application, a consumer control unit in a data cache system can determine whether data is stored in an entry by reading the storage flag or the free flag of the owner flag. This data cache system can reduce the interaction between the data writing thread and the data reading thread, and even allow the data writing thread and the data reading thread to run independently, thereby simplifying the management process of the data cache system.

[0015] In combination with the first aspect, in a possible implementation of the first aspect, the data cache system also includes: a producer ring register, used to store a producer ring flag, the producer ring flag is used to record whether the number of loops of the producer pointer in the K address ranges is an odd number or an even number, wherein the assignment of the owner flag is determined according to the assignment of the producer ring flag; the producer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the producer ring flag is an odd number; write data in the first address range, and update the first owner flag in the first address range from the second value to the first value; or, the producer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the producer ring flag is an even number; write data in the first address range, and update the first owner flag in the first address range from the first value to the second value.

[0016] It should be understood that, for the owner flag bit in the address range indicated by the producer pointer, when the number of cycles indicated by the producer ring flag bit is an odd number, the first value represents a storage flag, and the second value represents an idle flag. When the number of cycles indicated by the producer ring flag bit is an even number, the second value represents a storage flag, and the first value represents an idle flag.

[0017] Optionally, the embodiment of the present application does not limit the specific values ​​of the first value and the second value, as long as they can represent the storage identifier and the idle identifier respectively. Optionally, the first value and the second value can be represented by binary numbers. For example, the first value can be 0 and the second value can be 1. Alternatively, the first value can be 00 and the second value can be 11.

[0018] In an embodiment of the present application, the data write thread determines the assignment of the owner flag bit corresponding to the storage identifier according to the parity of the number of loops of the producer pointer, so that the data read thread can determine whether data is stored in the entry according to the parity of the number of loops of the consumer pointer and the assignment of the owner flag bit when reading data. This data cache system can reduce the interaction between the data write thread and the thread for reading data, thereby simplifying the management process of the data cache system.

[0019] In combination with the first aspect, in a possible implementation of the first aspect, the data cache system also includes: a consumer ring register, used to store a consumer ring flag, the consumer ring flag is used to record whether the number of loops of the consumer pointer in the K address ranges is an odd number or an even number; the consumer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the consumer ring flag is an odd number; and read data from the second address range when the second owner flag is recorded as the first value; or, the consumer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the consumer ring flag is an even number; and read data from the second address range when the second owner flag is assigned the second value.

[0020] In an embodiment of the present application, the data reading thread determines whether the value of the owner flag bit in the entry indicated by the consumer pointer is a storage flag or an idle flag based on the parity of the number of loops of the consumer pointer recorded in the consumer ring register, and then determines whether data is stored in the entry. This definition method of the data cache system can reduce the interaction between the producer thread and the consumer thread, thereby simplifying the management process of the data cache system.

[0021] In combination with the first aspect, in a possible implementation manner of the first aspect, the consumer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the consumer ring flag is an odd number; and when the second owner flag is assigned the second value, determine that no data is stored in the second address range; determine that the number of loops indicated by the consumer ring flag is an even number; and when the second owner flag is assigned the first value, determine that no data is stored in the second address range.

[0022] In combination with the first aspect, in a possible implementation manner of the first aspect, the first value is 1, and the second value is 0; or, the first value is 0, and the second value is 1.

[0023] In a second aspect, a control method for a data cache system is provided, wherein the data cache system comprises:

[0024] A cache space, wherein the cache space comprises K address ranges, wherein the K address ranges are respectively used to store K entries, wherein K is an integer greater than 0, and wherein each entry comprises an owner flag, wherein the owner flag is used to record a storage identifier or a free identifier, wherein the storage identifier is used to indicate that data is stored in the corresponding entry, and the free identifier is used to indicate that data is not stored in the corresponding entry; a producer pointer, wherein the producer pointer is used to point to an address range in the K address ranges for writing next data; and a consumer pointer, wherein the consumer pointer is used to point to an address range in the K address ranges for reading next data; the method comprises: writing data to a first address range indicated by the producer pointer, and updating a first owner flag in the first address range to the storage identifier; and determining whether to read data from a second address range according to a second owner flag in the second address range indicated by the consumer pointer.

[0025] Optionally, the producer pointer is used to point to the next address range for writing data among the K address ranges.

[0026] Optionally, the consumer pointer is used to point to the next address range for reading data among the K address ranges.

[0027] Optionally, the cache space can be set in a storage unit in the computer system, and the above-mentioned storage unit includes but is not limited to double data rate synchronous dynamic random access memory (DDR-SDRAM, DDR), read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), storage arrays and other storage media that can store data.

[0028] Optionally, the producer control unit and the consumer control unit may be executed by a processor in a computer system. The processor includes but is not limited to a central processor unit (CPU), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The producer control unit and the consumer control unit may be executed by the same processor or by different processors.

[0029] Optionally, the cache space, the producer control unit and the consumer control unit may be arranged in the same device, or may be arranged in different devices respectively.

[0030] In an embodiment of the present application, an owner flag is configured in the entry stored in each address range in the data cache system to indicate whether data is stored in the corresponding entry. The data writing thread can set the owner flag when writing data, and the data reading thread determines whether data is stored in the entry by reading the storage flag or the free flag in the owner flag. This data cache system can reduce the interaction between the data writing thread and the data reading thread, thereby simplifying the management process of the data cache system.

[0031] In combination with the second aspect, in a possible implementation of the second aspect, the determining whether to read data from the second address range based on the second owner flag in the second address range indicated by the consumer pointer includes: reading data from the second address range when the second owner flag in the second address range is recorded as the storage identifier; or determining that no data is stored in the second address range when the second owner flag is recorded as the free identifier.

[0032] In combination with the second aspect, in a possible implementation of the second aspect, the data cache system also includes: a producer ring register, used to store a producer ring flag, the producer ring flag is used to record whether the number of loops of the producer pointer in the K address ranges is odd or even, wherein the assignment of the owner flag is determined according to the assignment of the producer ring flag; writing data in the first address range and updating the first owner flag in the first address range to the storage identifier, including: determining that the number of loops indicated by the producer ring flag is an odd number; writing data in the first address range, and updating the first owner flag in the first address range from the second value to the first value; or, determining that the number of loops indicated by the producer ring flag is an even number; writing data in the first address range, and updating the first owner flag in the first address range from the first value to the second value.

[0033] It should be understood that, for the owner flag bit in the address range indicated by the producer pointer, when the number of cycles indicated by the producer ring flag bit is an odd number, the first value represents a storage flag, and the second value represents an idle flag. When the number of cycles indicated by the producer ring flag bit is an even number, the second value represents a storage flag, and the first value represents an idle flag.

[0034] Optionally, the embodiment of the present application does not limit the specific values ​​of the first value and the second value, as long as they can represent the storage identifier and the idle identifier respectively. Optionally, the first value and the second value can be represented by binary numbers. For example, the first value can be 0 and the second value can be 1. Alternatively, the first value can be 00 and the second value can be 11.

[0035] In combination with the second aspect, in a possible implementation of the second aspect, the data cache system also includes: a consumer ring register, used to store a consumer ring flag, the consumer ring flag is used to record whether the number of loops of the consumer pointer in the K address ranges is odd or even; when the second owner flag in the second address range is recorded as the storage identifier, reading data from the second address range includes: determining that the number of loops indicated by the consumer ring flag is an odd number; when the second owner flag is recorded as the first value, reading data from the second address range; or, the consumer control unit is configured to specifically perform the following operations: determining that the number of loops indicated by the consumer ring flag is an even number; when the second owner flag is assigned the second value, reading data from the second address range.

[0036] In combination with the second aspect, in a possible implementation of the second aspect, when the second owner flag is recorded as the idle flag, determining that no data is stored in the second address range includes: determining that the number of loops indicated by the consumer ring flag is an odd number; when the second owner flag is assigned the second value, determining that no data is stored in the second address range; or, determining that the number of loops indicated by the consumer ring flag is an even number; when the second owner flag is assigned the first value, determining that no data is stored in the second address range.

[0037] In combination with the second aspect, in a possible implementation manner of the second aspect, the first value is 1, and the second value is 0; or, the first value is 0, and the second value is 1.

[0038] According to a third aspect, a chip is provided, on which is disposed a data cache system as described in the first aspect or any possible implementation manner of the first aspect.

[0039] In a fourth aspect, a computer system is provided, wherein the computer system comprises the data cache system as described in the first aspect or any possible implementation manner of the first aspect.

[0040] In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium is used to store program code, wherein the program code includes instructions for executing the method of the second aspect or any possible implementation manner of the second aspect.

[0041] According to a sixth aspect, a computer program code is provided. When the computer program code is executed on a computer, the computer is used to execute the method of the second aspect or any possible implementation manner of the second aspect.

[0042] In the seventh aspect, a data cache system is provided, comprising: a cache space, the cache space comprising K address ranges, the K address ranges being used to store K entries respectively, K being an integer greater than 0, each entry comprising an owner flag, the owner flag being used to record a storage identifier or a free identifier, the storage identifier being used to indicate that data is stored in the corresponding entry, and the free identifier being used to indicate that data is not stored in the corresponding entry; the cache space being configured such that: when data is received in the first address range indicated by the producer pointer, the first owner flag in the first address range is updated to the storage identifier; the cache space being further configured such that: when the second owner flag in the second address range indicated by the consumer pointer is recorded as the storage identifier, the data in the second address range is read.

[0043] Optionally, the producer pointer is used to point to the next address range for writing data among the K address ranges.

[0044] Optionally, the consumer pointer is used to point to the next address range for reading data among the K address ranges.

[0045] Optionally, the cache space is further configured to: when the second owner flag bit in the second address range indicated by the consumer pointer is recorded as the free mark, no data is stored in the second address range.

[0046] Optionally, the cache space can be set in a storage unit in the computer system, and the above-mentioned storage unit includes but is not limited to double data rate synchronous dynamic random access memory (DDR-SDRAM, DDR), read-only memory (ROM), random access memory (RAM), storage array and other storage media that can store data.

[0047] In an embodiment of the present application, an owner flag is configured in the entry stored in each address range in the data cache system to indicate whether data is stored in the corresponding entry. The data writing thread can set the owner flag when writing data, and the data reading thread determines whether data is stored in the entry by reading the storage flag or the free flag in the owner flag. This data cache system can reduce the interaction between the data writing thread and the data reading thread, thereby simplifying the management process of the data cache system.

[0048] In combination with the seventh aspect, in a possible implementation manner of the seventh aspect, it also includes: a producer ring register, used to store a producer ring flag, the producer ring flag is used to record whether the number of loops of the producer pointer in the K address ranges is an odd number or an even number; the cache space is specifically configured to: when the number of loops indicated by the producer ring flag is an odd number and the first address range receives data, the first owner flag is updated from the second value to the first value; or, when the number of loops indicated by the producer ring flag is an even number and data is received in the first address range, the first owner flag is updated from the first value to the second value.

[0049] It should be understood that, for the owner flag bit in the address range indicated by the producer pointer, when the number of cycles indicated by the producer ring flag bit is an odd number, the first value represents a storage flag, and the second value represents an idle flag. When the number of cycles indicated by the producer ring flag bit is an even number, the second value represents a storage flag, and the first value represents an idle flag.

[0050] Optionally, the embodiment of the present application does not limit the specific values ​​of the first value and the second value, as long as they can represent the storage identifier and the idle identifier respectively. Optionally, the first value and the second value can be represented by binary numbers. For example, the first value can be 0 and the second value can be 1. Alternatively, the first value can be 00 and the second value can be 11.

[0051] In combination with the seventh aspect, in a possible implementation manner of the seventh aspect, it also includes: a consumer ring register, used to store a consumer ring flag, wherein the consumer ring flag is used to record whether the number of loops of the consumer pointer in the K address ranges is an odd number or an even number; the cache space is specifically configured as follows: when the number of loops indicated by the consumer ring flag is an odd number and the second owner flag is recorded as the first value, the data in the second address range is read; or, when the number of loops indicated by the consumer ring flag is an even number and the second owner flag is assigned the second value, the data in the second address range is read.

[0052] In combination with the seventh aspect, in a possible implementation manner of the seventh aspect, the first value is 1, and the second value is 0; or, the first value is 0, and the second value is 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic diagram of an application environment of an embodiment of the present application.

[0054] Figure 2 It is a schematic diagram of an application environment of yet another embodiment of the present application.

[0055] Figure 3 It is a schematic diagram of an application environment of yet another embodiment of the present application.

[0056] Figure 4 It is a schematic diagram of an application environment of yet another embodiment of the present application.

[0057] Figure 5 It is a schematic diagram of an application environment of yet another embodiment of the present application.

[0058] Figure 6 It is a schematic diagram of an application environment of yet another embodiment of the present application.

[0059] Figure 7 It is a structural diagram of a data cache system according to an embodiment of the present application.

[0060] Figure 8 It is a schematic diagram of the working status of a data cache system according to an embodiment of the present application.

[0061] Fig. 9 It is a schematic diagram of the structure of entries in a data cache system according to an embodiment of the present application.

[0062] Fig.10 It is a schematic diagram of the working status of a data cache system according to an embodiment of the present application.

[0063] Fig.11 This is a schematic diagram of the working status of a data cache system according to another embodiment of the present application.

[0064] Fig.12 It is a schematic diagram of an application environment of yet another embodiment of the present application. DETAILED DESCRIPTION

[0065] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0066] Figure 1 This is a possible application environment of the embodiment of the present application, such as Figure 1 As shown, the data cache system of the embodiment of the present application can be applied to a heterogeneous computing system. The heterogeneous computing system may include a main processor 101 and an accelerator 201. The main processor 101 and the accelerator 201 may be processors of the same type or processors of different types. For example, the main processor 101 may be a CPU, and the accelerator 201 may include an FPGA, an ASIC, etc. Alternatively, in some examples, the main processor 101 may be a complex instruction set computer (CISC), and the accelerator 201 may be a reduced instruction set computer (RISC). Optionally, the main processor 101 also includes a memory 102.

[0067] The main processor 101 and the accelerator 201 may be used to jointly maintain the data cache system. For example, the cache space in the data cache system may be set in the memory of the main processor 101 or in the accelerator 201. In the embodiment of the present application, the upper layer software used to write data to the data cache system may be referred to as a producer or a producer thread, and the upper layer software used to read data from the data cache system may be referred to as a consumer or a consumer thread.

[0068] Figure 1The main processor 101 and accelerator 201 in the embodiment can be used to maintain the producer thread and the consumer thread respectively. It should be noted that one or more data cache systems can be maintained between the main processor 101 and the accelerator 201. For different data cache systems, the main processor 101 can act as a producer or a consumer. Similarly, for different data cache systems, the accelerator 201 can act as a consumer or a producer. In addition, Figure 1 The main processor 101 or the accelerator 201 in the embodiment of the present application can also independently maintain the data cache system in the embodiment of the present application. For example, the main processor 101 can serve as a producer and a consumer of the same data cache system.

[0069] For example, Figure 2 This is a possible application scenario of another embodiment of the present application. Figure 2 As shown, a data cache system is jointly maintained between the main processor 101 and the accelerator 201. Among them, the main processor 101 is a producer, which is used to maintain the producer thread and write data to the cache space. The accelerator 201 is a consumer, which is used to maintain the consumer thread and read data from the cache space. It should be noted that the cache space can be set in the memory of the main processor 101, and can also be set in the accelerator 201. Alternatively, it can also be set in other storage devices connected to the main processor 101 or the accelerator 201, as long as the cache space can meet the requirement that both the main processor 101 and the accelerator 201 can access it.

[0070] For example, Figure 3 This is a possible application scenario of another embodiment of the present application. Figure 3 As shown, the main processor 101 and the accelerator 201 jointly maintain a data cache system. The accelerator 201 is a producer, which is used to maintain the producer thread and write data to the cache space. The main processor 101 is a consumer, which is used to maintain the consumer thread and read data from the cache space.

[0071] For example, Figure 4 This is a possible application scenario of another embodiment of the present application. Figure 4 As shown, the main processor 101 can also maintain a data cache system independently. The main processor 101 can simultaneously act as a producer and a consumer in a data cache system, and simultaneously maintain a producer thread and a consumer thread.

[0072] For example, Figure 5 This is a possible application scenario of another embodiment of the present application. Figure 5As shown, the accelerator 201 can also maintain a data cache system independently. The accelerator 201 can simultaneously serve as a producer and a consumer of a data cache system, and simultaneously maintain a producer thread and a consumer thread.

[0073] Those skilled in the art will appreciate that the main processor 101 and the accelerator 201 may simultaneously maintain Figures 2 to 5 That is, the main processor 101 and the accelerator 201 can simultaneously serve as producers or consumers of different data cache systems.

[0074] It should be noted that Figures 1 to 5 The application environment is only used as an example, and the data cache system of the embodiment of the present application is not limited to heterogeneous computing systems. The data cache system can also be maintained by a single processing device in a non-heterogeneous computing system, that is, the producer thread and the consumer thread are executed by the same processing device.

[0075] For example, Figure 6 This is a possible application scenario of yet another embodiment of the present application. Figure 6 This is a scenario where the data cache system is applied to non-heterogeneous computing systems. Figure 6 As shown, the computing device 301 can also maintain a data cache system independently. The computing device 301 can simultaneously act as a producer and a consumer of a data cache system, and simultaneously maintain a producer thread and a consumer thread. It should be noted that the cache space can be set in the memory of the computing device 301. Alternatively, it can also be set in other storage devices connected to the computing device 301, as long as the cache space can meet the requirement that the computing device 301 can access it.

[0076] The computing device 301 may include but is not limited to a CPU, FPGA, ASIC, RISC, etc.

[0077] Next, in conjunction with the accompanying drawings, the data caching system in the embodiment of the present application will be further introduced. In the embodiment of the present application, the data caching system can also be called a queue ring cache structure, or an extremely simple ring structure (extremely simple ring interface, ESRI).

[0078] Figure 7 Schematic diagram of the structure of a data cache system according to an embodiment of the present application. Figure 7As shown, the data cache system may include a cache space, a producer control unit, and a consumer control unit. The cache space is used to store data, and both the producer control unit and the consumer control unit can access the cache space. The producer control unit is used to execute a producer thread, and the consumer control unit is used to execute a consumer thread. The functions of the producer control unit and the consumer control unit can be implemented by software. In some examples, the producer control unit and the consumer control unit can be located in different processing devices. For example, Figure 1 The main processor 101 in the embodiment performs the function of the producer control unit, which is composed of Figure 1 The accelerator 201 in the embodiment performs the function of the consumer control unit. Optionally, the functions of the producer control unit and the consumer control unit may be performed by the same processing device. For example, the functions of the producer control unit and the consumer control unit may both be performed by Figure 1 The main processor 101 in the embodiment of the present invention is executed, or both are executed by Figure 7 The accelerator 201 in the embodiment may also be executed by Figure 6 Executed by the computing device 301 in.

[0079] Figure 8 1 is a schematic diagram of the working state of a data cache system according to an embodiment of the present application. The data cache system includes a cache space. The cache space can be set in a storage device accessible to both the producer and the consumer. For example, the location of the cache space can be as follows: Figures 1 to 6 As mentioned above, I will not repeat it here. Figure 8 As shown, the cache space includes K address ranges, the K address ranges are respectively used to store K entries, each entry includes an owner flag, and the owner flag is used to indicate whether data is stored in each entry. K is an integer greater than 0, as an example, Figure 8 K=16. The owner flag is used to record a storage flag or a free flag, the storage flag is used to indicate that data is stored in the corresponding entry, and the free flag is used to indicate that data is not stored in the corresponding entry.

[0080] It should be noted that, in the embodiment of the present application, the data stored in each entry may be a command, or may be other types of data except commands.

[0081] As an example, Fig. 9 Schematic diagram of the structure of entries in a data cache system according to an embodiment of the present application. Fig. 9As shown, the entry includes two fields, namely the owner flag and the command. Ownership can be a flag for communication between producers and consumers. For example, when initializing the data cache system, the owner flag in all entries can be set to 0 to indicate that no data is stored in the entry. Each time the upper-level software writes a command to an entry in the data cache system, the owner flag of the entry can be updated from 0 to 1, where 1 indicates that a command is stored in the entry. When reading a command, the upper-level software can determine whether a command is stored in the entry based on the value of the owner flag. Optionally, Fig. 9 The command field in the command can also be replaced by the data field.

[0082] Continue to see Figure 8 , the data cache system uses a producer pointer (PI) and a consumer pointer (CI) to maintain the cache space, the producer pointer is used to point to the next address range of the K address ranges for writing data, and the consumer pointer is used to point to the next address range of the K address ranges for reading data. In an embodiment of the present application, writing data may refer to writing data in an entry in the address range pointed to by the producer pointer, and reading data may refer to reading data in an entry in the address range pointed to by the consumer pointer.

[0083] The data cache system may respectively maintain the register corresponding to the producer pointer and the register corresponding to the consumer pointer. In some examples, if the producer thread and the consumer thread are executed by different processing devices, the producer pointer and the consumer pointer may be maintained by different processing devices. Figure 1 The main processor 101 in the Figure 1 The accelerator 201 in the embodiment maintains the consumer pointer. Optionally, if the producer thread and the consumer thread are executed by the same processing device, the producer pointer and the consumer pointer may be maintained by the same processing device.

[0084] Optionally, the producer control unit is configured to perform the following operations: determine a first address range indicated by the producer pointer; write data in the first address range, and update a first owner flag bit in the first address range to the storage identifier.

[0085] Optionally, the consumer control unit is configured to perform the following operations: determine a second address range indicated by the consumer pointer; and determine whether to read data from the second address range according to the second owner flag bit.

[0086] For example, the consumer control unit is specifically configured to: read data from the second address range when the second owner flag bit in the second address range is recorded as the storage identifier; and determine that no data is stored in the second address range when the second owner flag bit is recorded as the free identifier.

[0087] In an embodiment of the present application, an owner flag is configured in the entries stored in each address range in the data cache system to indicate whether data is stored in the corresponding entry, so that the data reading thread can determine whether data is stored in the entry by reading the storage flag or the free flag of the owner flag. This data cache system can reduce the interaction between the data writing thread and the thread for reading data, and even allow the data writing thread and the data reading thread to run independently, thereby simplifying the management process of the data cache system.

[0088] Optionally, continue to see Figure 8 The data cache system further includes a producer loop (PLoop) register for storing a producer loop flag, wherein the producer loop flag is used to record whether the producer pointer indicates that the number of loops of the K address ranges is an odd number or an even number. For example, PLoop=0 can be set to indicate an odd number, and PLoop=1 can be set to indicate an even number. Alternatively, PLoop=1 can be set to indicate an odd number, and PLoop=0 can be set to indicate an even number.

[0089] The producer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the producer ring flag is an odd number; write data in the first address range, and update the first owner flag in the first address range from the second value to the first value; or, the producer control unit is configured to specifically perform the following operations: determine that the number of loops indicated by the producer ring flag is an even number; write data in the first address range, and update the first owner flag in the first address range from the first value to the second value.

[0090] Optionally, the first value=1, and the second value=0; or, the first value=0, and the second value=1.

[0091] Optionally, the producer ring flag bit is assigned according to the following rule: the assignment of the producer ring flag bit is flipped once each time the producer pointer loops one round. For example, if the initial assignment of the producer ring flag bit is 0, the initial assignment of the producer ring flag bit remains 0 during the producer's first round of looping. After the producer pointer completes the first round of looping, the assignment of the producer ring flag bit flips from 0 to 1. During the producer's second round of looping, the initial assignment of the producer ring flag bit remains 1. After the producer pointer completes the second round of looping, the assignment of the producer ring flag bit flips from 1 to 0. During the producer's third round of looping, the initial assignment of the producer ring flag bit remains 0. In other words, the assignment of the producer ring flag bit is 0 when the producer pointer loops an odd number of times, and the assignment of the producer ring flag bit is 1 when the producer pointer loops an even number of times. Therefore, the producer ring flag bit can be used to indicate the parity of the producer pointer loop times.

[0092] Optionally, the owner flag is assigned according to the following rule: each time the producer pointer loops through a round, the assignment of the owner flag corresponding to the storage identifier is flipped once. Assuming that the initial assignment of the owner flag is the second value, when the producer pointer loops through an odd number of times, the producer control unit updates the assignment of the owner flag from the second value to the first value when writing data. When the producer pointer loops through an even number of times, the producer control unit needs to update the assignment of the owner flag from the first value to the second value when writing data. Therefore, the producer control unit needs to determine whether the assignment written to the owner flag is the first value or the second value based on the parity of the number of loops indicated by the producer pointer.

[0093] Optionally, in the embodiment of the present application, only the producer control unit may be allowed to update the value of the owner flag bit, while the consumer control unit cannot be used to update the value of the owner flag bit.

[0094] It can be seen from the above description that the assignment of the owner flag is determined according to the assignment of the producer ring flag. The meaning of the assignment of the owner flag is different depending on whether the number of loops of the producer pointer is an odd number or an even number. Therefore, when the upper-level software writes data in an entry in the data cache system, it can determine the assignment of the owner flag of the entry according to the current assignment of PLoop. This makes it easier for the upper-level software to determine when reading data whether the meaning indicated by the assignment of the owner flag is that data is stored or not stored.

[0095] In an embodiment of the present application, the data writing thread can determine the assignment of the owner flag bit corresponding to the storage identifier according to the parity of the number of cycles of the producer pointer, so that the data reading thread can determine whether data is stored in the entry according to the parity of the number of cycles of the consumer pointer and the assignment of the owner flag bit when reading data. Therefore, the data reading thread does not need to interact with the data writing thread to know which entries store data. This data cache system can reduce the interaction between the data writing thread and the thread for reading data, and can even run the data writing thread and the data reading thread independently, thereby simplifying the management process of the data cache system.

[0096] The data cache system also includes a consumer loop (CLoop) register for storing a consumer loop flag, wherein the consumer loop flag is used to record whether the producer pointer indicates that the number of cycles of the K address ranges is an odd number or an even number. For example, CLoop=0 can be set to indicate an odd number, and CLoop=1 can be set to indicate an even number. Alternatively, CLoop=1 can be set to indicate an odd number, and CLoop=0 can be set to indicate an even number.

[0097] The consumer control unit is configured to specifically perform the following operations: when the second owner flag bit in the second address range is recorded as the storage identifier, data is read from the second address range, including: determining that the number of loops indicated by the consumer ring flag bit is an odd number; when the second owner flag bit is recorded as the first value, data is read from the second address range; or, the consumer control unit is configured to specifically perform the following operations: determining that the number of loops indicated by the consumer ring flag bit is an even number; when the second owner flag bit is assigned the second value, data is read from the second address range.

[0098] It should be understood that, for the owner flag bit in the address range indicated by the producer pointer, when the number of cycles indicated by the producer ring flag bit is an odd number, the first value represents a storage flag, and the second value represents an idle flag. When the number of cycles indicated by the producer ring flag bit is an even number, the second value represents a storage flag, and the first value represents an idle flag.

[0099] Optionally, the embodiment of the present application does not limit the specific values ​​of the first value and the second value, as long as they can represent the storage flag and the idle flag respectively. Optionally, the first value and the second value can be represented by binary numbers. For example, the first value = 1, the second value = 0; or, the first value = 0, the second value = 1.

[0100] Optionally, the consumer ring flag bit is assigned a value in accordance with the following rule: the value of the consumer ring flag bit is flipped once each time the consumer pointer loops a round. For example, if the initial value of the consumer ring flag bit is 0, the initial value of the consumer ring flag bit remains 0 during the first round of looping of the consumer. After the consumer pointer completes the first round of looping, the value of the consumer ring flag bit flips from 0 to 1. During the second round of looping of the consumer, the initial value of the consumer ring flag bit remains 1. After the consumer pointer completes the second round of looping, the value of the consumer ring flag bit flips from 1 to 0. During the third round of looping of the consumer, the initial value of the consumer ring flag bit remains 0. In other words, the value of the consumer ring flag bit is 0 when the consumer pointer loops an odd number of times, and the value of the consumer ring flag bit is 1 when the consumer pointer loops an even number of times. Therefore, the consumer ring flag bit can be used to indicate the parity of the number of times the consumer pointer loops.

[0101] Optionally, the consumer control unit needs to follow the following rules when judging the meaning of the owner flag: each time the consumer pointer loops through a round, the assignment of the owner flag corresponding to the storage identifier is flipped once. It should be noted that the rule for the consumer control unit to judge the meaning of the assignment of the owner flag is related to the rule for the producer control unit to assign a value to the owner flag. For example, assuming that the initial assignment of the owner flag is the second value, when the producer pointer loops an odd number of times, the production control unit updates the assignment of the owner flag from the second value to the first value when writing data. Therefore, when the consumer pointer loops an odd number of times, if the assignment of the owner flag is the first value, it means that data is stored in the corresponding entry, and if the assignment of the owner flag is the second value, it means that no data is stored in the corresponding entry. The judgment rules when the consumer pointer loops an even number of times are similar and will not be repeated here.

[0102] In an embodiment of the present application, the data reading thread determines whether the value of the owner flag bit in the entry indicated by the consumer pointer is a storage flag or an idle flag based on the parity of the number of cycles of the consumer pointer recorded in the consumer ring register, and then determines whether data is stored in the entry. This definition method of the data cache system can reduce the interaction between the data writing thread and the data reading thread, and even allow the data writing thread and the data reading thread to run independently, thereby simplifying the management process of the data cache system.

[0103] For example, when the producer pointer loops an odd number of times, PLoop=0, and when the data cache system writes a command in the address range pointed to by the producer pointer, the owner flag bit is configured to be assigned a value of 1, where 1 indicates that a command is stored in the entry corresponding to the owner flag bit, and 0 indicates that a command is not stored in the entry corresponding to the owner flag bit. When the producer pointer loops an even number of times, PLoop=1, and when the data cache system writes a command in the address range pointed to by the producer pointer, the owner flag bit is configured to be assigned a value of 0, where 0 indicates that a command is stored in the entry corresponding to the owner flag bit, and 1 indicates that a command is not stored in the entry corresponding to the owner flag bit.

[0104] Optionally, when reading a command, the consumer pointer determines the meaning of the current owner flag assignment according to the consumer ring flag assignment. For example, when the consumer pointer loops an odd number of times, CLoop = 0. When reading a command according to the consumer pointer, if the owner flag assignment is configured as 1, it indicates that a command is stored in the entry and the upper-layer software can read the command; if the owner flag assignment is configured as 0, it indicates that no command is stored in the entry and the upper-layer software does not read the command. When the consumer pointer loops an even number of times, CLoop = 1. When reading a command according to the consumer pointer, if the owner flag assignment is configured as 0, it indicates that a command is stored in the entry and the upper-layer software can read the command; if the owner flag assignment is configured as 1, it indicates that no command is stored in the entry and the upper-layer software does not read the command.

[0105] Optionally, the number K of address ranges included in the data cache system in the embodiment of the present application may be 2. x , x is a positive integer greater than or equal to 1.

[0106] In some examples, the data cache system can be managed by producers and consumers. Among them, the producer can refer to an upper-level software module that performs write operations on entries, and the consumer can refer to an upper-level software module that performs read operations on entries. The producer is used to maintain a producer pointer to indicate the location that has been produced. The producer is also used to maintain a producer ring flag, indicating that a round of entries has been produced. The consumer is also used to maintain a consumer pointer, indicating the location to read the next entry. The consumer also maintains a consumer ring flag, indicating that a round of entries has been consumed. In an embodiment of the present application, producing an entry refers to a command written into an entry in the data cache system, and consuming an entry refers to a command read into an entry in the data cache system.

[0107] In an embodiment of the present application, the upper layer software can ensure that the data cache system does not overflow. For example, the producer can ensure that a maximum of K commands are sent to the data cache system, so PI will never exceed CI, and overflow will not occur. Therefore, the register indicating the full state and the register indicating the empty state may not be set in the data cache system. The full state means that the number of unread entries in the data cache system has reached K, and the empty state means that the number of entries in the data cache system that write commands is 0. This definition method of the data cache system can simplify the management process of the data cache system.

[0108] Fig.10 It is a schematic diagram of the working status of a data cache system according to an embodiment of the present application. Fig.10 The process of the producer pointer loop from the first round to the second round is shown. In which, the command to write to the data cache system can be called a production command or a production entry, and the command to read from the data cache system can be called a consumption command or a consumption entry. Fig.10 As shown, when the system is initialized, PI=0, CI=0, PLoop=0, CLoop=0, and ownership=0 of all entries, indicating that the commands in the entries have not been produced. When the first entry is produced, PI=0 is used as the index address, the ownership field in the entry is set to 1, and the command field is set to command 0 (command 0), indicating that the entry with PI=0 has been produced. The value of PI is then updated to PI=PI+1, that is, PI=1, to point to the next entry to be produced. PI continues to produce entries in this way, and after PI=K-1, the next value of PI is PI=0. At this time, the value of PLoop changes from 0 to 1, indicating that the producer pointer has completed the first round of production, and PI returns to the initial value of 0.

[0109] Fig.11 This is a schematic diagram of the working status of a data cache system according to another embodiment of the present application. Fig.11 The process of the consumer pointer cycle from the first round to the second round is shown. Fig.11 As shown in the figure, in the first round, when CLoop=0, the consumer uses the CI value as the index to check the ownership value in the entry. If ownership=1, it means that the command of the entry has been produced, and the consumer uses CI as the index to read the corresponding command in the entry. If ownership=0, it means that the command of the entry has not been produced.

[0110] As consumers continue to consume commands in entries, the CI value continues to increase, and the number of pending commands in the data cache system is lower than the maximum value K, so the producer can continue to produce. At this time, the producer starts the second round of production, PLoop = 1. After the producer produces a new command, it changes the corresponding ownership value from 1 to 0, indicating that the second round of entries has been produced.

[0111] After the consumer consumes K items in the first round, the value of CI returns to the initial value of 0, and the value of CLoop changes from 0 to 1, indicating that the consumer has consumed all the items in the first round. In the second round, the consumer needs to determine whether the ownership value is 0. Ownership = 0 means that the item has been produced, and ownership = 1 means that the item has not been produced.

[0112] It can be seen that the producer and consumer each have a ring register (PLoop and CLoop) to indicate the meaning of the ownership value. For example, when the value of PLoop (or CLoop) is 0, it means that the producer (or consumer) has looped an odd number of times, and ownership = 1 means that the entry has been produced and can be consumed. When the value of PLoop (or CLoop) is 1, it means that the producer (or consumer) has looped an even number of times, and ownership = 0 means that the entry has been produced and can be consumed.

[0113] In an embodiment of the present application, the producer ring register and the consumer ring register are used to record the cycle count status of the producer pointer and the consumer pointer, so that the upper-level software can determine the assignment meaning of the owner flag in the entry by reading the assignment of the producer ring register and the consumer ring register, and then determine whether a command is stored in the entry. This data cache system can reduce the interaction between the write data thread and the read data thread, and even allow the write data thread and the read data thread to run independently, thereby simplifying the management process of the data cache system.

[0114] Continue to see Fig.10 , when PLoop=1, Cloop=0, the data cache system is already full of K commands, and the consumer has not consumed any entries, and the number of commands in the data cache system has reached the system's command upper limit. In the embodiment of the present application, in order to avoid overflow of the data cache system, the upper-layer software can be designed to ensure that the producer will not continue to update the command when the command data reaches the upper limit. The above-mentioned design of the upper-layer software can be specifically referred to Fig.12 Description in .

[0115] Fig.12 It is a schematic diagram of an application scenario of yet another embodiment of the present application. Fig.12 In the embodiment, two data cache systems can be maintained between the main processor 101 and the accelerator 201, one for storing the command queue and the other for storing the completion queue. The command queue is used to store the commands to be processed, and the completion queue is used to store the completed commands. For the command queue, the main processor 101 is the producer and the accelerator 201 is the consumer. The main processor 101 is used to write commands in the command queue, and the accelerator 201 is used to read commands from the command queue. For the completion queue, the accelerator 201 is the producer and the main processor 101 is the consumer. Specifically, after reading the command, the accelerator 201 can process the command, and after completing the command, write the completed command into the completion queue, and the main processor 101 can read the command from the completion queue to know the currently completed command. The main controller can control the number of commands cached in the command queue, and after receiving the completion message of each command through the completion queue, send a new command to the command queue to ensure that the number of online commands does not exceed the upper limit.

[0116] For example, assume that the upper limit of the number of commands stored in the command queue is 256. The main processor 101 can first write 256 commands into the command queue. Then the main processor 101 is limited to no longer sending new commands to the command queue. After the accelerator 201 completes a command, the completion entry of the command can be written into the completion queue. The main processor 101 can learn that the command has been completed by reading the completion entry in the completion queue. Among them, the completion entry of the command can be understood as the completion message of the command. Therefore, the main processor 101 can send a new command to the command queue. In the subsequent process, after the main processor 101 receives the completion message of a command, it can send a new command to the command queue until no new commands are generated. This upper-level software design method can ensure that the number of commands in the command queue is less than or equal to 256, thereby avoiding the situation of command overflow in the data cache system.

[0117] In an embodiment of the present application, the computer system can ensure that the data cache system does not overflow through upper-level software, so the register indicating the full state and the register indicating the empty state may not be set in the data cache system. This definition method of the data cache system can simplify the management process of the data cache system.

[0118] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0119] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0120] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0121] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0123] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0124] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data cache system, characterized in that: include: A cache space, wherein the cache space includes K address ranges, the K address ranges are respectively used to store K entries, K is an integer greater than 0, each entry includes an owner flag, the owner flag is used to record a storage flag or a free flag, the storage flag is used to indicate that data is stored in the corresponding entry, and the free flag is used to indicate that data is not stored in the corresponding entry; The producer control unit is configured to perform the following operations: write data into a first address range indicated by the producer pointer, and update a first owner flag bit in the first address range to the storage identifier; The consumer control unit is configured to perform the following operations: determine whether to read data from the second address range according to the second owner flag bit in the second address range indicated by the consumer pointer.

2. The data cache system according to claim 1, characterized in that: The consumer control unit is configured to specifically perform the following operations: In the case where the second owner flag bit is recorded as the storage identifier, reading data from the second address range; or, When the second owner flag is recorded as the free mark, it is determined that no data is stored in the second address range.

3. The data cache system according to claim 1 or 2, characterized in that: Also includes: A producer ring register, used to store a producer ring flag, wherein the producer ring flag is used to record whether the number of cycles of the producer pointer in the K address range is an odd number or an even number; The producer control unit is configured to specifically perform the following operations: Determining that the number of cycles indicated by the producer ring flag is an odd number; Writing data into the first address range and updating the first owner flag in the first address range from the second value to the first value; or, The producer control unit is configured to specifically perform the following operations: Determining that the number of cycles indicated by the producer ring flag is an even number; Data is written in the first address range, and a first owner flag bit in the first address range is updated from the first value to the second value.

4. The data cache system according to claim 3, characterized in that: Also includes: A consumer ring register, used for storing a consumer ring flag, wherein the consumer ring flag is used for recording whether the number of cycles of the consumer pointer in the K address range is an odd number or an even number; The consumer control unit is configured to specifically perform the following operations: Determining that the number of cycles indicated by the consumer ring flag bit is an odd number; When the second owner flag is recorded as the first value, reading data from the second address range; or, The consumer control unit is configured to specifically perform the following operations: Determining that the number of cycles indicated by the consumer ring flag bit is an even number; When the second owner flag is assigned the second value, data is read from the second address range.

5. The data cache system according to claim 4, characterized in that: The consumer control unit is configured to specifically perform the following operations: Determining that the number of cycles indicated by the consumer ring flag bit is an odd number; When the second owner flag bit is assigned the second value, it is determined that no data is stored in the second address range; or, Determining that the number of cycles indicated by the consumer ring flag bit is an even number; When the second owner flag is assigned the first value, it is determined that no data is stored in the second address range.

6. The data cache system according to claim 3, characterized in that: The first value is 1, and the second value is 0; or, the first value is 0, and the second value is 1.

7. A control method for a data cache system, characterized in that: The data cache system comprises: a cache space, the cache space comprises K address ranges, the K address ranges are respectively used to store K entries, K is an integer greater than 0, each entry comprises an owner flag, the owner flag is used to record a storage flag or a free flag, the storage flag is used to indicate that data is stored in the corresponding entry, and the free flag is used to indicate that data is not stored in the corresponding entry; The method comprises: Writing data into a first address range indicated by a producer pointer, and updating a first owner flag in the first address range to the storage identifier; Whether to read data from the second address range is determined according to the second owner flag bit in the second address range indicated by the consumer pointer.

8. The method according to claim 7, characterized in that The determining whether to read data from the second address range according to the second owner flag bit in the second address range indicated by the consumer pointer comprises: In a case where the second owner flag bit in the second address range is recorded as the storage identifier, reading data from the second address range; or, When the second owner flag is recorded as the free mark, it is determined that no data is stored in the second address range.

9. The method according to claim 8, characterized in that The data cache system also includes: A producer ring register, used to store a producer ring flag, wherein the producer ring flag is used to record whether the number of cycles of the producer pointer in the K address ranges is an odd number or an even number, wherein the value of the owner flag is determined according to the value of the producer ring flag; The step of writing data in the first address range and updating the first owner flag in the first address range to the storage identifier includes: Determining that the number of cycles indicated by the producer ring flag is an odd number; Writing data into the first address range and updating the first owner flag in the first address range from the second value to the first value; or, Determining that the number of cycles indicated by the producer ring flag is an even number; Data is written in the first address range, and a first owner flag bit in the first address range is updated from the first value to the second value.

10. The method according to claim 9, characterized in that Also includes: A consumer ring register, used for storing a consumer ring flag, wherein the consumer ring flag is used for recording whether the number of cycles of the consumer pointer in the K address range is an odd number or an even number; In a case where the second owner flag bit in the second address range is recorded as the storage identifier, reading data from the second address range includes: Determining that the number of cycles indicated by the consumer ring flag bit is an odd number; When the second owner flag is recorded as the first value, reading data from the second address range; or, The consumer control unit is configured to specifically perform the following operations: Determining that the number of cycles indicated by the consumer ring flag bit is an even number; When the second owner flag is assigned the second value, data is read from the second address range.

11. The method according to claim 10, characterized in that Also includes: When the second owner flag bit is recorded as the free mark, determining that no data is stored in the second address range includes: Determining that the number of cycles indicated by the consumer ring flag bit is an odd number; When the second owner flag bit is assigned the second value, it is determined that no data is stored in the second address range; or, Determining that the number of cycles indicated by the consumer ring flag bit is an even number; When the second owner flag is assigned the first value, it is determined that no data is stored in the second address range.

12. The method according to any one of claims 9 to 11, characterized in that The first value is 1, and the second value is 0; or, the first value is 0, and the second value is 1.

13. A data cache system, characterized in that: include: A cache space, wherein the cache space includes K address ranges, the K address ranges are respectively used to store K entries, K is an integer greater than 0, each entry includes an owner flag, the owner flag is used to record a storage flag or a free flag, the storage flag is used to indicate that data is stored in the corresponding entry, and the free flag is used to indicate that data is not stored in the corresponding entry; The cache space is configured such that: when a first address range indicated by a producer pointer receives data, a first owner flag bit in the first address range is updated to the storage identifier; The cache space is further configured such that: when a second owner flag bit in a second address range indicated by a consumer pointer is recorded as the storage identifier, data in the second address range is read.

14. The data cache system according to claim 13, characterized in that: Also includes: A producer ring register, used to store a producer ring flag, wherein the producer ring flag is used to record whether the number of cycles of the producer pointer in the K address range is an odd number or an even number; The cache space is specifically configured to: when the number of cycles indicated by the producer ring flag is an odd number and the first address range receives data, update the first owner flag from the second value to the first value; or, When the number of cycles indicated by the producer ring flag is an even number and data is received in the first address range, the first owner flag is updated from the first value to the second value.

15. The data cache system according to claim 14, characterized in that: Also includes: A consumer ring register, used for storing a consumer ring flag, wherein the consumer ring flag is used for recording whether the number of cycles of the consumer pointer in the K address range is an odd number or an even number; The cache space is specifically configured as follows: when the number of cycles indicated by the consumer ring flag is an odd number and the second owner flag is recorded as the first value, data in the second address range is read; or, When the number of cycles indicated by the consumer ring flag is an even number and the value assigned to the second owner flag is the second value, data in the second address range is read.

16. The data cache system according to claim 14 or 15, characterized in that: The first value is 1, and the second value is 0; or, the first value is 0, and the second value is 1.

17. A data processing chip, characterized in that: include: A data cache system as claimed in any one of claims 1 to 6.

18. A computer system, characterized in that: include: A data cache system as claimed in any one of claims 1 to 6.

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