Semiconductor device and method for forming the same

Abstract

The present invention discloses a semiconductor device and a method for forming the same, the method comprising: forming a first groove and a second groove in a dense area and a sparse area of ​​a semiconductor substrate respectively, the density of the first groove being greater than the density of the second groove; depositing an initial isolation layer in the first groove and the second groove and on the semiconductor substrate; etching back the initial isolation layer to form a transition isolation layer, the transition isolation layer comprising a first convex thorn on the surface of the dense area transition isolation layer and a second convex thorn on the surface of the sparse area transition isolation layer, the density of the first convex thorn being greater than the density of the second convex thorn; performing a convex thorn flattening treatment on the transition isolation layer to remove at least a portion of the height of the first convex thorn and at least a portion of the height of the second convex thorn; then grinding the transition isolation layer to form a first isolation structure in the first groove and a second isolation structure in the second groove. The method reduces the height difference between the surface of the first isolation structure and the surface of the second isolation structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] In the manufacturing process of semiconductor devices, chemical mechanical polishing (CMP) is widely used to obtain a material layer with uniform thickness. In addition, for some semiconductor devices that require higher operating voltages, shallow trench isolation (STI) structures are usually required to be very deep to achieve high voltage requirements. For example, 0.15HV devices require higher operating voltage requirements.

[0003] The method of forming a shallow trench isolation structure generally includes: forming a trench in a semiconductor substrate, depositing a shallow trench isolation film in the trench and on the semiconductor substrate using a high density plasma deposition (HDP) process, and then planarizing the shallow trench isolation film to form a shallow trench isolation structure.

[0004] However, the performance of existing semiconductor devices including shallow trench isolation structures is poor. Summary of the invention

[0005] The purpose of the present invention is to solve the problem of poor performance of semiconductor devices caused by uneven depth of isolation structures in the prior art. The present invention provides a method for forming a semiconductor device, which can reduce the height difference between the top surfaces of a first isolation structure and a second isolation structure, thereby further improving the performance of the semiconductor device.

[0006] In order to solve the above technical problems, an embodiment of the present invention discloses a method for forming a semiconductor device, comprising:

[0007] Providing a semiconductor substrate, the semiconductor substrate comprising a dense region and a sparse region;

[0008] forming a first trench in the dense region of the semiconductor substrate, and forming a second trench in the sparse region of the semiconductor substrate, wherein the density of the first trench is greater than the density of the second trench;

[0009] depositing an initial isolation layer in the first trench and the second trench and on the semiconductor substrate;

[0010] Etching back the initial isolation layer to form a transition isolation layer, the transition isolation layer covers the top of the semiconductor substrate around the first trench and around the second trench, the transition isolation layer comprises a first convex thorn on the surface of the transition isolation layer in the dense area and a second convex thorn on the surface of the transition isolation layer in the sparse area, and the density of the first convex thorn is greater than the density of the second convex thorn;

[0011] Performing a burr-smoothing treatment on the transition isolation layer to remove at least a portion of the height of the first burr and at least a portion of the height of the second burr;

[0012] After the burr planarization process is performed, the transition isolation layer is ground to form a first isolation structure located in the first trench and a second isolation structure located in the second trench.

[0013] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein the method for performing the burr flattening treatment on the transition isolation layer comprises: etching the transition isolation layer using an isotropic etching process.

[0014] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein the isotropic etching process includes an isotropic wet etching process.

[0015] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, and the parameters of the isotropic wet etching process include: the etching solution used is a hydrofluoric acid solution, the volume percentage concentration of hydrofluoric acid is 0.5% to 5%, the temperature is 18 degrees Celsius to 28 degrees Celsius, and the etching time is 5 minutes to 30 minutes.

[0016] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein the transition isolation layer is subjected to a burr flattening treatment to remove a portion of the height of the first burr and a portion of the height of the second burr.

[0017] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein after the burr flattening treatment, the height of the remaining first burr object is less than or equal to 50 angstroms, and the height of the remaining second burr object is less than or equal to 50 angstroms.

[0018] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein the transition isolation layer is subjected to a burr flattening treatment to remove all of the first burrs and all of the second burrs.

[0019] According to another specific embodiment of the present invention, in a method for forming a semiconductor device disclosed in an embodiment of the present invention, the process of etching back the initial isolation layer to form a transition isolation layer includes an anisotropic dry etching process.

[0020] According to another specific embodiment of the present invention, in a method for forming a semiconductor device disclosed in an embodiment of the present invention, the process of grinding the transition isolation layer includes a chemical mechanical grinding process.

[0021] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, before forming the initial isolation layer, a mask structure is provided on the surface of the semiconductor substrate around the first trench and on the surface of the semiconductor substrate around the second trench, and after forming the initial isolation layer, the initial isolation layer also covers the mask structure; grinding the transition isolation layer until the top surface of the mask structure is exposed to form the first isolation structure and the second isolation structure;

[0022] The method for forming a semiconductor device further includes: after forming the first isolation structure and the second isolation structure, removing the mask structure.

[0023] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein the mask structure includes a stress buffer layer located on the surface of the semiconductor substrate around the first trench and on the surface of the semiconductor substrate around the second trench, a main mask layer located on top of the stress buffer layer, and a barrier layer located on top of the main mask layer; the transition isolation layer is ground until the top surface of the barrier layer is exposed.

[0024] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a method for forming a semiconductor device, wherein the material of the stress buffer layer includes silicon oxide; the material of the main mask layer includes silicon nitride; and the material of the barrier layer includes silicon oxynitride.

[0025] According to another specific embodiment of the present invention, a method for forming a semiconductor device disclosed in an embodiment of the present invention further includes: a depth of the first trench is 8000 angstroms to 10000 angstroms; a depth of the second trench is 8000 angstroms to 10000 angstroms.

[0026] According to another specific embodiment of the present invention, a method for forming a semiconductor device disclosed in an embodiment of the present invention also includes: the top surface of the first isolation structure is 600 angstroms to 1200 angstroms higher than the top surface of the semiconductor substrate; the top surface of the second isolation structure is 600 angstroms to 1200 angstroms higher than the top surface of the semiconductor substrate.

[0027] An embodiment of the present invention further discloses a semiconductor device, which is formed by the method for forming a semiconductor device in any of the above embodiments.

[0028] The beneficial effects of the present invention are:

[0029] In the method for forming a semiconductor device provided by the present invention, the depths of the first trench and the second trench are relatively large, so that the isolation performance of the first isolation structure and the second isolation structure is enhanced. Before grinding the transition isolation layer, the initial isolation layer is etched back to form a transition isolation layer, and the height of the transition isolation layer is less than the height of the initial isolation layer. In this way, in the process of grinding the transition isolation layer, the thickness of the transition isolation layer to be ground is small, which reduces the process cost. Since the transition isolation layer is subjected to burr flattening treatment, at least part of the height of the first burr object and at least part of the height of the second burr object are removed, so that the heights of the first burr object and the second burr object are reduced or the first burr object and the second burr object are completely removed. Therefore, in the process of grinding the transition isolation layer, the time required for grinding the first burr object and grinding the second burr object is small, and the blocking degree of the first burr object on the transition isolation layer in the grinding intensive area and the blocking degree of the second burr object on the transition isolation layer in the grinding intensive area are both small. Then, the difference between the rate of grinding the transition isolation layer in the grinding intensive area and the rate of grinding the transition isolation layer in the grinding intensive area is small, and accordingly, the height difference between the top surface of the first isolation structure and the top surface of the second isolation structure is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 4 It is a structural schematic diagram of the formation process of a semiconductor device;

[0031] Figure 5 is a flow chart of a method for forming a semiconductor device provided by an embodiment of the present invention;

[0032] Figures 6 to 11 It is a structural schematic diagram of a method for forming a semiconductor device provided by an embodiment of the present invention.

[0033] Reference numerals:

[0034] 100: semiconductor substrate; 111: first trench; 112: second trench; 120: initial isolation layer; 121: transition isolation layer; 131: first isolation structure; 132: second isolation structure; A: dense area; B: sparse area;

[0035] 200: semiconductor substrate; 211: first trench; 212: second trench; 201: stress buffer layer; 202: main mask layer; 203: barrier layer; 220: initial isolation layer; 221: transition isolation layer; 231: first isolation structure; 232: second isolation structure; T1: first protrusion; T2: second protrusion; M: dense area; N: sparse area. DETAILED DESCRIPTION

[0036] The following specific embodiments illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this implementation. On the contrary, the purpose of introducing the invention in conjunction with the implementation is to cover other options or modifications that may extend based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0037] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0038] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0039] The terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0040] In the description of this embodiment, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this embodiment can be understood according to specific circumstances.

[0041] As described in the background art, the performance of existing semiconductor devices including shallow trench isolation structures is relatively poor.

[0042] A method for forming a semiconductor device comprises: referring to Figure 1 , providing a semiconductor substrate 100, the semiconductor substrate 100 including a dense area A and a sparse area B; forming a first trench 111 in the dense area A of the semiconductor substrate 100, forming a second trench 112 in the sparse area B of the semiconductor substrate 100, the density of the first trench 111 being greater than the density of the second trench 112; referring to Figure 2 , depositing an initial isolation layer 120 in the first trench 111 and the second trench 112 and on the semiconductor substrate 100; Figure 3 , the initial isolation layer 120 is etched back to form a transition isolation layer 121; Figure 4 , grinding the transition isolation layer 121 to form a first isolation structure 131 located in the first trench 111 and a second isolation structure 132 located in the second trench 112 .

[0043] In the above formation method, the depths of the first trench 111 and the second trench 112 are relatively large, so that the isolation performance of the first isolation structure 131 and the second isolation structure 112 is enhanced, so as to be applied to semiconductor devices with higher operating voltages. Since the depths of the first trench 111 and the second trench 112 are large, a thicker initial isolation layer 120 needs to be deposited, and the thickness of the initial isolation layer 120 above the surface of the semiconductor substrate 100 is correspondingly thicker. Before grinding the transition isolation layer 121, the initial isolation layer 120 is etched back to form a transition isolation layer 121, and the height of the transition isolation layer 121 is less than the height of the initial isolation layer 120, so that in the process of grinding the transition isolation layer 121, the thickness of the transition isolation layer 121 that needs to be ground is smaller, thereby reducing the process cost.

[0044] However, after the initial isolation layer 120 is formed, the top surface of the initial isolation layer 120 is high and low floating. Figure 2The surface of the initial isolation layer 120 above the first trench 111 is lower than the surface of the initial isolation layer 120 above the semiconductor substrate 100 around the first trench 111, and the surface of the initial isolation layer 120 above the second trench 112 is lower than the surface of the initial isolation layer 120 above the semiconductor substrate 100 around the second trench 112. Therefore, after the initial isolation layer 120 is etched back, the surface of the formed transition isolation layer 121 has a first convex object T1 and a second convex object T2. The first convex object T1 is located on the surface of the transition isolation layer 121 in the dense area A, and the second convex object T2 is located on the surface of the transition isolation layer 121 in the sparse area B. The density of the first convex object T1 is greater than the density of the second convex object T2. Since the density of the first convex thorn T1 is greater than that of the second convex thorn T2, during the process of grinding the transition isolation layer 121, the blocking effect of the first convex thorn T1 on grinding is greater than the blocking effect of the second convex thorn T2 on grinding. Therefore, the grinding rate of the transition isolation layer 121 in the dense area B is lower than the grinding rate of the transition isolation layer 121 in the sparse area B, resulting in the surface height of the formed first isolation structure 131 being greater than the surface height of the second isolation structure 132. The difference in surface height between the first isolation structure 131 and the second isolation structure 132 is large, which makes it difficult to meet the requirements of process design.

[0045] In order to solve the above technical problems, the present invention proposes a method for forming a semiconductor device, referring to Figure 5 , including the following steps:

[0046] S01: providing a semiconductor substrate, wherein the semiconductor substrate comprises a dense region and a sparse region;

[0047] S02: forming a first trench in a dense area of ​​the semiconductor substrate, and forming a second trench in a sparse area of ​​the semiconductor substrate, wherein the density of the first trench is greater than the density of the second trench;

[0048] S03: depositing an initial isolation layer in the first trench and the second trench and on the semiconductor substrate;

[0049] S04: etching back the initial isolation layer to form a transition isolation layer, the transition isolation layer covers the top of the semiconductor substrate around the first trench and around the second trench, the transition isolation layer includes a first convex thorn object located on the surface of the transition isolation layer in a dense area and a second convex thorn object located on the surface of the transition isolation layer in a sparse area, and the density of the first convex thorn object is greater than the density of the second convex thorn object;

[0050] S05: performing a burr-smoothing treatment on the transition isolation layer to remove at least a portion of the height of the first burr and at least a portion of the height of the second burr;

[0051] S06: grinding the transition isolation layer to form a first isolation structure located in the first trench and a second isolation structure located in the second trench.

[0052] The method reduces the height difference between the surface of the first isolation structure and the surface of the second isolation structure.

[0053] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0054] The following is combined with Figures 6 to 11 The method for forming a semiconductor device provided by an embodiment of the present invention is described in detail.

[0055] refer to Figure 6 , a semiconductor substrate 200 is provided, and the semiconductor substrate 200 includes a dense area M and a sparse area N.

[0056] The material of the semiconductor substrate 200 is silicon, germanium or silicon germanium. The material of the semiconductor substrate 200 may also be other semiconductor materials, which will not be listed one by one here.

[0057] The density of devices formed in the dense area M of the semiconductor substrate 200 is greater than the density of devices formed in the sparse area N of the semiconductor substrate 200 .

[0058] Continue to refer Figure 6 , a first trench 211 is formed in a dense area M of a semiconductor substrate 200 , and a second trench 212 is formed in a sparse area N of the semiconductor substrate 200 , and the density of the first trench 211 is greater than the density of the second trench 212 .

[0059] The depths of the first trench 211 and the second trench 212 are relatively large, so that the isolation performance of the first isolation structure 231 and the second isolation structure 232 formed subsequently is enhanced, so as to be applied to semiconductor devices with higher operating voltages.

[0060] In one embodiment, the depth of the first trench 211 is 8000 angstroms to 10000 angstroms, such as 9000 angstroms, and the depth of the second trench 212 is 8000 angstroms to 10000 angstroms, such as 9000 angstroms.

[0061] In this embodiment, the depth of the first groove 211 is equal to the depth of the second groove 212. In other embodiments, the depth of the first groove 211 is different from the depth of the second groove 212.

[0062] In this embodiment, the opening of the first groove 211 is smaller than the opening of the second groove 212 .

[0063] The process of forming the second trench 212 of the first trench 211 is an etching process, including a dry etching process or a wet etching process.

[0064] In this embodiment, the second trench 212 is formed during the process of forming the first trench 211, which simplifies the process steps. In other embodiments, the first trench 211 and the second trench 212 are formed sequentially.

[0065] Specifically, the steps of forming the second groove 212 of the first groove 211 include: forming a stress buffer film, a main mask material film and a barrier film in sequence on the surface of the semiconductor substrate 200; patterning the barrier film, the main mask material film, the stress buffer film and the semiconductor substrate 200, forming the first groove 211 in the dense area M of the semiconductor substrate 200, and forming the second groove 212 in the sparse area N of the semiconductor substrate 200.

[0066] A mask structure is provided on the surface of the semiconductor substrate 200 around the first trench 211 and on the surface of the semiconductor substrate 200 around the second trench 212. The mask structure includes a stress buffer layer 201 located on the surface of the semiconductor substrate 200 around the first trench 211 and on the surface of the semiconductor substrate 200 around the second trench 212, a main mask layer 202 located on the top of the stress buffer layer 201, and a barrier layer 203 located on the top of the main mask layer 202. The stress buffer layer 201 is formed of a stress buffer film, the main mask layer 202 is formed of a main mask material film, and the barrier layer 203 is formed of a barrier film.

[0067] In this embodiment, the material of the stress buffer layer 201 includes silicon oxide, the material of the main mask layer 202 includes silicon nitride, and the material of the barrier layer 203 includes silicon oxynitride.

[0068] In one embodiment, the thickness of the stress buffer layer 201 is 200 angstroms to 400 angstroms, the thickness of the main mask layer 202 is 1500 angstroms to 2000 angstroms, and the thickness of the barrier layer 203 is 100 angstroms to 200 angstroms.

[0069] The stress buffer layer 201 has the following functions: buffering the stress of the main mask layer 202 on the semiconductor substrate 200 .

[0070] The main mask layer 202 has the following functions: in the process of patterning the first trench 211 and the second trench 212 , it serves as a mask for etching the semiconductor substrate 200 . The main mask layer 202 is made of a hard mask material, so the morphology of the first trench 211 and the second trench 212 can be better controlled.

[0071] The function of the barrier layer 203 includes: serving as a stop layer for subsequent grinding of the transition isolation layer 121 .

[0072] refer to Figure 7 An initial isolation layer 220 is deposited in the first trench 211 and the second trench 212 and on the semiconductor substrate 200 .

[0073] The process of forming the initial isolation layer 220 includes a high density plasma deposition process.

[0074] The material of the initial isolation layer 220 includes silicon oxide.

[0075] Since the first trench 211 and the second trench 212 have greater depths, a thicker initial isolation layer 220 needs to be deposited.

[0076] The top surface of the initial isolation layer 220 is floating. Specifically, the surface of the initial isolation layer 220 above the first trench 211 is lower than the surface of the initial isolation layer 220 above the semiconductor substrate 200 around the first trench 211, and the surface of the initial isolation layer 220 above the second trench 212 is lower than the surface of the initial isolation layer 220 above the semiconductor substrate 200 around the second trench 212.

[0077] The initial isolation layer 220 also covers the mask structure.

[0078] In one embodiment, the distance from the top surface of the initial isolation layer 220 to the top surface of the mask structure is 8000 angstroms to 11000 angstroms.

[0079] refer to Figure 8 , the initial isolation layer 220 is etched back to form a transition isolation layer 221, the transition isolation layer 221 covers the top of the semiconductor substrate 200 around the first trench 211 and the second trench 212, the transition isolation layer 221 includes a first convex object T1 located on the surface of the transition isolation layer 221 in a dense area M and a second convex object T2 located on the surface of the transition isolation layer 221 in a sparse area N, and the density of the first convex object T1 is greater than the density of the second convex object T2.

[0080] Since the top surface of the initial isolation layer 220 is uneven, after the transition isolation layer 221 is formed, the surface of the transition isolation layer 221 has a first convex ridge T1 and a second convex ridge T2 .

[0081] The process of etching back the initial isolation layer 220 to form a transition isolation layer includes an anisotropic dry etching process.

[0082] The initial isolation layer 220 is etched back to form a transition isolation layer 221, the height of which is less than that of the initial isolation layer 220. In this way, in the subsequent grinding process of the transition isolation layer 221, the thickness of the transition isolation layer 221 to be ground is smaller, thereby reducing the process cost.

[0083] In one embodiment, the height of the etched initial isolation layer 220 occupies 1 / 2 to 3 / 4 of the total height of the initial isolation layer 220 .

[0084] refer to Fig. 9 The transition isolation layer 221 is subjected to a burr planarization process to remove at least a portion of the height of the first burr object T1 and at least a portion of the height of the second burr object T2.

[0085] The method for performing the burr planarization treatment on the transition isolation layer comprises: etching the transition isolation layer by an isotropic etching process, wherein the isotropic etching process comprises an isotropic wet etching process.

[0086] The advantages of using an isotropic wet etching process for the burr flattening process include: using wet etching, the burrs (the first burr object T1 and at least part of the height of the second burr object T2) can be processed simultaneously above and around to reduce the size of the burr.

[0087] The parameters of the isotropic wet etching process include: the etching solution used is a hydrofluoric acid solution, the volume percentage concentration of the hydrofluoric acid is 0.5% to 5%, the temperature is 18 degrees Celsius to 28 degrees Celsius, and the etching time is 5 minutes to 30 minutes.

[0088] In the above isotropic wet etching process, the burrs can be fully removed by selecting the above parameter range.

[0089] In other embodiments, the burr planarization process adopts an isotropic dry etching process.

[0090] In this embodiment, the transition isolation layer 221 is subjected to a burr flattening treatment to remove a portion of the height of the first burr object T1 and a portion of the height of the second burr object T2. After the burr flattening treatment, the height of the remaining first burr object T1 is less than or equal to 50 angstroms, and the height of the remaining second burr object T2 is less than or equal to 50 angstroms.

[0091] In other embodiments, the transition isolation layer 221 is subjected to a burr flattening process to remove all first burrs T1 and all second burrs T2 .

[0092] refer to Fig.10 , grinding the transition isolation layer 221 to form a first isolation structure 231 located in the first trench 211 and a second isolation structure 232 located in the second trench 212 .

[0093] In this embodiment, the transition isolation layer 221 is ground until the top surface of the barrier layer 203 is exposed.

[0094] In this embodiment, the process of grinding the transition isolation layer 221 is a chemical mechanical grinding process.

[0095] In the present embodiment, since the transition isolation layer 221 is subjected to burr flattening treatment, at least a portion of the height of the first burr object T1 and at least a portion of the height of the second burr object T2 are removed, so that the heights of the first burr object T1 and the second burr object T2 are reduced or the first burr object T1 and the second burr object T2 are completely removed. Therefore, in the process of grinding the transition isolation layer 221, the time required for grinding the first burr object T1 and the second burr object T2 is relatively short, and the degree of obstruction of the first burr object T1 on the transition isolation layer 221 in the grinding intensive area M and the degree of obstruction of the second burr object T2 on the transition isolation layer 221 in the grinding intensive area M are relatively short. Therefore, the difference between the grinding rate of the transition isolation layer 221 in the grinding intensive area M and the grinding rate of the transition isolation layer 221 in the grinding intensive area M is relatively short, and accordingly, the height difference between the top surface of the first isolation structure 231 and the top surface of the second isolation structure 232 is relatively short.

[0096] In one embodiment, the top surface of the first isolation structure 231 is flush with the top surface of the second isolation structure 232 .

[0097] refer to Fig.11 After forming the first isolation structure 231 and the second isolation structure 232, the mask structure is removed.

[0098] The top surface of the first isolation structure 231 is 600 angstroms to 1200 angstroms higher than the top surface of the semiconductor substrate 200 ; the top surface of the second isolation structure 232 is 600 angstroms to 1200 angstroms higher than the top surface of the semiconductor substrate 200 .

[0099] In this embodiment, if the height of the first isolation structure 231 above the top surface of the semiconductor substrate 200 is less than 600A, the device yield is reduced; if the height of the first isolation structure 231 above the top surface of the semiconductor substrate 200 is greater than 1200A, the residue at the top corner of the first isolation structure 231 will increase when the gate polysilicon is subsequently formed, affecting the device performance. If the height of the second isolation structure 232 above the top surface of the semiconductor substrate 200 is less than 600A, the device yield is reduced; if the height of the second isolation structure above the top surface of the semiconductor substrate is greater than 1200A, the residue at the top corner of the second isolation structure 232 will increase when the gate polysilicon is subsequently formed, affecting the device performance.

[0100] It can be seen that the top surface of the first isolation structure 231 and the top surface of the second isolation structure 232 need to be controlled at a reasonable height to meet the requirements of process design.

[0101] In this embodiment, the difference between the top surface of the first isolation structure 231 and the top surface of the second isolation structure 232 is small, which is beneficial for simultaneously controlling the top surfaces of the first isolation structure 231 and the second isolation structure 232 to be within a preferred height range.

[0102] Correspondingly, the present invention also provides a semiconductor device formed by the above method.

[0103] Although the present invention has been illustrated and described with reference to certain preferred embodiments of the present invention, it should be understood by those skilled in the art that the above is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art may make various changes in form and details, including making several simple deductions or substitutions, without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a dense region and a sparse region; forming a first trench in the dense region of the semiconductor substrate, and forming a second trench in the sparse region of the semiconductor substrate, wherein the density of the first trench is greater than the density of the second trench; depositing an initial isolation layer in the first trench and the second trench and on the semiconductor substrate; Etching back the initial isolation layer to form a transition isolation layer, the transition isolation layer covers the top of the semiconductor substrate around the first trench and around the second trench, the transition isolation layer comprises a first convex thorn object located on the surface of the transition isolation layer in the dense area and a second convex thorn object located on the surface of the transition isolation layer in the sparse area, and the density of the first convex thorn object is greater than the density of the second convex thorn object; Performing a burr-smoothing treatment on the transition isolation layer to remove at least a portion of the height of the first burr and at least a portion of the height of the second burr; After the burr planarization process is performed, the transition isolation layer is ground to form a first isolation structure located in the first trench and a second isolation structure located in the second trench.

2. The method for forming a semiconductor device according to claim 1, wherein: The method for performing the burr flattening treatment on the transition isolation layer includes: etching the transition isolation layer by adopting an isotropic etching process.

3. The method for forming a semiconductor device according to claim 2, wherein: The isotropic etching process includes an isotropic wet etching process.

4. The method for forming a semiconductor device according to claim 3, wherein: The parameters of the isotropic wet etching process include: the etching solution used is a hydrofluoric acid solution, the volume percentage concentration of the hydrofluoric acid is 0.5% to 5%, the temperature is 18 degrees Celsius to 28 degrees Celsius, and the etching time is 5 minutes to 30 minutes.

5. The method for forming a semiconductor device according to claim 1, wherein: The transition isolation layer is subjected to a burr flattening treatment to remove a portion of the height of the first burr and a portion of the height of the second burr.

6. The method for forming a semiconductor device according to claim 5, wherein: After the burr flattening treatment is performed, the height of the remaining first burr objects is less than or equal to 50 angstroms, and the height of the remaining second burr objects is less than or equal to 50 angstroms.

7. The method for forming a semiconductor device according to claim 1, wherein: The transition isolation layer is subjected to a burr flattening treatment to remove all of the first burrs and all of the second burrs.

8. The method for forming a semiconductor device according to claim 1, wherein: The process of etching back the initial isolation layer to form a transition isolation layer includes an anisotropic dry etching process.

9. The method for forming a semiconductor device according to claim 1, wherein: The process of grinding the transition isolation layer includes a chemical mechanical grinding process.

10. The method for forming a semiconductor device according to claim 1, wherein: Before forming the initial isolation layer, a mask structure is provided on the surface of the semiconductor substrate around the first trench and on the surface of the semiconductor substrate around the second trench, and after forming the initial isolation layer, the initial isolation layer also covers the mask structure; Grinding the transition isolation layer until the top surface of the mask structure is exposed to form the first isolation structure and the second isolation structure; The method for forming a semiconductor device further includes: after forming the first isolation structure and the second isolation structure, removing the mask structure.

11. The method for forming a semiconductor device according to claim 10, wherein: The mask structure includes a stress buffer layer located on the surface of the semiconductor substrate around the first trench and on the surface of the semiconductor substrate around the second trench, a main mask layer located on the top of the stress buffer layer, and a barrier layer located on the top of the main mask layer; the transition isolation layer is ground until the top surface of the barrier layer is exposed.

12. The method for forming a semiconductor device according to claim 11, wherein: The material of the stress buffer layer includes silicon oxide; the material of the main mask layer includes silicon nitride; and the material of the barrier layer includes silicon oxynitride.

13. The method for forming a semiconductor device according to claim 1, wherein: Also includes: The depth of the first trench is 8000 angstroms to 10000 angstroms; the depth of the second trench is 8000 angstroms to 10000 angstroms.

14. The method for forming a semiconductor device according to claim 1, wherein: Also includes: The top surface of the first isolation structure is 600 angstroms to 1200 angstroms higher than the top surface of the semiconductor substrate; A top surface of the second isolation structure is 600 angstroms to 1200 angstroms higher than a top surface of the semiconductor substrate.

Images